DIGITAL PHASE DETECTOR.

The invention refers to a digital phase detector with two bistabile flip-flops switched into chain, whereby the first flip-flop at its signal input a digital signal sequence is supplied and at its clock input a reference clock pulse sequence and is connected the exit of the first flip-flop with the signal input of the second flip-flop, which at its clock input against-intimately to the first flip-flop with the reference clock is subjected, whereby with its exit a first phase rule signal output of screen end exclusive OR member is connected at the input side with the signal output of the first flip-flop and with the signal output of the second flip-flop and whereby one is connected with its exit a second phase rule signal output screen end logic circuit at the input side with the signal output of the first flip-flop and with an exit of the signal delay mechanism, those for their part with the data signal sequence is subjected.

A such arrangement is e.g. by the US patent 4,535,459 and from IEEE journal OF Lightwave Technology, VOL.LT-3, No.6, December 1985, well-known. During this well-known arrangement the signal delay of the data signal made for the compensation of the running time in the mentioned first flip-flop is caused by RC-delay sections. With low digital signal rates this may be sufficiently, with higher bit rates as for instance with 565 kbit/s is a run time compensation to RC-delay sections if necessary by very accurate co-ordinating with by manufacture tolerances the due differently failing signal gate-controlled rise time of the first flip-flop to be accomplished, whereby meanwhile despite accurate vote arising temperature developments, which cause another electro-dynamic behavior of the elements, remain unconsidered. The invention is the basis the task to show a way how with a digital phase detector of the kind initially specified an accurate signal running time reconciliation can be accomplished.

The task becomes erfindungsgemäß thus solved, daß the signal delay mechanism from two the first flip-flop corresponding, bistabile flip-flops against-intimately subjected with the data signal sequence to each other is formed, which in each case produce a digital signal, which is limited in each case by a resetting signal in its signal period and over the following logic circuit an associated phase rule signal produced with the occurrence of a rising digital signal flank at the exit a flip-flop of the signal delay mechanism and with the occurrence of a sloping digital signal flank at the exit of the other flip-flop of the signal delay mechanism; it is possible, da&szlig in further arrangement of the invention; the signal input of everyone against-intimately to each other of the flip-flops of the signal delay mechanism with a fixed signal, subjected with the data signal sequence, is subjected and a negating clock input a flip-flop as well as a not-negating clock input of the other flip-flop with the digital signal sequence subjected is daß the exit of that AND element of the exclusive OR member formed with two AND elements and this recapitulatory OR gate, which is steered with the negated output signal of the first flip-flop and with the not-negated output signal of the second flip-flop, connected with a resetting entrance the negating clock input of exhibiting flip-flop of the signal delay mechanism is da&szlig, and; the exit of that AND element of the exclusive OR member, which is steered with the not-negated output signal of the first flip-flop and with the negated output signal of the second flip-flop, with the resetting entrance the not-negating clock input of exhibiting flip-flop is connected.

The invention brings the advantage with itself, daß the signal running time of the first flip-flop in and the other flip-flop the signal delay mechanism, switched into chain, is accurately copied, so daß the second phase rule output signal “UP” by signal running times of the first flip-flop in relation to the first phase rule output signal, arising at the exit of the logic circuit, “down” the exclusive OR member is not temporally falsified. By the delimitation of the individual digital signals in their signal period possible overlaps in the frontier between the rising flank the one and the sloping flank of the other digital signal in the following logic circuit are avoided.

A favourable further training of the invention is characterized, da&szlig by it; the signal delay mechanism exists following logic circuit from two AND elements and a recapitulatory OR gate, whereby that is connected to an entrance of the two AND elements in each case with the signal output and/or other flip-flop of the signal delay mechanism and whereby the other entrance of that AND element, which with the inverted data signal sequence subjected a flip-flop of the signal delay mechanism is connected, with which not-inverted output signal of the first flip-flop is subjected, while the other entrance of the other AND element of the logic circuit with the inverted output signal of the first flip-flop is subjected. By large structural equality of the two the phase rule signals forming logic circuits and function equality of their logic gates so the accurate Laufzeitausgleich up to the exits of the phase detector, obtained first in the phase detector, is maintained. Zweckmäß igerweise lie in further arrangement of the invention the flip-flops of the signal delay circuit with the two bistabile flip-flops in the same layer level of an integrated circuit, with which also line running times within the respective circuit, switched into chain, temperature developments, doping as well as layer-specific Einfluß größ EN despite very high bit rates (e.g. 565 kbit/s) to remain unconsidered can.

On the basis of designs the invention is still more near described in the following. Shows

FIG 1

a circuit diagram of a remark example of a digital phase detector gemäß the invention, and

FIG 2

shows in it arising signal processes.

In the digital phase detector circuit with a first phase rule signal output, represented schematically in FIG 1, “down” and a second phase rule signal output “UP”, with which two flip-flops FF1, FF2 switched into chain are intended, whereby the digital signal sequence is supplied at the same time to the signal input of the flip-flop FF1 and a signal delay mechanism V, become on the one hand output signals of the signal delay mechanism V as well as output signals of the flip-flop FF1 over a logic circuit G to the phase rule output signal “UP” and on the other hand output signals of the trigger stages FF1 and FF2 over an exclusive OR member EXOR to a phase rule output signal “down” zusammengefaß t. A digital signal sequence de, as it is suggested in FIG 2 in line de, and a reference clock pulse sequence T, how it is outlined in FIG 2 in line T, may rest against the signal input D and/or clock input C of the flip-flop FF1. After the well-known function mode of a D-flip-flop the supplied digital signal sequence at the signal input D with the rising clock flank of the reference clock pulse sequence at the clock input C is taken over and connected through to the exit Q1 of the flip-flop. The second flip-flop FF2 of the flip-flops FF1, FF2 switched into chain is subjected at its signal input D by the output signal sequence of the flip-flop FF1 and at its negating clock input C with the reference clock T. At a circuit exit there at the input side supplied digital signal sequence de can with the output signal sequence of the first flip-flop FF1 (in FIG 2), now however in the reference timing pattern, to be again measured. The flip-flops FF3, FF4 belonging to the signal delay mechanism V are subjected at the same time with the flip-flop FF1 with the digital signal sequence de. The digital signal sequence de rests the negated clock input C of the flip-flop FF3 and against the clock input C of the flip-flop FF4. The data inputs D of the two flip-flops FF3, FF4 are firm with a “1” - signal (logical level “1”) subjects, so daß with the occurrence of rising digital signal flanks the pulse rates at the signal outputs of the flip-flops FF3 and FF4, outlined in FIG 2 in the lines Q3 and Q4, result, whereby the pulse time is determined by the flip-flops FF3, FF4 supplied resetting signals ug1 and ug2. These resetting signals result from AND circuits of the output signal Q1 and/or Q1 of the flip-flop FF1 with the output signal Q2 and/or Q2 of the flip-flop FF2. But two the exclusive OR member EXOR associated AND elements UG1, UG2 are intended. In FIG 2 the pulse rate with ug1 and/or ug2, arising at the exit of and element UG1 and/or UG2, is characteristic.

At the data signal exit (Q1 in FIG 1) of the first flip-flop FF1 arising output signal sequence (Q1 in FIG 2) negated with at the exit (Q4 in FIG 1) of the flip-flop FF4 arising pulse rate (Q4 linked in FIG 2) over and element UG4; the pulse rate arising at the exit of the flip-flop FF3 (Q3 in FIG 2) becomes linked with the pulse rate (Q1 in FIG 2) of the flip-flop FF1 over an AND element UG3. The pulse rates ug3, ug4 resulting from it (in FIG 2) over an OR gate OG2 to a “UP signal” zusammengefaß t, as it is suggested in FIG 2 in line “UP”. The “down signal” necessary for the Phasenvergleich is formed in a linkage of the pulse rates ug1 and ug2 by the OR gate OG1 of the exclusive OR member EXOR.

In the design the FIG 1 represented switching configuration to the digital Phasenvergleich of digital signals (e.g. data signals) with the reference clock pulse sequence T supplies with phase balance at the exits of the OR gate OG1, OG2 same pulse rates “down”, to “UP”, which are against each other transferred by a half elementary period. With Phasenungleichheit between digital signal and reference clock pulse sequence the pulse rates are “down”, “UP” in the consequence of their impulses just as, in the duration of their impulses however differently, as this actually (from the US patent 4,535,459 and IEEE… (Siche in front)) admits is and from there not further to be described here needs.