ДВУХКОНТУРНАЯ СХЕМА ФАЗОВОЙ АВТОПОДСТРОЙКИ ЧАСТОТЫ (ФАПЧ) И СХЕМА ДЕМОДУЛЯЦИИ СИГНАЛА ЦВЕТНОСТИ, ИСПОЛЬЗУЮЩАЯ ДВУХКОНТУРНУЮ СХЕМУ ФАПЧ

Изобретение относится к схеме ФАПЧ, генерирующей тактовый сигнал дискретизации, синхронизированный по фазе с сигналом цветовой синхронизации, и к схеме демодуляции сигнала цветности. Техническим результатом является разработка схемы ФАПЧ, изменяющей фазу тактового сигнала дискретизации для аналого-цифрового (А/Ц) преобразования, и схемы демодуляции сигнала цветности, высокоточно демодулирующей цветоразностный сигнал с использованием схемы ФАПЧ. Технический результат достигается тем, что двухконтурная схема снабжена схемами фиксации, А/Ц-преобразования, вывода опорного сигнала цветовой синхронизации, ФАПЧ и фазового детектирования, что дает возможность преобразовывать тактовый сигнал дискретизации, выдаваемый схемой ФАПЧ на схему А/Ц-преобразования, в сигнал, имеющий частоту N•Fпн и синхронизированный по фазе с сигналом цветовой синхронизации, и непрерывно изменять фазу сигнала в соответствии со значением опорной фазы. А схема демодуляции преобразует выходной сигнал схемы А/Ц-преобразования ...

СПОСОБ И СХЕМА УПРАВЛЕНИЯ СИСТЕМОЙ ФАЗОВОЙ АВТОПОДСТРОЙКИ ЧАСТОТЫ С ЦИФРОВОЙ ОБРАБОТКОЙ ДЛЯ СЕТЕВОЙСИНХРОНИЗАЦИИ

Изобретение раскрывает управляющий алгоритм системы фазовой автоподстройки частоты с цифровой обработкой (ЦФАПЧ) для сетевой синхронизации для обеспечения технического результата, заключающегося в предотвращении фазового скачка, вырабатываемого во время изменения рабочего режима. Этот алгоритм предусматривает в случае, если и один и другой опорные тактовые сигналы аномальны, преобразование быстрого или нормального режима в режим удержания, без изменения заранее заданной опорной величины девиации фазы, при восстановлении нормального отслеживания тактового сигнала в режиме удержания, в качестве опорной величины девиации фазы используют значение, полученное путем вычитания среднего значения данных девиации фазы в режиме удержания из среднего значения данных девиации фазы для заранее заданного промежутка времени после преобразования из режима удержания в быстрый режим. 2 с. и 5 з.п. ф-лы, 7 ил.

Устройство автоматической подстройки частоты

УСТРОЙСТВО АВТОМАТИЧЕСКОЙ ПОДСТРОЙКИ ЧАСТОТЫ, содержащее соединенные последовательно входной смеситель , усилитель промежуточной частоты , видеодетектор, амплитудный селектор, фазовый детектор, а также соединенные последовательно фильтр нижних частот и гетеродин, выход которого подключен к другому входу входного смесителя, о т л и ч а ющ е е с я тем, что, с целью повышения точности, между выходом усилителя промежуточной частоты и другим входом фазового детектора включены последовательно соединенные формирователь импульсов и делитель частоты, а выход фазового детектора соединен с входом фильтра нижних частот. i ь СЛ С ...

Фильтр квадратурной составляющей

Устройство автоматического слежения за частотой

Устройство для фазовой автоматической подстройки частоты

Способ преобразования сопротивления датчика в функцию частоты

GENAUER DIGITALER, FEHLERTOLERANTER TAKTGEBER

Taktrückgewinnungsschaltung und Verfahren zur Phasendetektion

Phasenverriegelter Datendetektor.

Regelkreis mit integral wirkendem Regler

STARTEN DER ZEITSYNCHRONISIERUNG IN EINER ANORDNUNG ZUM ABLEITEN EINES TAKTIMPULSSIGNALS.

System und Verfahren zur Beseitigung des Verstärkungsfehlers eines Phasendetektors bei der Taktrückgewinnung verursacht durch eine datenabhängig variierende Anzahl von Flankenwechseln

HOCHGESCHWINDIGKEITSDIGITALPHASENINTERPOLIERER MIT LASTZYKLUSKORREKTURSCHALTKREIS

Es ist eine Schaltung und Architektur beschrieben, die Phaseninterpolierer- (PI, Phase Interpolator) Mixer mit Datenzykluskorrektur (DCC, Duty Cycle Correction) kombiniert, um Querkonflikt zwischen den Dreizustandswechselrichterpaaren des Mixers zu verhindern. Der Steuercode für die p-Typ- und n-Typ-Netzwerke in dem PI-Mixer sind entkoppelt und DCC-Mechanismen sind in den PI-Mixercodedecodierungsschema vermengt, um eine Niederlatenzphaseninterpolation und Lastzykluskorrektur zu ermöglichen. Die Schaltung weist einen ersten Mixerschaltkreis auf, der von einem ersten Code steuerbar ist; einen zweiten Mixerschaltkreis, der von einem zweiten Code steuerbar ist; einen Knoten, der mit Ausgängen des ersten und zweiten Mixers gekoppelt ist; und einen Wächterschaltkreis, der mit dem Knoten gekoppelt ist, wobei der erste und zweite Mixer Mixer mit drei stabilen Zuständen sind.

STROMAUSGANGSSCHALTUNG.

Time base phase variation for digital oscilloscope

The phase of the time-base for a digital oscilloscope can be modulated through the summation of the voltage between the phases and the output from the phase detector, in a phase-locked loop. The phase locked loop consists of a reference time base (502), an output time base (514) and a pilot input (516), which controls the phase error between the reference input and the output. This pilot input is produced through a digital/analogue converter, working from a series of numbers from a microprocessor, corresponding to the signal value. The phase is modulated by adding this pilot voltage to the output (520) of a phase detector (504), such that the sum of the two (524) supplies a loop filter (508).

Data channels synchronization system has transmit phase locked loop to generate clock signals to synchronize channel circuits that receive core data streams

A core phase locked loop (PLL) (102) receives the reference clock signal and provides a core clock signal to a core circuit (104). A transmit PLL (122) receives the reference clock signal and generates clock signals to synchronize the channel circuits (124) that receive core data streams. The channel circuits convert the core data streams into serial data streams. An Independent claim is also included for data channels synchronization method.

VERFAHREN UND SCHALTUNG ZUM SCHNELLEN FREQUENZWECHSEL EINES PHASENGEREGELTEN OSZILLATORS

PLL-Schaltung mit reduzierter Einschwingzeit

Jitterdetektionsvorrichtung und Phasenregelschleife unter Verwendung des erfassten Jitters

Paketbasierter direkter digitaler Synthesizer zur Minimierung von mathematischem Rauschen und Rauschen eines Digital-Analog-Konverters

Geräteschaltkreis, der für die Ausführung einer Funktion der direkten digitalen Synthese (DDS) in einem elektronischen Prüfgerät konfiguriert ist, wobei das Gerät für den Betrieb bei einer Vielzahl von gewünschten Betriebsfrequenzen ausgelegt ist und der Schaltkreis Folgendes umfasst: eine DDS-Logikschaltung (102), die so konfiguriert ist, dass sie auf der Basis einer Anzahl N von Bits und bei einer vorgegebenen Systemtaktfrequenz arbeitet und die direkte digitale Synthese an einer Vielzahl von aufeinander folgenden Paketen von sinusartigen Wellen ausführt, wobei jedes Paket eine Dauer einer Periode aufweist, die eine vorgegebene Anzahl M von Folgen einer oder mehrerer sinusartigen Wellen umfasst, einen Rechner (100) zur Paketauslegung, der die Anzahl M von sinusartigen Wellen des Pakets und einen entsprechenden Schrittregisterwert so bestimmt, dass die Sinuswelle am Ende eines Pakets der Sinuswelle zu Beginn des direkt nachfolgenden Pakets entspricht, wobei der Rechner (100) zur Paketauslegung ...

Verfahren und Vorrichtung zur Simplex-Datenübertragung

The invention relates to a method for carrying out simplex data transmission of a data telegram that is modulated to a carrier frequency, in particular, for carrying out the simplex radio transmission in a radio access control system. According to the invention, the data telegram is repeatedly transmitted in order to increase the interference immunity, whereby the repeated transmission is carried out using at least two different carrier frequencies.

Digitaler Phasendetektor

Gemäß einem Beispiel wird ein digitaler Phasendetektor zur Verwendung mit einem Phasenregelkreis offenbart. Der digitale Phasendetektor ist so konfiguriert, dass er in einer Niederfrequenzumgebung funktioniert und Rausch und Transienten in einem Signal filtert, während er außerdem gegenüber verworfenen Phasenimpulsen tolerant ist. In einigen Ausführungsformen ist der digitale Phasendetektor so konfiguriert, dass er bis zu zwei REFCLK-Flanken in Bezug auf ein FBCLK-Signal misst und eine Flanke als nacheilend klassifiziert, wenn die Flanke in der ersten Hälfte von REFCLK auftritt, und eine Flanke als voreilend klassifiziert, wenn die Flanke in der zweiten Hälfte von REFCLK auftritt. Wenn beiden Flanken voreilend oder beide nacheilend sind, wird die kleinere der beiden als die Phase verwendet. Wenn eine voreilend ist und eine nacheilend ist, wird die Differenz als die Phase verwendet.

RADARSYSTE M MIT INTERNER RAMPENLINEARITÄTSMESSUNGSFÄHIGKEIT

Eine Phasenregelschleife (PLL) für ein Radarsystem umfasst einen Oszillator, der ausgebildet ist, um eine Ausgangsfrequenz aufzuweisen, und einen Multi-Modulus-Teiler (MMD), der ausgebildet ist, um aufeinanderfolgende Frequenzmodulationsrampen der Oszillator-Ausgangsfrequenz zu implementieren, wobei jede Frequenzmodulationsrampe bei einer ersten Frequenz beginnt und bei einer zweiten Frequenz endet. Die PLL wird durch ein Abwärtsmischen einer Ausgangssignals des Multi-Modulus-Teilers zu einer Frequenz über null Hertz, Messen der abwärtsgemischten Ausgangssignals des Multi-Modulus-Teilers, um eine Mehrzahl von Multi-Modulus-Teiler-Ausgangssignalmessungen für jede Frequenzmodulationsrampe zu erzeugen, und Berechnen der Frequenz des Multi-Modulus-Teilers basierend auf der Mehrzahl von Multi-Modulus-Teiler--Ausgangssignalmessungen für jede Frequenzmodulationsrampe betrieben.

Schaltung zum Synchronisieren eines Oszillators mit Hilfe einer Synchronisierwechselspannung

Taktregenerator

Schaltungsanordnung für einen Phasenkomparator

SPEICHERBLOCKAUSWAHL UNTER VERWENDUNG VON MEHREREN WORTLEITUNGEN ZUR ADRESSIERUNG EINER EINZIGEN SPEICHERZELLENZEILE

Tastverhältniskorrekturschaltkreis, integrierter Schaltkreis, Phasenregelkreisschaltung, Verzögerungsregelkreisschaltung, Speicherbauelement und Verfahren zum Erzeugen eines Taktsignals

Unterdrückung von niederfrequentem Rauschen von einem Phasendetektor in einer Phasensteuerschleife

Die offenbarte Erfindung schafft eine Struktur und ein Verfahren zum Verbessern der Leistungsfähigkeit einer Phasenregelschleife durch Unterdrücken von niederfrequentem Rauschen, das durch einen Phasendetektor erzeugt wird. Dies wird erreicht durch Aufwärtswandlung der In-Band-Frequenzkomponenten in der Phasendifferenz zwischen Referenzsignal und Rückkopplungssignal zu einem höheren Frequenzbereich, wo eine Rauschleistungsfähigkeit eines Phasendetektors verbessert ist. Die aufwärts gewandelte Phasendifferenz wird an einen Phasendetektor geliefert, der konfiguriert ist, um basierend auf dieser Phasendifferenz ein Fehlersignal zu bestimmen. Das Fehlersignal wird an einen Abwärtswandler ausgegeben, der konfiguriert ist, um das Fehlersignal abwärts zu wandeln (z. B. zurück zu dem ursprünglichen Frequenzbereich), wodurch eigentlich das niederfrequente Rauschen des Fehlersignals (erzeugt durch den Phasendetektor) aufwärts gewandelt wird, bevor dasselbe an ein Filter geliefert wird, das konfiguriert ...

Phasenregelschleife

Digital frequency locked loop

Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.

Communication systems

Radio equipment, and method and program of determining signal transmission speed

FREQUENCY SYNTHESISERS

MONOSTABLE MULTIVIBRATOR

Improved phase locked loop

FREQUENCY TUNING FOR A PHASE LOCKED LOOP

Power-saving frequency synthesiser

A frequency synthesiser is provided including a programmable divider, a register for holding a divisor word, a reference source and a sample-and-hold phase detector, in which the register is maintained active during power-down and in which a sequence controller is provided for controlling the sequence of activations of the synthesiser on power up and supplies a substantially constant voltage, during power-down, to the output of the phase detector equivalent to the in-lock output of the detector.

Phase-locked loop oscillator control circuit

Apparatus and method for enabling elements of a phase locked loop

An apparatus and method enables elements of a phase locked loop (PLL) (300). The PLL (300) includes a plurality of elements (202, 203, 204, 205). Each element produces an output signal (207, 208, 209, 116 or 117). Each element has a response time t3-t2 defined by the difference in time between a first time t2 at which the element is enabled and a second time t3, occurring after the first time t2, at which the output signal of the element reaches a steady state condition. A voltage controlled oscillator (204) of the plurality of elements, having a first response time t3-t2 is enabled at the first time t2 responsive to a first control signal (302). A loop divider (205) of the plurality of elements, having a second response time less than the first response time t3-t2, is enabled responsive to the first response time t3-t2 and a second control signal (303). The present invention advantageously provides fast lock time for the PLL (300). ...

Method and apparatus for implementing frequency hopping in a TDMA system

Intermittent operation receiver with variable pre-heat time for its phase-locked circuit

Frequency-multiplying delay locked loop

A frequency multiplier circuit (100) comprising a delay line receiving at one end thereof a reference clock (102) for generating clock tap outputs from respective ones of a plurality of period matched delay elements (101); a clock combining circuit (TOG) responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period. The delay line may be included in a delay-locked loop to match the period of the delay elements (101). A plurality of combining circuits cells (TOG) are provided, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each cell providing complementary outputs. A selector (106) is responsive to a selection control signal from a phase detector (112) for selecting an output from one of a pair of complementary outputs of one of the combining cells.

A delay locked loop device

Method and apparatus for generating and synchronizing multiple clocks

Clock recovery circuitry

Clock recovery circuitry for recovering a clock signal from a data signal comprises sampling means (46) for sampling the data signal at a plurality of sampling points, bit reversal detecting means (48) for determining a sampling point at which the data signal changes state, selecting means (50) for selecting a phase from amongst a plurality of candidate phases based on a sampling point at which the data signal is determined to change state, and phase setting means (38, Fig 4) for setting the phase of the clock signal in dependence on the selected phase. The circuitry may be used to produce an estimate of a desired phase of the clock signal for supply to a phase locked loop. This can allow the phase locked loop to be brought quickly into lock.

Communication semiconductor integrated circuit and radio communication system

A communication semiconductor integrated circuit has an oscillator circuit (TXVCO 240) forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit (RFVCO 250) forming part of a reception PLL circuit and an oscillator circuit (IFVCO 230) for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A synthesizer 262 includes a circuit (32,Fig3) for measuring the oscillating frequency of the oscillator circuit 240 forming part of the transmission PLL circuit and a synthesizer 261 includes a circuit(22,Fig2) for measuring the oscillating frequency of the oscillator circuit 250 forming part of the reception PLL circuit ...

Handling jitter in differential data signals

PHASE DETECTOR CIRCUIT

Dual-gain loop circuitry for programmable device

Method and device for determining a synchronization fault in a network node

Digital phase control circuit for controlling phase error

A digital phase control circuit 20 for controlling a phase error between a phase of an output signal of an oscillating circuit and a phase of a reference signal. A pulse cycle of the output signal is changed in response to a control input value S. The digital phase control circuit comprises a phase comparator 21 for judging an advance/delay of a phase of the output signal, and a counter circuit 22 for counting up or down according to a judgement of the phase comparator circuit 21 and for changing a count, when that judgement has been reversed, to approximately a mean value of the counts made during the successive same judgements, this count being used as the control input value S.

Frequency synthesizer

Correlation circuit reduces oscillator perturbations in a phase locked loop

A method of controlling the oscillator in a phase locked loop (PLL) is disclosed. The PLL comprises a controlled oscillator 201, a phase detector 202 and a loop filter 203 which outputs a low frequency compensation signal in dependence upon the output of the oscillator 205 and a reference signal 206. A correlator 208 correlates an interfering signal 211 and the low frequency compensation signal from the loop filter 203. An adaptive filter 210 processes the interfering signal 211 in dependence on a correlation signal from the correlator 208 and outputs a high frequency compensation signal. A summation unit 212 combines the low frequency compensation signal from the loop filter 203 and the high frequency compensation signal from the adaptive filter 210 to form a control signal to drive the input of the oscillator. The method finds application where a phase locked loop would not otherwise be able to compensate for disturbances caused by a transmitted signal that lies outside the passband of ...

Method and apparatus for reducing capacitor-switching transient signals

In a logging-while-drilling apparatus a phase-locked loop locks onto the carrier of a received PSK signal, and provides timing signals for the demodulation. The phase-locked loop includes a voltage controlled oscillator, and a phase comparator a variable bandwidth filter, which couples the comparator output to the control terminal of the VCO. A controller is coupled to the variable filter to change the bandwidth of the filter (300) as a function of the received input signal. Before phaselock is achieved a wide bandwidth is chosen for the filter, and after lock a narrower bandwidth is chosen for loop stability. Bandwidth is changed by switching in one of capacitors C11-C13 and resistors R11-R13. The filter gain factor is consequently changed. To prevent loss of phaselock during switching, the capacitors not being switched in are kept pre-charged to appropriate voltages by circuitry 421-426. ...

Horizontal scanning frequency multiplying circuit

A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with an input horizontal synchronizing signal having a horizontal scanning frequency fH of a television signal, a phase-locked-loop (PLL) for producing a signal having a frequency NfH (N is an integer over 1), a first counter supplied with an output signal of a voltage controlled oscillator within the PLL as a clock signal, for producing a counted output every time the clock signal is counted for a predetermined counting time T1 and supplying this counted output to the flip-flop to reset the flip-flop, a second counter supplied with the output signal of the voltage controlled oscillator as a clock signal, for counting this clock signal, a counted value setting circuit for producing a high-level output according to an output of the second counter when the second counter counts for a predetermined counting time T2, where T2>T1, and an OR-gate supplied with the input horizontal synchronizing signal and an output ...

FREQUENCY AND PHASE SYNCHRONISING ARRANGEMENTS

PHASE-CONTROLLED OSCILLATOR CIRCUITS

VARIABLE FREQUENCY OSCILLATOR SYSTEM

AUTOMATIC FREQUENCY CONTROL OF OSCILLATORS

Logging method and device.

Device including/understanding an oscillator being stabilized automatically on the frequency of an impulse control signal.

ANORDNUNG FUER EINE STARR PHASENGEREGELTEN MIKROWELLENSENDER, INSBESONDER FUER RICHT- FUNKGERAETE

SWITCHING CONFIGURATION WITH A PHASE-LOCKED LOOP

FREQUENCY GENERATOR WITH SEVERAL VOLTAGE-CONTROLLED OSCILLATORS

FILTER FOR A PHASE RULE LOOP

PLL ZYKLUSSCHLUPFKOMPENSATION

FREQUENCY DETECTOR FOR BOLTING DEVICE

DIGITAL PHASE COMPARATOR

PHASE RULE LOOP

PROCEDURE AND DEVICE FOR THE CLOCK RECUPERATION FROM A DATA SIGNAL

DELAY AUTOMATIC CONTROL LOOP WITH PRECISION-STEERED DELAY

PROCEDURE AND DEVICE FOR THE CLOCK CLOCK RECUPERATION IN A TELECOMMUNICATION SYSTEM

PROCEDURE AND DEVICE FOR THE REDUCTION OF THE CLOCK PULSE SHIFT IN A SAMPLE SLAVE SYSTEM WITH SEVERAL HIDDEN CLOCK CYCLES

SCHALTUNGSANORDNUNG ZUR SYNCHRONISATION

HIGH-CONFIGURABLE PHASE RULE LOOP STRUCTURE FOR A PROGRAMMABLE LOGICAL COMPONENT

MULTIPLE SWITCHING AND ALERTING DEVICE

SYNCHRONISATION CIRCUIT FOR THE SYNCHRONIZATION OF A PHASE SYNCHRONISATION LOOP

BIT TIMING SIGNAL RENDITION CIRCUIT

PHASE-LOCKED RULE LOOP

OSCILLATOR CIRCUIT

WITH A FREQUENCY READJUSTING CIRCUIT OF PROVIDED OSCILLATORS

SWITCHING CONFIGURATION FOR STEERING THE COLOR CHANGE-OVER WITH A STRAHLINDEXFARBFERNSEHEMPF|NGER

PROCEDURE AND DEVICE FOR THE PHASE AND FREQUENQUENZVERGLEICH

FREQUENCY DETECTOR

PLL SYNTHESIZER WITH IMPROVED VCO VORABSTIMMUNG

SWITCHING CONFIGURATION FOR THE MUTUAL SYNCHRONIZATION OF IN THE NODES OF A TIME MULTIPLEX COMMUNICATIONS NETWORK, IN PARTICULAR PCM TIME MULTIPLEX COMMUNICATIONS NETWORK, PLANNING OFFICE CLOCK OSCILLATORS

PROCEDURE AND SWITCHING CONFIGURATION FOR THE MINIMIZATION OF A CHANGE PORTION OF A PHASE DETECTOR OUTPUT SIGNAL OF A PHASE-LOCKED LOOP

CURRENT REDUCTION FOR A SYNTHESIZING ARRANGEMENT

SWITCHING CONFIGURATION FOR THE BALANCING OF THE THERMAL TRACKING OF A PHASE DETECTOR.

PROCEDURE AND SWITCHING CONFIGURATION FOR A PHASE COMPARATOR.

DIGITAL PHASE DETECTOR.

PHASE LOCKING LOOP WITH VARIABLE RANGE.

GRIND in PLL CIRCUIT.

SWITCHING CONFIGURATION FOR THE PRODUCTION OF A CLOCK PULSE.

DEMODULATOR ARRANGEMENT FOR TWO-PHASEDIGITALMODULATED SIGNALS.

SPLIT LOOP FILTER.

Гибридный синтезатор частот с автокомпенсацией фазовых помех

Полезная модель относится к области радиоэлектроники. Технический результат заключается в снижении уровня паразитных спектральных составляющих, уровня фазового шума и шумовой полосы синтезируемого сигнала формирователя. Технический результат достигается за счёт гибридного синтезатора частот с автокомпенсацией фазовых помех, содержащего: опорный генератор; цифровой вычислительный синтезатор; выходной фильтр цифрового вычислительного синтезатора; петлю фазовой автоподстройки частоты, содержащую: фазовый детектор, фильтр нижних частот и генератор, управляемый напряжением; делитель частоты; автокомпенсатор фазовых искажений, состоящий из опорного тракта, содержащего дифференцирующую цепь, Т-триггер; информационного тракта, содержащего дифференцирующую цепь, двухполупериодный выпрямитель, Т-триггер; усилитель; сумматор; управляемый фазовращатель. 1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 194 942 U1 (51) МПК H03L 7/085 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H03L 7/085 (2019.08) (21)(22) Заявка: 2019132827, 15.10.2019 (24) Дата начала отсчета срока действия патента: Дата регистрации: 30.12.2019 (45) Опубликовано: 30.12.2019 Бюл. № 1 Адрес для переписки: 600000, г. Владимир, ул. Горького, 87, ВлГУ, патентная группа (73) Патентообладатель(и): Федеральное государственное бюджетное образовательное учреждение высшего образования "Владимирский Государственный Университет имени Александра Григорьевича и Николая Григорьевича Столетовых" (ВлГУ) (RU) U 1 1 9 4 9 4 2 R U (54) Гибридный синтезатор частот с автокомпенсацией фазовых помех (57) Реферат: Полезная модель относится к области фазовой автоподстройки частоты, содержащую: радиоэлектроники. Технический результат фазовый детектор, фильтр нижних частот и заключается в снижении уровня паразитных генератор, управляемый напряжением; делитель спектральных составляющих, уровня фазового частоты; автокомпенсатор фазовых искажений, шума и шумовой полосы ...

Receiving device and demodulation device

To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.

Pll circuit, method for operating pll circuit and system

A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to generate a first phase difference; an operating circuit to subtract a value obtained by subtracting the first phase difference from the second counted value from the first counted value to generate a phase difference signal; and an oscillator to change a frequency of the output clock signal based on the phase difference signal.

Sampling phase correcting host controller, semiconductor device and method

One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

Signal transmission system with clock signal generator configured for generating clock signal having stepwise/smooth frequency transition and related signal transmission method thereof

A signal transmission system includes a first clock signal generator and a second clock signal generator. The first clock signal generator is configured for generating a first clock signal according to clock information derived from a transmitted signal, wherein the transmitted signal is changed in response to a frequency change of a second clock signal, and the first clock signal generator enters a frequency-unlocked state if the second clock signal has a frequency transition from a first frequency to a second frequency during a first time period. The second clock signal generator is configured for generating the second clock signal having the frequency transition from the first frequency to the second frequency during a second time period longer than the first time period such that the first clock signal generator stays in a frequency-locked state during the second time period.

Digital frequency locked delay line

A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.

Techniques for Varying a Periodic Signal Based on Changes in a Data Rate

A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal. The phase adjustment circuit causes the phase of the second periodic signal and a phase of a third periodic signal to vary based on a variation in the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The circuit varies a frequency of the third periodic signal to correspond to changes in a data rate of the data signal between at least three different data rates that are based on at least three data transmission protocols.

Phase locked loop and method for operating the same

A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal.

Injection-Locked Oscillator

A signal generator for generating an output signal with a frequency that is a multiple of a frequency of a reference signal, the signal generator including an oscillator configured to generate the output signal in dependence on the reference signal and a control signal and a control circuit configured to generate the control signal to comprise a series of pulses in which one or more of the pulses is offset in phase relative to the reference signal, the control circuit thereby being capable of controlling the frequency and/or phase of the output signal.

Fractional-N PLL Using Multiple Phase Comparison Frequencies to Improve Spurious Signal Performance

SEARCHES A fractional spur compensation technique is implemented in a fractional-N PLL using multiple phase comparison frequencies F pd , one of which is selected for any channel frequency F ch in a target frequency band to obtain a selected offset frequency F os between the channel frequency F ch and its primary fractional spur throughout the target frequency band. Other features of an exemplary implementation of the fractional spur compensation technique include (a) maintaining the phase comparison frequency at less than a predetermined maximum value, (b) using a programmable reference frequency multiplier with selectable multiplication factors and/or a programmable reference frequency divider with selectable divide ratios to generate multiple phase comparison frequencies derived from a predetermined reference frequency F ref , and (c) using a programmable charge pump to select different charge pump currents for respective phase comparison frequencies to reduce loop gain variation.

1 to 2n-1 fractional divider circuit with fine fractional resolution

A fractional divider has been provided that allows for division ratios of 1:1 to 1:2 N-1 with fine fractional resolution. To accomplish this, a phase blender (which is under the control of a state machine) is used to “blend” or interpolate consecutive phases of a clock signal from a delay locked loop to achieve a low deterministic jitter, while a sigma delta modulator can also be used to maintain low deterministic jitter while achieving the desired frequency resolution.

Glitch-free oversampling clock and data recovery

A clock and data recovery (CDR) circuit includes an edge detector, an edge selector, and a phase selector. The edge detector is arranged to detect edges of serial input data and to provide an edge detection result. The serial input data is oversampled utilizing multiple clock phases. The edge selector for selecting one of the multiple clock phases for a recovered clock is arranged to provide an edge selection result, to receive the last edge selection result as a first input, and to receive the edge detection result as a second input. The phase selector is arranged to provide the recovered clock and recovered data.

Method and system of synchronizing data to reference time signal with data resampling

A device receives a data signal and a reference timing signal provided from a first clock. The device includes a sample clock that operates independently from the first clock, wherein the sample clock outputs a sample clock signal that is asynchronous with the reference timing signal; a sampler for sampling a data signal in accordance with the sample clock signal and outputting a sampled data signal; and a resampler for resampling the sampled data signal according to a resampling ratio and outputting a resampled data signal such that a number of data samples in the resampled data signal within a synchronization time interval defined with respect to the reference timing signal equals a nominal number of data samples that would occur in the sampled data signal within the synchronization time interval when the sample clock signal was synchronized to the reference timing signal.

Frequency synthesizer

There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

Device having digitally controlled oscillator

A device includes a digital-to-time converter and an interpolator having a data input and a data output coupled to the digital-to-time converter. The interpolator may be configured to receive a converter control signal at the data input and to provide an interpolated converter control signal at the data output. An interpolation rate of the interpolator may depend on the converter control signal.

Two-point modulation device using voltage controlled oscillator, and calibration method

Included are: a modulation section including a feedback circuit configured to conduct feedback control of an output signal from a voltage controlled oscillator based on an inputted modulation signal, and a feed-forward circuit configured to calibrate the modulation signal and outputting the calibrated modulation signal to the voltage controlled oscillator; a signal output section configured to output, to the modulation section, a predetermined reference signal instead of the modulation signal when a calibration is conducted; and a gain correction section configured to, in a state where the feedback circuit is forming an open loop, calculate a frequency transition amount of the reference signal outputted by the voltage controlled oscillator, and correct a gain used for calibrating the modulation signal at the feed-forward circuit based on the calculated frequency transition amount.

Radio communication apparatus

According to one embodiment, an analog unit performs frequency conversion of a reception signal. A digital unit performs demodulation processing of the reception signal subjected to the frequency conversion by the analog unit. A PLL circuit generates a clock of the digital unit. A PLL-setting changing unit performs, based on the reception signal, a setting change of parameters of the PLL circuit to thereby control the jitter of the clock.

Device and method for compensating a signal propagation delay

A device for compensating a delay τ suffered by a first periodic signal ref(t) during propagation between a first and second end of a first transmission connection, comprising at least: first means able to generate a second signal ref(t+τ) corresponding to the first signal ref(t) the phase of which is advanced by a time equal to the delay τ, second means able to generate, from a third signal ref(t−τ) obtained at the second end of the first transmission connection and corresponding to the first signal ref(t) the phase of which is delayed by the delay τ, and from the second signal ref(t+τ), a fourth signal in phase with the first signal ref(t).

Spur reduction technique for sampling pll's

Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Digital phase lock loop

An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.

Fractional digital pll with analog phase error compensator

Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.

Semiconductor Integrated Circuit and Control Method for Clock Signal Synchronization

There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

Delay lock loop and method for generating clock signal

A delay lock loop (DLL) including a voltage control delay line (VCDL), a phase frequency detecting loop (PFD loop), and a phase limiting loop is provided. The VCDL generates an output clock signal according to a DC voltage signal, wherein the VCDL delays an input clock signal by a specific period so as to generate the output clock signal. The PFD loop generates the DC voltage signal according to the phase difference of the input clock signal and the output clock signal and is controlled by an initiation signal. The phase limiting loop limits the delay of the output clock signal to be less than a delay time and generates the initiation signal to enable the PFD loop. Furthermore, a clock signal generating method is also provided.

System and method for reducing holdover duration

A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The second signal is used for disciplining the LO. The LO error corrector is capable of disciplining the LO using a source that is less accurate than a preferred second signal, if the preferred second signal is unavailable to discipline the LO.

State machine for deskew delay locked loop

A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to the falling edge of REFCLK, and, if so, add enough delay to DCLK to ensure that the DLL locks only to the rising edge of REFCLK and never accidentally to the falling edge.

Estimation of Sample Clock Frequency Offset Using Error Vector Magnitude

A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/T S ′ of a receiver and an intended sample clock rate 1/T S . The receiver captures samples of a received baseband signal at the rate 1/T S ′, operates on the captured samples to generate an estimate for the clock rate offset, and fractionally resamples the captured samples using the clock rate offset. The resampled data represents an estimate of baseband symbols transmitted by the transmitter. The action of operating on the captured samples involves computing an error vector signal and then estimating the clock rate offset using the error vector signal. The error vector signal may be computed in different ways depending on whether or not carrier frequency offset and carrier phase offset are assumed to be present in the received baseband signal.

Signal Processing Circuit and Method

A signal processing circuit for providing a modulated analog transmit signal on the basis of a digital transmit data signal is configured to vary a resolution in dependence on a detected or predefined parameter when providing the modulated analog transmit signal.

Receiver training with cycle slip detection and correction

In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Fast lock clock-data recovery for phase steps

A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Phase detector, phase detecting method, and clock-and-data recovery device

A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.

Sampling clock selection module of serial data stream

A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.

Clock and data recovery system, phase adjusting method, and phasedetector

Disclosed is a phase discriminator, including: a first XOR gate connected to a trigger and a delay unit, a second XOR gate connected to the trigger and a latch, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first offset current source circuit outputting a first adjustable offset circuit for controlling amplitude of the error signal output by the first XOR gate; and/or, the second XOR gate is a current mode logic XOR gate, the second XOR gate comprises a second offset current source circuit outputting a second adjustable offset circuit for controlling amplitude of reference signal output by the second XOR gate. Also disclosed are a clock and data recovery system and a phase adjustment method. The present invention can prevent introducing noise coupling to the voltage control oscillator (VCO) module.

Circuit and method for preventing false lock and delay locked loop using the same

The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.

Variable modulus modulator for fractional-n frequency synthesizers

A variable modulus sigma delta (ΣΔ) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a ΣΔ noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC′ and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the ΣΔ noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

Apparatus and method for advanced synchronous strobe transmission

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a core clocks generator, and a synchronous strobe driver. The resistor network is configured to provide a ratio signal that indicates an amount to advance a synchronous data strobe associated with a data group. The core clocks generator is coupled to the ratio signal, and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

Dll phase detection using advanced phase equalization

A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an Onlx mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal is used to terminate the ForceSL and Onlx modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during Onlx exit, and resulting in faster DLL locking time.

Phase locked loop

A method for generating a signal is provided. A control signal is generated in response to a comparison between a reference signal and a feedback signal. Then, charge is provided to first and second low pass filters (LPFs). The first and second LPFs have first and second bandwidths, respectively, and the second bandwidth is greater than the first bandwidth. First and second gains are then applied to the outputs from the first and second LPFs, respectively, so as to generate first and second voltages, respectively. The first gain is also greater than the second gain. The feedback signal is then generated from the sum of the first and second voltages.

Method and system for frequency synchronization

The present invention provides a method of synchronising the frequency of a slave clock to that of a master, preferably using a packet network. An aspects of the invention provide a method of synchronizing the frequency of a slave clock in a slave device to a master clock in a master device, the method including the steps of: a) receiving in the slave device a first message from said master device having a first time-stamp which is a time-stamp of said master clock indicating the time of sending of said first message; b) extracting said time-stamp from said message and initializing a counter in the slave device which counts an output of said slave clock; c) receiving in the slave device a further message from said master device and reading the value of said counter at the time of receipt of said further message; d) extracting a further time-stamp which is the precise time of sending of the further message according to said master clock; e) determining an error signal which is representative of the difference between said value of the counter and the difference between said first and further time-stamps; and f) adjusting the frequency of said slave clock based on said error signal. An apparatus for synchronizing the frequency of a clock in a slave device which is communicatively coupled to a master device is also provided.

Low power edge and data sampling

An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

Integrated circuit

There is provided an integrated circuit in which a reference-signal source generates a reference signal having a basic frequency, a phase locked loop includes a voltage-controlled oscillator, a first frequency divider to generate a first frequency-divided signal based on the signal by N, a phase detector, a charge pump and a loop filter, the second frequency generates a second frequency-divided signal based on the signal generated by the voltage-controlled oscillator by M, wherein a minimum absolute value of a difference between the basic frequency multiplied by “K” and a frequency of the second frequency-divided signal is equal to or less than a low cutoff frequency of a bandpass filter or equal to or higher than a high cutoff frequency of the bandpass filter, the bandpass filter being represented by a transfer function from an input of the voltage-controlled oscillator to an output of the phase locked loop.

Reducing phase locked loop phase lock time

There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected.

ACCUMULATOR-TYPE FRACTIONAL N-PLL SYNTHESIZER AND CONTROL METHOD THEREOF

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider () for feeding back an output of a VCO () of an output stage to a preceding stage is generated using an error signal from an accumulator (). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector () are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider () is suppressed. 1. An accumulator-type fractional N-PLL synthesizer comprising:a VCO;a fractional frequency divider, disposed in a feedback path of an output signal of the VCO, for generating a frequency divider output signal of a fractional frequency division number;an accumulator for supplying an overflow signal for periodically switching a frequency division number of the fractional frequency division number, to the fractional frequency divider; anda phase detector for detecting a phase difference between the frequency divider output signal and a predetermined reference signal to generate a control input signal to the VCO based on the detected phase difference,wherein the accumulator generates an error signal having fractional phase error information, andwherein the phase detector corrects the phase difference between the frequency divider output signal and the reference signal, using the error signal.2. The accumulator-type fractional N-PLL synthesizer according to claim 1 , wherein the phase detector generates the phase difference as a UP signal and a DN signal claim 1 ...

DIGITAL PHASE LOCKED LOOP

A phase locked loop circuit () includes a controllable oscillator () for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit () for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit () for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator () is driven by the outputs of the first and second phase detections circuits. 1. A phase locked loop circuit , comprising:a controllable oscillator for generating an output signal of desired frequency;a first phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a first edge of a reference signal;a second phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a second edge of a reference signal; andcircuitry for controlling said controllable oscillator responsive to said outputs of said first and second phase detections circuits.2. The phase locked loop circuit of and further comprising circuitry for adjusting the output of said second phase detection circuit to account for a variation of said reference signal from a 50% duty cycle.3. The phase locked loop circuit of wherein said outputs of said first and second phase detection circuits are added on each edge of said reference signal.4. The phase locked loop circuit of wherein said outputs of said first and second phase detection circuits are added on a predetermined edge of said reference signal.5. The phase locked loop circuit of wherein said first detection circuit generates an output responsive to the output signal and a rising edge of said reference signal and said second detection circuit generates an output responsive to the output signal and a falling ...

CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES

An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation. 112-. (canceled)13. An integrated circuit (“IC”) comprisingphase-locked loop (“PLL”) circuitry including charge pump circuitry, voltage-controlled oscillator circuitry, and phase-frequency detector circuitry coupled to one another in a closed loop series; andcircuitry for supplying a controllably variable amount of charge pump current to the charge pump circuitry.14. The integrated circuit defined in further comprising:programmable circuitry for controlling the circuitry for supplying to determine the amount of charge pump current the circuitry for supplying supplies to the charge pump circuitry.15. The integrated circuit defined in wherein the circuitry for supplying supplies a controllable number of multiples of a nominal amount of charge pump current to the charge pump circuitry.16. An integrated circuit (“IC”) comprising:phase-locked loop circuitry including charge pump circuitry, voltage-controlled oscillator circuitry, and phase-frequency detector circuitry coupled to one another in a closed loop series, and controllably variable voltage regulator circuitry for supplying a regulated voltage to the charge pump circuitry, the regulated voltage being controllably variable.17. The integrated circuit defined in further comprising:power supply circuitry for supplying a power supply signal having a power supply ...

Dual Phase Detector Phase-Locked Loop

A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duration that compensates for a phase error in the feedback signal.

METHOD OF OPERATING PHASE-LOCK ASSISTANT CIRCUITRY

A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal. 1. A method of operating a charge pump of a phase-lock assistant circuit , the method comprising:determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock;determining a second relative timing relationship of the phase of the data signal to a phase of a second phase clock, the first and second phase clocks having a 45° phase difference;generating an up signal and a down signal in response to the first relative timing relationship and the second relative timing relationship; anddriving the charge pump circuit according to the up signal and the down signal.2. The method of claim 1 , wherein the determining the first relative timing relationship comprises:setting a first signal to a high logic level if a rising edge of the data signal falls within phase 90° to 180° of the first phase clock or phase 270° to 360° of the first phase clock; andsetting a second signal to the high logic level if the rising edge of the data signal falls within phase 0° to 90° of the first phase clock or phase 180° to 270° of the first phase clock.3. The method of claim 2 , wherein the setting the first and second signals are performed by a phase detector claim 2 , and the determining the first relative timing relationship further comprises:receiving the data signal and the first phase clock by the phase detector.4. The method of claim 3 , wherein ...

TEMPERATURE COMPENSATED FREQUENCY REFERENCE COMPRISING TWO MEMS OSCILLATORS

A temperature compensated frequency reference comprising first MEMS oscillator (MEMS) used as frequency reference oscillator (REF) for phase locked loop, and means for temperature compensation of phase locked loop output frequency (Fout), wherein the phase locked loop comprises a second MEMS oscillator (MEMS) used as electronically controlled oscillator (VCO) of phase locked loop. 1. A temperature compensated frequency reference comprising a first MEMS oscillator used as frequency reference oscillator for phase locked loop , and means for temperature compensation of phase locked loop output frequency , wherein the phase locked loop comprises a second MEMS oscillator used as electronically controlled oscillator of phase locked loop.2. A temperature compensated frequency reference according to claim 1 , where the temperature compensation means include means for controlling the fractional division ratio of the phase locked loop frequency divider.3. A temperature compensated frequency reference according to claim 1 , wherein the second MEMS resonator in the electronically controlled oscillator is controlled by electrostatic means or by heating means.4. A temperature compensated frequency reference according to claim 1 , wherein the first and second MEMS oscillators are formed in same die.5. A temperature compensated frequency reference according to claim 1 , wherein the output of the second MEMS oscillator is used as an input for a second phase locked loop device inside the first phase locked loop.6. A temperature compensated frequency reference according to claim 1 , wherein the output of the second MEMS resonator is used as an input for at least one second phase locked loop device outside the first phase locked loop.7. A frequency synthesis device comprising a frequency reference according to .8. A frequency synthesis device according to claim 7 , wherein output frequency of electronically controlled oscillator may be controlled in order to tune or modulate the output ...

CLOCK DATA RECOVERY CIRCUIT AND TRANSCEIVER SEMICONDUCTOR INTEGRATED CIRCUIT CONTAINING THE SAME

A clock data recovery circuit which has a high degree of jitter tolerance and can alleviate increase in the phase number of a multi-phase clock, power consumption, and a semiconductor chip area is provided. Each circuit of plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit. The first detection circuit detects that a data edge leads in phase more than −1 phase from an edge detection phase, the second detection circuit detects that the data edge laggs in phase more than +1 phase from the edge detection phase. In response to the first output signal or the second output signal, the edge detection phase is changed by the amount of −1 phase or +1 phase. When the data edge is detected in the range of ±1 phase, a next edge detection phase is maintained in the current state. 1. A clock data recovery circuit comprising:a sampling circuit;an edge detector;a phase selection signal generating circuit; anda clock data generating circuit,wherein the sampling circuit samples a received data signal with the use of multi-phase clock signals, and generates a plurality of sampling signals,wherein the edge detector responds to the sampling signals and the multi-phase clock signals, and generates a plurality of edge detection signals,wherein the phase selection signal generating circuit responds to the edge detection signals and the multi-phase clock signals, and generates a plurality of phase selection signals,wherein the clock data generating circuit responds to the sampling signals, the phase selection signals, and the multi-phase clock signals, and generates a reproduction clock and reproduction data,wherein the edge detector comprises a plurality of edge detection circuits which respond to the sampling signals and the multi-phase clock signals and generate the plural edge detection signals,wherein each of the plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit,wherein ...

Method for Suppression of Spurs from a Free Running Oscillator in Frequency Division Duplex (FDD) and Time Division Duplex (TDD) Wireless Systems

Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.

Leakage Tolerant Delay Locked Loop Circuit Device

Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.

DELAY LOCKED LOOP

A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal. 1. A delay locked loop comprising:a closed loop circuit configured to generate preliminary delay information;a control unit configured to update the preliminary delay information into delay information in response to a control signal; anda first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.2. The delay locked loop of claim 1 , wherein the control signal is activated during a period in which a system claim 1 , comprising the delay locked loop claim 1 , does not use the output clock signal.3. The delay locked loop of claim 2 , wherein the first delay unit is deactivated when the control signal is activated.4. The delay locked loop of claim 1 , wherein the preliminary delay information is periodically generated regardless of the control signal.5. The delay locked loop of claim 4 , wherein when the control signal is activated claim 4 , the preliminary delay information and the delay information have the same value claim 4 , andwhen the control signal is deactivated, the delay information maintains a value which was last updated when the control signal is activated.6. The delay locked loop of claim 1 , wherein the control unit comprises:a transfer section configured to update the preliminary delay information into the delay information in response to the control signal; anda storage section configured to store the delay information updated by the transfer section.7. The delay locked loop of claim 1 , wherein the closed loop circuit comprises:a second delay unit configured to delay the ...

DELAY-LOCKED-LOOP CIRCUIT

A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency. 120.-. (canceled)21. A delay-locked-loop (DLL) circuit , comprising:a first DLL configured to adjust a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a first frequency; anda second DLL configured to adjust the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a second frequency,wherein the second DLL is configured to operate in response to a mode register set signal.22. The DLL circuit as claimed in claim 21 , wherein the first frequency is a low frequency and the second frequency is a high frequency.23. The DLL circuit as claimed in claim 21 , wherein the first DLL is configured to operate in response to the mode register set signal.24. The DLL circuit as claimed in claim 21 , wherein the first DLL stores locking information of the first internal clock signal having a low frequency and the second DLL stores locking information of the second internal clock signal having a high frequency claim 21 , and during a subsequent operation the DLL circuit generates an internal clock signal synchronized with the external clock signal using the locking information of the first internal clock signal and the ...

Method And Apparatus For Eliminating The Effects Of Fequency Offsets In A Digital Communication System

The present invention aims at eliminating the effects of frequency offsets between two transceivers by adjusting frequencies used during transmission. In this invention, methods for correcting the carrier frequency and the sampling frequency during transmission are provided, including both digital and analog implementations of such methods. The receiver determines the relative frequency offset between the transmitter and the receiver, and uses this information to correct this offset when the receiver transmits its data to the original transmitter in the return path, so that the signal received by the original transmitter is in sampling and carrier frequency lock with the original transmitter's local frequency reference. 1. A device in a communication system including a first transceiver unit and a second transceiver unit disposed remotely from the first transceiver unit , the second transceiver unit operable to communicate in a continuous bi-directional manner for direct exchange of information with the first transceiver unit , the device comprising:means for detecting a sampling frequency offset between a first sampling frequency used by the first transceiver unit to transmit a first signal, and a second sampling frequency used by the second transceiver unit to receive the first signal, by continuously comparing signals received by the second transceiver unit with signals detected by the second transceiver unit; andmeans for adjusting sampling points of data to be transmitted by the second transceiver unit in response to the detected sampling frequency offset, whereby an error associated with the sampling frequency offset is reduced.2. A device according to claim 1 , wherein the means for detecting the sampling frequency offset includes means for performing a variable delay on a digital representation of the first signal so as to lock onto the sampling frequency offset.3. A device according to claim 1 , wherein the means for adjusting the sampling points includes ...

CLOCK GENERATOR, SEMICONDUCTOR DEVICE, AND CLOCK GENERATING METHOD

There is provided a clock generator for generating a modulation waveform which is high in the effect of suppressing a spectrum and making a circuit scale smaller than a modulation system using the Hershey-kiss waveform. More specifically, a modulation waveform generation unit generates a tangent waveform or a tangent+triangular waveform as an SSCG modulation waveform and provides an oscillator with a signal in which the SSCG modulation waveform is combined with the output of a low pass filter of a PLL loop. 1. A clock generator comprising:an oscillator variably controlling the frequency of an oscillation clock thereof; anda modulation waveform generation unit generating a modulation waveform for modulating the frequency of oscillation clock of the oscillator,the clock generator outputting a frequency-modulated clock signal from the oscillator based on the modulation waveform,wherein the modulation waveform is configured such that the amount of change in frequency per unit time is larger in the area before and after the upper limit of a frequency modulation range and the area before and after the lower limit of a frequency modulation range than in the other area.2. The clock generator according to claim 1 , further comprising:a detector comparing phase or phase and frequency between a reference clock to be input and the oscillation clock from the oscillator or the clock in which the oscillation clock is divided;a charge pump generating a signal with a level corresponding to a comparison result of the detector;a first filter smoothing the output of the charge pump; anda circuit supplying a signal in which the output signal of the first filter is combined with the modulation waveform of the modulation waveform generation unit as a control signal for varying a frequency.3. The clock generator according to claim 1 ,wherein the modulation waveform generation unit comprises:a storage unit storing a signal obtained by delta-sigma modulating a tangent waveform or a waveform ...

System and method for an accuracy-enhanced dll during a measure initialization mode

A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.

CLOCK GENERATOR

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal. 1. A clock generator , for generating an output clock signal , the clock generator comprising:a first clock signal input, for receiving a first input clock signal;a first frequency comparator, for generating a first frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the first input clock signal;a first subtractor, for forming a first error signal representing a difference between an input desired frequency ratio and the first frequency comparison signal;a first digital filter, for receiving the first error signal and forming a filtered first error signal;a second clock signal input, for receiving a second input clock signal;a second frequency comparator, for generating a second frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the second input clock signal;a second subtractor, for forming a second error signal representing a difference between the filtered first error signal and the second frequency comparison signal;a second digital filter, for ...

CLOCK AND DATA RECOVERY CIRCUIT

The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal. 1. A clock and data recovery (CDR) circuit , comprising:a phase locked loop (PLL) circuit, providing a reference voltage;a first delay device, delaying an input data according to a control signal so as to generate a first delay signal;an edge detector, generating an edge signal according to the first delay signal and the input data;a second delay device, delaying the edge signal so as to generate a second delay signal;a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage;a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; andan amplifier, amplifying the phase signal by a factor so as to generate the control signal.2. The clock and data recovery circuit as claimed in claim 1 , wherein the PLL circuit comprises:a phase frequency detector, generating a phase frequency signal according to a reference clock and a divided clock;a charge pump, generating a current signal according to the phase frequency signal;a low pass filter, ...

PLL CIRCUIT, CALIBRATION METHOD AND WIRELESS COMMUNICATION TERMINAL

An ILFD controller sets a control parameter on the basis of a frequency of a frequency-divided signal and a frequency of a reference signal measured by a clock counter. A VCO controller selects an oscillation band that defines an oscillation frequency of a VCO and also selects an oscillation band of the VCO on the basis of the frequency of the reference signal and a frequency of a frequency-divided signal that is a result obtained by frequency-dividing an output signal, which is delivered from the VCO in response to the selected oscillation band, by means of an ILFD and a frequency divider. 1. A PLL circuit comprising:a voltage controlled oscillator configured to output a high frequency signal;an injection locked frequency divider configured to frequency-divide the output high frequency signal;a frequency divider configured to frequency-divide the frequency-divided signal into a frequency of a reference signal;a phase frequency detector configured to compare the frequency-divided signal from the frequency divider with the reference signal and configured to output a phase difference and a frequency difference;a charge pump configured to convert the output phase difference and the frequency difference into an electric current;a loop filter configured to generate a control voltage for the voltage controlled oscillator in accordance with the thus-converted electric current and configured to apply the generated control voltage to the voltage controlled oscillator; anda calibration circuit configured to control an oscillation band which determines an oscillation frequency of the voltage controlled oscillator and configured to control a control parameter for activating the injection locked frequency divider in a determined operating range, whereinthe calibration circuit is configured to adjust the oscillation band of the voltage controlled oscillator in accordance with a frequency-divided signal of the adjusted injection locked frequency divider after adjustment of the ...

HIGH FREQUENCY QUADRATURE PLL CIRCUIT AND METHOD

A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit. 1. A method , comprising:phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of the PLL circuit; andtuning a phase of the output signal of the PLL circuit by adjusting the injection current based on an output of a phase detector circuit, wherein the adjusting the injection current comprises adjusting at least one of: a magnitude of the injection current and a pulse width of the injection current.2. The method of claim 1 , wherein the adjusting the injection current comprises adjusting the magnitude of the injection current.3. The method of claim 1 , wherein the adjusting the injection current comprises adjusting the pulse width of the injection current.4. The method of claim 1 , wherein the adjusting the injection current comprises adjusting both the magnitude of the injection current and the pulse width of the injection current.5. The method of claim 1 , wherein the PLL circuit comprises: a phase detector claim 1 , the charge pump claim 1 , a loop filter claim 1 , a voltage control oscillator claim 1 , and a frequency divider.6. The method of claim 5 , wherein the phase detector circuit is separate from the phase detector included in the PLL circuit.7. The method of claim 1 , wherein the phase detector circuit is separate from the PLL circuit.8. The method of claim 1 , wherein ...

DIGITAL PHASE LOCKED LOOP DEVICE AND METHOD IN WIRELESS COMMUNICATION SYSTEM

A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval. 1. An apparatus of a digital Phase Locked Loop (PLL) in a wireless communication system , the apparatus comprising:a Digitally Controlled Oscillator (DCO) configured to generate a frequency signal based on an input Digital Tuning Word (DTW);a divider configured to divide the frequency signal at an integer ratio;a Phase Frequency Detector (PFD) configured to generate a signal representing a phase difference between a divided frequency signal and a reference signal;a Time to Digital Converter (TDC) configured to measure a time interval of the phase difference using the signal representing the phase difference;a delay comparator configured to calculate a time interval when rising edges coincide from values measured by the TDC; anda level scaler configured to generate a DTW that operates the DCO using a digital code representing the time interval.2. The apparatus of claim 1 , wherein the TDC is configured to measure the time interval step by step.3. The apparatus of claim 1 , wherein the TDC comprises:a first TDC comprising a plurality of delay cells configured to delay by a time ‘a’ and measure the time interval on the ...

WIRELESS APPARATUS

A wireless apparatus includes a clock generation PLL circuit of a digital baseband section. A variable output regulator receives as an input a VCO control voltage for controlling an oscillation frequency of a VCO in the PLL circuit, varies an output voltage in accordance with the VCO control voltage, and supplies, as a supply voltage, the output voltage to a power terminal of a high frequency circuit, such as an amplifier. The VCO control voltage changes in accordance with temperature or process variations, and the supply voltage of the high frequency circuit is controlled in accordance with the VCO control voltage. For this reason, performance deterioration ascribable to the temperature or process variations can be compensated for. 1. A wireless apparatus comprising:a PLL circuit that has a voltage controlled oscillator configured to oscillate a signal having a frequency commensurate with a control voltage;a variable output regulator configured to change an output voltage in accordance with the control voltage; anda high frequency circuit that is supplied with, as a supply voltage, the output voltage of the variable output regulator.2. The wireless apparatus according to claim 1 , wherein the PLL circuit and the high frequency circuit are fabricated on a same integrated circuit.3. The wireless apparatus according to claim 2 , wherein the high frequency circuit includes at least any one of an amplifier configured to amplify a high frequency signal claim 2 , a high frequency circuit section of a modulator claim 2 , and a high frequency circuit section of a demodulator. The invention relates to a wireless apparatus having a digital baseband section and a high frequency circuit.In a wireless apparatus, in particular, an amplifier for amplifying a high frequency signal undergoes great performance variation for reasons of variations in semiconductor manufacturing processes or temperature variations that occur during actual operation. For instance, if a decrease in an ...

Delay-locked loop with phase adjustment

A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.

Oscillator with highly-adjustable bang-bang control

A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

High-Speed Serial Data Transceiver and Related Methods

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

METHOD FOR ENCODER FREQUENCY-SHIFT COMPENSATION

A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals. 1. A method for encoder frequency-shift compensation , comprising:determining frequency values of an input encoder signal;determining repeatable frequency-shifts of the frequency values; andgenerating a frequency-shift compensated clock using the repeatable frequency-shifts.2. The method of claim 1 , further comprising recording the frequency-shifts in an encoder index claim 1 , said encoder index providing encoder clock signals.3. The method of claim 1 , wherein the frequency values are converted to clock signals and processed in a counter chip.4. The method of claim 1 , wherein determining repeatable frequency-shifts of the frequency values comprises using a phase locked loop.5. The method of claim 1 , wherein determining repeatable frequency-shifts of the frequency values comprises calculating the differences in an encoder index encoder clock frequency phase and the values learned in a phase locked loop.6. The method of claim 1 , wherein generating a frequency-shift compensated clock comprises using a synthesizer to analyze values determined in the phase locked loop and of each encoder clock signal received from an encoder index.7. The method of claim 2 , further comprising using a voltage controlled oscillator to analyze phase differences between an encoder index clock signal and the input encoder signal.8. The method of claim 1 , further comprising using a feedforward filter to output direct and delayed signal processing elements and using a feedforward gain adjust to increase the power or amplitude of the ...

Method for locking a delay locked loop

A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector receives a first rise edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the rise edge has passed through the delay line, and in response, sends the injector a second trigger to send a next single fall edge of the clock input signal to the delay line. A charge pump determines a timing difference between the delay edge signal and a reference edge signal sent from the injector. The charge pump sends the control signal to the delay line to adjust the delay setting of the delay line based on the timing difference.

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes a first chip including a first port configured to receive an operation clock signal, a first circuit configured to operate in synchronization with the operation clock signal, and a second chip mounted on the first chip. The second chip includes a delay control part configured to generate a delay control signal indicating a delay amount based on a cycle of a reference clock signal, plural delay circuits connected in multiple stages and configured to delay clock signals input to the plural delay control circuits based on the delay control signal and sequentially output the delayed clock signals to a subsequent stage, and a second port connected to the first port and configured to receive the operation clock signal based on the delayed clock signals output from the plural delay circuits. 1. A semiconductor apparatus comprising: a first port configured to receive an operation clock signal, and', 'a first circuit configured to operate in synchronization with the operation clock signal; and, 'a first chip including'}a second chip mounted on the first chip; a delay control part configured to generate a delay control signal indicating a delay amount based on a cycle of a reference clock signal,', 'a plurality of delay circuits connected in multiple stages and configured to delay clock signals input to the plural delay control circuits based on the delay control signal and sequentially output the delayed clock signals to a subsequent stage, and', 'a second port connected to the first port and configured to receive the operation clock signal based on the delayed clock signals output from the plural delay circuits., 'wherein the second chip includes'}2. The semiconductor apparatus as claimed in claim 1 , wherein the second port is connected to the first port by way of a through-electrode penetrating the second chip.3. The semiconductor apparatus as claimed in claim 1 ,wherein the first port is formed on a surface of the first chip facing the ...

SYNCHRONIZATION METHOD FOR CURRENT DIFFERENTIAL PROTECTION

A synchronization method for current differential protection comprises: selecting a point on the transmission line protected by the current differential protection; measuring the current and the voltage of each of the terminals of said transmission line; calculating the compensating voltage at the selected point respectively according to the measured current and the voltage of the each terminal; detecting and calculating the synchronization error by comparing all the compensating voltages. 1. A synchronization method for current differential protection , the method comprising:selecting a point on a transmission line protected by a current differential protection;measuring a current and a voltage of each of multiple terminals of said transmission line;calculating a compensating voltage at a selected point respectively according to the measured current and the voltage of each of the multiple terminals;detecting and calculating a synchronization error by comparing all the compensating voltages.2. The method according to claim 1 , wherein said current and voltage of each of the multiple terminals are measured before a fault or after a fault.3. The method according to claim 1 , wherein said current and voltage of each of the multiple terminals are vectors or sampling values.4. The method according to claim 1 , wherein the current and the voltage of each of the multiple terminals are phase quantities or sequence quantities.5. The method according to claim 1 , wherein said point is selected from one of any points of transmission line or a T connected point of the multi-terminal transmission lines.6. The method according to claim 5 , wherein for a two-terminal transmission line claim 5 , said point is selected from any points of transmission line claim 5 , preferably from the middle or the end of the transmission line;for a three-terminal transmission line, said point is selected from one of the T connected point or an end of the transmission line;for a transmission line ...

CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP

A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop. 1. A phase locked loop (PLL) device comprising:a phase detector;an analog loop filter comprising a plurality of filter elements;a voltage controlled oscillator (VCO);a time to digital converter (TDC);a digital loop filter;a digital to analog converter (DAC); anda switching mechanism responsive to a first control signal value to configure the PLL device into an analog loop comprising the phase detector, analog loop filter, and VCO and responsive to a second control signal value to configure the PLL device into a hybrid digital-analog loop comprising the phase detector, TDC, DAC, and VCO and further configured to connect the plurality of filter elements to form an integrator between the DAC and the VCO.2. The PLL device of claim 1 , wherein the DAC comprises a current source output stage connected to the integrator when the PLL device is configured in the hybrid digital-analog loop.3. The PLL device of claim 1 , wherein the switching element is configured to connect the plurality of filter elements to form the analog loop filter when the PLL device is configured in the analog loop.4. The PLL device of claim 3 , wherein the switching element is configured to connect the plurality of filter elements to form the analog loop filter having a response comprising a first pole at an origin claim 3 , a zero at a first frequency and a second pole a second frequency greater than the first frequency.5. The PLL device of claim 3 , further comprising a charge pump connected ...

Method and Device for Clock Recovery

A method and a device for processing a signal determine a timing phase over an observation interval of an input signal. A frequency estimation is determined based on the timing phase. A phase correction is determined for the observation interval based on the timing phase and the frequency offset. Then the phase correction is used to adjust the timing of the input signal. Also, a communication system with at least one such device is described. 121-. (canceled)22. A method of processing a signal , the method comprising:determining a timing phase over an observation interval of an input signal;determining a frequency estimation based on the timing phase;determining a phase correction for the observation interval based on the timing phase and the frequency estimation; andadjusting a timing of the input signal by using the phase correction.23. The method according to claim 22 , wherein the step of adjusting the timing of the input signal comprises utilizing the phase correction to adjust at least one interpolator in a path of the input signal.24. The method according to claim 22 , wherein the step of determining the timing phase comprises averaging the timing phase over the entire observation interval comprising N blocks of parallel samples.25. The method according to claim 22 , which comprises compensating a frequency offset in the input signal by incrementing a phase accumulator with each clock cycle by the frequency estimation.26. The method according to claim 25 , wherein the step of determining the phase correction comprises comparing the phase accumulator with a predetermined threshold.28. The method according to claim 22 , which comprises calculating the frequency estimate by way of a second order PLL wherein the timing phase is processed at the rate of the observation interval.29. The method according to claim 22 , which comprises generating a decimation signal in case an irregular order of samples is determined.30. The method according to claim 22 , which ...

PLL CIRCUIT

A PLL circuit, for extracting phase error information from a demodulated signal in which a variance of a phase or an amplitude changes depending on a signal-to-noise power ratio, and providing negative feedback control, to thereby suppress a phase error of the demodulated signal, includes: a phase error detector for producing a phase error signal corresponding to a value of the phase error as the phase error information; a limiter circuit for limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and a loop filter for producing a control signal based on the limited phase error signal to determine frequency characteristics. 15.-. (canceled)6. A clock synchronization circuit to be used in a 2-QAM demodulator , where n is an integer of 4 or more , the clock synchronization circuit comprising:a voltage-controlled oscillator producing a sampling clock signal in accordance with a control signal;an A/D converter converting an analog baseband signal, which has been converted into a baseband by a quadrature demodulator, into a digital signal in synchronization with the sampling clock signal;a phase error detector extracting, from the digital signal, a phase error corresponding to an optimum sampling phase of the analog baseband signal and the sampling clock signal to produce a phase error signal corresponding to a value of the phase error;a limiter circuit limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; anda loop filter producing, based on the limited phase error signal, the control signal so that the phase of the sampling clock signal matches with the optimum phase, to thereby determine frequency characteristics of a loop.7. A demodulator of a multilevel quadrature amplitude modulation scheme claim 6 , which uses the clock synchronization circuit according to .8. A method for clock synchronization of a demodulator claim 6 , ...

Loop filter for current-controlled-oscillator-based phase locked loop

A loop filter of a phase-locked loop (PLL) that uses a current-controlled oscillator (CCO) includes a capacitor, a voltage-to-current (V-to-I) converter, and a charge pump. The input node of the loop filter receives a first current from an external charge pump. The combination of the capacitor and the V-to-I converter generates a first component of the output current of the loop filter based on the first current. The charge pump of the loop filter generates a second component of the output current. The loop filter is implemented without the need for a zero-frequency-determining resistor, the resistor instead being realized by the product of the first current, the second component of the output current and the transconductance of the V-to-I converter. Phase noise reduction in the PLL, as well as implementation of the loop filter with a smaller area, are thus made possible.

Dual mode clock/data recovery circuit

A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

PHASE FREQUENCY DETECTOR AND CHARGE PUMP FOR PHASE LOCK LOOP FAST-LOCKING

The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques. 1. A phase frequency detector comprising:at least one first flip-flop for providing an up signal responsive to a first clock signal;a first delay element coupled to the at least one first flip-flop, wherein the at least one first flip-flop and the first delay element provides a plurality of delayed up pulses;at least one second flip-flop for providing a down signal responsive to a second clock signal;a second delay element coupled to the at least one second flip-flop; wherein the at least one second flip-flop and the second delay element provide a plurality of delayed down pulses;a first gate for receiving the plurality of delayed up pulses; anda second gate for receiving the plurality of delayed down pulses;wherein the delayed up and down pulses are outputted to other circuitry to provide increased gain.2. The phase frequency detector of claim 1 , wherein the at least one first flip-flop and the at least one second flip-flop comprise first and second flip-flops claim 1 , wherein the first delay element is coupled to an output of the first flip-flop and the second delay element is coupled to an output of the second flip-flop.3. The phase frequency detector of claim 1 , wherein the first clock comprises a divider clock signal claim 1 , the second clock comprises a reference clock signal claim 1 , and the other circuitry comprises at least one charge pump.4. The phase frequency detector of claim 1 , wherein the first and second delay elements comprise first and second delay chains.5. The phase frequency detector of claim 1 , wherein the first and second delay elements comprise first and ...

Variable unit delay circuit and clock generation circuit for semiconductor apparatus using the same

A clock generation circuit includes, inter alia, a first phase detection block comparing initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and outputting an initial phase difference detection signal corresponding to a comparison result; a second phase detection block comparing phases of the reference clock signal and the output clock signal, and outputting a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and delaying the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and outputting the output clock signal; and a delay control block generating the control voltage which has the voltage level corresponding to the phase detection signal.

Phase-Locked Loop Control Voltage Determination

A method and circuit is provided for determining a control voltage of a voltage controlled oscillator with fast frequency lock of a phase-locked loop and which is advantageous to the situation when an ultra-low frequency reference is used. The method and circuit determines a current error between a reference clock signal and a feedback clock signal, and checks if the error is larger than the threshold value which checks if an error sign indicator is set, i.e. the error has switched sign since startup of feedback loop; if the error sign indicator is not set, the circuit determines a divisor, k, using the current error, e, current control voltage, u, previous error e, and previous control voltage, u; however, if the error sign indicator is set the circuit determines a divisor, k, using stored values for the latest control voltage and error when the error was negative and stored values for the latest control voltage and error when the error was positive; furthermore, the method and circuit determines a control voltage step using the determined error divided by the divisor, k, and determines a new control voltage using the current control voltage, u, and the determined control voltage step.

FREQUENCY SYNTHESIZER

A phase difference detecting circuit includes a sync detecting circuit for detecting establishment of phase sync from phase difference signals D and U generated by a D-type flip-flop and a switch for supplying, unless the sync detecting circuit detects the establishment of the phase sync, the control voltage Vgenerated by the current-output-matching loop filter to a voltage-controlled oscillator and for supplying, when the sync detecting circuit detects the establishment of the phase sync, the control voltage Vgenerated by the voltage-output-matching loop filter to the voltage-controlled oscillator 1. A frequency synthesizer including a reference signal source for generating a reference signal , a sync signal output circuit for dividing a high-frequency signal and for outputting a high-frequency signal after division as a sync signal , a phase difference detecting circuit for detecting phase difference between the reference signal generated by the reference signal source and the sync signal output from the sync signal output circuit and for outputting control voltage corresponding to the phase difference , and a voltage-controlled oscillator for generating a high-frequency signal with a frequency corresponding to the control voltage output from the phase difference detecting circuit and for outputting the high-frequency signal to the sync signal output circuit and to an outside , wherein the phase difference detecting circuit comprises:a first phase comparator for generating a phase difference signal from detection timing of a signal edge of the reference signal and a signal edge of the sync signal;a first control voltage generating circuit for generating the control voltage corresponding to the phase difference signal generated by the first phase comparator;a first flip-flop for inverting amplitude of its output signal every time it detects a signal edge of the sync signal;an inverter for inverting amplitude of the reference signal;a second flip-flop for inverting ...

System and method for determining a time for safely sampling a signal of a clock domain

A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Automatic detection and compensation of frequency offset in point-to-point communication

Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency.

Digital PLL Circuit and Clock Generator

A circuit according to the present invention includes: an oscillator; an divider; a time-to-digital converter comparing the phase and frequency of a reference clock signal REF from the divider with an internal clock signal and outputting digital data D based on the comparison results; a digital loop filter receiving the D and outputting digital data W a data holder holding the W from the filter in time series manner; a switch selecting either digital data W from the holder or the W and outputting the selected data as digital data W a digitally controlled oscillator with oscillation frequency controlled based on the W and a data controller switching input data of the switch, and starting/halting the operation of the oscillator, the divider, the converter and the filter. Current consumption by the digital PLL circuit can be reduced. 1. A digital PLL circuit comprising:a time to digital converter for comparing a reference clock signal with an internal clock signal and outputting a first digital data based on obtained comparison results;a digital loop filter for receiving the first digital data and outputting second digital data;a digitally controlled oscillator, an oscillation frequency of which is controlled based on the second digital data;a data holder for holding the second digital data in a time series manner; anda data controller for controlling switching in order to selectively transmit either the second digital data held in the data holder in accordance with the time series or the second digital data from the digital loop filter to the digitally controlled oscillator.2. The digital PLL circuit according to claim 1 , wherein claim 1 , when the data controller selects the second digital data held by the data holder in the time series manner for transmission to the digitally controlled oscillator claim 1 , the data controller halts at least either the time to digital converter or the digital loop filter.3. The digital PLL circuit according to claim 1 , wherein ...

Transmission/reception device and information processing device

A transmission/reception device includes a transmission circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals to be sent to another device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew; and a reception circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals sent from another transmission/reception device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew.

Phase locked loop with digital compensation for analog integration

A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Capacitor leakage compensation for pll loop filter capacitor

An output portion of a charge pump receives control signals from a phase frequency detector and in response outputs positive current pulses and negative current pulses to a loop filter. A current control portion of the charge pump controls the output portion such that the magnitudes of the positive and negative current pulses are the same. Within the current control portion there is a “Charge Pump Output Voltage Replica Node” (CPOVRN). The voltage on this CPOVRN is maintained to be the same as a voltage on the charge pump output node. A capacitor leakage compensation circuit indirectly senses the voltage across a leaking capacitor of the loop filter by sensing the voltage on the CPOVRN. The compensation circuit imposes the sensed voltage across a replica capacitor, mirrors a current leaking through the replica, and supplies the mirrored current in the form of a compensation current to the leaking capacitor.

SEMICONDUCTOR DEVICE GENERATING PHASE-CONTROLLED CLOCK SIGNAL

The semiconductor device includes a frequency detection circuit that outputs a frequency detection signal based on a frequency of a first clock signal; a phase comparison circuit that compares a phase of the first clock signal with a phase of a reference clock signal and outputs a phase comparison signal according to a result of the comparison; and a phase adjustment circuit that outputs a second clock signal by shifting the phase of the first clock signal according to the phase comparison signal. An amount of the phase of the first clock signal according to the phase comparison signal is variable according to the frequency detection signal. 1. A semiconductor device comprising:a frequency detection circuit outputting a frequency detection signal based on a frequency of a first clock signal;a phase comparison circuit comparing a phase of the first clock signal with a phase of a reference clock signal to generate a phase comparison signal; anda phase adjustment circuit outputting a second clock signal by shifting the phase of the first clock signal based on the phase comparison signal, an amount of shifting the phase of the first clock signal being variable according to the frequency detection signal.2. The semiconductor device as claimed in claim 1 , wherein the frequency detection circuit includes a first circuit that counts one of the first and second clock signals for a predetermined period claim 1 , and outputs the frequency detection signal based on a count value thereof.3. The semiconductor device as claimed in claim 2 , wherein the frequency detection circuit further includes a second circuit that defines the predetermined period claim 2 , the second circuit being activated at a time of an initial operation of the semiconductor device.4. The semiconductor device as claimed in claim 3 , wherein the second circuit includes a trimming circuit that adjusts the predetermined period.5. The semiconductor device as claimed in claim 1 , whereinthe phase adjustment ...

DIGITAL NRZI SIGNAL FOR SERIAL INTERCONNECT COMMUNICATIONS BETWEEN THE LINK LAYER AND PHYSICAL LAYER

Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal. 1. A method comprising:determining an initial state of a data signal received in a serial interconnect interface;detecting a state change in the received data signal;determining whether the detected state change in the data signal corresponds to an end of packet (EOP) condition;generating a pulse of a length dependent upon the determination of the EOP condition;aligning the generated pulse with the state change of the data signal; andtransmitting the pulse from a physical layer of the USB interface to a link layer of the USB interface.2. The method of claim 1 , wherein determining whether the detected state change corresponds to an EOP condition includes identifying whether the state change has a single ended zero signature.3. The method of claim 2 , wherein the single ended zero signature includes both data lines of a differential ended serial bus being driven low for two bit times relative to the speed of transmission claim 2 , followed by a state change for one bit time.4. The method of claim 1 , wherein the generated pulse length is short if the EOP condition is not detected.5. The method of claim 1 , wherein the generated pulse length is long if the EOP condition is detected.6. The method of claim 1 , wherein the received data signal includes a non return to zero invert (NRZI) encoded signal.7. An apparatus comprising:a converter to generate a pulse in response to an end of packet ( ...

PHASE LOCKED LOOP AND PHASE COMPARISON METHOD

In a phase locked loop, a first frequency divider divides the frequency of an input signal. A low-pass filter receives a frequency-divided signal output from the first frequency divider and having an average phase difference calculated by a calculation unit, cuts off high-frequency components of the received signal, and outputs a resultant signal. A voltage controlled oscillator varies the frequency of a signal to be output based on the signal output from the low-pass filter. A second frequency divider divides the frequency of the signal output from the voltage controlled oscillator. The calculation unit calculates a phase difference between signals individually output from the first frequency divider and the second frequency divider for each phase in one cycle of the signal output from the first frequency divider, and calculates an average phase difference based on the calculated phase differences. 1. A phase locked loop for generating an output signal whose wavenumber matches a wavenumber of a signal with gaps , input thereto , the phase locked loop comprising:a first frequency divider configured to divide a frequency of the input signal;a second frequency divider configured to divide a frequency of the output signal; anda calculation unit configured to calculate a phase difference between a signal output from the first frequency divider and a signal output from the second frequency divider in one cycle of the output signal of the first frequency divider, and then calculate an average phase difference based on calculated phase differences.2. The phase locked loop according to claim 1 , whereinthe calculation unit subtracts the average phase difference from a phase difference in a certain phase.3. The phase locked loop according to claim 1 , wherein a count accumulation unit configured to divide the input signal into equally-spaced wavenumber intervals and calculate a first cumulative count value by accumulating count values of a counter, captured at interval ...

Pll circuit, method of controlling pll circuit, and digital circuit

A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.

I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL

An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. 1. An apparatus comprising:a phase mixer configured to receive an enable signal and a delayed signal to provide an adjustment signal having a delay relative to the enable signal responsive, at least in part, to mixing the enable signal and the first delayed signal,wherein the delayed signal is based, at least in part, on the enable signal.2. The apparatus of claim 1 , further comprising:a timing adjustment circuit coupled to the phase mixer and configured to receive the adjustment signal, the timing adjustment circuit further configured to delay the adjustment signal.3. The apparatus of claim 1 , wherein the apparatus is included in a delay model.4. The apparatus of claim 1 , wherein the phase mixer is a first phase mixer claim 1 , the apparatus further comprising:a second phase mixer coupled to the first phase mixer and configured to receive the enable signal, the second phase mixer further configured to provide the delayed signal based, at least in part, on the enable signal.5. The apparatus of claim 1 , wherein the enable signal comprises an on-die termination signal.6. The apparatus of claim 1 , wherein the phase mixer comprises a plurality of stages claim 1 , each of the plurality of stages configured to receive the enable signal and the delayed signal and selectively provide either the enable signal or the delayed signal based claim 1 , at least in part ...

SEMICONDUCTOR INTEGRATED CIRCUIT

An SSCG generating a center-spread modulated clock centering on a frequency obtained by multiplying an input reference clock frequency by a predetermined number is configured to include a phase comparator, a VCO, and a modulation circuit formed by a frequency divider and a division ratio modulation circuit. The division ratio modulation circuit supplies the frequency divider with a division ratio modulated above and below the predetermined multiplication number, and outputs a magnitude relationship involved as a spread direction identification signal. The diagnostic circuit includes a counter that counts the modulated clock and, based on the spread direction identification signal, performs counting operations during an up-spread or down-spread period. Based on the values counted for a predetermined period, the operating status of the SSCG is diagnosed for the presence or absence of a failure, for example. 1. A semiconductor integrated circuit comprising a clock generator receiving input of a reference clock so as to generate a modulated clock based on the input reference clock , and a diagnostic circuit;wherein said clock generator includes:a phase comparator comparing the phase of said reference clock with that of a feedback clock;an oscillator receiving input of said modulated clock of which the oscillating frequency is controlled based on output from said phase comparator, anda modulation circuit receiving input of said modulated clock so as to output said feedback clock;wherein said modulation circuit includes a frequency divider, and a division ratio modulation circuit supplying a division ratio to said frequency divider;wherein said frequency divider outputs said feedback clock by dividing the output of said oscillator by said division ratio;wherein said division ratio modulation circuit is fed with a multiplication count and has at least one of two periods, one of the two periods being one in which said division ratio modulation circuit outputs a value larger ...

Low jitter clock recovery circuit

A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.

LOOP FILTER

A delay lock loop includes a phase frequency detector, a loop filter, and a voltage controlled delay circuit. The phase frequency detector is used for outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock. The loop filter includes a first capacitor, a second capacitor, and a first switch. The first capacitor is charged or discharged and the first switch is turned off during a phase tracking period. The first capacitor and the second capacitor are charged or discharged and the first switch is turned on during a phase locking period. The voltage controlled delay circuit is used for outputting the feedback clock according to the reference clock and a control voltage outputted by the loop filter. 1. A loop filter , comprising:a first input terminal for receiving an upper switch signal;a second input terminal for receiving a lower switch signal;an output terminal for outputting a control voltage;a first capacitor having a first terminal coupled to the output terminal of the loop filter, and a second terminal coupled to ground;a second capacitor having a first terminal, and a second terminal coupled to the ground; anda first switch coupled between the first terminal of the first capacitor and the first terminal of the second capacitor;wherein the first capacitor is charged/discharged and the first switch is turned off in phase tracking, and the first switch is turned on in phase locking.2. The loop filter of claim 1 , further comprising:an upper circuit having a first terminal for receiving a first voltage, a second terminal coupled to the output terminal of the loop filter, and a third terminal coupled to the first input terminal of the loop filter for receiving the upper switch signal;a lower circuit having a first terminal coupled to the output terminal of the loop filter, a second terminal coupled to the ground, and a third terminal coupled to the second input terminal of the loop filter for receiving the lower ...

Frequency Synthesizer

The present invention discloses a frequency synthesizer. The frequency synthesizer includes a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal; a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal; a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; and a frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter. 1. A frequency synthesizer , comprising:a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal;a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal;a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; anda frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter.2. The frequency synthesizer of claim 1 , wherein the phase-locked loop comprises:a phase frequency detector, for receiving the delay reference signal and the feedback frequency dividing signal, and accordingly generating a phase error signal;a charge pump, for generating a control voltage signal according to the phase error signal;a loop filter, for filtering the control voltage signal, so as to generate a filtering signal; anda voltage-controlled oscillator, for generating the output signal according to the filtering signal.3. The frequency synthesizer of claim 1 , wherein the delay parameter is a delay phase and the frequency dividing parameter is a frequency dividing ratio.4. The frequency synthesizer of claim 1 , wherein the control unit generates the delay parameter and ...

Phase-locked loop calibration system and method

In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.

Digital phase locked loop circuitry and methods

Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

PLL CIRCUIT

A PLL circuit includes a low-pass filter configured to generate a control voltage according to an output current from a charge pump. The low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion. Also, the preceding stage circuit portion includes plural charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump and configured to be driven by a first switch control signal, and a second switch connected between the capacitor and the succeeding stage circuit portion and configured to be driven by a second switch control signal. 1. A PLL circuit comprising:a voltage controlled oscillator configured to output a signal of frequency according to a control voltage;a frequency divider configured to perform frequency division on the output signal from the voltage controlled oscillator;a phase frequency detector configured to compare phases of an input clock and an output signal from the frequency divider;a charge pump configured to output a current according to an output signal from the phase frequency detector; anda low-pass filter configured to generate the control voltage according to the output current from the charge pump,wherein the low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion, andthe preceding stage circuit portion includes a plurality of charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump ...

WIDE FREQUENCY RANGE DELAY LOCKED LOOP

A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power. 1. A memory device comprising:a delay locked loop; andan input for receiving an external clock signal for routing to the delay locked loop, a digital delay circuit configured to enable digital delay elements of the digital delay circuit in providing coarse phase adjustment in the delay locked loop, the digital delay circuit providing a coarse delayed differential clock signal;', 'an analog delay circuit configured to provide fine phase adjustment in the delay locked loop in response to a control signal, the analog delay circuit receiving the coarse delayed differential clock signal and producing a fine delayed clock signal, the analog delay circuit comprising parallel symmetric loads to cause the fine delay, the control signal being operative to vary an effective resistance of the symmetric loads;', 'circuitry to provide the fine delayed clock signal as the internal clock signal;', 'a phase detector circuit configured to compare the external clock signal and the internal clock signal; and', 'a lock detector circuit in communication with the phase detector circuit and the analog delay circuit, the lock detector circuit being configured to: i) hold the digital delay circuit at a fixed delay; and ii) provide the control signal to the analog delay circuit., 'the delay locked loop being configured to synchronize an internal clock signal with the external clock signal, the delay locked loop comprising2. The memory device of claim 1 , further comprising circuitry for providing the fine delayed clock ...

Self-biased oscillator

Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first differentiator having an output node and an input node; and a second differentiator with adjustable resistance or capacitance, the second differentiator having an input node coupled to the output node of the first differentiator, and having an output node coupled to the input node of the first differentiator.

PHASE-FREQUENCY DETECTION METHOD

The present invention relates to a method and device for phase-frequency detection in a phase-lock loop circuit. The method comprises receiving compare edge of a reference clock signal and compare edge of a feedback clock signal, maintaining a phase/frequency detector, PFD, state machine with three PFD states, UP, DOWN, and IDLE, based on the received compare edges of the reference and feedback clock signals, recording current and previous time the state machine stays in UP or DOWN states, generating an UP or DOWN signal based on transition of PFD states and the comparison between recorded current time and recorded previous time; and outputting a digital control signal to a feedback frequency control device based on the UP or DOWN signal. A device and system is arranged to execute the method according to the present invention. 1. A method for detecting phase/frequency error in a digital phase-locked loop (PLL) comprising:receiving compare edge of a reference clock signal and compare edge of a feedback clock signal;maintaining a phase/frequency detector, (PFD) state machine with three PFD states, UP, DOWN, and IDLE, based on the received compare edges of the reference and feedback clock signals;recording current and previous time the PFD state machine stays in UP or DOWN states;generating an UP or DOWN signal based on transition of PFD states and a comparison between recorded current time and recorded previous time; andoutputting a digital control signal to a feedback frequency control device based on the UP or DOWN signal.2. The method according to claim 1 , wherein recording current and previous time the PFD state machine stays in UP or DOWN states is performed by using a current UP time counter claim 1 , a previous UP time counter claim 1 , a current DOWN time counter claim 1 , and a previous DOWN time counter.3. The method according to claim 2 , wherein generating an UP or DOWN signal based on the recorded current and previous time comprises:generating an UP ...

TIMING MONITOR FOR PLL

Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device. 1. An apparatus , comprising:an identification block arranged to receive at least two signals and to output an identity signal indicating that one of the at least two signals is logically true and another of the at least two signals is logically false;a counter block arranged to count a quantity of successive identity signals referencing the one of the at least two signals; anda comparison block arranged to output an alert signal based on a comparison of a count of the counter block to a preselected threshold value.2. The apparatus of claim 1 , wherein the counter block is arranged to output an up count or a down count based on a relative temporal position of the at least two signals.3. The apparatus of claim 2 , wherein the counter block is arranged to output an up count when the one of the at least two signals is logically true and the one of the at least two signals temporally leads the other of the at least two signals.4. The apparatus of claim 2 , wherein when the counter block outputs an up count claim 2 , the counter block resets the down count.5. The apparatus of claim 1 , wherein the at least two signals are outputs from a phase detector of a phase-locked loop (PLL) device.6. The apparatus of claim 1 , wherein the at least two signals are binary pulse signals.7. A system claim 1 , comprising:a phase-locked-loop (PLL) device, including:a phase detector arranged to compare a phase of a reference frequency with a phase of a modified frequency and output a control signal on at least one of two outputs based on the comparison, the modified frequency comprising an output frequency of the PLL divided by a divider value; anda charge pump arranged to adjust the output frequency of ...

PHASE LOCKED LOOP CIRCUIT

A phase locked loop circuit includes a phase frequency detector, a control circuit, a charge pump, a loop filter, a supply circuit, a ring oscillator, a frequency divider and a voltage detector. The phase frequency detector generates a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal. The control circuit generates a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal. The charge pump generates a current signal according to the first control signal and/or the second control signal. The voltage detector monitors a supply voltage of the supply circuit, and controls the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high reference voltage. 1. A phase locked loop circuit , comprising:a phase frequency detector, generating a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal;a control circuit, generating a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal;a charge pump, generating a current signal according to the first control signal and/or the second control signal;a loop filter, generating a filtered signal according to the current signal; a supply circuit, providing a supply voltage according to the filtered signal; and', 'a ring oscillator, generating an output signal according to the supply voltage;, 'a voltage-controlled oscillator, comprisinga frequency divider, generating the feedback signal according to the output signal; anda voltage detector, monitoring the supply voltage, and controlling the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high ...