Partially parallel quasi-cyclic low-density parity-check (QC-LDPC) decoding method based on row message passing (RMP) scheduling

1. RMP-based scheduling partial parallel QC-LDPC decoding method, characterized in that it includes the following steps:

Step one, the row being heavy as a, b of the list of check matrix H QC-LDPC code (M, N) to, the specific method is:

(1) find the most code check matrix QC-LDPC small fitted to the matrix, and its magnitude is I×I, I is a constant;

(2) in the list of each division 1 under the condition of, in order to each J a partition check matrix is divided into K subzones, wherein I=nJ, M=KJ, n is an integer, normal circumstances n= 1, in other words I=J;

(3) multi-channel parallel decoding of the determination processing of several P, with Pl=J, for each partition l each of the decoding processing of the number of path;

Stated, on the basis of the subregion, scheduling based on RMP QC-LDPC code decoder, its composition includes:

The variable node RAM_λ soft information storage unit, for the initialization of the iterative decoding process soft information and variable node information storage, which includes memory blocks block P M λp RAM; section p block Mλp RAM memory blocks, each of the partitions stored in the decoding iteration p path of the non-zero elements of the row corresponding to the soft information of the variable node;

Check node RAM_Λ soft information storage unit, the iterative decoding process for updating the soft information of the check node memory, which includes memory blocks block P RAM M Λ_p; the memory block RAM p block M Λ_p, each partition is stored in the decoding iteration p path of the non-zero elements of the row corresponding to the soft information of the check node;

Memory address module ADU, QC-LDPC in the decoder used for producing the soft information of the variable node for storage units and the check node soft information storage unit; the memory address RAM_λ RAM_Λ producing children module and a memory address module to give birth production, each sub-block is composed of a P a P the initial address memory and an address offset calculator; each sub-module has integrated signal output port P, the output from the initial address memory from a P an initial address the memory and counter; the ADU 2P one output port, and respectively of the module RAM_Λ RAM_ λ module and a P read-write port is connected with the read/write address port;

IDU iterative decoding module, used to check node in the iterative process soft information to the soft information and variable node parallel update the arithmetic, the computation module CNU comprising a P;

Decoding a decision module DJU, used for the soft information of the variable node to be in the storage unit the information output judgment processing;

Soft information exchange module INU, the iterative decoding is used for the different RAM from RAM_λ module in the data storage block to the corresponding CNU calculating module, and to return the updated data to the corresponding memory block RAM; a INU 2P input port and 2P one output port, the input port P and the output port in the module RAM_λ RAM is connected with the output port and the input port, the input port and output port P with a a P RAM CNU computing module is connected with the output port and input port; through INU module integrated signal, the output P RAM_λ module assigned to the soft information CNU module in a P, and the output of the module a P CNU soft information is stored to the corresponding module RAM_λ in RAM;

Decoding process control module PCU, for generating the control signal of the whole decoding process, including INU module integrated signal;

The memory block of each block and Mλp RAM M Λ_p contains two read-write port, the read-write mode is "pre-read write-behind", each read-write port p CNU the computation module is connected with the block, each port, each responsible for route of data read/write;

Step three, the based on the establishment of the second step of scheduling of RMP QC-LDPC code decoder initializes the iterative decoder: a frame of the received channel-likelihood ratio soft information information, in accordance with the parity check matrix of the channel partitions in variable node information is stored to soft information storage unit the RAM_λ Mλp RAM P block in the memory block, the block memory block section p Mλp in accordance with the data of the address of a row of the route section p corresponding to where the non-zero elements of the corresponding columns, each memory block of the memory address range is 0-aJ -1, a code QC-LDPC of the row being heavy, paragraph for each partition J p path corresponding to the number of rows; at the same time, the check node soft information storage unit of the data stored in the RAM_Λ all initialized to 0, and initialization iter_time the number of iterations for the 0 time;

Step four, carry out iterative decoding operation: decoding process control module PCU and a memory address module ADU common control the iterative decoding module IDU and soft information storage module operation update;

Step 4. a) iterative decoding module a in the IDU p k CNU calculation module in each division the section of the channel parallel information p iterative decoding calculation, information module input from the variable node RAM_λ soft information storage unit and check node RAM_Λ soft information storage unit, the results of iterative decoding of the two saved to a corresponding position on the storage unit;

Wherein updating the path of the section i the rows of information, with a computation module CNU p variable node corresponding to the soft information storage unit of the memory block RAM RAM_λ, a section is one of the stored information RAM p memory address generation module in accordance with the address of the ADU read out is given, the address obtained RAM_λ can be obtained in accordance with the following calculation : < road decoding initialization address section aodirenc addr_kp0aodirenc p district k>+ <i-1>;

In updating the road section i the rows of information, with a computation module CNU p check node corresponding to the soft information storage unit of the memory block is RAM_Λ RAM p RAM wherein a section of the information stored in the memory address module ADU in accordance with the address read out, in accordance with the address obtained RAM_Λ memory block is a sequence of continuous addresses a, QC-LDPC code for a row being heavy;

Step 4. b) the results of the computation module calculates CNU through the soft information exchange module are respectively stored into the variable node INU soft information storage unit RAM_λ and check node RAM_Λ soft information corresponding to the memory cell in the memory block, write address is composed of a read address corresponding to a delay of the clock pulse;

Step 4. c) repeat steps 4. a)-step 4. b), until the completion of the each partition all rows of the update;

Step 4. d), repeating step 4. a)-step 4. c), the whole check matrix until the completion of the updating of all of the partitions;

Step five, repeat step four, until reaching the maximum iteration times, and the variable node RAM_λ soft information in the memory cells in each memory block is sequentially read in accordance with data stored in the judgment, the decoded result.