MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Advantage of the present invention and features, and an electronic component connected to the drawing appended with the achieving activitycopyright will reference the carry in particular embodiments. However the present invention are described in which an embodiment may be a limited but can be embodied in the form of various different, completely to only the present embodiment of the present disclosure, this invention is in consultation with a knowledge of the confirming button to complete and has provided for transmitting the, the invention relates to construe defined by category only disclosed. The same references refer to the same components herein over professional.

Terms used in embodiments are disclosed herein for limiting positioned that is even endured. Herein, in a single may be phrase not specially mentioned plurality type comprises a unit. Used herein 'includes (comprises)' and/or '(comprising) comprising' handle components, steps, operation and/or element comprises at least one other components, steps, operation and/or devices does not exclude the presence or addition.

Also, example embodiments of the present invention discussed herein that excels in cross-section and/or planarity are ideal products on be described are disclosed. In drawings present, and regions are exaggerated for effective thickness content description are disclosed. The, manufacturing technique and/or tolerances of form can be modified by example degrees. Thus, the embodiments of the present invention limited to a certain form which is shown in the form of manufacturing process generates comprising variations are disclosed. For example, the etching area shown at right angles having an predetermined angular or round may be in the form disclosed. The, drawing exemplified regions are coarse has attribute, drawing exemplified areas in the region of for example the shape of form which categories for limiting tastes.

Figure 1 shows a memory device according to embodiments of the invention represented by the block to determine are disclosed.

The reference also 1, memory device includes a memory cell array (1), word line decoder (2), word line driver (3), bit line decoder (4), read and write circuit (5), and control logic (6) can be comprising.

Memory cell array (1) has a plurality of memory blocks (BLK0 non-BLKn) which, memory blocks (BLK0 non-BLKn) each have a plurality of memory cells, and a plurality of memory cells electrically connected to a plurality of word lines, bit lines, a source can be lines.

Word line decoder (2) is also decodes the input address, selecting one of the word lines can be. Word line decoder (2) is decoded address in word line driver (3) can be provided. Word line driver (3) has a control logic (6) in response to the voltage generating circuit (not shown) generated from the word line voltage of a selected word line word lines can be selected and each provided. Word line decoder (2) and word line driver (3) has a plurality of memory blocks (BLK0 non-BLKn) can be the semiconductor chip, along a selected memory block in the block selecting signals (either BLK0 non-BLKn) driving signals of word lines can be.

Bit line decoder (4) is also decodes the input address, selecting one of the bit lines (or, either pair) can be. Bit line decoder (4) has a plurality of memory blocks (BLK0 non-BLKn) can be the center, along the block selecting signals (BLK0 non-BLKn) bit lines of the selected memory block can be data information.

Read and write circuit (5) memory cell array via the bit line (1) can be connected. Read and write circuit (5) and a bit line decoder (4) (not shown) from a bit line select signal can be in response to an address in a burst. Read and write circuit (5) is also can be configured to exchange data with. Read and write circuit (5) has a control logic (6) can be operated by a control. Read and write circuit (5) has a control logic (6) receives power from (e.g., voltage or current) and providing the selected bit line can be.

Control logic (6) can control the overall operation of the memory device. Control logic (6) receives the control signals and external voltage, can be operating in accordance with received control signals. Control logic (6) generating internal operation voltage required external power can be. Control logic (6) in response to a control signal read, write, and/or can delete the Image signal.

Figure 2 shows a memory cell array according to embodiments of the invention are disclosed formatting data memory device. In other words, also described with reference to Figure 2 shows a memory cell array 1 one example of formatting data also are disclosed.

The reference 2 also, memory cell array (1) has a plurality of word lines (WL), bit lines (BL1, BL2), source lines (SL), and unit memory cells (10) can be comprising. (BL1, BL2) bit lines can be arranged perpendicular to the word lines (WL). As shown in fig. 2, source lines (SL) can be parallel to the bit lines (SL). Which are not limited alone or, alternatively 2 also shown, source lines (SL) can be parallel to the word lines (WL).

Unit memory cells (10) with a word line (WL) and a pair of bit lines (BL1, BL2) across can be connected between. Each unit memory cells (10) is 1 and 2 memory devices (ME1, ME2; memory elements) (SE1, SE2; select element) and 1 and 2 can be selected elements comprising.

More specifically, first selection element (SE1) 1 1 (ME1) 1 memory device has a first bit line (BL1) can be connected between the, (ME2) (SE2) 2 2 2 memory device has a first selection device can be connected between the first bit line (BL2). 1 (SE1) has a first selection device connected between the source line (SL) on 1 memory device (ME1) can be, first selection element (SE2) 2 2 (ME2) connected between the source line (SL) to the second memory device can be. (SE1, SE2) first one source line (SL) selected elements 1 and 2 can be share, can be controlled by the same word line (WL). Also, 1 2 1 second or backward direction perpendicular to the first direction a plurality of unit memory cells (10) the source line (SL) can be the semiconductor chip.

At least one of memory cell (10) with a word line (WL) (BL1, BL2) pair of bit lines can be selected by. In some embodiments, each of the first and 1 (ME1, ME2) 2 memory devices energized by an electrical pulse applied to the variable resistive element can be switched into two resistance state. (ME1, ME2) the materials comprising the first 1 and 2 memory devices according to size and/or orientation of the current, or voltage size and/or orientation and its resistance value in accordance may be changed, even if the current or voltage changes its resistance value in valleys that may have blocked nonvolatile properties. According to some embodiments, the memory elements (ME1, ME2) 2 - 1 and second magnetic structure configured to resistance (magnetoresistance) characteristics may have. For example, each of the first memory elements (ME1, ME2) 1 and 2 with reference to the magnetic tunnel junction pattern 9a or 9b can be also be also carry. According to other embodiments, the memory elements (ME1, ME2) 1 2 first and the perovskite (perovskite) comprising compounds or transition metal oxides (transition metal oxide) can be.

(SE1, SE2) selected elements 1 and 2 first diode, PNP bipolar transistor (PNP bipolar transistor), NPN bipolar transistor (NPN bipolar transistor), NMOS field effect transistor (NMOS FET), or PMOS field effect transistor (PMOS FET) can be either. In some embodiments, selected elements (SE1, SE2) (WL) first word lines 1 and 2 in accordance with the voltages and current supply to the first control (ME1, ME2) 1 2 memory devices can be.

Figure 3 shows a unit memory cell formatting data memory device according to embodiments of the invention are disclosed. In other words, Figure 3 shows a reference memory cell in one example formatting also through a browser unit 2 also are disclosed.

The reference also 3, a unit memory cell (10) and second (ME1, ME2) as memory elements 1 and 2 include a magnetic tunnel junction patterns (MTJP1, MTJP2), 1 2 (SE1, SE2) as selection device comprising first and can be selectively. 1 free pattern (FP1) first magnetic tunnel junction pattern (MTJP1) is 1, 1 (PP1) first fixed pattern, and interposed between the first tunnel barrier pattern comprising 1 (TBP1) can be. The similarly, second magnetic tunnel junction pattern 2 (FP2) 2 (MTJP2) is free pattern, first fixed pattern (PP2) 2, and interposed between the first tunnel barrier pattern comprising 2 (TBP2) can be. Each of the first and fixed patterns 2 1 (PL1, PL2) may have the magnetization direction fixed in one direction. 1 1 (PP1) parallel to the magnetization direction of the first free pattern (FP1) is fixed pattern may have a configurable to or antiparallel magnetization direction, the magnetization direction of the first free pattern (FP2) 2 2 (PP2) is parallel or antiparallel magnetization direction variable to fixed pattern may have. According to embodiments of the present invention, each of the first magnetic tunnel junction patterns 1 and 2 (MTJP1, MTJP2) 9a or 9b also carry also refers to the magnetic tunnel junction pattern can be substantially equal.

(BL1, BL2) first bit lines 1 and 2 can be disposed across the word line (WL), source line (SL) 1 2 (SE1, SE2) and second selectively can be the semiconductor chip. A first bit line (BL1) between a first selection transistor (SE1) 1 1 1 wherein (MTJP1) can be connected, the first and second source line (SL) 1 1 (MTJP1) magnetic tunnel junction pattern selection transistor (SE1) can be connected. The first bit line selection transistor (SE2) 2 2 2 (BL2) first and second magnetic tunnel junction pattern (MTJP2) can be connected, the first and second source line (SL) 2 wherein (MTJP2) 2 selection transistor (SE2) can be connected.

According to some embodiments, as shown in fig. 3, 1 first bit line (BL1) can be connected to the first free pattern (FP1) 1, 1 (PP1) 1 (SE1) first fixed pattern can be connected to the first selection transistor. These embodiments, 2 (FP2) is first selection transistor can be connected to free pattern 2 (SE2), bit line (BL2) 2 (PP2) is first fixed pattern 2 can be connected.

According to other embodiments, also shown in 3 alternatively, 1 (PP1) first bit line (BL1) can be connected to the first fixed pattern 1, 1 (FP1) 1 (SE1) first free pattern can be connected to the first selection transistor. These embodiments, (SE2) 2 (PP2) is first fixed pattern 2 can be connected to the selection transistor, is connected to a first bit line (BL2) 2 2 free pattern (FP2) can be. Or less, in order to simplify descriptions, the first bit line (BL1) 1 1 (FP1) first free pattern, first fixed pattern (PP1) 1 1 (SE1) to first selection transistor, the first select transistor (SE2) 2 2 (FP2) first free pattern, first and second bit line (BL2) 2 (PP2) fixed pattern connected to embodiment 2 is described as follows.

In some embodiments, selected unit memory cell (10) data '1' for writing, the word line (WL) turn - on voltage can be applied to the disclosed. (BL1, BL2) 1 1 2 first and second bit lines bit line voltage is applied, a second bit line voltage source line (SL) 1 1 than the source line voltage can be applied to the disclosed.

The voltage conditions, 1 (SE1, SE2) is turned - 2 first and second selectively 1 is powered on and the source line (SL) (MTJP1, MTJP2) 2 magnetic tunnel junction patterns can be electrically connected. Also, a source line (SL) second first bit line (BL1) 1 1 flowing in writing current (I_W1 ) 1 wherein (MTJP1) can be provided first, second bit line (BL2) source line (SL) 2 2 in flowing first writing current (I_W2 ) 2 (MTJP2) first magnetic tunnel junction pattern can be provided. In this case, 1 and 2 in terms of first magnetic tunnel junction patterns (MTJP1, MTJP2), 1 first writing current (I_W1 ) 2 first writing current (I_W2 ) Flow can be opposite directions. In other words, these embodiments, (BL1, BL2) first bit lines 1 and 2 the same time that voltage is applied, the first magnetic tunnel junction pattern (MTJP1) 1 2 (MTJP2) opposite to the first magnetic tunnel junction pattern of writing current can be supplied.

Specifically, 1 first writing current (I_W1 ) Has a free pattern (FP1) 1 1 1 wherein (MTJP1) in fixed pattern (PP1) of direction can be provided, the electrons are first fixed pattern (PP1) 1 1 (FP1) direction in free pattern can be provided. In this case, fixed pattern 1 (PP1) first the same spin electrons tunnel barrier pattern to a first direction (TBP1) 1 1 (FP1) torque (torque) apply the first tunneling free pattern be. The, the magnetization direction of the first free pattern (FP1) 1 1 (PP1) parallel to the first magnetization direction of the fixed pattern can be changed. Alternatively, 2 second writing current (I_W2 ) 2 2 (PP2) of the second magnetic tunnel junction pattern (MTJP2) 2 (FP2) can be provided in fixed pattern free pattern, the first pattern (FP2) 2 (PP2) direction in free electrons 2 fixed pattern can be provided. In this case, the direction opposite to the spin of electrons having first fixed pattern (PP2) 2 2 2 a first tunnel barrier pattern (TBP2) (FP2) first free pattern reflected first tunneling an inaccurate free pattern 2 (FP2) torque capable of applying disclosed. The, second antiparallel to the magnetization direction of the free pattern (FP2) 2 2 (PP2) and second fixed pattern can be changed.

In this way, selected unit memory cell (10) data '1' when writing a, 1 (MTJP1) first magnetic tunnel junction pattern can be changed to parallel magnetization directions, the second magnetic tunnel junction pattern 2 (MTJP2) antiparallel grudge magnetization directions can be changed to. I.e., 1 second magnetic tunnel junction pattern (MTJP1) may have a low resistance state, a first magnetic tunnel junction pattern 2 (MTJP2) may have high resistance state.

In some embodiments, selected unit memory cell (10) data '0' for writing, the word line (WL) turn - on voltage can be applied to the disclosed. (BL1, BL2) 2 1 2 first and second bit lines bit line voltage is applied, a second bit line voltage source line (SL) 2 2 larger than the source line voltage can be applied to the disclosed.

Plural conditions, each of the first magnetic tunnel junction patterns (MTJP1, MTJP2) 1 and 2, 1 and 2 are first writing current (I_W1 , I_W2 ) Can be current are provided in the opposite direction. The, data '1' when writing in contrast, the second magnetic tunnel junction pattern 1 (MTJP1) magnetization directions can be modified so as to antiparallel grudge, 2 (MTJP2) first magnetic tunnel junction pattern can be changed to parallel magnetization directions. I.e., first magnetic tunnel junction pattern uses high resistance state (MTJP1) may have 1, 2 magnetic tunnel junction pattern (MTJP2) may have a first resistance state.

As above-mentioned, the first magnetic tunnel junction pattern (MTJP1) 2 1 first magnetic tunnel junction pattern (MTJP2) may have different resistance state is, selected unit memory cell (10) when reading the data, 1 and 2 first magnetic tunnel junction patterns (MTJP1, MTJP2) resistance value of one of the reference (reference) can be used. I.e., a unit memory cell (10) is a first magnetic tunnel junction pattern 1 (MTJP1) resistance value corresponding to the difference of the electrical magnetic tunnel junction pattern 2 (MTJP2) may have a sensing margin (sensing margin), the, a unit memory cell (10) can be of the motor.

Figure 4 shows a memory cell array according to embodiments of the invention representing plane memory device are disclosed. In other words, Figure 4 shows a 1 and 2 one example of memory cell array through a browser a also may also representing plane are disclosed. Figure 5 shows a I a-I ' as in the cross-section according to the line of Figure 4, according to embodiments of the present invention exhibits unit memory cell memory device. In other words, also described with reference to Figure 5 shows a 2 and 3 representing one example also the tunnel cross-section also are disclosed.

The reference also 4, memory cell array (1) includes a unit memory cells (10) can be comprising. Unit memory cells (10) is 1 direction (D1) and (D2) (D1) 1 2 2 along the direction intersecting the direction can be two-dimensionally arranged. Unit memory cells (10) of the second substrate (110) and second (not shown) disposed on selected elements 2 1, and 1 and 2 comprising magnetic tunnel junction patterns (MTJP1, MTJP2) can be. According to some embodiments, in terms flat, and second magnetic tunnel junction patterns 2 1 1 (D1) (MTJP1, MTJP2) is arranged zigzag along direction but, limited to the present invention are not correct.

Unit memory cells (10) connected to a pair of bit lines (BL1, BL2) each of the can be. 1 bit line (BL1) is 1 (D1) extending along a first direction can be, arranged along a first direction (D1) 1 unit memory cells (10) 1 (MTJP1) of magnetic tunnel junction patterns can be electrically connected. 2 bit line (BL2) is 1 (D1) extending along a first direction can be, arranged along a first direction (D1) 1 unit memory cells (10) 2 (MTJP2) of magnetic tunnel junction patterns can be electrically connected.

Or less, and also with reference to the 5 also 4, unit memory cells (10) for each of the specifically described as follows.

The reference also 4 and 5 also, substrate (110) can be provided. Substrate (110) (SE1, SE2) is 1 and 2 can be selectively comprising. (SE1, SE2) 1 and 2 first selectively controlled through a word line (not shown) can be. Further, source line (not shown) the source region of the select transistor (SE1) 1 are further provided a first source region of the first selection transistor can be the semiconductor chip 2 (SE2).

Substrate (110) on the interlayer insulating film 1 (120) can be provided. A first interlayer insulating film 1 (120) is, in one example, silicon oxide, silicon nitride, or silicon oxynitride comprising and/can be.

A first bit line (BL2) 2 1 and 2 contact plug (PLG1, PLG2) and substrate (110) can be provided on. 1 1 has a first contact plug (PLG1) interlayer insulation film (120) through the substrate (110) connected to a drain region of the first selection transistor included 1 (SE1) can be. 1 has a first contact plug 2 (PLG2) interlayer insulation film (120) through the substrate (110) 2 (SE2) included in the first selection transistor can be connected to the drain region. 2 bit line (BL2) is first interlayer insulating film 1 (120) can be disposed within, 1 extending along a first direction (D1) can be. A first bit line (BL2) 2 (PLG1, PLG2) 1 and 2 contact plug and can be located substantially the same level. Herein, 'level' substrate (110) height from the upper surface of big. First contact plugs 1 and 2 and each of the bit line (BL2) 2 (PLG1, PLG2) can be conductive material.

A first interlayer insulating film 1 (120) on the interlayer insulating film 2 (122) can be provided. A first interlayer insulating film 2 (122) is, in one example, silicon oxide, silicon nitride, or silicon oxynitride comprising and/can be.

(BE1, BE2) and landing pad lower electrode 1 and 2 first (LPAD) can be provided. A first interlayer insulating film 2 is lower electrode 1 (BE1) (122) (PLG1) through 1 can be electrically connected to the first contact plug, lower electrode 2 (BE2) is first interlayer insulating film 2 (122) through 2 (BL2) can be electrically connected to the first bit line. The second interlayer insulating film 2 (LPAD) landing pad (122) through 2 (PLG2) can be electrically connected to the first contact plug. (BE1, BE2) and landing pad lower electrode 1 and 2 first (LPAD) can be each of the conductive material. In one example, the first lower electrode (BE1, BE2) and landing pad (LPAD) 1 and 2 each of the copper, aluminum, tungsten, or titanium metal such as can be.

The upper surface of the lower electrode 1 and 2 first (BE1, BE2) are located at a higher level than the upper surface of the landing pad (LPAD) can be. Specifically, an upper surface of the first interlayer insulating film 2 (LPAD) landing pad (122) located substantially on the same level as the top of the can. In other words, an upper surface of the first interlayer insulating film 2 (LPAD) landing pad (122) can be the top of the 151m. Each of the first and second bottom electrodes (BE1, BE2) 1 2 2 interlayer dielectric (122) on the upper side of projecting top may have. The, lower electrode (BE1, BE2) 2 2 1 and first upper plane of each of is an interlayer insulating film (122) can be located at a higher level than the upper surface of. According to some embodiments, a top surface of the first lower electrode 1 and 2 (BE1, BE2) can be located substantially on the same level.

In terms flat, 1 first lower electrode (BE1) (LPAD) (IV1) 2 (BE2) and landing pad lower electrode spacing between landing pad (LPAD) (IV2) 2 (BE1, BE2) is the distance between the lower electrode and the distance between 1 (IV3) may be less than disclosed.

According to some embodiments, as shown in fig. 5, a second interlayer insulating film 2 (122) remaining on the protective insulating film (130r) can be provided. Residual protective insulating film (130r) on a top surface thereof comprising the recess region (RR) can be. Residual protective insulating film (130r) (LPAD) can be covering the upper surface of the landing pad, the, (LPAD) are not exposed to an upper surface of the landing pad thereof can. In terms flat, residual protective insulating film (130r) landing pad overlapping the at least one recess region (RR) (LPAD) can be, and first (BE1, BE2) can be spaced from the lower electrode 2 1 2000. Residual protective insulating film (130r) on the uppermost surface and the upper surface of the lower electrode 1 2 (BE1, BE2) substantially equal to the first level can be located. In other words, residual protective insulating film (130r) on the uppermost surface with the upper surface of the lower electrode 1 and 2 first (BE1, BE2) can be 151m. Residual protective insulating film (130r) recess region (RR) 1 2 and the upper surface of the bottom side of the first lower electrode (BE1, BE2) low level than can be located. Residual protective insulating film (130r) can be insulating material. In one example, residual protective insulating film (130r) silicon, silicon nitride, or silicon oxynitride comprising and/can be.

According to other embodiments, as shown in fig. 6, a first interlayer insulating film 2 (122) remaining on the protective insulation patterns (130p) can be provided. Such embodiments are also etched with reference to add carry 6.

(BE1) 1 first lower electrode are sequentially stacked on the first lower electrode pattern (OBEP1) selective 1, 1 wherein (MTJP1) first, selective first electrode pattern 1 (OTEP1), and 1 (TEP1) electrode pattern can be provided. Also, the first lower electrode 2 (BE2) are sequentially stacked on the first lower electrode pattern (OBEP2) selective 2, 2 magnetic tunnel junction pattern (MTJP2) first, selective first electrode pattern 2 (OTEP2), and 2 (TEP2) electrode pattern can be provided.

First and 1 2 1 2 and upper and lower electrode patterns (OBEP1, OBEP2) selective selective electrode patterns such as the titanium nitride and/or nitride tantalum [nyum[nyum] With (OTEP1, OTEP2) conductive metal nitride can be. The first electrode pattern (TEP) 1 and 2, in one example, tungsten, tantalum, aluminum, copper, gold, is, titanium, and/or the metal of conductive metal nitride can be.

1 free pattern (FP1) first magnetic tunnel junction pattern (MTJP1) is 1, 1 (PP1) first fixed pattern, and interposed between the first tunnel barrier pattern comprising 1 (TBP1) can be. A first magnetic tunnel junction pattern 2 (FP2) 2 (MTJP2) is free pattern, first fixed pattern (PP2) 2, and interposed between the first tunnel barrier pattern comprising 2 (TBP2) can be. First free pattern (FP1) 1, 1 (PP1) first fixed pattern, and a second tunnel barrier pattern 1 (TBP1) 2 (FP2) order laminated free pattern, first fixed pattern (PP2) 2, and tunnel barrier pattern 2 (TBP2) can be same as the order in laminated.

According to some embodiments, as shown in fig. 5, (PP1, PP2) fixed patterns, tunnel barrier patterns (TBP1, TBP2), in the order of (FP1, FP2) and free patterns can be stacked disclosed. Which are not limited alone or, according to other embodiments, also shown in 3 alternatively, (FP1, FP2) free patterns, tunnel barrier patterns (TBP1, TBP2), (PP1, PP2) can be laminated in the order of and fixed-pattern are disapproval. Or less, in order to simplify descriptions, (PP1, PP2) fixed patterns, tunnel barrier patterns (TBP1, TBP2), (FP1, FP2) stacked in the order of embodiment and free patterns are disclosed therein.

The device as well as in Figure 3, the lower electrode contact plug 1 1 (PP1) and first fixed pattern (BE1) substrate by using (PLG1) (110) (SE1) included in 1 second can be connected to the drain region of the selection transistor. Also, the first lower electrode (BE2) 2 2 2 (PP2) is fixed pattern (BL2) can be connected to a first bit line through. 1 and 2 for the second magnetic tunnel junction patterns (MTJP1, MTJP2), 9a and/or 9b also also it relates with reference to the other.

A first interlayer insulating film 2 (122) on, 1 2 3 covering the first and second magnetic tunnel junction patterns (MTJP1, MTJP2) interlayer insulation film (124) can be provided. A first interlayer insulating film 3 (124) is, in one example, silicon oxide, silicon nitride, or silicon oxynitride comprising and/can be.

A first interlayer insulating film 3 (124) (LPAD) through landing pad electrically connecting contact (INC) can be provided. The third hard mask (INC) can be conductive material. In one example, the third hard mask (INC) copper, aluminum, tungsten, or titanium metal such as can be.

A first interlayer insulating film 3 (124) on 1 bit line (BL1) and mutually (INP) can be provided. 1 first bit line (BL1) is 1 (TEP1) can be electrically connected to the electrode pattern. (INP) mutually electrode pattern electrically connecting the first connection contact (INC) 2 (TEP2) can. The, the device as well as in Figure 3, 1 1 (FP1) is first free pattern electrode pattern through the first bit line (BL1) can be connected to 1 (TEP1). Also, the first electrode pattern is free pattern (FP2) 2 2 (TEP2), mutually (INP), the third hard mask (INC), landing pad (LPAD), and substrate by using 2 contact plug (PLG2) (110) (SE2) contained in the first 2 can be connected to the drain region of the selection transistor. Each of the first bit line (BL1) 1 (INP) can be mutually and conductive material. In one example, each of the first bit line (BL1) and mutually 1 (INP) copper, aluminum, tungsten, or titanium metal such as can be.

Figure 6 shows a I a-I ' as in the cross-section according to the line of Figure 4, according to embodiments of the present invention exhibits unit memory cell memory device. In other words, also described with reference to Figure 6 shows a 2 and 3 representing one example also the tunnel cross-section also are disclosed.

The reference also 4 and 6 also, a unit memory cell (10) is also a 5 4 and also through a browser unit similar to memory cells disclosed. Specifically, a unit memory cell (10) residual protective insulating film (130r) remains on the protective insulation patterns (130p) also except that 4 and 5 also replaced with a memory cell through a browser unit can be substantially the same configuration. The, or less residual protective insulation patterns (130p) is described for protection, description is given of a remaining configurations dispensed to each other.

Residual protective insulation patterns (130p) is an interlayer insulating film 2 (122) can be provided on. Residual protective insulation patterns (130p) 1 2 (BE1, BE2) each of the first and each of the lower electrode (first interlayer insulating film 2 (122) that engages on the upper side of) the upper covers a sidewall of be. Residual protective insulation patterns (130p) between (LPAD) to expose the upper surfaces of landing pad can be. Residual protective insulation patterns (130p) upper surface of the upper surface of the lower electrode 1 and 2 are substantially equal to the first level (BE1, BE2) can be located. In other words, residual protective insulation patterns (130p) with the upper surface of the upper surface of the lower electrode (BE1, BE2) 1 and 2 are first 151m the Optocomponents. Residual protective insulation patterns (130p) can be insulating material. In one example, residual protective insulation patterns (130p) silicon, silicon nitride, or silicon oxynitride comprising and/can be.

4 and 5 is also 7a to 7h also through a browser a also a unit sensing device indicating according to embodiments of the cross-section are disclosed. 5 4 and also through a browser unit memory cell also a substantially the same construction for an add the same reference number is provided, in order to simplify descriptions can be dispensed description redundant.

The reference also 4 and also 7a, 1 (SE1, SE2) selectively a substrate comprising first and 2 (110) can be provided.

Substrate (110) on the interlayer insulating film 1 (120) can be formed. A first interlayer insulating film 1 (120) is, in one example, silicon oxide, silicon nitride, or silicon oxynitride comprising and/can be. A first interlayer insulating film 1 (120) is, in one example, chemical vapor deposition (Chemical Vapor Deposition: CVD) process or physical vapor deposition (Physical Vapor Deposition: PVD) can be formed by processes.

A first interlayer insulating film 1 (120) penetrating through both the 1 and 2 contact plug (PLG1, PLG2) can be formed. (PLG1) 1 (SE1) has a first contact plug 1 can be connected to the selection transistor, the first select transistor connected to the second contact plug (PLG2) 2 2 (SE2) can be. In addition, a second interlayer insulating film 1 (120) disposed over the 2 bit line (BL2) can be formed.

A first interlayer insulating film 1 (120) on the interlayer insulating film 2 (122) can be formed. A first interlayer insulating film 2 (122) is, in one example, silicon oxide, silicon nitride, or silicon oxynitride comprising and/can be. A first interlayer insulating film 2 (122) is, in one example, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) can be formed by processes.

A first interlayer insulating film 2 (122) (PH1) 1 penetrating through both the through hole can be formed. A first through hole (PH1) 1 2 (PLG2) can be exposed by the second contact plug. Forming a first interlayer insulating film 2 is 1 through hole (PH1) (122) (not shown) photoresist pattern is formed, the photoresist pattern at the fifth and second interlayer insulating film 2 (122) comprising etching can be.

The reference 4 and also 7b also, filling holes (PH1) first landing pad 1 (LPAD) can be formed. (LPAD) landing pad to form a conductive layer (not shown) filling holes (PH1) 1 is formed, and interlayer insulating film 2 (122) until the selectively to expose the upper surfaces of the can. The, landing pad upper surface of the first interlayer insulating film 2 (LPAD) (122) located substantially on the same level as the top of the can. Landing pad (LPAD) 2 (PLG2) can be connected to the second contact plug.

The reference also 4 and also 7c, first interlayer insulating film 2 (122) on the protective insulating film (130) can be formed. Protective insulating film (130) (LPAD) can be covering the upper surface of the landing pad, the, (LPAD) are not exposed to an upper surface of the landing pad thereof can. Protective insulating film (130) can be insulating material. In one example, protective insulating film (130) is silicon oxide, silicon nitride, or silicon oxynitride comprising and/can be. Protective insulating film (130) is, in one example, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) can be formed by processes.

Protective insulating film (130) and interlayer insulating film 2 (122) penetrating through both the 2 and 3 through-holes (PH2, PH3) can be formed. First and second through holes forming the channel layer 2 3 (PH2, PH3) (130) (not shown) to form a photoresist pattern is, and the photoresist pattern as an etch mask corresponding to insulating film (130) and interlayer insulating film 2 (122) can be used to etch a pattern as a mask. A first through hole (PH2) 2 (PLG1) can be exposed by the second contact plug 1, second bit line (BL2) (PH3) first through hole 3 by 2 can be exposed.

The reference also 4 and also 7d, first through hole 2 is filled in a lower electrode (BE1) (PH2) 1, 2 and 3 is filled in a through hole (PH3) lower electrode (BE2) can be formed. (BE1, BE2) forming a first lower electrode 1 and 2 and 3 through-holes (PH2, PH3) film 2 is formed (not shown) fills, and protective insulation film (130) until the selectively to expose the upper surfaces of the can. The, upper surface of first conductive patterns 1 and 2 (BE1, BE2) are protective insulating film (130) located substantially on the same level as the top of the can, (LPAD) can be located at a higher level than the upper surface of the landing pad. 1 first lower electrode (BE1) 1 (PLG1) can be connected to the first contact plug, the first lower electrode is connected to bit line (BL2) 2 2 (BE2) can be.

The reference also 4 and also 7e, protective insulating film (130) on, the lower electrode film (OBEL) selective, magnetic tunnel junction film (MTJL), selective (OTEL) upper electrode, and an upper electrode film (TEL) can be sequentially. Each of the films (OBEL, MTJL, OTEL, TEL), in one example, chemical vapor deposition (CVD) process, or physical vapor deposition (PVD) can be formed by processes.

The lower electrode film (OBEL) and optionally selective upper electrode conductive metal nitride such as tantalum nitride or titanium nitride/[nyum[nyum] With (OTEL) can. According to some embodiments, the lower electrode film selective (OBEL) and optionally at least one upper electrode (OTEL) can be omitted. In the warming, in order to simplify descriptions, the lower electrode film (OBEL) and optionally selective (OTEL) upper electrode formed embodiments are disclosed but, limited to the present invention are not correct.

A stacked magnetic tunnel junction film (MTJL) fixed bed (PL), tunnel barrier film (TBL), and free layer comprising (FL) can be. However, the present invention which are not limited to, fixed bed (PL) (FL) free layer is stacked sequence can be interchanged. For the magnetic tunnel junction film (MTJL), 9a and/or 9b also also it relates with reference to the other.

(TEL) upper electrode mask pattern has (MP) can be formed. In terms flat, mask patterns (MP) is lower electrode 1 and 2 (BE1, BE2) can be overlapping. Mask patterns (MP) is, in one example, silicon oxide, silicon nitride, or silicon oxynitride comprising and/can be.

The reference also 4 and also 7f, 1 2 1 2 and first and upper electrode patterns (TEP1, TEP2) and selective upper electrode patterns can be formed (OTEP1, OTEP2). A first upper electrode patterns 1 and 2 and 2 and 1 (TEP1, TEP2) selective electrode pattern mask patterns are formed (OTEP1, OTEP2) (MP) at the fifth upper electrode film (TEL) and optionally (OTEL) can be sequentially patterning the upper electrode. The patterning process is, as one example, in a dry etching process such as reactive ion etching (Reactive Ion Etching: RIE) can be performed using.

The reference also 7g and also 4, on the first lower electrode (BE1) 1 1 1 and selective lower electrode patterns (OBEP1) magnetic tunnel junction patterns can be formed (MTJP1), on the first lower electrode (BE2) 2 2 1 (MTJP2) and selective lower electrode patterns (OBEP2) magnetic tunnel junction patterns can be formed. A first magnetic tunnel junction patterns 1 and 2 (MTJP1, MTJP2), 1 and 2 and selective mask patterns to form a lower electrode patterns (OBEP1, OBEP2) (MP) at the fifth magnetic tunnel junction film by patterning the lower electrode film (OBEL) (MTJL) and optionally a can. The patterning process is, in one example, can be performed using ion beam etching (Ion Beam Etching: IBE) process.

Magnetic tunnel junction film (MTJL) and optionally by patterning the lower electrode film (OBEL), protective insulating film (130) is etched portion of residual protective insulating film (130r) can be formed. Residual protective insulating film (130r) (LPAD) can be covering the upper surface of the landing pad, the, (LPAD) are not exposed to an upper surface of the landing pad thereof can.

Generally magnetic tunnel junction pattern by a process, wet etching 1308. landing pad is exposed. In this case, isotropically etching by-products generated in the re-deposition process is performed on the magnetic tunnel junction can be, thereby magnetic tunnel junction pattern free layer and fixed layer short 1308.. In order to prevent short-circuit problems such wider spacing between magnetic tunnel junction pattern when landing pad, magnetic memory elements of the degree of integration can be lower.

According to the embodiments of the present invention according to a method of manufacturing them, landing pad (LPAD) on protective insulating film (130) formed therein. The, 1 and 2 (MTJP1, MTJP2) a step for forming a first magnetic tunnel junction patterns by, landing pad (LPAD) is can be as an etching mask. The, first and 2 1 (FP1, FP2) magnetic tunnel junction patterns (MTJP1, MTJP2) (PP1, PP2) between the insulation layers and fixed free layers can be prevent. The, magnetic memory can be thickness.

Further, according to the embodiments of the present invention according to a method of manufacturing them, landing pad (LPAD) since the re-deposition phenomenon can be prevented by a dry etching process, landing pad (LPAD) 1 or 2 (MTJP1) first magnetic tunnel junction pattern can be formed proximate the magnetic tunnel junction pattern (MTJP2). In other words, the second landing pad lower electrode (BE1) or 2 (BE2) (LPAD) 1 can be formed proximate the lower electrode. In one example, as shown in fig. 4, in one aspect a flat, 1 first lower electrode (BE1) (LPAD) (IV1) 2 (BE2) and landing pad lower electrode spacing between landing pad (LPAD) (IV2) 2 (BE1, BE2) is the distance between the lower electrode and the distance between 1 (IV3) may be less than disclosed. The, magnetic memory for improving the degree of integration can be.

The reference also 4 and also 7h, first interlayer insulating film 2 (122) on, 1 2 3 covering the first and second magnetic tunnel junction patterns (MTJP1, MTJP2) interlayer insulation film (124) can be formed. A first interlayer insulating film 3 (124) is, in one example, silicon oxide, silicon nitride, or silicon oxynitride comprising and/can be. A first interlayer insulating film 3 (124) is, in one example, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) can be formed by processes. Further, the upper surface of the first upper electrode patterns (TEP1, TEP2) 1 and 2 are first interlayer insulating film 3 is removed from the (124) can be flattened.

The reference 4 and also 5 also again, first interlayer insulating film 3 (124) (LPAD) through landing pad connecting contact (INC) can be formed. Further, a first interlayer insulating film 3 (124) 1 (INP) on bit line (BL1) and connecting pattern can be formed. 1 first bit line (BL1) can be electrically connected to the first electrode pattern (TEP1) 1, 2 mutually (INP) electrode pattern electrically connecting the first connection contact (INC) (TEP2) can. According to some embodiments, the third hard mask (INC), mutually (INP), and 1 (BL1) part of the bit line can be different semiconductor.

8a and 8b is also a reference to 4 also also 6 through a browser according to embodiments of the cross-section representing the unit sensing device are disclosed. 4 and also through a browser unit memory cell configuration substantially the same reference also 6 for an add the same reference number is provided, in order to simplify descriptions can be dispensed description redundant.

The tunnel is, also 4, and also with reference to the described test socket 7a to 7f manufacturing method of preparation process can be substantially the same. Descriptions in order to simplify the description is given of a dispensed and, 4 and also through a browser process for protection of a 7f also after described substrate.

The reference also 4 and also 8a, on the first lower electrode (BE1) 1 1 1 and selective lower electrode patterns (OBEP1) magnetic tunnel junction patterns can be formed (MTJP1), on the first lower electrode (BE2) 2 2 1 (MTJP2) and selective lower electrode patterns (OBEP2) magnetic tunnel junction patterns can be formed. A first magnetic tunnel junction patterns 1 and 2 (MTJP1, MTJP2), 1 and 2 and selective mask patterns to form a lower electrode patterns (OBEP1, OBEP2) (MP) at the fifth magnetic tunnel junction film by patterning the lower electrode film (OBEL) (MTJL) and optionally a can. The patterning process is, in one example, can be performed using ion beam etching (IBE) process.

Magnetic tunnel junction film (MTJL) and optionally by patterning the lower electrode film (OBEL), protective insulating film (130) is etched portion of residual protective insulation patterns (130p) can be formed. Residual protective insulation patterns (130p) between (LPAD) to expose the upper surfaces of landing pad can be.

Such embodiments, protective insulating film (130) forming the tunnel junction patterns (MTJP1, MTJP2) landing pad serves as an etching mask during the process is (LPAD) can be performed. The, according to the embodiments of the present invention according to a method of manufacturing them, 1 and 2 first (FP1, FP2) magnetic tunnel junction patterns (MTJP1, MTJP2) (PP1, PP2) and fixing the free layers can be enable recycle between the insulation layers. The, magnetic memory can be thickness.

The reference also 4 and also 8b, a first interlayer insulating film 2 (122) on, 1 2 3 covering the first and second magnetic tunnel junction patterns (MTJP1, MTJP2) interlayer insulation film (124) can be formed. Further, the upper surface of the first upper electrode patterns (TEP1, TEP2) 1 and 2 are first interlayer insulating film 3 is removed from the (124) can be flattened.

6 also 4 and also the reference again, first interlayer insulating film 3 (124) (LPAD) through landing pad connecting contact (INC) can be formed. Further, a first interlayer insulating film 3 (124) 1 (INP) on bit line (BL1) and connecting pattern can be formed. 1 first bit line (BL1) can be electrically connected to the first electrode pattern (TEP1) 1, 2 mutually (INP) electrode pattern electrically connecting the first connection contact (INC) (TEP2) can. According to some embodiments, the third hard mask (INC), mutually (INP), and 1 (BL1) part of the bit line can be different semiconductor.

9a and 9b according to embodiments of the present invention also includes a magnetic tunnel junction pattern to explain the concept are disclosed. Magnetic tunnel junction pattern (MTJP) is 1 magnetic pattern (MP1), tunnel barrier pattern (TBP), comprising 2 magnetic pattern (MP2) and can be. 1 magnetic pattern (MP1) 2 magnetic pattern (MP2) and one of either the first magnetic tunnel junction (magnetic tunnel junction: MTJ) and free pattern, the other fixed pattern be a magnetic tunnel junction. Or less, in order to simplify descriptions 1 magnetic pattern (MP1) 2 (MP2) first fixing pattern free pattern described first magnetic pattern but, conversely, 1 magnetic pattern (MP1) first (MP2) 2 magnetic pattern is first free pattern can be fixed pattern. (MTJP) electrical resistance of the magnetic tunnel junction pattern depend on the magnetization direction of the free pattern and the fixed pattern can be disclosed. For example, electrical resistance of the magnetic tunnel junction pattern (MTJP) are parallel to the magnetization direction of the free pattern and the fixed pattern (parallel) that they can be compared with the much larger when antiparallel grudge (antiparallel). As a result, magnetic tunnel junction pattern (MTJP) of electrical resistance can be modulated by varying the magnetization direction of the free pattern, this can be used as the basis for storing data in magnetic memory device according to the present invention.

The reference also 9a, 1 magnetic pattern (MP1) (MP2) and the first barrier pattern (TBP) the top of the tunnel 2 magnetic pattern magnetization direction substantially parallel magnetization magnetic layer for forming structure than disclosed. These embodiments, the first layer comprising an anti-ferromagnetic material (anti-a ferromagnetic material) 1 magnetic pattern (MP1) comprising ferromagnetic material (ferromagnetic material) can be layer. The anti-ferromagnetic material layer including PtMn, IrMn, MnO, MnS, MnTe, MnF₂ , FeCl₂ , FeO, CoCl₂ , CoO, NiCl₂ , At least one of NiO and Cr can. In some embodiments, the anti-ferromagnetic material layer is at least one rare metal (precious metal) can be selected. The rare-metal is ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au) or silver (Ag) can be comprising. The ferromagnetic material layer having a CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO₂ , MnOFe₂ O₃ , FeOFe₂ O₃ , NiOFe₂ O₃ , CuOFe₂ O₃ , MgOFe₂ O₃ , EuO and Y₃ Fe₅ O₁₂ At least one can.

The first 2 magnetic pattern (MP2) comprising a material having a variable magnetization direction can. 2 magnetic pattern (MP2) can be first ferromagnetic material. In one example, 2 magnetic pattern (MP2) is first FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO₂ , MnOFe₂ O₃ , FeOFe₂ O₃ , NiOFe₂ O₃ , CuOFe₂ O₃ , MgOFe₂ O₃ , EuO and Y₃ Fe₅ O₁₂ At least one can be selected.

The first 2 magnetic pattern (MP2) can be of layers. In one example, a plurality of ferromagnetic material layers comprising a layer comprising a non-magnetic material interposed between the layers can be. In this case, the ferromagnetic material layer and a layer including a non-magnetic material constituting the synthetic pinned (synthetic antiferromagnetic layer) can be. The synthetic antiferromagnetic layers may magnetic storage for reducing a critical current density, thermal stability can be improved.

Tunnel barrier pattern (TBP) magnesium oxide (Mg), titanium (Ti) oxide, aluminum (Al), zinc (MgZn)- magnesium oxide, boron (MgB)- magnesium oxide, titanium (Ti) and vanadium (V) comprising at least one nitride nitride can. In one example, the magnesium oxide (MgO) can be a monolayer of tunnel barrier pattern (TBP). Alternatively, tunnel barrier pattern can be (TBP) includes a plurality of layers. Chemical vapor deposition (CVD) process (TBP) tunnel barrier pattern can be formed using.

The reference also 9b, 1 magnetic pattern (MP1) (MP2) and second barrier pattern on the upper surface of the tunnel 2 magnetic pattern (TBP) magnetization direction substantially perpendicular vertical magnetization structure may have. These embodiments, 1 magnetic pattern (MP1) (MP2) L1 and the first 2 magnetic pattern₀ A material having a crystal structure, a material having a dense hexagonal lattice, and amorphous RE-a TM (Rare provided Earth Transition Metal) comprising at least one alloy can. In one example, the Fe 2 magnetic pattern (MP2) and first (MP1) 1 magnetic pattern₅₀ Pt₅₀ , Fe₅₀ Pd₅₀ , Co₅₀ Pt₅₀ , Co₅₀ Pd₅₀ And Fe₅₀ Ni₅₀ L1 comprising₀ At least one of crystal structure material can be. Alternatively, hexagonal lattice (MP2) and second (MP1) 1 magnetic pattern having 10 to 45 at a hot 2 magnetic pattern. % Cobalt content of platinum (Pt)- platinum (CoPt) (disordered alloy) or Co disordered alloy₃ (Ordered alloy) can be ordered alloy comprising Pt. Alternatively, iron (Fe) and second (MP1) 2 magnetic pattern (MP2) 1 magnetic pattern, cobalt and nickel (Ni) (Co) at least one metal terbium (Tb) selected and rare earth, dysprosium (Dy) and gadolinium (Gd) amorphous alloy comprising at least one at least one RE-a TM can be selected.

1 magnetic pattern (MP1) 2 magnetic pattern (MP2) and second (interface perpendicular magnetic anisotropy) having vertical magnetic anisotropy can be of such material. The vertical magnetic anisotropy may possess magnetic layer having magnetization interface being adjacent a vertical magnetization direction from other layers by the influence of the interface between pipe substrate. Wherein, if there is no factor is the "magnetization characteristics inherent" externally, its widest surface characteristics of the magnetic layer magnetization direction parallel to big. In one example, the catabolic pathway having magnetic layer magnetization if there is no factor externally formed on the substrate, the magnetic layer can be substantially parallel to the magnetization direction of the substrate.

In one example, 1 magnetic pattern (MP1) 2 magnetic pattern (MP2) and second cobalt (Co), iron (Fe) and nickel (Ni) can be at least one. 1 magnetic pattern (MP1) (MP2) screen and first 2 magnetic pattern (B), zinc (Zn), aluminum (Al), titanium (Ti), ruthenium (Ru), tantalum (Ta), silicon (Si), is (Ag), gold (Au), copper (Cu), carbon (C) and nitrogen (N) further comprises a non-magnetic material comprising at least one can be. In one example, the first CoFe or NiFe (MP2) 1 magnetic pattern (MP1) and 2 magnetic pattern comprising a, further comprises boron (B) can be. In addition, a saturation magnetization amount (MP2) and second (MP1) 1 magnetic pattern 2 magnetic pattern is formed in, and titanium (Ti) 2 magnetic pattern (MP2) 1 magnetic pattern (MP1) first, aluminum (Al), silicon (Si), magnesium (Mg), tantalum (Ta) and silicon (Si) further comprises at least one can be. 1 magnetic pattern (MP1) first (MP2) chemical vapor deposition (CVD) process or the sputtering process and 2 magnetic pattern can be formed using.

A magnetic tunnel junction film (MTJL) 7e also refers to the above-mentioned magnetic tunnel junction pattern (MTJP) on Au can be substantially the same.

Or more, attached HTML page through embodiments of the present invention are described but, this invention is a person who has knowledge of the present invention demonstrates its technical idea consultation or essential characteristics without changing other form can be carried out may be understand are disclosed. The exemplary embodiments discussed or more definitive not understood to all sides which must substrate.