RADIO FREQUENCY SWITCHING CIRCUITRY WITH REDUCED SWITCHING TIME

The present disclosure relates to driver circuitry for radio frequency (RF) switching circuitry, and in particular to RF switching circuitry with faster switching times.

Radio frequency (RF) switching circuitry is an essential part of any wireless communication device. RF switching circuitry may be used to route RF signals between various nodes (e.g., a power amplifier and an antenna, an antenna and a low noise amplifier (LNA), and the like), to change the impedance of one or more nodes, or any number of other functions. Exemplary RF switching circuitry 10 is shown in FIG. 1. The RF switching circuitry 10 includes a number of field effect transistors (FETs) 12 (numbered individually from 12A to 12N) coupled drain (D) to source (S) between an input node 14 and an output node 16. A gate drive node 18 is coupled to a gate (G) of each of the FETs 10 via a common resistor R_Cand a number of gate resistors R_G. Specifically, the common resistor R_Cis coupled between the gate drive node 18 and a gate (G) of a first one of the FETs 12A. Each of the gate resistors R_Gis coupled between the gate contacts (G) of each adjacent pair of the FETs 12.

A gate drive signal DRV_Gprovided at the gate drive node 18 places the FETs 12 in one of an on state or an off state. In the on state of the FETs 12, a low impedance path is provided between the input node 14 and the output node 16, thereby allowing an RF input signal RF_INat the input node 14 to pass to the output node 16. In the off state of the FETs 12, a high impedance path is provided between the input node 14 and the output node 16, thereby preventing the RF input signal RF_INat the input node 14 from reaching the output node 16. The RF switching circuitry 10 may be provided in a series configuration or a shunt configuration. In the series configuration, the input node 14 and the output node 16 are RF signal nodes. In the shunt configuration, the input node 14 is an RF signal node and the output node 16 is a ground node or coupled to a fixed impedance.

The gate drive signal DRV_Gmay switch between a positive power supply voltage V_PPand a negative power supply voltage V_NN. Generally, the negative power supply voltage V_PPis provided by a voltage regulator while the negative power supply voltage V_NNis generated from the positive power supply voltage V_PPusing a charge pump. In the case of a mobile device, the positive power supply voltage V_PPmay correspond with a battery voltage or a downregulated version thereof. The negative power supply voltage V_NNmay be generated in proportion to the magnitude of the positive power supply voltage V_PP(e.g., if the positive power supply voltage V_PPis 2.5V, the negative power supply voltage V_NNmay be −2.5V).

A typical gate drive signal DRV_Gis illustrated in FIG. 2. To maintain the FETs 12 in an off state, the gate drive signal DRV_Gis provided at the negative power supply voltage V_NN. The negative power supply voltage V_NNmaintains the gate-to-source voltage V_GSof each one of the FETs 12 well below a threshold voltage V_THthereof, ensuring that the FETs 12 remain off even when a drain-to-source voltage V_DSof each one of the FETs 12 is large. To transition the FETs 12 into an on state, the gate drive signal DRV_Gslews from the negative power supply voltage V_NNto the positive power supply voltage V_PP. As the gate-to-source voltage V_GSof the FETs 12 rises above the threshold voltage V_THthereof, the FETs 12 turn on.

As will be appreciated by those skilled in the art, each one of the FETs 12 has an associated gate capacitance due to the physical structure thereof. This gate capacitance, along with the resistance provided by the common resistor R_Cand the gate resistors R_G, degrades the switching speed of the RF switching circuitry 10 as illustrated by Equation (1):

τ=RC  (1)

where τ is the time required to charge or discharge the capacitance of each one of the FETs 12, which is inversely proportional to the time required to transition between the on state and the off state of the FETs 12, R is the resistance seen at the gate drive node 18, and C is the capacitance seen at the gate drive node 18. Such a reduction in the switching speed of the FETs 12 becomes problematic when RF standards (e.g., 5G, WiFi) demand very fast switching speeds (e.g., 100-200 ns).

One way to increase the switching speed of the RF switching circuitry 10 is by reducing the size of the common resistor R_Cand/or the gate resistors R_G. While doing so decreases the time constant r by reducing the resistance R seen at the gate drive node 18, it also increases the insertion loss of the RF switching circuitry 10 as large values of the common resistor R_Cand/or gate resistors R_Gprevent leakage of the RF input signal RF_INinto the gate (G) of each one of the FETs 12. Another way to increase the switching speed of the RF switching circuitry 10 is by reducing the size of the FETs 12. While doing so decreases the gate capacitance of each one of the FETs and thus the time constant r by reducing the capacitance C seen at the gate drive node 18, it also decreases the power handling capability of the RF switching circuitry 10.

In light of the above, there is a need for an RF switch with improved switching time that maintains low insertion loss and high power handling capability.

The present disclosure relates to driver circuitry for radio frequency (RF) switching circuitry, and in particular to RF switching circuitry with faster switching times. In one embodiment, RF switching circuitry includes an input node, an output node, a gate drive node, a plurality of field-effect transistors (FETs), and switch acceleration circuitry. The plurality of FETs are coupled between the input node, the output node, and the gate drive node. When a positive power supply voltage is provided at the gate drive node, the plurality of FETs turn on and provide a low impedance path between the input node and the output node. When a negative power supply voltage is provided at the gate drive node, the plurality of FETs turn off and provide a high impedance path between the input node and the output node. The switch acceleration circuitry includes a bypass FET and multi-level driver circuitry. The bypass FET selectively bypasses the common resistor in response to a multi-level drive signal. The multi-level driver circuitry uses a built-in gate to capacitance of the bypass FET to provide the multi-level drive signal at an overvoltage that is above the positive power supply voltage. By using the built-in gate capacitance of the bypass FET to provide the multi-level drive signal at an overvoltage that is above the positive power supply voltage, the multi-level driver circuitry is able to maintain the bypass FET in an on state during transitions of the plurality of FETs between states without the need for extra circuitry (e.g., a charge pump).

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 3 shows radio frequency (RF) switching circuitry 20 including switch acceleration circuitry 22 according to one embodiment of the present disclosure. The basic structure of the RF switching circuitry 20 is similar to that shown in FIG. 1 above and includes a number of field effect transistors (FETs) 24 (numbered individually as 24A to 24N) coupled drain (D) to source (S) between an input node 26 and an output node 28. A gate drive node 30 is coupled to a gate (G) of each of the FETs 24 via a common resistor R_Cand a number of gate resistors R_G. Specifically, the common resistor R_Cis coupled between the gate drive node 30 and a first one of the FETs 24A. Each one of the gate resistors R_Gis coupled between the gate contacts (G) of each adjacent pair of the FETs 24.

A gate drive signal DRV_Gprovided at the gate drive node 30 places the FETs 24 in one of an on state or an off state. In the on state of the FETs 24, a low impedance path is provided between the input node 26 and the output node 28, thereby allowing an RF input signal RF_INat the input node 26 to pass to the output node 28. In the off state of the FETs 24, a high impedance path is provided between the input node 26 and the output node 28, thereby preventing the RF input signal RF_INat the input node 26 from reaching the output node 28. The RF switching circuitry 20 may be provided in a series configuration or a shunt configuration. In the series configuration, the input node 26 and the output node 28 are RF signal nodes. In the shunt configuration, the input node 26 is an RF signal node and the output node 28 is a ground node or coupled to a fixed impedance. As discussed herein, a low impedance path is one in which any FETs provided therein are on. As will be appreciated by those skilled in the art, FETs essentially provide a closed circuit when on, presenting a resistance that is equal to an on-state resistance of the one or more FETs. A high impedance path is one in which any FETs provided therein are off. As will be appreciated by those skilled in the art, FETs essentially provide an open circuit when off, presenting a resistance that is equal to an off-state resistance of the one or more FETs.

The gate drive signal DRV_Gmay be provided by a gate driver (not shown), which switches the gate drive signal DRV_Gbetween a positive power supply voltage V_PPand a negative power supply voltage V_NNin response to a digital or logic-level control signal. Generally, the positive power supply voltage V_PPis provided by a voltage regulator while the negative power supply voltage V_NNis generated from the positive power supply voltage V_PPusing a charge pump. In the case of a mobile device, the positive power supply voltage V_PPmay correspond with a battery voltage or a downregulated version thereof. The negative power supply voltage V_NNmay be generated in proportion to the magnitude of the positive power supply voltage V_PP(e.g., if the positive power supply voltage V_PPis 2.5V, the negative power supply voltage V_NNmay be −2.5V).

As discussed above, the switching speed of the RF switching circuitry 20 is limited due to the combination of resistance of the common resistor R_Cand the gate resistors R_Gand capacitance of the FETs 24. In order to increase the switching speed of the RF switching circuitry 20, the switch acceleration circuitry 22 is configured to selectively bypass the common resistor R_Cas discussed below. To do so, the switch acceleration circuitry 22 includes a bypass FET 32 coupled across the common resistor R_C. Specifically, a drain (D) of the bypass FET 32 is coupled to the gate drive node 30, and a source contact (S) of the bypass FET 32 is coupled to the gate (G) of a first one of the FETs 24A. A gate (G) of the bypass FET 32 is configured to receive a multi-level drive signal DRV_ML. The multi-level drive signal DRV_MLmay switch between the negative power supply voltage V_NN, ground, and an over-voltage V_O, which is greater than the positive power supply voltage V_PP. When the multi-level drive signal DRV_MLis provided at the negative power supply voltage V_NNor ground, the bypass FET 32 remains off. At some point when the multi-level drive signal DRV_MLis between ground and the over-voltage V_O, the bypass FET 32 turns on.

When the bypass FET 32 is on, the common resistor R_Cis bypassed and thus not presented to the gate drive node 30. When the bypass FET 32 is off, the common resistor R_Cis not bypassed and thus presented to the gate drive node 30. Bypassing the common resistor R_Csubstantially reduces the resistance R presented to the gate drive node 30 and therefore the time constant r discussed above with respect to Equation (1). Accordingly, the switching speed of the RF switching circuitry 20 may be substantially improved when the common resistor R_Cis bypassed.

A large resistance at the gate (G) of each one of the FETs 24 is necessary to avoid leakage of the RF input signal RF_INinto the gate (G). Accordingly, it is desirable to bypass the common resistor R_Conly when turning on or off the RF switching circuitry 20 and not during steady state operation thereof. Doing so increases the switching speed of the RF switching circuitry 20 without adversely affecting the insertion loss thereof. FIG. 4 shows an exemplary multi-level drive signal DRV_MLaccording to one embodiment of the present disclosure configured to do so. The gate drive signal DRV_Gfor the FETs 24 is also shown for context. Specifically, FIG. 4 shows the gate drive signal DRV_Gas a solid line and the multi-level drive signal DRV_MLas a dashed line.

To maintain the FETs 24 and the bypass FET 32 in an off state, the gate drive signal DRV_Gand the multi-level drive signal DRV_MLare provided at the negative power supply voltage V_NN. As discussed above, the negative power supply voltage V_NNmaintains the gate-to-source voltage V_GSof each one of the FETs 24 well below a threshold voltage V_THthereof, ensuring that the FETs 24 remain off even when a drain-to-source voltage V_DSof each one of the FETs 24 is large. Similarly, the negative power supply voltage V_NNmaintains the gate-to-source V_GSvoltage of the bypass FET 32 well below a threshold voltage V_THthereof such that the bypass FET 32 remains off. To transition the FETs 24 into an on state, the gate drive signal DRV_Gslews from the negative power supply voltage V_NNto the positive power supply voltage V_PP. As the gate-to-source voltage V_GSof the FETs 24 rises above the threshold voltage V_THthereof, the FETs 24 turn on. Before this occurs, however, the multi-level drive signal DRV_MLslews from the negative power supply voltage V_NNto ground. Then, as the gate drive signal DRV_Gslews from the negative power supply voltage V_NNto the positive power supply voltage V_PP, the multi-level drive signal DRV_MLsimilarly slews from ground to the over-voltage V_O, maintaining a headroom of 2.5V above the switching control signal CNT_SW. As discussed below, the multi-level drive signal is provided by utilizing the built-in capacitance of the bypass FET 32 and thus does not require separate circuitry (e.g., a charge pump) to generate the over-voltage V_O. As the gate-to-source voltage V_GSof the bypass FET 32 rises above the threshold voltage V_THthereof, the bypass FET 32 turns on to bypass the common resistor R_C. The 2.5V headroom above the switching control signal CNT_SWensures that the bypass FET 32 remains on throughout the entirety of the turn on of the FETs 24. If the bypass control signal CNT_BPdid not maintain a headroom above the switching control signal CNT_SW, the gate-to-source voltage V_GSof the bypass FET 32 would not be sufficiently greater than the threshold voltage V_THthereof, and the bypass FET 32 would turn off.

When the gate drive signal DRV_Gis done slewing from the negative power supply voltage V_NNto the positive power supply voltage V_PPand the FETs 24 are thus turned on, the multi-level drive signal DRV_MLdrops to ground such that the bypass FET 32 is turned off and the common resistor R_Cis no longer bypassed. Doing so reduces leakage of the RF input signal RF_INfrom drain-to-gate or source-to-gate in each of the FETs 24 while the RF input signal RF_INis passed from the input node 26 to the output node 28.

To turn the FETs 24 back off, the process is reversed. The bypass FET 32 is first turned on by raising the multi-level drive signal DRV_MLfrom ground back to the over-voltage V_O. The gate drive signal DRV_Gslews from the positive power supply voltage V_PPback to the negative power supply voltage V_NN, and the multi-level drive signal DRV_MLmaintains a 2.5V headroom over the gate drive signal DRV_Gduring this slewing.

The gate drive signal DRV_Gand the multi-level drive signal DRV_MLshown in FIG. 4 represent ideal waveforms. Operating the RF switching circuitry 20 and the switch acceleration circuitry 22 in this manner significantly increases the switching speed of the RF switching circuitry 20 without increasing insertion loss or reducing power handling capability. However, generating the multi-level drive signal DRV_MLmay require a significant increase in area and complexity of the RF switching circuitry 20 due to the requirement that the multi-level drive signal DRV_MLrange from the negative power supply voltage V_NNto the over-voltage V_O. As discussed above, gate drive signals for RF switches are generally provided by a gate driver that is capable of providing voltages between the negative power supply voltage V_NNand the positive power supply voltage V_PP. Those skilled in the art will appreciate that the positive power supply voltage V_PPmay be provided by a regulated voltage source (e.g., a main power supply), while the negative power supply voltage V_NNmay be generated from the positive power supply voltage V_PPusing a charge pump. To provide the over-voltage V_Oaccording to conventional means, an additional charge pump would be required. Since charge pumps consume a relatively large area in a device, this would significantly increase the area and complexity of the RF switching circuitry 20 and thus may be unsuitable for certain applications (e.g., mobile devices) in which space is limited.

To solve this problem, FIG. 5 shows the RF switching circuitry 20 and the switch acceleration circuitry 22 according to one embodiment of the present disclosure. The RF switching circuitry 20 is substantially similar to that described above with respect to FIG. 3. The switch acceleration circuitry 22 includes the bypass FET 32, acceleration control signal generator circuitry 34, and multi-level driver circuitry 36. The acceleration control signal generator circuitry 34 is configured to receive a switching control signal CNT_SWfrom a switching control signal input node 38 and provide a delayed switching control signal CNT_SWDand an acceleration control signal CNT_ACC. The delayed switching control signal CNT_SWDis provided to a gate driver 40, which provides one of the positive power supply voltage V_PPand the negative power supply voltage V_NNas the gate drive signal DRV_Gto the gate drive node 30. The switching control signal CNT_SW, the delayed switching control signal CNT_SWD, and the acceleration control signal CNT_ACCmay be digital or logic-level signals (e.g., from 0V to 2.5V). Accordingly, the acceleration control signal generator circuitry 34 may be digital circuitry, the details of which are discussed below. The gate driver 40 may provide the negative power supply voltage V_NNwhen the delayed switching control signal CNT_SWDis low and provide the positive power supply voltage V_PPwhen the delayed switching control signal CNT_SWDis high.

The multi-level driver circuitry 36 is configured to receive the acceleration control signal CNT_ACCand provide the multi-level drive signal DRV_MLto the bypass FET 32. Specifically, the multi-level driver circuitry 36 uses a built-in capacitance of the bypass FET 32 to provide the multi-level drive signal DRV_MLusing only the positive power supply voltage V_PPand the negative power supply voltage V_NN, thereby foregoing the need for additional charge pumps or other voltage generators in the RF switching circuitry 20 as discussed below.

FIG. 6 shows details of the acceleration control signal generator circuitry 34 according to one embodiment of the present disclosure. The signal delay circuitry includes an exclusive-NOR gate 42 and a number of inverters 44. The exclusive-NOR gate 42 includes a first input node 46A and a second input node 46B. The first input node 46A is coupled to a switching control signal input node 48, at which the switching control signal CNT_SWis provided. The inverters 44 are coupled in series between the switching control signal input node 48 and the second input node 46B. An output of the exclusive-NOR gate 42 is coupled to an acceleration control signal output node 50, which provides the acceleration control signal CNT_ACC. A delayed switching control signal output node 52 is coupled to an output of one of the inverters 44 that is not directly coupled to the second input node 46B of the exclusive-NOR gate 42. Those skilled in the art will appreciate that the acceleration control signal generator circuitry 34 shown in FIG. 6 is merely exemplary. That is, there are any number of ways to create the acceleration control signal CNT_ACCand the delayed switching control signal CNT_SWDfrom the switching control signal CNT_SW, all of which are contemplated herein.

FIG. 7 illustrates exemplary waveforms for the switching control signal CNT_SW, the acceleration control signal CNT_ACC, and the delayed switching control signal CNT_SWDaccording to one embodiment of the present disclosure. As illustrated, when the switching control signal CNT_SWtransitions from low to high, the acceleration control signal CNT_ACCtransitions from high to low since the first input node 46A of the exclusive-NOR gate 42 is high while the second input node 46B is low. As the rising edge of the switching control signal CNT_SWpropagates through each of the inverters 44, the switching control signal CNT_SWis inverted and slightly delayed. When the rising edge of the switching control signal CNT_SWreaches the delayed switching control signal output node 52, the delayed switching control signal CNT_SWDtransitions from low to high. The delay between the rising edge of the switching control signal CNT_SWand the delayed switching control signal CNT_SWDis determined by the number of inverters 44 between the switching control signal input node 48 and the delayed switching control signal output node 52. The rising edge of the switching control signal CNT_SWcontinues propagating through the remaining inverters 44 between the delayed switching control signal output node 52 and the second input node 46B of the exclusive-NOR gate 42, where it eventually causes the acceleration control signal CNT_ACCto transition from low to high due to the fact that both the first input node 46A and the second input node 46B of the exclusive-NOR gate 42 are high at this point.

When the switching control signal CNT_SWtransitions from high to low, the acceleration control signal CNT_ACCtransitions from high to low since the first input node 46A of the exclusive-NOR gate 42 is now low while the second input node 46B is high. The falling edge of the switching control signal CNT_SWthen propagates through the inverters 44 to the delayed switching control signal output node 52, causing the delayed switching control signal CNT_SWDto transition from high to low. When the falling edge of the switching control signal CNT_SWpropagates through the remaining inverters 44 between the delayed switching control signal output node 52 and the second input node 46B of the exclusive-NOR gate 42, the acceleration control signal CNT_ACCtransitions from low to high because both the first input node 46A and the second input node 46B of the exclusive-NOR gate 42 are now low.

FIG. 8 shows the multi-level driver circuitry 36 according to one embodiment of the present disclosure. For context, the bypass FET 32, the gate driver 40, and the common resistor R_Dare also shown. The multi-level driver circuitry 36 includes a first multi-level driver FET 54, a second multi-level driver FET 56, a first sub-driver 58, and a second sub-driver 60. The first multi-level driver FET 54 includes a drain (D) configured to receive the positive power supply voltage V_PP, a source (S) coupled to an anode (A) of a multi-level driver diode 62, and a gate (G) coupled to an output of the first sub-driver 58. An input of the first sub-driver 58 is coupled to an acceleration control signal input node 64. A cathode (C) of the multi-level driver diode 62 is coupled to a multi-level drive signal output node 66. The second multi-level driver FET 56 includes a drain (D) coupled to the multi-level drive signal output node 66, a source (S) coupled to an output of the second sub-driver 60, and a gate (G) coupled to the output of the first sub-driver 58. An input of the second sub-driver 60 is configured to receive the delayed switching control signal CNT_SWD. An output resistor R_Ois coupled between the multi-level drive signal output node 66 and the gate (G) of the bypass FET 32. A number of overvoltage protection diodes 68 are coupled anode (A) to cathode (C) between the gate (G) of the bypass FET 32 and an output of the gate driver 40.

In one embodiment, the first multi-level driver FET 54 is a p-channel depletion mode metal-oxide semiconductor FET (MOSFET) configured to be on when a voltage below a threshold voltage of the device is provided at the gate (G) and turn off when a voltage above the threshold voltage of the device is provided at the gate (G). The first sub-driver 58 may be configured to provide one of the positive power supply voltage V_PPand the negative power supply voltage V_NNat the output thereof based on the acceleration control signal CNT_ACC. Specifically, the first sub-driver 58 may provide the positive power supply voltage V_PPat the output thereof when the acceleration control signal CNT_ACCis high and provide the negative power supply voltage V_NNat the output thereof when the acceleration control signal CNT_ACCis low. The second multi-level driver FET 56 may be an n-channel enhancement mode MOSFET configured to be off when a voltage below a threshold voltage of the device is provided at the gate (G) and turn on when a voltage above the threshold voltage of the device is provided at the gate (G). The second sub-driver 60 may be configured to provide one of the negative power supply voltage V_NNor ground to the source (S) of the second multi-level driver FET 56 based on the delayed switching control signal CNT_SWD. Specifically, the second sub-driver 60 may be configured to couple the output thereof to ground when the delayed switching control signal CNT_SWDis high and provide the negative power supply voltage V_NNat the output thereof when the delayed switching control signal CNT_SWDis low.

When the switching control signal CNT_SWis low and the RF switching circuitry 20 is in a steady-state condition, the acceleration control signal CNT_ACCis high and the delayed switching control signal CNT_SWDis low. In response to these control signals, the first sub-driver 58 provides the positive power supply voltage V_PPat the output thereof and the second sub-driver 60 provides the negative power supply voltage V_NNat the output thereof. The first multi-level driver FET 54 is thus off (depletion mode) while the second multi-level driver FET 56 is on (enhancement mode). Accordingly, the multi-level drive signal output node 66 is coupled to the negative power supply voltage V_NNand held there, as illustrated in the first portion of the multi-level drive signal DRV_MLshown in FIG. 4. When the switching control signal CNT_SWtransitions from low to high, the acceleration control signal CNT_ACCtransitions from high to low. Accordingly, the first sub-driver 58 provides the negative power supply voltage V_NNat the output thereof, causing the first multi-level driver FET 54 to turn on and the second multi-level driver FET 56 to turn off. The multi-level drive signal output node 66 is thus coupled to VPP through the first multi-level driver FET 54. The gate drive signal DRV_Gis still at the negative power supply voltage V_NNat this time. To avoid overloading the bypass FET 32 with a large gate-to-source or gate-to-drain voltage, the overvoltage protection diodes 68 limit the voltage at the multi-level drive signal output node 66. In one embodiment, the overvoltage protection diodes 68 limit the voltage at the multi-level drive signal output node 66 to −2.5V above a voltage of the gate drive signal DRV_G.

Those skilled in the art will appreciate that the bypass FET 32 has an associated gate capacitance. As the delayed switching control signal CNT_SWDtransitions from low to high causing the output of the gate driver 40 to slew from the negative power supply voltage V_NNto the positive power supply voltage V_PP, the charge stored in the gate capacitance of the bypass FET 32 allows the gate (G) thereof and thus the multi-level drive signal output node 66 to float above the positive power supply voltage V_PP. The multi-level driver diode 62 prevents current from flowing back into the multi-level drive signal output node 66 in order to keep the charge in the gate capacitance of the bypass FET 32. This ensures a headroom between the gate drive signal DRV_Gand the multi-level drive signal DRV_MLas shown in FIG. 4. As discussed above, this headroom ensures that the bypass FET 32 remains on throughout the transition of the FETs 24 in the RF switching circuitry 20 from off to on, thereby bypassing the common resistor R_Dduring the transition and significantly improving switching times.

The transition from low to high of the delayed switching control signal CNT_SWDalso causes the second sub-driver 60 to couple the output thereof to ground. As the acceleration control signal CNT_ADDtransitions from low to high, the first sub-driver 58 provides the positive power supply voltage V_PPat the output thereof, thereby turning the first multi-level driver FET 54 off and the second multi-level driver FET 56 on. Accordingly, the multi-level drive signal output node 66 is effectively coupled to ground. The same process is effectively reversed when turning the FETs 24 in the RF switching circuitry 20 from on to off.

Notably, the multi-level driver circuitry 36 shown in FIG. 8 is merely exemplary. Those skilled in the art will appreciate that the functionality of the multi-level driver circuitry 36 may be implemented in any number of ways, all of which are contemplated herein. In general, the multi-level driver circuitry 36 is able to generate a multi-level drive signal DRV_MLusing only the positive power supply voltage V_PPand the negative power supply voltage V_NNwithout using any additional charge pumps. To do so, the multi-level driver circuitry 36 leverages a built-in gate capacitance of the bypass FET 32. Doing so allows for lean and simple circuitry that is able to increase the switching speed of RF switching circuitry 20 using a single control signal.

In addition to bypassing the common resistor R_C, the principles of the present disclosure may also be used to bypass one or more of the gate resistors R_Gand/or one or more drain-source bias resistors R_DSas illustrated in FIG. 9. Those skilled in the art will appreciate that the RF switching circuitry 20 may include the drain-source bias resistors R_DSbetween a drain (D) and a source (S) of each one of the FETs 24. Additional bypass FETs 70 may be provided in order to bypass one or more of these drain-source bias resistors R_DSand/or one or more of the gate resistors R_G. The same multi-level drive signal DRV_MLmay be used for each one of these additional bypass FETs 70, or additional multi-level drive signals DRV_MLmay be generated on an individual or group basis for these additional bypass FETs 70 using the principles described throughout the present disclosure.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.