Cascode switches including normally-off and normally-on devices and circuits comprising the switches

Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described.

HIGH FREQUENCY SWITCH CIRCUIT

A high frequency switch circuit including: a first rectifier circuit including at least one rectifier element having one end connected between the gate terminal of a first MOSFET circuit and a first control terminal and the other end connected to ground, and a second rectifier circuit including at least one rectifier element having one end connected between the gate terminal of a second MOSFET circuit and a second control terminal and the other end connected to ground. The circuit further includes a connecting section connecting the forward-current input terminal side of at least one of the rectifier elements of the first rectifier circuit and one of the main terminal sides of the first MOSFET circuit, and connecting the forward-current input terminal side of at least one of the rectifier elements of the second rectifier circuit and one of the main terminal sides of the second MOSFET circuit. 1. A high frequency switch circuit that makes use of a first control voltage applied to a first control terminal for controlling the connection between a common signal terminal and a first signal terminal and/or a second control voltage applied to a second control terminal for controlling the connection between the common signal terminal and a second signal terminal , whereby to selectively switch the connection of the common signal terminal to either the first signal terminal or the second signal terminal , the high frequency switch circuit comprising:a first signal section including a first MOSFET circuit one of whose main terminals is connected to the common signal terminal, the other of whose main terminals is connected to the first signal terminal and whose gate terminal is connected to the first control terminal, and a first rectifier circuit including at least one rectifier element one of whose ends is connected between the gate terminal of the first MOSFET circuit and the first control terminal and the other of whose ends is connected to ground, whereby the direction ...

DIGITALLY CONTROLLED HIGH SPEED HIGH VOLTAGE GATE DRIVER CIRCUIT

The present invention relates to semiconductor technology. In particular, the present invention relates to high-speed, high voltage switching for a high voltage generator for an X-ray system. Switching elements, e.g. IGBTs or MOS-FETs, are employed for high-speed high voltage switching. However, circuit elements or parasitic elements at an input of the switching element limit the switching speed of the switching element. The present invention proposes applying a higher than allowed voltage to the input of the switching element, e.g. a voltage higher than the maximum allowed gate voltage of an IGBT or MOS-FET, to increase switching speed. A feedback loop is provided for save operation. thus, a switching circuit () for high speed switching is provided, comprising an amplifier circuit (), comprising an output () being adapted to be connectable to an input () of a switching arrangement (), wherein the voltage provided by the output () exceeds a maximum gate voltage, wherein the amplifier circuit () is controllable so that a current internal gate voltage does not to exceed the maximum internal gate voltage. 12. Switching arrangement () , comprising{'b': '8', 'i': 'b', 'an input (), and'}{'b': '4', 'at least one switching element (), comprising'}{'b': '10', 'an internal gate port (); and'}an output port;{'b': 4', '10, 'wherein the switching element () is adapted for switching a high voltage at the output port in response to a voltage received at the internal gate port ();'}{'b': '10', 'wherein a maximum internal gate voltage is defined for the internal gate port ();'}{'b': 6', '8', '10, 'i': a,b', 'b, 'wherein at least one circuit element () is arranged between the input () and the internal gate port (); and'}{'b': 4', '10, 'i': 'b', 'sub': 'gate', 'wherein the switching element () comprises a tap port () for providing the current internal gate voltage U.'}22. Switching arrangement () according to claim 1 ,{'b': '4', 'wherein the switching element () is at least one ...

Gate drive circuit

A gate drive circuit for driving an IGBT serving as a power semiconductor device includes a constant-current gate drive circuit that charges a gate capacity of the IGBT at a constant current, and a constant-voltage gate drive circuit that is connected in parallel to the constant-current gate drive circuit between input and output terminals thereof via a series circuit constituted by a MOSFET and a resistor, and charges the gate capacity of the IGBT at a constant voltage, wherein the gate drive circuit charges the gate capacity of the IGBT using both the constant-current gate drive circuit and the constant-voltage gate drive circuit at the time of driving the IGBT.

DRIVER FOR SWITCHING ELEMENT AND CONTROL SYSTEM FOR ROTARY MACHINE USING THE SAME

In a driver, a discharging module discharges, at a discharging rate, the on-off control terminal of a switching element in response to a drive signal being shifted from an on state to an off state. A changing module determines whether a condition including a level of a sense signal being higher than a threshold level during the on state of the drive signal is met, and changes the discharging rate of the on-off control terminal in response to the drive signal being shifted from the off state to the on state upon determination that the condition is met. A loosening module loosens the condition after a lapse of a period since the shift of the drive signal from the off state to the on state in comparison to the condition immediately after the shift of the drive signal from the off state to the on state. 1. A driver for driving , in response to a drive signal , a voltage-controlled switching element having a conductive path , an on-off control terminal , and a sense terminal from which a sense signal correlated with an amount of current flowing through the conductive path is output , the driver comprising:a discharging module configured to discharge, at a predetermined discharging rate, the on-off control terminal of the voltage-controlled switching element for changing the voltage-controlled switching element from an on state to an off state in response to the drive signal being shifted from an on state to an off state;a changing module configured to:determine whether a condition for executing reduction of the discharging rate of the on-off control terminal of the voltage-controlled switching element is met, the condition including a level of the sense signal being higher than a threshold level during the on state of the drive signal; andchange the discharging rate of the on-off control terminal in response to the drive signal being shifted from the off state to the on state upon determination that the condition is met; anda loosening module configured to loosen the ...

DRIVE UNIT FOR DRIVING VOLTAGE-DRIVEN ELEMENT

A controller of a drive unit is configured so as to control a voltage supplied to a gate resistor of a voltage-driven element by using of a voltage of a feedback connector when an electrical connection between the feedback connector and the gate resistor of the voltage-driven element is ensured. Further, the controller of the drive unit is configured so as to control the voltage supplied to the gate resistor of the voltage-driven element by using of a voltage of an output connector when the electrical connection between the feedback connector and the gate resistor of the voltage-driven element is not ensured. 1. A drive unit for driving a voltage-driven element , the drive unit comprising:a first connector configured so as to be connected to a gate resistor of the voltage-driven element;a feedback connector configured so as to be connected to the gate resistor of the voltage-driven element;a second connector configured so as to be connected to a driving power source;a switching element having a first input-output electrode connected to the first connector and a second input-output electrode connected to the second connector; anda controller connected to a control electrode of the switching element and the feedback connector, whereinthe controller is configured so as to:(1) control a voltage supplied to the gate resistor of the voltage-driven element by using a voltage at the feedback connector when an electrical connection between the feedback connector and the gate resistor of the voltage-driven element is ensured, and(2) control the voltage supplied to the gate resistor of voltage-driven element by using a voltage at the first connector when the electrical connection between the feedback connector and the gate resistor of the voltage-driven element is not ensured.2. The drive unit according to claim 1 , whereinthe controller includes an error amplifier, a reference power source, and a resistance member,the error amplifier has one input connector connected to the ...

SEMICONDUCTOR DEVICE AND CIRCUIT FOR CONTROLLING POTENTIAL OF GATE OF INSULATED GATE TYPE SWITCHING DEVICE

A semiconductor device outputs a signal to control a gate potential a switching device. The semiconductor device includes a first signal output terminal, and is capable of receiving or internally creating a reference signal, which varies between a first potential and a second potential. The semiconductor device can switch between first and second operations. The first operation outputs to the first signal output terminal a signal that is at a third potential when the reference signal is at the first potential, and that is at a fourth potential higher than the third potential when the reference signal is at the second potential. The second operation outputs to the first signal output terminal a signal that is at the fourth potential when the reference signal is at the first potential, and that is at the third potential when the reference signal is at the second potential. 13-. (canceled)4. A circuit for controlling a potential of a gate of an insulated gate type switching device , the circuit comprising:a semiconductor device comprising a first signal output terminal, and configured to output a signal to control a potential of a gate of an insulated gate type switching device;an inverting circuit connected to the first signal output terminal, and configured to invert the signal output to the first signal output terminal and to output the inverted signal;a first insulated gate type switching device including a gate that is connected the inverting circuit and receives the inverted signal output from the inverting circuit;a second insulated gate type switching device connected to the first insulated gate type switching device in series; anda low potential wiring being at a potential lower than an average potential of the signal output from the inverting circuit;whereinthe semiconductor device is capable of receiving a reference signal or internally creating the reference signal,the semiconductor device is capable of switching between a first operation and a second ...

Circuit Comprising an Accelerating Element

A circuit includes a switching element with a first terminal, a second terminal and a control terminal. The circuit also includes an impedance network coupled between the control terminal and a switching node. The circuit also includes a first accelerating element coupled between the control terminal and a first node. The first node is different from the switching node. The circuit is configured to temporarily activate the first accelerating element when a switching state of the switching element is to be changed. 1. A circuit , comprising:a switching element with a first terminal, a second terminal and a control terminal;an impedance network coupled between the control terminal and a switching node; anda first accelerating element coupled between the control terminal and a first node, the first node being different from the switching node;wherein the circuit is configured to temporarily activate the first accelerating element when a switching state of the switching element is to be changed.2. The circuit of claim 1 , wherein the first node is the first terminal.3. The circuit according to claim 1 , wherein the first accelerating element is coupled with a first terminal to the control terminal of the switching element and is configured to temporarily charge or discharge the control terminal when a switching state of the switching element is to be changed; andwherein a second accelerating element is coupled with a first terminal to the control terminal of the switching element and is configured to temporarily charge or discharge the control terminal when a switching state of the switching element is to be changed.4. The circuit according to claim 1 , wherein the first accelerating element is coupled with a first terminal to the control terminal of the switching element and is configured to temporarily charge or discharge the control terminal when a switching state of the switching element is to be changed.5. The circuit according to claim 1 , wherein a first device ...

Active-matrix substrate, display panel and display device including the same

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate ( 20 a ) are provided gate lines ( 13 G) and source lines. On the active-matrix substrate ( 20 a ) are further provided: gate drivers ( 11 ) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line ( 13 G); and lines ( 15 L 1 ) each for supplying a control signal to the associated gate driver ( 11 ). A control signal is supplied by a display control circuit ( 4 ) located outside the display region to the gate drivers ( 11 ) via the lines ( 15 L 1 ). In response to a control signal supplied, each gate driver ( 11 ) drives the gate line ( 13 G) to which it is connected.

SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD

A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor. 1a power transistor;a gate resistor connected between a gate of the power transistor and a connecting point in a drive circuit of the power transistor,a switchable element connected between the connecting point and a source of the power transistor, the switchable element being configured such that when the power transistor isin a turn-on state, a voltage value of the connecting point is high, a voltage value at the gate is low and the switchable element is off,in an on-state, the voltage value of the connecting point is high, the voltage value at the gate is high and the switchable element is off,in a turn-off state, the voltage value of the connecting point is low, the voltage value at the gate is high and the switchable element is on, andin an off-state, the voltage value of the connecting point is low, the voltage value at the gate is low and the switchable element is on.. A semiconductor device comprising: This Utility Patent Application is a continuation application of U.S. application Ser. No. 13/799,641, filed Mar. 13, 2013, which is a continuation application of U.S. application Ser. No. 12/873,902, filed Sep. 1, 2010, now U.S. Pat. No. 8,427,207, which is a divisional application of U.S. application Ser. No. 12/036,823, filed Feb. 25, 2008; all of which are incorporated herein by reference.This disclosure relates to a semiconductor device arrangement with at least one power transistor and at least one gate resistor, the power transistor having an extremely high switching speed owing to very low device capacitances. In the turn-off process, the so-called decommutation process, ...

Anti-ringing technique for switching power stage

A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.

High-Speed Switch with Accelerated Switching Time

A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch. 1. A multiport switch comprising: (1) switch control input;', '(2) a field effect transistor (FET) having a gate, source and drain;', '(3) a reset circuit having an signal input, signal output, reset control input and reference input signal output being coupled to the gate of the FET, the reset circuit configured to reset the FET by connecting the gate of the FET to the signal input when the reset circuit is inactive and to the reference input when the reset circuit is active;, '(a) at least one switch branch comprising(b) a reset processor having a reset processor input coupled to the switch control input and a reset processor output coupled to the reset control input, the reset processor configured to output a reset pulse from the reset processor output in response to a change in the state of a signal received at the reset processor input.2. The switch of claim 1 , having four switch branches claim 1 , two signal inputs and a common port claim 1 , the first of the four switch branches configured to connect the first signal input to the common port and the second switch branch configured to connect the second signal input to ground during a first mode of operation claim 1 , the third and fourth switch branches being open during the first mode of ...

Methods and Devices to Improve Switching Time by Bypassing Gate Resistor

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained. 1. A switching circuit comprising:an input terminal; a series arrangement of a plurality of main FET switches, and', 'a plurality of main bypass switch blocks,, 'a main switch stack comprisingwherein: the input terminal at a first end, and', 'corresponding gates of the plurality of the main FET switches at a second end;, 'i) each main bypass switch block of the plurality of the main bypass switch blocks comprises a bypass switch coupling across a main gate resistor, the main gate resistors being coupled withii) the switching circuit is configured to receive a control voltage applied at the input terminal, the control voltage being configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa, andiii) the bypass switches are configured to be open when the plurality of the main FET switches are in the OFF or the ON state and to be closed when the plurality of the main switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the main gate resistors.2. The switching circuit of claim 1 , wherein: a series arrangement of a plurality of first bypass FET switches;', 'a series arrangement of a plurality of second bypass FET switches;', 'a plurality of first bypass gate resistors coupled with corresponding gates of the plurality of the first bypass FET switches and coupled with the input terminal; and', 'a plurality of second bypass gate resistors coupled with corresponding gates of ...

CIRCUIT ARRANGEMENT FOR PRECHARGING AN INTERMEDIATE CIRCUIT CAPACITANCE OF A HIGH-VOLTAGE ON-BOARD NETWORK

The present invention relates to a circuit arrangement for switching a high-voltage MOSFET () for precharging an intermediate circuit capacitance of a high-voltage on-board network with a first circuit assembly (), by means of which the switching times of a high-voltage MOSFET used for charging the intermediate circuit capacitance can be reduced. 2. The circuit arrangement as claimed in claim 1 , wherein the output terminal is connected to a gate of the high-voltage MOSFET.31. The circuit arrangement as claimed in claim 1 , wherein a capacitance (C) is connected between the first input terminal and the second input terminal.412. The circuit arrangement as claimed in claim 1 , further comprising a second circuit assembly () claim 1 , the second circuit assembly comprising:a third input terminal,{'b': 3', '3, 'a first energy store (C) including a passive discharge means (R),'}{'b': '4', 'a first switch (T),'}{'b': '5', 'a second switch (T),'}a second output terminal,a third and a fourth output terminal,{'b': '2', 'a second ohmic resistor (R) and'}{'b': 4', '3', '4', '4', '4', '5', '2', '4', '2', '5', '4', '5, 'a third ohmic resistor (R), wherein the first energy store (C) is connected to the third input terminal and is configured to supply energy to a control input of the first switch (T), the first switch (T) and the third ohmic resistor (R) are connected to a control connection of the second switch (T), a third connection of the second ohmic resistor (R) and the third ohmic resistor (R) is connected to the second output terminal, the second ohmic resistor (R) is connected to the second switch (T), and a fourth connection of the first switch (T) and the second switch (T) is connected to the fourth output terminal, and wherein the third output terminal is connected to the first input terminal and the fourth output terminal is connected to the second input terminal.'}5457456. The circuit arrangement as claimed in claim 1 , the circuit arrangement further comprising a ...

FAULT TOLERANT LOW LEAKAGE SWITCH

Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET. 1. A semiconductor die with fault tolerant switching , the semiconductor die comprising:a first pad and a second pad;a switch including a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series between the first pad and the second pad in a first voltage domain;a gate driver configured to control a gate voltage of the switch PFET and a gate voltage of the switch NFET, wherein the gate driver is in a second voltage domain; and a first diode and a first clamp FET in series between the first pad and the second pad, and', 'a first gate bias circuit configured to bias a gate of the first clamp FET., 'a clamp electrically connected in parallel with the switch, the clamp including a forward protection circuit including2. The semiconductor die of claim 1 , wherein the clamp further comprises a reverse protection circuit including a second diode and a second clamp FET in series between the first pad and the second pad claim 1 , and a second gate bias circuit configured to bias a gate of the second clamp FET claim 1 , wherein an anode of the first diode and a cathode of the second diode are electrically connected to a common node.3. The ...

CONTROL CIRCUIT AND CONTROL METHOD FOR SWITCH CIRCUIT AND SWITCHING-MODE POWER SUPPLY CIRCUIT

The present invention provides a control circuit and a control method for a switch circuit and a switching-mode power supply circuit. The control method comprises following steps: detecting an output voltage or an output current, and adjusting an upper limit value and a lower limit value of an inductor current according to a result of comparing the output voltage or the output current with the corresponding reference; and sampling the inductor current, and controlling a main switch transistor in the circuit to be switched off when a sampling current rises to the upper limit value, and controlling the main switch transistor to be switched on when the sampling current drops to the lower limit value. In the present invention, the inductor current is fast in response without overshoot, the output voltage drops very little, there is no overshoot in a process of voltage recovery, and circuit transient response is fast. 1. A control method for a switch circuit , comprising following steps:detecting an output voltage or output current in a circuit, and increasing an upper limit value and a lower limit value of an inductor current when the output voltage is lower than a preset reference voltage or the output current is lower than a preset reference current; and decreasing the upper limit value and the lower limit value of the inductor current when the output voltage is higher than the preset reference voltage or the output current is higher than the preset reference current; andsampling the inductor current in the circuit to obtain a sampling current, and controlling a main switch transistor in the circuit to be switched off when the sampling current rises to the upper limit value of the inductor current; and controlling the main switch transistor to be switched on when the sampling current drops to the lower limit value of the inductor current.2. The control method for the switch circuit according to claim 1 , wherein detecting the output voltage or the output current in ...

Feed-Forward Current Compensation for CMOS Signal Path

An integrated circuit has a CMOS signal path coupled for receiving a data signal. A compensation circuit is coupled to a power supply rail of the CMOS signal path for injecting a compensation current into the power supply rail. The compensation circuit can be a charge pump operating in response to the data signal to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a replica CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a voltage regulator and current mirror including an input coupled to the voltage regulator. The replica CMOS signal path receives an operating potential from the voltage regulator. An output of the current mirror injects the compensation current into the power supply rail each transition of the data signal. 1. A semiconductor device , comprising:a CMOS signal path including an input coupled for receiving a data signal from a data terminal; anda replica CMOS signal path including an input coupled for receiving the data signal and an output providing a compensation current into a first power supply rail of the CMOS signal path each transition of the data signal.2. The semiconductor device of claim 1 , wherein the CMOS signal path includes a plurality of serially coupled buffers or inverters.3. The semiconductor device of claim 1 , wherein the replica CMOS signal path includes a plurality of serially coupled buffers or inverters.4. The semiconductor device of claim 1 , further including a voltage regulator coupled to the first power supply rail of the CMOS signal path.5. The semiconductor device of claim 1 , further including a level shifter coupled between the data terminal and the input of the replica CMOS signal path.6. The semiconductor device of claim 1 , further including a capacitor coupled between the first power supply rail of the CMOS signal path and a second power ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor layer, a first conductor disposed on the semiconductor layer, a second conductor disposed on the semiconductor layer so as to be separated from the first conductor, a relay portion that is formed on the semiconductor layer so as to straddle the first conductor and the second conductor and that is made of a semiconductor having a first conductivity type region and a second conductivity type region, a first contact by which the first conductivity type region and the second conductivity type region are electrically connected to the first conductor, and a second contact that electrically connects the first conductivity type region of the relay portion and the second conductor together and that is insulated from the second conductivity type region. 1. A semiconductor device comprising:a semiconductor layer;a first conductor disposed on the semiconductor layer;a second conductor disposed on the semiconductor layer so as to be separated from the first conductor;a relay portion that is formed on the semiconductor layer so as to straddle the first conductor and the second conductor and that is made of a semiconductor having a first conductivity type region and a second conductivity type region;a first contact by which the first conductivity type region and the second conductivity type region are electrically connected to the first conductor; anda second contact that electrically connects the first conductivity type region of the relay portion and the second conductor together and that is insulated from the second conductivity type region.2. The semiconductor device according to claim 1 , further comprising a functional element formed at the semiconductor layer claim 1 , whereinthe first conductor includes an external terminal to which electric power is supplied from outside, andthe second conductor includes a wiring that supplies electric power supplied to the first conductor to the functional element.3. The semiconductor ...

BOOTSTRAPPED SWITCHING CIRCUIT

The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology. 1. A bootstrapped switching circuit with accelerated turn on , comprising:a sampling switch receiving a voltage input signal and a gate voltage;a bootstrapped voltage generator comprising a positive feedback loop to generate the gate voltage for turning on the sampling switch, said positive feedback loop comprising an input transistor receiving the voltage input signal and an output transistor outputting the gate voltage of the sampling switch; anda jump start circuit to turn on the output transistor for a limited period of time during which the input transistor is turning on at a startup of the positive feedback loop.2. The bootstrapped switching circuit of claim 1 , wherein the jump start circuit is coupled to a gate of the output transistor.3. The bootstrapped switching circuit of claim 1 , wherein the jump start circuit ceases to turn on the output transistor after the limited period of time and allows the positive feedback loop to operate.4. The bootstrapped switching circuit of claim 1 , wherein:the jump start circuit comprises a transistor receiving a clock signal used for activating the positive feedback loop; andthe transistor is turned on by a delayed version of the clock signal to output the clock signal to turn on the output transistor for the limited period of time.5. The bootstrapped switching circuit of claim 4 , wherein the jump start circuit further comprises two ...

INPUT BUFFER

The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology. 1. An input buffer comprising:an input receiving a voltage input signal;a push pull circuit outputting a voltage output signal at an output, wherein the push pull circuit comprises a first transistor of a first type, a second transistor of a second type complementary to the first type; anda first level shifter coupled to the input for shifting a voltage level of the voltage input signal by a first amount of voltage shift across the first level shifter and generating a first level shifted voltage signal to bias the first transistor, wherein the first amount of voltage shift provided by the first level shifter is independent of a frequency of the voltage input signal.2. The input buffer of claim 1 , further comprising:a second level shifter coupled to the input for shifting the voltage level of the voltage input signal by a second amount of voltage shift across the second level shifter and generating a second level shifted voltage signal to bias the second transistor.3. The input buffer of claim 1 , wherein the first amount of voltage shift is programmable.4. The input buffer of claim 1 , wherein an amount of current claim 1 , flowing through a resistive element and provided by one or more current sources claim 1 , sets the first amount of voltage shift across the first level shifter.5. The input buffer of claim 2 , wherein a sum of the first amount of voltage shift and the second amount ...

Systems and methods for controlling switching circuitry

An electronic device for controlling switching circuitry is described. The electronic device includes line voltage measuring circuitry configured to measure a line voltage to produce a line voltage measurement. The electronic device also includes load voltage measuring circuitry configured to measure a load voltage to produce a load voltage measurement. The electronic device further includes a processor coupled to the line voltage measuring circuitry and the load voltage measuring circuitry. The processor is configured to adjust a control signal for a transition of the switching circuitry based on the line voltage measurement and the load voltage measurement to minimize heat generation and electromagnetic interference creation by the switching circuitry.

Driver device for transistors, and corresponding integrated circuit

A driver device is for switching on and off a transistor for supplying a load by driving a control electrode of the transistor. The driver device includes a first terminal connected to the control electrode of the transistor, a second terminal connected between the transistor and the load, and a current-discharge path coupled to the first terminal. The current-discharge path includes a diode and is activated when the transistor is switched off. The diode becomes non-conductive to interrupt the current-discharge path when the voltage on the second terminal reaches a threshold value.

Semiconductor device and semiconductor device control methods

Methods of controlling semiconductor device and semiconductor device are provided in which a semiconductor device can define a normally operational ambient temperature at a low level. The Microcontroller includes a logical block, a temperature sensor for measuring junction temperature, a power consumption circuit for consuming predetermined power, and a Controller for controlling the consumption of power by the power consumption circuit such that the temperature measured at the temperature sensor is not less than a predetermined operational lower limit temperature of the logical block 110.

ACTIVE-MATRIX SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate () are provided gate lines (G) and source lines. On the active-matrix substrate () are further provided: gate drivers () each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (G); and lines (L) each for supplying a control signal to the associated gate driver (). A control signal is supplied by a display control circuit () located outside the display region to the gate drivers () via the lines (L). In response to a control signal supplied, each gate driver () drives the gate line (G) to which it is connected. 1. An active-matrix substrate comprising:a plurality of data lines;a plurality of lines crossing the plurality of data lines and including at least gate lines; anda driving circuit connected with at least one of the plurality of lines for controlling a potential of this line in response to a control signal supplied from outside a display region that includes pixel regions defined by the data lines and the gate lines,wherein the driving circuit includes a plurality of switching elements,the driving circuit is connected with one of the gate lines and controls the potential of this gate line by applying one of a selection voltage and a non-selection voltage to the gate line in response to the control signal, andthe switching elements include a first switching element that is located over two of the pixel regions.2. The active-matrix substrate according to claim 1 , further comprising: a pixel electrode located in one of the pixel regions and connected with one of the gate lines and one of the data lines claim 1 ,wherein a shield layer made of transparent conductive film is provided between one of the switching ...

CASCODE SWITCHES INCLUDING NORMALLY-OFF AND NORMALLY-ON DEVICES AND CIRCUITS COMPRISING THE SWITCHES

Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described. 127- (canceled)28. A switch comprising:a normally-on semiconductor device comprising a gate, a source and a drain;a normally-off semiconductor device comprising a gate, a source and a drain coupled to the normally-on semiconductor device, wherein the source of the normally-on semiconductor device is coupled to the drain of the normally-off semiconductor device and the gate of the normally-on semiconductor device is coupled to the source of the normally-off semiconductor device; andan avalanche prevention circuit coupled across the normally-off semiconductor device, wherein the avalanche prevention circuit relieves the normally-off semiconductor device of avalanche energy.29. The switch of claim 28 , wherein the avalanche prevention circuit relieves the normally-off semiconductor device of avalanche energy when a voltage on the drain of the normally-off semiconductor device goes high.30. The switch of claim 28 , wherein the avalanche prevention circuit comprises a Zener diode claim 28 , wherein an anode of the Zener diode is coupled ...

GATE DRIVER CIRCUIT, MOTOR DRIVER CIRCUIT, AND HARD DISK APPARATUS

A gate driver circuit drives a switching transistor. A variable current source generates a reference current configured to switch between a first current amount and a second current amount smaller than the first current amount. A current distribution circuit is configured to switch between a source enabled state in which a source current proportional to the reference current is sourced to a gate node of the switching transistor and a disabled state in which the source current is made equal to zero. A first transistor fixes the gate node of the switching transistor to a high voltage in an on-state of the first transistor. A second transistor fixes the gate node of the switching transistor to a low voltage in an on-state of the second transistor. 1. A gate driver circuit that drives a switching transistor , comprising:a variable current source that generates a reference current configured to switch between a first current amount and a second current amount smaller than the first current amount;a current distribution circuit configured to switch between a source enabled state in which a source current proportional to the reference current is sourced to a gate node of the switching transistor and a disabled state in which the source current is made equal to zero;a first transistor that fixes the gate node of the switching transistor to a high voltage in an on-state of the first transistor; anda second transistor that fixes the gate node of the switching transistor to a low voltage in an on-state of the second transistor.2. The gate driver circuit according to claim 1 , whereinthe variable current source is configured to switch between an on-state and an off-state, and a first current source that, in the on-state, generates a first current that defines a slew rate of the switching transistor, and', 'a second current source that generates a second current smaller than the first current., 'the variable current source includes'}3. The gate driver circuit according to claim ...

RADIO FREQUENCY SWITCH WITH IMPROVED SWITCHING TIME

A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load. 1. A radio frequency (RF) switch comprising:an RF domain section having a plurality of RF switching elements;a DC domain section having circuitry configured for controlling the RF switching elements in response to one or more control signals; wherein the DC domain section comprises an oscillator for generating a clock signal, the oscillator includes a biasing stage having a variable resistive load which is configurable for varying the frequency of the clock signal during determined time periods, anda detection section configured for determining when to vary the variable resistive load when at least one signal derived from the one or more control signals is transitioning between logic states.2. An RF switch as claimed in claim 1 , further comprising a resistive load provided between the RF domain section and the DC domain section; anda bypass circuit configured for selectively bypassing at least a portion of the resistive load.3. An RF switch as claimed in claim 2 , wherein the resistive load comprises a resistor element.4. An RF switch as claimed in claim 3 , further comprising at least one filter which includes the resistor element.5. A RF switch as claimed in claim 4 , wherein the resistive load further comprises an equivalent resistance provided between an output node of the filter and a terminal of an RF switching element.6. An RF switch as claimed in claim 2 , wherein the bypass circuit is selectively controlled for bypassing at least a portion of the resistive load at determined time periods.7. An RF switch as claimed in ...

Driving apparatus for driving switching elements of power conversion circuit

A driving apparatus for driving switching elements of a power conversion circuit. In the apparatus, a first determination unit determines whether or not a dead time that occurs immediately after a setting of discharge rate is changed is greater than the dead time assumed at the time of designing. When the dead time occurring immediately after the setting of discharge rate is changed is greater than the dead time assumed at the time of designing, a shift unit shifts in time at least one of transition to an OFF state of one of the upper-arm and lower-arm switching elements and transition to an ON state of the other of the upper-arm and lower-arm switching elements immediately after the transition to the OFF state so as to reduce a time difference between the transition to the OFF state and the transition to the ON state.

Methods and Devices to Improve Switching Time by Bypassing Gate Resistor

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained. 1. (canceled)2. A switching circuit comprising:an input terminal;a series arrangement of a plurality of main FET switches, and an NMOS FET and a PMOS FET, wherein drain terminals of the NMOS FET and the PMOS FET are connected together and source terminals of the NMOS FET and the PMOS FET are connected together, and', 'a main gate resistor coupled across drain-source of each of the NMOS FET and PMOS FET, the main gate resistor coupling the input terminal to a gate terminal of a corresponding main FET switch of the plurality of main FET switches., 'at least one main bypass switch block comprising3. The switching circuit of claim 2 , further comprising an NMOS FET gate resistor and a PMOS FET gate resistor claim 2 , wherein a gate terminal of the NMOST FET is coupled to the input terminal through the NMOS FET gate resistor claim 2 , and a gate terminal of the PMOS FET is coupled to the input terminal through the PMOS FET gate resistor.4. The switching circuit of configured to receive a control voltage applied at the input terminal claim 2 , the control voltage being configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa.5. The switching circuit of claim 4 , wherein the at least one main bypass switch block is configured to be open at least during a portion of a first time interval during which the plurality of the main FET switches are in the OFF or the ON state and to be closed at least during a ...

DIFFERENTIAL OUTPUT CIRCUIT

A differential output circuit includes: input transistors that receive differential input signals; n stages of cascode transistors (n≥2) cascode connected to the input transistors; output terminals connected to the drains of n-th stage cascode transistors; an intermediate potential generating circuit that supplies an intermediate potential of potentials of the output terminals to the gates of the n-th stage cascode transistors; and a dividing circuit that supplies divided potentials resulting from the intermediate potential being divided into (n−1) stages to the respective gates of the (n−1)-th through first stages of the cascode transistors in descending order of potential. 1. A differential output circuit , comprising:a first input transistor and a second input transistor that receive respective differential input signals, the respective differential input signals having mutually inverted phases; andn stages of first cascode transistors (n being a natural number greater than or equal to 2) cascode connected to the first input transistor and n stages of second cascode transistors cascode connected to the second input transistor,wherein when the first cascode transistor connected to a drain of the first input transistor is a first stage first cascode transistor, the first cascode transistor connected farthest from the first input transistor is an n-th stage first cascode transistor, the second cascode transistor connected to a drain of the second input transistor is a first stage second cascode transistor, and the second cascode transistor connected farthest from the second input transistor is an n-th stage second cascode transistor, with respect to each of the n stages, a gate of a k-th stage of the first cascode transistors (1≤k≤n) and a gate of a k-th stage of the second cascode transistors are connected, andthe differential output circuit further comprises:a first output terminal connected to a drain of the n-th stage first cascode transistor;a second output ...

RADIO FREQUENCY SWITCHING CIRCUITRY WITH REDUCED SWITCHING TIME

RF switching circuitry includes a plurality of FETs coupled between an input node, an output node, and a gate drive node. When a positive power supply voltage is provided at the gate drive node, the plurality of FETs turn on and provide a low impedance path between the input node and the output node. When a negative power supply voltage is provided at the gate drive node, the plurality of FETs turn off and provide a high impedance path between the input node and the output node. Switch acceleration circuitry in the RF switching circuitry includes a bypass FET and multi-level driver circuitry. The bypass FET selectively bypasses the common resistor in response to a multi-level drive signal. The multi-level driver circuitry uses a built-in gate to capacitance of the bypass FET to provide the multi-level drive signal at an overvoltage that is above the positive power supply voltage. 1. Radio frequency (RF) switching circuitry comprising:an input node, an output node, and a gate drive node; turn on and provide a low impedance path between the input node and the output node when a gate drive signal at the gate drive node is provided at a positive power supply voltage; and', 'turn off and provide a high impedance path between the input node and the output node when the gate drive signal is provided at a negative power supply voltage, wherein the high impedance path has a higher impedance than the low impedance path; and, 'a plurality of field-effect transistors (FETs) coupled between the input node, the output node, and the gate drive node such that a gate contact of each one of the FETs is coupled to the gate drive node via a common resistor, wherein the plurality of FETs are configured to a bypass FET configured to selectively bypass the common resistor in response to a multi-level drive signal; and', 'multi-level driver circuitry configured to use a built-in gate capacitance of the bypass FET in order to provide the multi-level drive signal at an overvoltage that is ...

GATE DRIVE CONTROL METHOD FOR SiC AND IGBT POWER DEVICES TO CONTROL DESATURATION OR SHORT CIRCUIT FAULTS

A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change. 1. A method of controlling a power semiconductor device by a master control unit (MCU) , the method comprising:determining, by the MCU, a voltage across the power semiconductor device or a current through the power semiconductor device; selecting, by the MCU, a first set of multi-level turn ON/OFF (MLTO) signals that include a first set of voltage levels, and', in a stepwise decreasing manner over a first period of time to turn OFF the power semiconductor device, or', 'in a stepwise increasing manner over the first period of time to turn ON the power semiconductor device; and, 'driving, by the MCU, the power semiconductor device with the first set of MLTO signals], 'in response to the voltage across the power semiconductor device or the current through the power semiconductor device being less than or equal to a predetermined level selecting, by the MCU, a second set of MLTO signals that include a second set of voltage levels, and', in a stepwise decreasing manner over a second period of time to turn OFF the power semiconductor device, or', ...

Gate driver circuit for power converters incorporating normally on transistors and method thereof

The present invention is in relation to a synchronous buck converter comprising gate driver circuit, incorporated with passive elements for conversion of unipolar voltage produced by a standard gate driver to a bipolar voltage along with bootstrap technique to drive the normally on metal oxide semiconductor field effect transistor.

One-Transistor Devices for Protecting Circuits and Autocatalytic Voltage Conversion Therefor

Devices having one primary transistor, or a plurality of primary transistors in parallel, protect electrical circuits from overcurrent conditions. Optionally, the devices have only two terminals and require no auxiliary power to operate. In those devices, the voltage drop across the device provides the electrical energy to power the device. A third or fourth terminal can appear in further devices, allowing additional overcurrent and overvoltage monitoring opportunities. Autocatalytic voltage conversion allows certain devices to rapidly limit or block nascent overcurrents. 1. A device for protecting a circuit having a primary current path from an overcurrent condition , comprising:a first terminal and a second terminal configured to route the primary current path through the device;a first transistor comprising a first gate, a first drain, and a first source;wherein the first transistor is a depletion mode, normally-on transistor;wherein the first transistor is arranged in series in the primary current path between the first terminal and the second terminal;a driver circuitry, the driver circuitry comprising a voltage converter and an oscillator,wherein an output voltage of the voltage converter or a derivative voltage thereof is adapted to be electrically connected to an input of the oscillator,wherein the driver circuitry is configured to convert an input voltage to a first releasably-stored voltage, and wherein the driver circuitry is configured to apply the first releasably-stored voltage or a derivative voltage thereof as a gate voltage at the first gate relative to the first source;wherein, when a first positive voltage and a normal current condition exist from the first terminal to the second terminal, the first transistor is configured to pass current between the first terminal and the second terminal;wherein, when a second positive voltage and an overcurrent condition exist from the first terminal to the second terminal, the driver circuitry is configured to ...

HIGH-SPEED DIGITAL SIGNAL DRIVER WITH LOW POWER CONSUMPTION

The present disclosure provides an inverter driver circuit including: an input configured to receive an input signal; an output configured to provide an output signal; a parallel circuit between the input and the output, wherein the parallel circuit includes a first circuit path parallel to a second circuit path between the input and the output, wherein the first circuit path includes an output sustaining circuit and the second circuit path includes an output driving circuit; and an inverting delay circuit coupled to the output of the inverter driver circuit and coupled to the output driving circuit, wherein the inverting delay circuit is configured to provide a control signal to the output driving circuit, wherein the control signal is a delayed and inverted version of the output signal. 1. An inverter driver circuit comprising:an input configured to receive an input signal;an output configured to provide an output signal;a parallel circuit between the input and the output, wherein the parallel circuit includes a first circuit path parallel to a second circuit path between the input and the output, wherein the first circuit path includes an output sustaining circuit and the second circuit path includes an output driving circuit; andan inverting delay circuit coupled to the output of the inverter driver circuit and coupled to the output driving circuit, wherein the inverting delay circuit is configured to provide a control signal to the output driving circuit, wherein the control signal is a delayed and inverted version of the output signal.2. The inverter driver circuit of claim 1 , wherein the output sustaining circuit includes a first output sustaining transistor and a second output sustaining transistor claim 1 , wherein gates of the first and the second output sustaining transistor are continuously operatively connected to the input and drains of the first and second output sustaining transistors are continuously operatively connected to the output.3. The ...

SWITCHING TIME REDUCTION OF AN RF SWITCH

A switch for a radio frequency signal switch assembly including a first node coupled to one of an input and an output of the switch assembly and a second node coupled to a reference voltage, a control node, a common resistor coupled to the control node, a plurality of transistors coupled between the first and second nodes, each transistor of the plurality of transistors having a gate, a drain, and a source, and a plurality of gate resistors coupled between the common resistor and the gates of the plurality of transistors, the plurality of gate resistors having a scaled arrangement of values selected based on a voltage differential across each of the plurality of gate resistors to improve switching speed. 1. A switch for a radio frequency signal switch assembly comprising:a first node coupled to one of an input and an output of the switch assembly and a second node coupled to a reference voltage;a control node;a common resistor coupled to the control node;a plurality of transistors coupled between the first and second nodes, each transistor of the plurality of transistors having a gate, a drain, and a source; anda plurality of gate resistors coupled between the common resistor and the gates of the plurality of transistors, the plurality of gate resistors having a scaled arrangement of values selected based on a voltage differential across each of the plurality of gate resistors to improve switching speed.2. The switch of wherein a control signal received by the control node is applied to the gates of the plurality of transistors through the common resistor and the plurality of gate resistors.3. The switch of wherein the control signal is configured to operate the switch in an on state by turning on each of the plurality of transistors such that an RF signal received at the first node is provided to the second node.4. The switch of wherein the control signal is configured to operate the switch in an off state by turning off each of the plurality of transistors such ...

DRIVER FOR A POWER FIELD-EFFECT TRANSISTOR, RELATED SYSTEM AND INTEGRATED CIRCUIT

A method of controlling a power field-effect transistor includes controlling a plurality of different phases of a gate-to-source voltage of the power field-effect transistor. Without comparing the gate-to-source voltage of the power field effect transistor to a plurality of reference voltages, the method includes discriminating between the different phases of the gate-to-source voltage based on the plurality of reference voltages. At least one of the plurality of reference voltages is based on a threshold voltage of at least one field-effect transistor. 1. A method of driving a power field-effect transistor , comprising: supplying in the first phase a first charging current to a gate of the power field-effect transistor as long as the voltage between the gate and a source of the power field-effect transistor is less than a first reference voltage;', 'supplying in the second phase a second charging current to the gate of the power field-effect transistor once the voltage between the gate and source of the power field-effect transistor is equal to or greater than the first reference voltage and less than a second reference voltage; and', 'supplying in the third phase a third charging current to the gate of the power field-effect transistor once the voltage between the gate and source of the power field-effect transistor is equal to or greater than the second reference voltage., 'controlling the power field-effect transistor in first, second and third phases to turn on the power field-effect transistor, the controlling including2. The method of claim 1 , wherein supplying in the third phase the third charging current comprises driving the gate to a maximum drive voltage and in a fourth phase maintaining the gate at approximately the maximum drive voltage.3. The method of further comprising controlling the power field-effect transistor in fifth claim 2 , sixth and seventh phases to turn off the power field-effect transistor claim 2 , the controlling including claim 2 , ...

DRIVER CIRCUIT, CORRESPONDING DEVICE, APPARATUS AND METHOD

A (pre) driver circuit includes first and second output terminals configured to be coupled to a power transistor. A differential stage has non-inverting and inverting inputs for receiving an input voltage. The input voltage is replicated as an output voltage across the first and second output terminals as a drive signal for the power transistor. The differential stage includes a differential transconductance amplifier in a voltage follower arrangement configured to provide continuous regulation of a voltage at the first output terminal with respect to the second output terminal. 1. A circuit comprising:a first output terminal configured to be coupled to a control terminal of a power transistor;a second output terminal configured to be coupled to a conduction terminal of the power transistor;a first current generator; and a first transistor having a control terminal coupled to the first current generator, and', 'a second transistor having a current path coupled between a current path of the first transistor and the first output terminal, and a control terminal coupled to the control terminal of the first transistor; and, 'a transconductance amplifier comprisinga capacitor coupled between the control terminal of the first transistor and the second output terminal, wherein the transconductance amplifier is configured to receive an input voltage across the capacitor, and produce a regulated output voltage at the first output terminal with respect to the second output terminal based on the input voltage, and wherein the first current generator is configured to provide slew rate control at the control terminal of the first transistor.2. The circuit of claim 1 , further comprising a first diode having a cathode coupled to the control terminal of the first transistor claim 1 , and an anode coupled at an intermediate node that is coupled between the current path of the first transistor and the current path of the second transistor.3. The circuit of claim 1 , further ...

METHODS AND CIRCUITRY FOR DRIVING A DEVICE

Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle. 1. A drain sense circuit , comprising:a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider; anda current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.2. The drain sense circuit of claim 1 , wherein the input of the transistor is a drain of the transistor or a source of the transistor claim 1 , and wherein the input of the transistor is configured to receive a drain or drain/source voltage of the transistor.3. The drain sense circuit of claim 1 , wherein the capacitive voltage divider is a high ratio capacitive voltage divider.4. The drain sense circuit of claim 1 , wherein the capacitive voltage divider comprises:a capacitor array comprising a first capacitor coupled in parallel with a second capacitor; anda third capacitor coupled in series with the capacitor array.5. The drain sense circuit of claim 4 , wherein the capacitor array further comprises:a first switch coupled between the first capacitor and the third capacitor at the node; anda second switch coupled between the second capacitor and the third capacitor at the node.6. The drain sense circuit of claim 5 , further comprising calibration circuitry coupled to control the first switch and the second switch.7. The drain sense circuit of claim 6 , further comprising ...

High-Speed Switch with Accelerated Switching Time

A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch. 1 (1) switch control input;', '(2) a field effect transistor (FET) having a gate, source and drain;', '(3) a reset circuit having an signal input, signal output, reset control input and reference input signal output being coupled to the gate of the FET, the reset circuit configured to reset the FET by connecting the gate of the FET to the signal input when the reset circuit is inactive and to the reference input when the reset circuit is active;, '(a) at least one switch branch comprising(b) a reset processor having a reset processor input coupled to the switch control input and a reset processor output coupled to the reset control input, the reset processor configured to output a reset pulse from the reset processor output in response to a change in the state of a signal received at the reset processor input.. A multiport switch comprising: This application is a continuation of commonly owned and co-pending U.S. application Ser. No. 15/659,311, filed Jul. 25, 2017, entitled “High-Speed Switch with Accelerated Switching Time”, the disclosure of which is incorporated herein by reference in its entirety.This disclosure generally relates to switches and more specifically to high-speed switches for switching radio frequency and other electronic signals.A ...

DRIVING CIRCUIT, CONVERTER AND DRIVING METHOD

A driving circuit includes a main output terminal electrically coupled to a switch element, a first voltage generating circuit and a second voltage generating circuit. The first voltage generating circuit is electrically coupled with the main output terminal. The first voltage generating circuit comprises a first comparator and a voltage divider circuit. The first voltage generating circuit is configured to generate a first voltage at the main output terminal during a predetermined time interval of a turn-on duration of a switching period. The second voltage generating circuit is electrically coupled with the main output terminal. The second voltage generating circuit is configured to generate a second voltage at the main output terminal during a remaining time interval of the turn-on duration of the switching period. The predetermined time interval is ahead of the remaining time interval, and the first voltage is higher than the second voltage. 1. A driving circuit for driving a switch element , comprising:a main output terminal electrically coupled to the switch element;a first voltage generating circuit electrically coupled with the main output terminal, wherein the first voltage generating circuit comprises a first comparator and a voltage divider circuit electrically coupled with the first comparator, and the first voltage generating circuit is configured to generate a first voltage at the main output terminal during a predetermined time interval of a turn-on duration of a switching period; anda second voltage generating circuit electrically coupled with the main output terminal, wherein the second voltage generating circuit is configured to generate a second voltage at the main output terminal during a remaining time interval of the turn-on duration of the switching period, and the second voltage is higher than a threshold voltage of the switch element;wherein the predetermined time interval is ahead of the remaining time interval, and the first voltage is ...

Low-power-consumption high-speed zero-current switch

A low-power-consumption high-speed zero-current switch includes a delay controller, a driving stage and a power transistor MN, wherein: an input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN; the delay controller includes a gate signal generator, a sampling circuit and a current controller, and three of which form a negative feedback loop for stabilizing the turn-on voltage Vand the turn-off voltage Vto 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0. The present invention no longer uses a high-power-consumption high-speed comparator, but uses a low-power-consumption delay controller to generate turn-on and turn-off signals of the power transistor. 1. A low-power-consumption high-speed zero-current switch , which comprises a delay controller , a driving stage and a power transistor MN , wherein: an input of the delay controller is connected with an external clock CLK , an output of the delay controller is connected with an input of the driving stage , and an output of the driving stage is connected with a gate of the power transistor MN;the delay controller comprises a gate signal generator, a sampling circuit and a current controller;{'sub': ON', 'D', 'GN', 'GN', 'ON', 'D', 'ON', 'D', 'ON', 'D', 'ON', 'D, 'the gate signal generator is configured to use the external clock CLK and two currents Iand Icontrolled by the current controller to generate a gate signal Vof the power transistor MN required by the zero-current switch; the sampling circuit comprises a sampling logic unit and a switched capacitor sampling unit; the sampling logic unit is configured to utilize the external clock CLK and the gate signal Vof the power transistor MN to control the switched capacitor sampling unit for sampling source-drain voltages of the zero- ...

POST FABRICATION TUNING OF AN INTEGRATED CIRCUIT

An integrated circuit includes a transistor Which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed. 1. An integrated circuit comprising:at least one transistor having a plurality of electrical connections and a normal performance characteristic controlled by one or more physical properties of said transistor, said normal performance characteristic arising during normal operations of said transistor that apply normal electrical signals within respective normal ranges to at least some of said plurality of electrical connections of said transistor, said normal performance characteristic having a value resulting in incorrect operation of said integrated circuit upon normal switching of said transistor; anda tuner configured to apply during a tuning operation a tuning stimulus to said transistor permanently to change at least one of said one or more physical properties of said transistor that control said normal performance characteristic such that upon resuming modified normal operations with said normal electrical signals said transistor operates with a changed normal performance characteristic, ...

MILLER TRANSITION CONTROL GATE DRIVE CIRCUIT

Aspects of the present disclosure are directed toward designs and methods of improving driving of switching devices. One proposed solution to improving driving of switching devices is an auxiliary control circuit that selectively guides the switching device through at least one switching region, permitting an improved operation of the switching device. 1. A circuit , comprising:a first switching device coupled to a load;a first voltage source configured to generate an electrical signal at a voltage level at least equal to a threshold voltage of the first switching device; anda second switching device between the first switching device and the first voltage source, wherein the second switching device is configured to provide a shaped current to the first switching device in response to a control signal, wherein the shaped current is generated based at least in part on the electrical signal generated by the first voltage source, and wherein the shaped current actuates the first switching device.2. The circuit of claim 1 , comprising a first impedance between the first voltage source and the second switching device and a second impedance between the second switching device and the first switching device.3. The circuit of claim 1 , comprising a control signal generator configured to provide the control signal to the second switching device based at least in part on one or more feedback signals from the first switching device claim 1 , the second switching device claim 1 , the load claim 1 , or any combination thereof claim 1 , as part of a control loop.4. The circuit of claim 1 , wherein the second switching device comprises a current-controlled switch claim 1 , a voltage-controlled switch claim 1 , a metal-oxide-semiconductor field-effect transistor (MOSFET) device claim 1 , an insulated-gate bipolar transistors (IGBTs) claim 1 , a bipolar transistors (BJTs) claim 1 , or any combination thereof.5. The circuit of claim 1 , comprising a resistor-capacitor (RC) circuit ...

SIGNAL SELECTION CIRCUIT AND SEMICONDUCTOR DEVICE

Provided is a signal selection circuit including a control circuit capable of generating a drive signal having a fast rise/fall time. A positive feedback circuit is provided to the control circuit, which generates the drive signal for controlling a plurality of switches configured to switch an input signal to provide the signal to an output terminal. 1. A signal selection circuit , comprising:a first switch arranged between a first input terminal and a first output terminal;a second switch arranged between a second input terminal and the first output terminal;a third switch arranged between the first input terminal and a second output terminal;a fourth switch arranged between the second input terminal and the second output terminal; and 'output a first control signal for controlling the first switch and the fourth switch, and a second control signal for controlling the second switch and the third switch by a clock signal provides from a clock input terminal,', 'a control circuit configured to'} a first inverter connected to the clock input terminal; and', 'a positive feedback circuit connected to both ends of the first inverter., 'the control circuit comprising2. A signal selection circuit according to claim 1 , wherein the positive feedback circuit comprises:a first MOS transistor having a gate connected to an input terminal of the first inverter;a second MOS transistor having a gate connected to an output terminal of the first inverter;a second inverter having an input terminal connected to a drain of the first MOS transistor, and an output terminal connected to a drain of the second MOS transistor; anda third inverter having an input terminal connected to the drain of the second MOS transistor, and an output terminal connected to the drain of the first MOS transistor.3. A semiconductor device claim 1 , comprising the signal selection circuit of .4. A semiconductor device claim 2 , comprising the signal selection circuit of . This application claims priority under ...

RADIO FREQUENCY SWITCHING CIRCUIT AND APPARATUS WITH REDUCED SWITCHING RESPONSE DELAY

A radio frequency switching circuit includes a switching circuit comprising a plurality of switching transistors connected between a first terminal and a second terminal, a gate resistor circuit comprising a plurality of gate resistors, each of the plurality of gate resistors having a first node connected to a respective gate of each of the plurality of switching transistors, and a gate buffer circuit comprising a plurality of gate buffers, each of the plurality of gate buffers being connected to a respective second node of each of the plurality of gate resistors, wherein each of the plurality the gate buffers is configured to provide a first gate signal to the gate of each of the plurality of switching transistors through each of the plurality of gate resistors. 1. A radio frequency switching circuit comprising:a switching circuit comprising a plurality of switching transistors connected between a first terminal and a second terminal, each of the plurality of switching transistors comprises at least a first transistor and a second transistor;a gate resistor circuit comprising a plurality of gate resistors, each of the plurality of gate resistors having a first node connected to a respective gate of each of the plurality of switching transistors; anda gate buffer circuit comprising a plurality of gate buffers, each of the plurality of gate buffers being connected to a respective second node of each of the plurality of gate resistors,wherein each of the plurality the gate buffers is configured to provide a first gate signal to the gate of each of the plurality of switching transistors through each of the plurality of gate resistors.2. The radio frequency switching circuit of claim 1 , wherein each of the plurality of gate buffers comprises:a first buffer configured to receive the first gate signal; anda second buffer connected in parallel with the first buffer, and configured to receive the first gate signal.3. The radio frequency switching circuit of claim 2 , ...

VOLTAGE COMPARATOR

Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time. 1. A power-up system , comprising:a voltage comparator configured to compare a voltage of a first supply rail with a voltage of a second supply rail, and to output an output signal based on the comparison; anda controller configured to determine whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the output signal of the voltage comparator, and, upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time, to initiate switching of a plurality of switches coupled between the first and second supply rails.2. The system of claim 1 , wherein the first supply rail is an internal supply rail claim 1 , and the second supply rail is an external supply rail.3. The system of claim 1 , wherein the output signal of the voltage comparator has a first logic state when the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail claim 1 , and the controller is configured to initiate switching of the plurality of switches when the output signal of the voltage comparator stays at the first ...

APPARATUS FOR PERFORMING LEVEL SHIFT CONTROL IN AN ELECTRONIC DEVICE WITH AID OF PARALLEL PATHS CONTROLLED BY DIFFERENT CONTROL SIGNALS FOR CURRENT CONTROL PURPOSES

An apparatus for performing level shift control in an electronic device includes an input stage positioned in a level shifter of the electronic device, and an output stage positioned in the level shifter and coupled to the input stage through a set of intermediate nodes. The input stage is arranged for receiving at least one input signal of the level shifter through at least one input terminal of the input stage and controlling voltage levels of the set of intermediate nodes according to the at least one input signal. The input stage includes a hybrid current control circuit coupled to the at least one input terminal and arranged for performing current control for the input stage. The hybrid current control circuit is equipped with multiple sets of parallel paths for controlling currents passing through the set of intermediate nodes, respectively, each set may include two or more paths in parallel. 1. An apparatus for performing level shift control in an electronic device , the apparatus comprising at least one portion of the electronic device , the apparatus comprising: 'a hybrid current control circuit, coupled to the at least one input terminal, arranged for performing current control for the input stage, wherein the hybrid current control circuit is equipped with multiple sets of parallel paths for controlling currents passing through the set of intermediate nodes, respectively, each set of the multiple sets of parallel paths comprises a first path on which a first switching unit and at least one passive component are positioned, and further comprises a second path on which a second switching unit is positioned, and the first switching unit and the second switching unit are controlled by different control signals, respectively; and', 'an input stage, positioned in a level shifter of the electronic device, arranged for receiving at least one input signal of the level shifter through at least one input terminal of the input stage and controlling voltage levels of ...

GATE DRIVE CONTROL SYSTEM FOR SiC AND IGBT POWER DEVICES TO CONTROL DESATURATION OR SHORT CIRCUIT FAULTS

A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

ACTIVE-MATRIX SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate () are provided gate lines (G) and source lines. On the active-matrix substrate () are further provided: gate drivers () each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (G); and lines (L) each for supplying a control signal to the associated gate driver (). A control signal is supplied by a display control circuit () located outside the display region to the gate drivers () via the lines (L). In response to a control signal supplied, each gate driver () drives the gate line (G) to which it is connected. 1. An active-matrix substrate comprising:a plurality of data lines;a plurality of lines crossing the plurality of data lines and including at least gate lines; anda driving circuit connected with at least one of the plurality of lines for controlling a potential of this line in response to a control signal supplied from outside a display region that includes pixel regions defined by the data lines and the gate lines,the driving circuit including a plurality of switching elements,at least one of the plurality of switching elements being located in one of the pixel regions.228.-. (canceled) The present invention relates to an active-matrix substrate, a display panel and a display device including the same, and, more particularly, to the arrangement of gate drivers.Display panels are known where gate drivers are provided along a side of an active-matrix substrate and source drivers are provided along an adjacent side thereof. JP 2004-538511 A discloses a technique to provide, along one side of the pixel element array, a row driving circuit for driving column address conductors for supplying data signals and a ...

SWITCHING POWER CONVERSION APPARATUS AND MULTI-LEVEL SWITCHING POWER CONVERTER CIRCUIT THEREIN

A switching power conversion apparatus includes: a multi-level power stage, a PWM control circuit, a multi-level driver circuit, a bootstrap capacitor control circuit and a driving power control circuit. The bootstrap capacitor control circuit includes bootstrap capacitor control switches. During a charging period, a bootstrap control signal controls the bootstrap capacitor control switches, to electrically connect a second bootstrap node to the ground voltage level, whereby the supply voltage charges the bootstrap capacitor via the bootstrap diode. During a pumping period, the bootstrap control signal controls the bootstrap capacitor control switches to electrically connect the second bootstrap node to one of the upper-gate nodes or the switching node, whereby the voltage of the first bootstrap node is pumped to a corresponding pumping voltage level. 1. A switching power conversion apparatus which is configured to operably convert a first voltage to a second voltage or convert the second voltage to the first voltage , the switching power conversion apparatus comprising:an inductor having one end electrically connected to the second voltage and having another end electrically connected to a switching node;a multi-level switching power converter circuit coupled to the inductor via the switching node;a conversion capacitor, which is coupled to the multi-level switching power converter circuit;a bootstrap diode having a current input terminal coupled to a supply voltage and having a current output terminal coupled to a first bootstrap node; anda bootstrap capacitor having one end coupled to the first bootstrap node, and having another end which is coupled to the multi-level switching power converter circuit via a second bootstrap node; a plurality of upper-gate switches which are connected in series to form an upper-gate switch group, the upper-gate switch group being coupled between the first voltage and the switching node, wherein the upper-gate switch group includes ...

Diode Circuit

An integrated circuit includes a transistor having a control electrode and a load current path to activate and to deactivate a load current path between a first terminal and a second terminal. A diode is in parallel with the load current path of the transistor. The integrated circuit includes a detector circuit to generate a control signal depending on a voltage between the first terminal and the second terminal. The integrated circuit includes a driver circuit having a main branch and a first feedforward branch. The main branch includes circuit components to generate a control voltage for the control electrode of the transistor in accordance with the control signal, and the feedforward branch comprises circuit components to generate a charging current or, alternatively, a discharging current as a reaction to a slope of the control signal, the current charging or discharging, respectively, the control electrode of the transistor. 1. An integrated circuit comprising:a first terminal and a second terminal;a MOS transistor having a control electrode and a load current path, which is configured to activate and to deactivate a load current path between the first terminal and the second terminal;a diode arranged in parallel with the load current path of the MOS transistor;a detector circuit configured to generate a control signal depending on a voltage between the first terminal and the second terminal; anda driver circuit having a main branch and a first feedforward branch,wherein the main branch receives the control signal and comprises circuit components configured to generate a control voltage for the control electrode of the MOS transistor in accordance with the control signal, andwherein the first feedforward branch comprises circuit components configured to generate a charging current or discharging current as a reaction to a slope of the control signal, said charging current or discharging current charging or discharging, respectively, the control electrode of the ...

ENERGY STORAGE ELEMENT CONTROL CIRCUIT

An energy storage element control circuit includes a charge transistor having a first node adapted to be coupled to an output node of the energy storage element control circuit and a second node adapted to be coupled to a terminal of an energy storage element. The energy storage control circuit also includes a boot capacitor having a first node and a second node. The energy storage element further includes a comparator that includes a first input node coupled to the first node of the charge transistor and a second input node adapted to be coupled to the terminal of the energy storage element. The comparator also includes an output node. 1. An energy storage element control circuit comprising:a charge transistor having a first node adapted to be coupled to an output node of the energy storage element control circuit and a second node adapted to be coupled to a terminal of an energy storage element;a boot capacitor having a first node and a second node; a first input node coupled to the first node of the charge transistor;', 'a second input node adapted to be coupled to the terminal of the energy storage element; and', 'an output node;, 'a comparator includinga controller having a boot output node coupled to the first node of the boot capacitor, the controller being coupled between the output node of the comparator and the boot capacitor; anda buffer coupled between the controller and the first node of the boot capacitor, and a positive voltage rail of the buffer is adapted to be coupled to the terminal of the energy storage element.23-. (canceled)4. The energy storage element control circuit of claim 1 , in which the controller is configured to assert a boot signal at the boot output node in response to assertion of a comparator output signal from the comparator indicating that a voltage of the energy storage element exceeds a voltage at the output node of the energy storage element control circuit by at least a threshold voltage level.5. The energy storage element ...

ACTIVE-MATRIX SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate () are provided gate lines (G) and source lines. On the active-matrix substrate () are further provided: gate drivers () each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (G); and lines (L) each for supplying a control signal to the associated gate driver (). A control signal is supplied by a display control circuit () located outside the display region to the gate drivers () via the lines (L). In response to a control signal supplied, each gate driver () drives the gate line (G) to which it is connected. 1. An active-matrix substrate comprising:a plurality of data lines;a plurality of lines crossing the plurality of data lines and including at least gate lines; anda driving circuit connected with at least one of the plurality of lines for controlling a potential of this line in response to a control signal supplied from outside a display region that includes pixel regions defined by the data lines and the gate lines,wherein the driving circuit includes a plurality of switching elements,at least one of the plurality of switching elements is located in one of the pixel regions,the driving circuit is connected with one of the gate lines and controls the potential of this gate line by applying one of a selection voltage and a non-selection voltage to the gate line in response to the control signal, andthe driving circuit is provided in each of K regions (K is a natural number, K≥2) arranged in a direction in which the gate lines of the display region extend, each driving circuit being provided for every K gate lines, the driving circuits being provided on different gate lines in different regions.2. The active- ...

ELECTRONIC SWITCH AND ELECTRONIC APPARATUS INCLUDING THE SAME

An electronic switch includes a first NMOS transistor connected between a positive input terminal and an output terminal; a first diode, a second resistor, a first capacitor, and a third switching element sequentially connected in series between a drain of the first NMOS transistor and a negative input terminal; a first resistor connected between a positive input terminal and a node between the first capacitor and the third switching element; a third resistor connected between a gate of the first NMOS transistor and a node between the second resistor and the first capacitor; and a second capacitor, a second diode, and a fourth resistor connected in parallel between a source of the first NMOS transistor and a node between the third resistor and the gate of the first NMOS transistor. 1. An electronic switch , comprising:a first NMOS transistor connected between a positive input terminal and an output terminal;a first diode, a second resistor, a first capacitor, and a third switching element sequentially connected in series between a drain of the first NMOS transistor and a negative input terminal;a first resistor connected between a positive input terminal and a node between the first capacitor and the third switching element;a third resistor connected between a gate of the first NMOS transistor and a node between the second resistor and the first capacitor; anda second capacitor, a second diode, and a fourth resistor connected in parallel between a source of the first NMOS transistor and a node between the third resistor and the gate of the first NMOS transistor.2. The electronic switch according to claim 1 , further comprising a third diode connected in series between the third switching element and the negative input terminal.3. The electronic switch according to claim 1 , further comprising a second NMOS transistor connected in series in a reverse direction between the first NMOS transistor and an output terminal.4. The electronic switch according to claim 1 , ...

METHODS AND CIRCUITRY FOR DRIVING A DEVICE

Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor. 1. A drain sense circuit comprising:a voltage sensing circuit includes a capacitive voltage divider and having an input node and an output node, the input node of the voltage sensing circuit adapted to be coupled to an input of a transistor and the capacitive voltage divider includes:a first capacitora second capacitor; anda third capacitor, the third capacitor is coupled in parallel with the first capacitor and the second capacitor is coupled in series with the first and third capacitors; anda current sensing circuit having an input node and an output node, the input node of the current sensing circuit adapted to be coupled to the input of the transistor, the output node of the current sensing circuit coupled between a first resistor and a second resistor included in a resistive divider in the current sensing circuit, the output node of the current sensing circuit being different than the output node of the voltage sensing circuit.2. The drain sense circuit of claim 1 , wherein the input of the transistor is a drain of the transistor or a source of the transistor claim 1 , and wherein the input of the transistor is adapted to receive a drain or drain to source voltage of the transistor.3. The drain sense circuit of claim 1 , wherein the first capacitor is rated to a voltage of the input of the transistor.4. The drain sense circuit of claim 1 , wherein a capacitor array includes the first capacitor and the third capacitor; andthe ...

Transient Stabilized SOI FETs

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same Vas during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same Vas during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both Vand Vclose to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects. 1. An integrated circuit fabricated on a silicon-on-insulator (SOI) substrate , including at least one metal-oxide-semiconductor field effect transistor (FET) susceptible to accumulated charge and having a Vcharacteristic and configured such that , in a standby mode , the FET maintains essentially the same Vcharacteristic as during an active mode.2. The invention of claim 1 , wherein the SOI substrate includes a trap rich layer susceptible to accumulated charge in or near such trap rich layer.3. The invention of claim 1 , further including at least one substrate contact near at least one FET.4. The invention of claim 1 , further including at least a partial ring of substrate contacts around at least one FET.5. A circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit claim 1 , the circuit including:{'sub': 'D', '(a) at least one metal-oxide-semiconductor field effect transistor (FET) susceptible to accumulated charge and having a drain, a source, a gate, a VS characteristic, and a signal path through the FET between the drain and ...

INPUT BUFFER

The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology. 1. An input buffer comprising:an input to receive a voltage input signal;a first transistor of a first type;a second transistor of a second type complementary to the first type, wherein a source of the second transistor is coupled to a source of the first transistor;an output at the sources of the first transistor and the second transistor; anda first level shifter to generate a first level shifted voltage based on the voltage input signal and to set a voltage difference between a gate of the first transistor and a gate of the second transistor.2. The input buffer of claim 1 , wherein the first transistor and the second transistor are biased by at least the first level shifter to have a determined amount of current flowing through the first transistor and the second transistor.3. The input buffer of claim 1 , wherein:the first level shifted voltage signal biases the gate of the first transistor.4. The input buffer of claim 1 , wherein:the first level shifter shifts the voltage input signal by a first amount of voltage shift.5. The input buff of claim 4 , the first amount of voltage shift is sufficient to keep the first transistor and the second transistor on.6. The input buffer of claim 1 , further comprising:a second level shifter to generate a second level shifted voltage based on the voltage input signal.7. The input buffer of claim 6 , wherein:the second level shifted voltage ...

One-Transistor Devices for Protecting Circuits and Autocatalytic Voltage Conversion Therefor

Devices having one primary transistor, or a plurality of primary transistors in parallel, protect electrical circuits from overcurrent conditions. Optionally, the devices have only two terminals and require no auxiliary power to operate. In those devices, the voltage drop across the device provides the electrical energy to power the device. A third or fourth terminal can appear in further devices, allowing additional overcurrent and overvoltage monitoring opportunities. Autocatalytic voltage conversion allows certain devices to rapidly limit or block nascent overcurrents. 1. A device for protecting a circuit having a primary current path from an overcurrent condition , comprising:a first terminal and a second terminal configured to route the primary current path through the device;a first transistor comprising a first gate, a first drain, and a first source;wherein the first transistor is a depletion mode, normally-on transistor;wherein the first transistor is arranged in series in the primary current path between the first terminal and the second terminal; the driver circuitry comprising a first voltage converter circuitry adapted to receive a first input voltage derived solely from a voltage between the first terminal and the second terminal, and convert the first input voltage to a first releasably-stored voltage,', 'the driver circuitry further comprising a jumpstart voltage converter adapted to convert a second input voltage to a second releasably-stored voltage more quickly than the first voltage converter converts the first input voltage,', 'wherein the driver circuitry is configured to apply a gate voltage at the first gate relative to the first source;, 'a driver circuitry;'} 'the first transistor is configured to pass current between the first terminal and the second terminal; and', 'wherein, when a first positive voltage and a normal current condition exist from the first terminal to the second terminal,'} 'the driver circuitry is configured to drive the ...

CASCODE SWITCHES INCLUDING NORMALLY-OFF AND NORMALLY-ON DEVICES AND CIRCUITS COMPRISING THE SWITCHES

A cascode switch comprising a normally-on semiconductor device comprising a gate, a source and a drain, and a normally-off semiconductor device comprising a gate, a source and a drain. The drain of the normally-off semiconductor device coupled to the normally-on semiconductor device, the source of the normally-on semiconductor device coupled to the drain of the normally-off semiconductor device and the gate of the normally-on semiconductor device coupled to the source of the normally-off semiconductor device. The cascode switch further comprises a leakage current clamp coupled across the normally-off semiconductor device, the leakage current clamp circuit configured to prevent the drain of the normally-off semiconductor from going too high due to leakage current. 1. A cascode switch comprising:a normally-on semiconductor device comprising a gate, a source and a drain;a normally-off semiconductor device comprising a gate, a source and a drain coupled to the normally-on semiconductor device, the source of the normally-on semiconductor device coupled to the drain of the normally-off semiconductor device and the gate of the normally-on semiconductor device coupled to the source of the normally-off semiconductor device; anda leakage current clamp coupled across the normally-off semiconductor device, the leakage current clamp circuit configured to prevent the drain of the normally-off semiconductor from going too high due to leakage current.2. The cascode switch of claim 1 , wherein the leakage current clamp comprises a first Zener diode claim 1 , the first Zener diode having a breakdown voltage that prevents the drain of the normally-off semiconductor from going too high.3. The cascade switch of claim 2 , wherein an anode of the first Zener diode is coupled to the source of the normally-off semiconductor device and a cathode of the first Zener diode is coupled to the drain of the normally-off semiconductor device.4. The cascade switch of claim 3 , wherein the leakage ...

DEVICE AND METHOD FOR CONTROLLING SWITCHING

The present invention concerns a device and a method for controlling the switching from a conducting state to a non conducting state or from a non conducting state to a conducting state of a semiconductor power switch providing current to a load, the device receiving an input signal that is intended to drive the semiconductor power switch. The invention:—senses the derivative of the drain to source current going through the semiconductor power switch in order to obtain a voltage representative of the sensed derivative of drain to source current,—amplifies the voltage representative of the sensed derivative of drain to source current,—adds the amplified voltage representative of the derivative of the sensed drain to source current to the input signal during a given time period. 19-. (canceled)10. Device for controlling the switching from a conducting state to a non conducting state or from a non conducting state to a conducting state of a semiconductor power switch providing current to a load , the device receiving an input signal that is intended to drive the semiconductor power switch , characterized in that the device comprises:a sensor for sensing the derivative of the drain to source current going through the semiconductor power switch in order to obtain a voltage representative of the sensed derivative of drain to source current,an amplifier for amplifying the voltage representative of the sensed derivative of drain to source current,an adder for adding the amplified voltage representative of the derivative of the sensed drain to source current to the input signal during a given time period that is equal to the sum of the gate transition time, the voltage transition time and the current transition time plus a predetermined margin and the adding is performed using an exclusive or logic operation of the input signal and the input signal delayed by the given time period.11. The device according to claim 10 , wherein the sensor for sensing the derivative of the ...

HIGH SPEED DRIVER FOR HIGH FREQUENCY DCDC CONVERTER

A gate driver circuit includes a pulse generator that receives an input signal and generates a pulse signal in response to a switch-on command included in the input signal. The pulse signal has a pulse with a pulse length that is dependent on a level of a pulse control signal. The circuit further includes a sampling circuit that samples an output voltage subsequent to the pulse and stores a respective sampled value, and a controller that receives the sampled value of the output voltage and a reference voltage and updates the level of the pulse control signal based on the sampled value and the reference voltage. A driver circuit generates the output voltage based on the pulse signal. 1. A circuit comprising:a pulse generator configured to receive an input signal and to generate a pulse signal in response to a switch-on command included in the input signal, the pulse signal having a pulse with a pulse length that is dependent on a level of a pulse control signal;a sampling circuit configured to sample an output voltage subsequent to the pulse and to store a respective sampled value;a controller configured to receive the sampled value of the output voltage and a reference voltage and to update the level of the pulse control signal based on the sampled value and the reference voltage; anda driver circuit configured to generate the output voltage based on the pulse signal.2. The circuit of claim 1 ,wherein the pulse control signal has a predetermined initial level before being updated for a first time.3. The circuit of claim 2 ,wherein the initial level is set to such a level, that a resulting pulse length is short enough that the generated output voltage is below a predefined maximum voltage value.4. The circuit of claim 1 ,wherein the driver circuit operably receives a supply voltage that is higher than a predetermined maximum voltage value.5. The circuit of any of claim 1 ,wherein the driver circuit includes an output resistor.6. The circuit of claim 1 ,wherein the ...

PRE-CONDITIONING A NODE OF A CIRCUIT

Pre-conditioning circuitry for pre-conditioning a node of a circuit to support a change in operation of the circuit, wherein the circuit is operative to change a state of the node to effect the change in operation of the circuit, and wherein the pre-conditioning circuitry is configured to apply a voltage, current or charge directly to the node to reduce the magnitude of the change to the state of the node required by the circuit to achieve the change in operation of the circuit. 1. Pre-conditioning circuitry for pre-conditioning a node of a circuit to support a change in operation of the circuit ,wherein the circuit is operative to change a state of the node to effect the change in operation of the circuit,wherein the pre-conditioning circuitry is configured to apply a voltage, current or charge directly to the node to reduce the magnitude of the change to the state of the node required by the circuit to achieve the change in operation of the circuit,wherein the pre-conditioning circuitry comprises:monitor circuitry configured to monitor a voltage of the circuitry; andcontrol circuitry configured to apply the voltage, current or charge to the node if a characteristic of the monitored voltage meets a predefined condition.2. Pre-conditioning circuitry according to claim 1 , wherein the change in operation of the circuit is in response to: start-up of the circuit; a transient in a supply voltage to the circuit; a change in the supply voltage to the circuit claim 1 , a transient in a load of the circuit; or a change in the load of the circuit.3. (canceled)4. Pre-conditioning circuitry according to claim 1 , wherein the characteristic comprises a magnitude or rate of change of the monitored voltage.5. Pre-conditioning circuitry according to claim 1 , wherein the voltage comprises a supply voltage or an output voltage of the circuit.6. Pre-conditioning circuitry according to claim 1 , wherein the circuit comprises a low dropout regulator circuit.7. Pre-conditioning ...

High-side transistor driver for power converters

The high-side transistor driver according to the present invention includes a high-side transistor, a low-side transistor, a drive-buffer and an on/off transistor. When the low-side transistor is turned on, a charge-pump diode and a bootstrap capacitor produce a floating voltage. The drive-buffer will propagate the floating voltage to switch on the high-side transistor. The on/off transistor is used to switch the drive-buffer. The high-side transistor drive further includes a speed-up circuit. The speed-up circuit has a capacitive coupling for generating a differential signal. When the on/off transistor is turned off, the speed-up circuit accelerates the charge-up of the parasitic capacitor of the on/off transistor, thus accelerating high-side transistor switching.

Voltage generation circuit

[과제] 부하가 가벼워져도 전원 노이즈의 발생을 억제한다. [해결 수단] 전압 생성 회로(100)는 직류 전원에 접속된 트랜지스터(TR1)를 구동 펄스(PDR1)의 공급으로 도통시켜서 출력 전압(VOUT)을 생성한다. 비교 회로(50)는 오차 신호(Err)의 크기에 따른 기간만큼 액티브가 되는 제어 신호(CTL)를 생성한다. 구동부(80)는 제어 신호(CTL)의 액티브 기간과 기준 시간(Tref)에 의거하여 P채널 트랜지스터(TR1) 및 N채널 트랜지스터(TR2)의 온·오프를 제어한다. 리셋 신호 생성 회로(60)는 제어 신호(CTL)의 주파수를 하한 주파수(fmin)로부터 상한 주파수(fmax)까지의 범위에서 제어한다. [Problem] Even when the load is light, generation of power supply noise is suppressed. [Solution] The voltage generation circuit 100 conducts the transistor TR1 connected to the DC power supply by supplying the driving pulse PDR1 to generate the output voltage VOUT. The comparison circuit 50 generates a control signal CTL that is active for a period corresponding to the magnitude of the error signal Err. The driver 80 controls the on / off of the P-channel transistor TR1 and the N-channel transistor TR2 based on the active period of the control signal CTL and the reference time Tref. The reset signal generation circuit 60 controls the frequency of the control signal CTL in the range from the lower limit frequency fmin to the upper limit frequency fmax.

开关电路

一实施方式的开关电路(10)包括至少一个具有输入端子(21)、输出端子(22)及公共端子(23)的半导体开关元件，且其通过对输入端子与公共端子之间施加脉冲状信号而开关输出端子与公共端子之间的电流。该开关电路具备电容抑制元件部(50)，其连接在输入端子与输出端子之间、输入端子与公共端子之间及输出端子与公共端子之间的至少一个，且电容抑制元件部使连接有电容抑制元件部的半导体开关元件的端子间的寄生电容比在脉冲状信号的时钟频率的N倍(N为1以上的整数)的频率下未连接电容抑制元件部的情况更低。

包括常闭和常开器件的共源共栅开关以及包括这样的开关的电路

描述了包括共源共栅布置的常闭半导体器件和常开半导体器件的开关。开关包括连接在常开器件的栅极与常闭器件的源极之间的电容器。开关还可以包括与电容器并行地连接在常开器件的栅极与常闭器件的源极之间的齐纳二极管。开关还可以包括反向串行布置在常闭器件的栅极与源极之间的一对齐纳二极管。还描述了包括多个常开和/或多个常闭器件的开关。常开器件能够是诸如SiC JFET的JFET。常闭器件能够是诸如Si MOSFET的MOSFET。常开器件能够是高电压器件并且常闭器件能够是低电压器件。还描述了包括开关的电路。

Switch circuit

一实施方式的开关电路(10A)包括具有输入端子(21)、输出端子(22)及公共端子(23)的第一半导体开关元件～第四半导体开关元件(20)。以在第一半导体开关元件及第四半导体开关元件导通(截止)时剩余的半导体开关元件成为截止(导通)的方式，对各半导体开关元件的输入端子施加脉冲状信号。开关电路具备：第一电容元件(60)，连接在第二半导体开关元件的输出端子与第四半导体开关元件的输入端子之间；及第二电容元件(61)，连接在第二半导体开关元件的输入端子与第四半导体开关元件的输出端子之间。第一及第二电容元件分别具有如下电容：使第四及第二半导体开关元件各自的输入端子与输出端子间的寄生电容在对第四及第二半导体开关元件供给的脉冲状信号的时钟频率的N倍(N为1以上的整数)的频率下降低。

Method and device for controlling a power output stage

적절한 전자기적 간섭을 가지고 구동하기 위해, 회로 차단기(T)는 드레인 전류(Id)가 임계치 전류(Is)를 초과할 때까지 높은 충전 전류(Ig1)로 충전되고, 그리고 나서 드레인 전압(Vd)이 미리 설정된 임계치 전압(Vs) 아래로 떨어질 때까지 적정한 상승률과 관련된 작은 충전 전류(Ig2)를 가지고 충전되며, 그리고 나서 미리 설정된 기간(Tv) 동안 상기 높은 충전 전류(Ig1)를 가지고 충전된다; 상기 회로 차단기를 닫기 위해 역시퀀스가 뒤따른다. In order to drive with appropriate electromagnetic interference, the circuit breaker T is charged with a high charging current Ig1 until the drain current Id exceeds the threshold current Is, and then the drain voltage Vd is increased. It is charged with a small charge current Ig2 associated with an appropriate rate of rise until it falls below a predetermined threshold voltage Vs, and then charged with the high charge current Ig1 for a preset period Tv; A sequence is also followed to close the circuit breaker.

Voltage conversion circuit and control circuit thereof

本发明提供一种电压转换电路及其控制电路。控制电路包括电压选择电路、缓冲电路以及下拉开关。电压选择电路接收输入电压以及输出电压，并选择输入电压以及输出电压中电压值较小者作为选中电压。缓冲电路接收选中电压，并提供选中电压以作为参考电压。下拉开关的控制端接收致能信号，以依据致能信号而被导通或被断开，其中，下拉开关依据致能信号而导通，以将驱动开关的控制端的电压拉低至参考电压，并使驱动开关被断开。

Output signal controller apparatus of op amplifier

본 발명은 오류 증폭기의 출력신호 제어장치에 관한 것으로, 전류제어모드 DC-DC 컨버터에서 오류 증폭기의 출력 노드에 클램프부를 직렬로 연결하고, 클램프부는 저항분배 및 BJT를 이용하여 PWM 생성용 비교기에 인가되는 VERR 신호의 하이 값 및 로우 값을 설정하고 있다. 이때 하이 값은 저항 R1 및 R2의 값으로 조절 가능하며, 로우 값은 상기 BJT의 V BE 전압만큼 옵셋 값이 주어져서 고정된 값으로 설정된다. 이와 같은 본 발명에 따르면, 종래 오류 증폭기의 출력노드에 클램프부를 병렬 연결할 때에 오류 증폭기의 이득이 감소하게 되는 문제를 완전하게 방지할 수 있다. The present invention relates to an apparatus for controlling an output signal of an error amplifier. In a current control mode DC-DC converter, a clamp unit is connected in series to an output node of an error amplifier, and the clamp unit is applied to a comparator for PWM generation using resistance distribution and BJT. The high and low values of the VERR signal are set. At this time, the high value can be adjusted to the values of resistors R1 and R2, and the low value is V BE of the BJT. The offset value is given by the voltage and is set to a fixed value. According to the present invention, it is possible to completely prevent the problem that the gain of the error amplifier is reduced when the clamp unit is connected in parallel to the output node of the conventional error amplifier.

Output stage for a digital circuit

입력 신호에 따라 한 2진값 또는 다른 2진값을 갖는 신호를 방출하는 디지털회로의 출력단이 콜렉터에서 방출될 신호가 탭 오프될 수 있고, 입력 신호에 따른 전류가 베이스에 공급되는 출력 트랜지스터(T1)를 포함한다. 출력 트랜지스터(T1)의 베이스에 이르는 라인에 장치(R1,24)를 설치하여 출력 트래지스터(T1)의 콜렉터-에미터 경로를 통해 흐르는 전류에 따라 베이스 전류를 설정한다. According to the input signal, the output terminal of the digital circuit that emits a signal having one binary value or the other binary value can be tapped off from the collector, and the output transistor T1 is supplied with a current according to the input signal to the base. Include. Devices R1 and 24 are placed on the line leading to the base of the output transistor T1 to set the base current according to the current flowing through the collector-emitter path of the output transistor T1.

Switched mode dcdc converter efficiency improvement by adaptive driver stage

在一种开关模式感应DCDC转换器中，检测组件检测参数，该开关模式感应DCDC转换器具有经由电感器且经由第一开关传导第一电流路径的第一模式以及经由该电感器且经由第二开关传导第二电流路径的第二模式。检测组件输出延长其中一个开关的切断时间的偏置信号以便减少另一开关上的电压累积。

Driving circuit, converter and driving method

一種驅動電路用以驅動一開關元件。驅動電路包含一主輸出端、一第一電壓產生電路以及一第二電壓產生電路。主輸出端電性耦接開關元件。第一電壓產生電路電性耦接主輸出端。第一電壓產生電路包含一第一比較器及電性耦接第一比較器的一分壓電路。第一電壓產生電路用以於一切換週期之開啟期間的預設時間區間內在主輸出端產生一第一電壓。第二電壓產生電路電性耦接主輸出端。第二電壓產生電路用以於切換週期之開啟期間的剩餘時間區間內在主輸出端產生一第二電壓。第二電壓高於開關元件的臨界電壓。預設時間區間早於剩餘時間區間，第一電壓高於第二電壓。

Switching circuit

【課題】半導体スイッチの寄生容量の充放電時間を短縮し、オーバドライブによらず速度の向上と電力効率の向上を図り得るスイッチング回路を提供する。 【解決手段】半導体スイッチ素子２０ａ、２０ｄがＯＮ（ＯＦＦ）のとき残りの半導体スイッチ素子がＯＦＦ（ＯＮ）となるように、各半導体スイッチ素子の入力端子にパルス状信号が印加される。スイッチング回路は、半導体スイッチ素子２０ｂの出力端子と半導体スイッチ素子２０ｄの入力端子の間に接続されるキャパシタンス素子６０と、半導体スイッチ素子２０ｂの入力端子と半導体スイッチ素子の出力端子２０ｄの間に接続されるキャパシタンス素子６１とを備える。キャパシタンス素子６０，６１は、半導体スイッチ素子２０ｂ、２０ｄの各々の入力端子と出力端子間の寄生容量を、半導体スイッチ素子２０ｂ、２０ｄに供給されるパルス状信号のクロック周波数のＮ倍の周波数において低減する容量を有する。 【選択図】図１

Actively tracking switching speed control of a power transistor

A method for driving a transistor includes the steps of: generating an off-current during a plurality of turn-off switching events to control a gate voltage at a gate terminal of the transistor, in which the step of generating an off-current includes sinking a first portion of the off-current from the gate terminal to discharge a first portion of the gate voltage, and sinking a second portion of the off-current from the gate terminal during the boost period to discharge a second portion of the gate voltage; measuring a transistor parameter indicative of an oscillation of a drain-source voltage of the transistor for a first turn-off switching event in which the transistor transitions to an off state; activating the first portion of the off-current for a second turn-off switching event; activating a second portion of the off-current for a second turn-off switching event including adjusting the length of the boost period based on the measured transistor parameter. Thus, the switching loss of the power transistor is reduced.

Switching Mode Converter Providing Safe Bootstrapping Enabling System On Chip And Method For Controlling Thereof

시스템 온 칩 구현이 가능하고 안전한 부트스트랩 기능을 제공하는 스위칭 모드 컨버터 및 그 제어 방법이 개시된다. 본 발명의 일 실시예에 따른 스위칭 모드 컨버터는 일측이 접지와 연결된 제1 반도체 소자의 다른 일측과 입력 전원 사이에 연결되는 스위칭 소자; 일측이 상기 제1 반도체 소자의 상기 다른 일측과 연결되는 부트스트랩 커패시터; 공용 차지 펌프의 출력단과 상기 부트스트랩 커패시터의 다른 일측 사이에 연결되는 전류 소스; 및 상기 부트스트랩 커패시터의 충전과 상기 스위칭 소자의 게이트 전압을 제어하도록 상기 전류 소스의 출력 전류를 제어하는 제어부를 포함하고, 상기 제어부는 상기 부트스트랩 커패시터의 충전 전압을 검출하고, 상기 검출된 상기 충전 전압에 기초하여 상기 전류 소스의 출력 전류를 제어함으로써, 시스템 온 칩(SoC) 구현이 가능하고, 안전한 부트스트랩 기능을 제공할 수 있으며, 스위칭 소자의 게이트 전압이 필요 이상으로 높아지는 것을 방지하여 스위칭 소자를 보호할 수 있고, 외부 커패시터들을 필요로 하지 않기 때문에 제품 단가가 오르는 것을 방지할 수 있다. Disclosed is a switching mode converter and a control method thereof that provide a system-on-chip implementation and provide a secure bootstrap function. A switching mode converter according to an embodiment of the present invention includes: a switching device connected between an input power source and another side of a first semiconductor device connected to ground; A bootstrap capacitor having one side connected to the other side of the first semiconductor element; A current source connected between an output end of the common charge pump and the other end of the bootstrap capacitor; And a control unit for controlling an output current of the current source so as to control the charging of the bootstrap capacitor and the gate voltage of the switching element, wherein the control unit detects a charging voltage of the bootstrap capacitor, By controlling the output current of the current source based on the voltage, it is possible to implement a system on chip (SoC), to provide a safe bootstrap function, to prevent the gate voltage of the switching element from becoming higher than necessary, And it is possible to prevent the product cost from rising because the external capacitors are not needed.

DC voltage converter

본 발명의 벅-부스트 DC-DC 컨버터는 부하의 소비 전력에 따라서 PFM 방식과 PWM 방식 으로 동작 모드를 전환 가능하며, PWM 방식으로 동작하면서도 DCM 모드로 동작할 수 있는 스킴을 제공한다.

Switch drive circuit and battery control circuit

本申请提供一种开关驱动电路，所述开关驱动电路包括开关驱动端口、放电电路、电压产生电路以及驱动端口导通电路。所述放电电路用于为电压产生电路提供供电电压。所述电压产生电路用于根据微控制器输出信号将供电电压进行升压后输出驱动电压，所述驱动电压用于控制与开关驱动端口连接的电子开关模块导通或截止。所述驱动端口导通电路用于根据微控制器输出的第一控制信号以控制开关驱动端口导通电压产生电路与电子开关模块之间的连接。本申请还提供一种电池控制电路。根据本申请实施方式提供的所述开关驱动电路及电池控制电路具备功能安全要求、拓展性强、成本低廉，并且驱动电压及驱动能力可以灵活调整。

Circuit including acceleration components

本发明涉及包括加速元件的电路。电路包括具有第一端子、第二端子和控制端子的切换元件。电路还包括被耦合在控制端子与切换节点之间的阻抗网络。电路还包括被耦合在控制端子与第一节点之间的第一加速元件。该第一节点与切换节点不同。该电路被配置为当切换元件的切换状态将被改变时暂时激活第一加速元件。

Drive circuit

【課題】駆動電圧を調整可能な駆動回路を提供すること。 【解決手段】駆動回路１は、キャパシタＣｘを有するチャージポンプ部３を備えている。チャージポンプ部３のキャパシタＣｘは、オン期間において第１端子ＩＮ１が第２端子ＩＮ２よりも高電位に充電され、オフ期間において第１端子ＩＮ１を負極端子ＩＮＮに接続するとともに第２端子ＩＮ２をメインスイッチング素子Ｍ１のゲートに接続するように構成されている。チャージポンプ部３は、指示信号Ｓ１に基づいてキャパシタＣｘに充電される充電電圧値を調整可能に構成されている。 【選択図】図１

Device for high voltage pulses generation

A circuit arrangement for generating high voltage pulses from DC voltage comprising a transformer, a secondary winding and at least two primary windings of said transformer, said primary windings at least one diode and a switching circuit are serial connected; said series circuit is connected to a voltage source, a capacitor is connected to the common terminal of said voltage source and of said primary windings, further said switching circuit is formed from the emitter-collector-section of a switching transistor, on the base of said switching transistor the output of a transistor amplifier is connected and the input of said transistor amplifier is coupled with the output of the control circuit. According to the invention the input (18) of said transistor amplifier (15) is formed from the base of a second transistor (30), between said input (18) and the output of said control circuit (16) two serial connected resistors (17a and 17b) are inserted, to the common terminal of both said resistors (17a and 17b) the emitter-collector-section of a first transistor (24) is connected, to the base of said first transistor (24) a voltage divider is connected, the branch (25) of which standing on the collector side is divided and connected to said voltage source (7), between the dividing point of said branch (25) and the common terminal of said primary winding (3) of said transformer (1) and of said switching transistor (14) a capacitor (26) is inserted, the resistor (27) of said voltage divider inserted on the emitter side is connected to a current control resistor (28), which is in series with the emitter-collector-circuit of said switching transistor (14).

Gate drive circuit and power conversion device

Insulated gate semiconductor device with built-in control circuit

Frequency Compensation Circuit Comprising Differential Amplifiers with Cross-Coupling Transistors

본 발명의 차동 증폭기는 다알링톤 차동 트랜지스터 쌍 (T 1 /T 3 , T 2 /T 4 ) 및 상기 다알링톤 차동 트랜지스터 쌍(T 1 /T 3 , T 2 /T 4 )의 상호 콘덕턴스를 증가시키기 위한 교차 결합 트랜지스터 쌍(T 5, T 6 )을 포함하며, 교차 결합 차동 트랜지스터 쌍이 설치되므로써 차동 증폭기의 부의 입력 임피던스가 고주파에서 보상되며, 차동 증폭기의 이득은 교차 결합 차동 트랜지스터 쌍(T 5, T 6 )의 제어 전극들 사이의 캐패시터(30) 및 상기 제어 전극과 직렬로 결합된 저항 (26, 28)을 가지는 보상 회로에 의해 감소된다. The differential amplifier of the present invention increases the mutual conductance of a multi-arlington differential transistor pair (T 1 / T 3 , T 2 / T 4 ) and the multi-arlington differential transistor pair (T 1 / T 3 , T 2 / T 4 ). Cross-coupled transistor pairs (T 5, T 6 ), and the negative coupling impedance of the differential amplifier is compensated at high frequencies by the installation of the cross-coupled differential transistor pairs . It is reduced by a compensation circuit having a capacitor 30 between the control electrodes of T 6 and resistors 26 and 28 coupled in series with the control electrode.

Interface control circuit with active circuit charge or discharge

An interface control circuit comprising a buffer, an inverter, an OR gate and delay means. The interface control circuit can be utilized in digital systems for communication handshaking such that a buffer output current will actively flow through line stray capacitance thereby greatly reducing the rise time from a LOW state to a HIGH state, or charges in the line stray capacitance will actively discharge through the buffer means if negative logic mode is used thereby enabling a great reduction in fall time, therefore a much faster and efficient digital system can be obtained through the use of the invention.

Circuit arrangement for controlling a power enhancement MOSFET

The control circuit uses a charge pump, with the gate (G) of the MOSFET (1) coupled via a rectifier (7) and a capacitor (6) to a control terminal (9), receiving an AC signal for switching the MOSFET. The gate-source capacitance of the MOSFET is discharged via a second enhancement MOSFET (10) with the same channel type as the power enhancement MOSFET. The gate of the second enhancement MOSFET is coupled to the junction between a resistor (12) and a third MOSFET (11), with switching of the power enhancement MOSFET via a pair of controlled switches (16,17) associated with respective current sources (18,19) connected to the gates of the second and third MOSFETs.

To Output Ripple Voltage Control the Hysteretic Buck Converter Using Thermister

서미스터를 이용하여 출력 리플 전압을 조절하는 히스테리틱 벅 컨버터는 복수의 레퍼런스 전압들을 공급하는 기준 전압부; 상기 복수의 레퍼런스 전압들 중 적어도 하나와 출력 전압을 비교하는 비교기; 상기 비교기의 출력에 응답하여, 서미스터의 온도에 대응하는 펄스 폭을 갖는 제1 스위치 신호를 생성하는 펄스 컨트롤러; 및 상기 제1 스위치 신호를 기초로 상기 복수의 레퍼런스 전압들 중 어느 하나의 레퍼런스 전압을 선택하기 위한 제어 신호를 생성하는 제어 신호 생성부를 포함한다. A hysteretic buck converter for adjusting an output ripple voltage using a thermistor includes: a reference voltage unit for supplying a plurality of reference voltages; A comparator for comparing an output voltage with at least one of the plurality of reference voltages; A pulse controller responsive to the output of the comparator for generating a first switch signal having a pulse width corresponding to the temperature of the thermistor; And a control signal generator for generating a control signal for selecting any one of the plurality of reference voltages based on the first switch signal.

Patent JPH054849B2

Driving circuit

Driver for switching element and control system for rotary machine using the same

一种开关元件驱动器以及使用该驱动器的回转式机械控制系统。在驱动器中，放电模块响应于驱动信号从接通状态变换到断开状态使开关元件的接通断开控制端以一定放电速率进行放电。改变模块确定是否满足条件，该条件包括在驱动信号的接通状态期间感测信号的电平大于阈值电平，并且在确定满足该条件时，响应于驱动信号从断开状态变换到接通状态使接通断开控制端的放电速率改变。放宽模块使得自驱动信号从断开状态变换到接通状态起经过一时段之后的条件与紧接在驱动信号从断开状态变换到接通状态后的条件相比被放宽。

Power supply apparatus

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor circuit with an insulated gate device and an associated control circuit

CONTROLLING A MOS TRANSISTOR

Controlling a mos transistor

L'invention concerne un dispositif de commande (10) d'un transistor de puissance (5), ledit dispositif comportant : un dispositif d'amplification (15) pour contrôler la grille du transistor (5) via un signal de commande de sortie, ledit dispositif comprenant : une première entrée reliée au drain du transistor, le tout formant une première portion de circuit ; une deuxième entrée reliée à la source du transistor, le tout formant une deuxième portion de circuit. Le dispositif de commande comporte un moyen pour produire un courant de polarisation (I1,I2), ledit courant étant injecté dans une des dites première et deuxième entrées (NEG, POS) de manière à provoquer un décalage de la mesure de tension drain-source et conserver un régime de fonctionnement linéaire dudit signal de commande de sortie, avant l'ouverture du transistor, et un même nombre N de jonctions semi-conductrices dans les première et deuxième portions de circuit. Application notamment sur les dispositifs de chargement de batteries.

DEVICE FOR CONTROLLING AN ELECTRONIC SWITCH OF A CONSUMER

CONTROL DEVICE FOR AN INSULATED GRID SWITCH / SWITCH, HIGH CURRENT, VERY HIGH CURRENT, AND PULSE SWITCH / SWITCH

GRID CONTROL CIRCUIT OF A SWITCHING POWER MOS TRANSISTOR

La présente invention concerne un circuit de commande de grille d'un transistor MOS de puissance 1 dont une première électrode principale D est connectée à une tension haute VC C par l'intermédiaire d'une charge L, dont une deuxième électrode principale S est connectée à la masse et dont la grille G est connectée, pendant la durée de fermeture, à une source de tension basse VD D , comprenant des moyens S1 pour relier au moment de la fermeture du transistor MOS de puissance sa première électrode principale à sa grille. The present invention relates to a gate control circuit of a power MOS transistor 1 of which a first main electrode D is connected to a high voltage VC C via a load L, of which a second main electrode S is connected. to ground and the gate G of which is connected, during the closing time, to a low voltage source VD D, comprising means S1 for connecting, when the power MOS transistor is closed, its first main electrode to its gate.

CONTROLLING A MOS TRANSISTOR

L'invention concerne un dispositif de commande (10) d'un transistor de puissance (5), ledit dispositif comportant :- un dispositif d'amplification (15) pour contrôler la grille du transistor (5) via un signal de commande de sortie, ledit dispositif comprenant :- une première entrée reliée au drain du transistor, le tout formant une première liaison,- une deuxième entrée reliée à la source du transistor, le tout formant une deuxième liaison,caractérisé en ce qu'il comporte :- au moins un courant de polarisation (11) couplé à une des entrées, ledit courant étant destiné à effectuer un décalage de la mesure de tension drain-source pour le dispositif d'amplification (15) commande la grille du transistor (5) en régime linéaire avant de l'ouvrir, et- un même nombre N de jonctions semiconductrices entre la première et la deuxième liaisons.Application notamment sur les dispositifs de chargement de batteries. The invention relates to a device (10) for controlling a power transistor (5), said device comprising: - an amplification device (15) for controlling the gate of the transistor (5) via an output control signal , said device comprising: a first input connected to the drain of the transistor, the whole forming a first connection, a second input connected to the source of the transistor, the whole forming a second connection, characterized in that it comprises: minus a bias current (11) coupled to one of the inputs, said current being for shifting the drain-source voltage measurement for the amplification device (15) controls the gate of the transistor (5) in linear mode before opening it, and the same number N of semiconductor junctions between the first and second links. Application in particular to battery charging devices.

ATTACK CIRCUIT FOR POWER TRANSISTORS IN PARALLEL BRANCHES

L'INVENTION CONCERNE LES CIRCUITS DE COMMANDE DE TRANSISTORS DE PUISSANCE. LORSQUE DEUX TRANSISTORS DE PUISSANCE Q, Q BRANCHES EN PARALLELE ONT DES TEMPS DE DEBLOCAGE DIFFERENTS, LE TRANSISTOR QUI SE DEBLOQUE LE PLUS RAPIDEMENT CONDUIT PENDANT UN CERTAIN TEMPS LA TOTALITE DU COURANT ET PEUT ETRE DETRUIT PAR UN ECHAUFFEMENT EXCESSIF. POUR Y REMEDIER, LE CIRCUIT D'ATTAQUE DE L'INVENTION 52 RETARDE D'UNE VALEUR APPROPRIEE L'INSTANT INITIAL DU DEBLOCAGE DU TRANSISTOR QUI SE DEBLOQUE LE PLUS RAPIDEMENT, AFIN QUE LES DEUX TRANSISTORS ARRIVENT SIMULTANEMENT DANS LEUR ETAT DE CONDUCTION TOTALE. APPLICATION AUX ONDULEURS DE PUISSANCE. THE INVENTION RELATES TO POWER TRANSISTOR CONTROL CIRCUITS. WHEN TWO Q, Q POWER TRANSISTORS IN PARALLEL BRANCHES HAVE DIFFERENT RELEASE TIMES, THE QUICKLY RELEASED TRANSISTOR DRIVES THE ENTIRE CURRENT FOR A CERTAIN TIME AND CAN BE DESTROYED BY EXCESSIVE HEATING. TO REMEDY, THE ATTACK CIRCUIT OF THE INVENTION 52 DELAYS BY AN APPROPRIATE VALUE THE INITIAL INSTANT OF UNLOCKING OF THE QUICKLY UNLOCKED TRANSISTOR, SO THAT THE TWO TRANSISTORS ARRIVE SIMULTANEOUSLY IN THEIR TOTAL CONDUCTION STATE. APPLICATION TO POWER INVERTERS.