Thin-film transistor

A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 mum. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.

Methods of crystalizing amorphous silicon layer and fabricating thin film transistors using the same

Method for fabricating thin film transistor

A liquid crystal display and a method of manufacturing the same

Data transmission apparatus and method

A liquid crystal display

Method for crystalizing amorphous silicon layer and method for fabricating tft

Method of fabricating thin film transistors for a liquid crystal display

Liquid crystal panel having etched test electrodes

A method of manufacturing a liquid crystal panel prevents the introduction of static electricity from the exterior of a liquid crystal panel. According to the method, edges of a lower glass substrate on which a liquid crystal material layer and an upper glass substrate are disposed are dipped into an etchant. At this time, the ends of the test electrodes formed on the lower glass substrate are removed. The ends of the test electrodes are removed, and consequently an introduction path of stripe-shaped defect is not generated within the liquid crystal panel. Also, the yield of the liquid crystal panel is greatly improved.

Thin film transistor with electrodes having compressive and tensile stress

A thin film transistor includes a substrate, a gate electrode on the substrate, a gate insulating layer on the substrate and covering the gate electrode, an active layer on the gate insulating layer, an ohmic contact layer on the active layer and not overlapping the gate electrode, and a source electrode and a drain electrode connected to the ohmic contact layer. Each of the source electrode and the drain electrode has a double-layered structure of a first metal layer having tensile stress and a second metal layer having compressive stress.

Structure of a pad in a liquid crystal display device and a method for manufacturing thereof

An LCD is constructed such that a side edge of a common electrode disposed on an entire surface of an upper substrate and a pad disposed on the lower substrate facing the upper substrate are not overlapped. The LCD includes an active panel having a gate pad and a source pad spaced at a predetermined distance D from the edge of the color filter panel which faces the active panel.

Method of forming an insulating layer pattern in a liquid crystal display

A method of forming an insulating layer pattern in a liquid crystal display which enables the formation of an insulating layer pattern on a substrate under a low temperature without the need of expensive equipment and complicated processes, wherein the formation speed of the insulating layer is accelerated. The method includes the steps of forming an organic thin layer containing silicon on an insulated substrate, exposing the thin layer to a gaseous ambience including, oxygen, generating a plurality of oxygen radicals and silicon radicals by applying ultraviolet rays to the thin layer using a mask having a predetermined pattern, forming an insulating layer by reacting the silicon radicals with the oxygen radicals, and defining an insulating layer pattern by removing a portion of the thin layer free of the ultraviolet rays.

Method for manufacturing a substrate of a liquid crystal display device

A method of manufacturing a substrate of an LCD prevents defective patterning of pixel electrodes and improves an aperture ratio of pixels by simplifying the steps of manufacturing a substrate of an LCD. A protection layer is formed on a substrate and the protection layer includes a light developable organic(BCB) layer which is patterned directly by exposing using a mask instead of patterning with a photo resist. The portion of the light developable organic layer remaining on the bottom part of contact holes after patterning is etched using a gate insulating layer. The etching process using the gate insulating layer is performed partially in order to expose the surface of the gate pad by using a plasma gas having about 85% CF4 and about 15% O2.

Multi-domain liquid crystal display device

A multi-domain vertical alignment liquid crystal display device includes upper and lower substrates having upper and lower alignment layers, a pixel electrode on the lower substrate, and a liquid crystal layer between the upper and lower alignment layers. The upper alignment layer is alignment-treated to define a specified alignment direction. The pixel electrode is arranged to define a desired pattern of slits or floating electrodes. The liquid crystal layer includes liquid crystal molecules having negative dielectric anisotropy (DELTA).

Liquid crystal display having only one common line extending along substrate edge

A liquid crystal display includes a first substrate having a plurality of pixel electrodes arranged in a matrix, a plurality of row terminals and common electrode terminals arranged on one side of two adjacent sides of the first substrate, a plurality of column terminals and common electrode terminals arranged on the other side of the two adjacent sides of the first substrate; a second substrate arranged to be opposite to the first substrate and to interpose a liquid crystal display with the first substrate and having a counter electrode for performing liquid crystal display by applying a voltage across the pixel electrodes and the counter electrode. The conductive region being connected to at least one of the common electrode terminals to apply a common potential to the counter electrode. Instead of using a common drive circuit, a single conductive region is formed along only a single one of the two remaining sides of the first substrate so as to allow for measuring of at least one of ...