СПОСОБ ВЫДЕЛЕНИЯ ВРЕМЕНИ ЗАДАЧИ, ПОЗВОЛЯЮЩИЙ ДЕТЕРМИНИРОВАННОЕ УСТРАНЕНИЕ ОШИБОК В РЕАЛЬНОМ ВРЕМЕНИ

Изобретение относится к области многозадачных систем реального времени. Техническим результатом является выполнение задач приложения реального времени на многозадачном компьютере. Раскрыт способ выполнения задач приложения реального времени на многозадачном компьютере (RTS), причем каждая задача (А, В) содержит по меньшей мере одну операцию (Ti) обработки, причем способ содержит этапы, на которых: определяют временные окна, каждое из которых связано с выполнением операции обработки задачи приложения, выделяют для каждой операции обработки, имеющей временное окно, лимит (Qi) времени и запас (Mi) времени, причем время, выделенное для операции обработки посредством лимита времени и запаса времени, является более коротким, чем продолжительность временного окна, связанного с операцией обработки, во время выполнения приложения многозадачной системой активируют каждую операцию обработки в начале временного окна, с которым она связана, по истечении лимита времени одной из операций обработки активируют ...

СИСТЕМА И СПОСОБ ИЗМЕНЕНИЯ ФУНКЦИОНАЛА ПРИЛОЖЕНИЯ

Изобретение относится к вычислительной технике. Технический результат заключается в увеличении стабильности работы компьютера за счет изменения функционала приложения в зависимости от определенных событий и функциональных модулей. Система изменения функционала приложения содержит функциональные модули антивирусного приложения: файловый антивирус, веб-антивирус, модуль обновления антивирусных баз, средство установки для установки обновления и передачи списка функциональных модулей, для которых было установлено обновление средству наблюдения и средству изменения функционала; средство наблюдения для выявления событий, наступивших с момента установки обновления, и определения превышения порогового значения выявленными событиями; средство изменения функционала для определения функциональных модулей, которые повлияли на превышение порогового значения выявленными средством наблюдения событиями, изменения настроек средства установки таким образом, чтобы далее загружались только обновления антивирусных ...

АВТОМАТИЗИРОВАННОЕ ВОССТАНОВЛЕНИЕ И ПЕРЕДАЧА ПО ИНСТАНЦИИ В КОМПЛЕКСНЫХ РАСПРЕДЕЛЕННЫХ ПРИЛОЖЕНИЯХ

... 1. Способ, выполняемый, по меньшей мере частично, в вычислительном устройстве, для автоматизированного восстановления и передачи по инстанции оповещений в распределенных системах, при этом способ содержит этапы, на которых:принимают от машины отслеживания оповещение, связанное с обнаруженной проблемой;пытаются сопоставить оповещение с действием по восстановлению;если оповещение сопоставлено с действием по восстановлению, то выполняют действие по восстановлению; иначепередают по инстанции оповещение назначенному лицу; иобновляют записи, связанные с сопоставлением оповещения с действием по восстановлению.2. Способ по п.1, дополнительно содержащий этапы, на которых:собирают диагностическую информацию, связанную с обнаруженной проблемой;предоставляют собранную диагностическую информацию назначенному лицу, если оповещение передается по инстанции; ииспользуют собранную диагностическую информацию при обновлении записей.3. Способ по п.2, в котором собранная диагностическая информация включает в ...

СПОСОБ И СЧИТЫВАЕМЫЙ КОМПЬЮТЕРОМ НОСИТЕЛЬ ДЛЯ ЗАГРУЗКИ СОДЕРЖИМОГО ФАЙЛА ДАННЫХ

... 1. Способ загрузки файла данных, включающего в себя одну или более частей, содержащий этапы: выполняют попытку загрузить каждую часть файла данных в первом режиме, причем в первом режиме выполняется минимальная проверка целостности в отношении каждой из частей; определяют в первом режиме, является ли часть файла данных незагружаемой; и в ответ на определение, что часть является незагружаемой, выполняют попытку загрузить файл данных во втором режиме, в котором более тщательную проверку целостности выполняют в отношении каждой из частей и в котором загрузка каждой незагружаемой части пропускается. 2. Способ по п.1, в котором при попытке загрузить файл данных во втором режиме выполняется определение, может ли быть незагружаемая часть восстановлена, и в ответ на определение, что незагружаемая часть может быть восстановлена, восстанавливают незагружаемую часть и загружают восстановленную часть. 3. Способ по п.2, дополнительно содержащий в ответ на определение, что незагружаемая часть не может ...

Mehrrechnersystem in einem Kraftfahrzeug

VERFAHREN ZUR NACHSCHLAGTABELLENFREIEN SPEICHERREPERATUR

Verschiedene Ausführungsformen der vorliegenden Offenbarung richten sich an ein Verfahren zur Speicherreparatur unter Verwendung eines Nachschlagtabelle-freien (LUT-freien) dynamischen Speicherzuweisungsprozesses. Ein Array von Speicherzellen, das eine Vielzahl von Reihen und eine Vielzahl von Spalten aufweist, ist bereitgestellt. Weiter weist jede Speicherzelle des Arrays mehrere Datenzustände und einen permanenten Zustand auf. Eine oder mehrere abnormale Speicherzellen ist /sind in einer Reihe des Arrays identifiziert und in Antwort darauf, dass eine abnormale Speicherzelle identifiziert ist, wird die abnormale Speicherzelle auf den permanenten Zustand gesetzt. Die abnormalen Speicherzellen weisen defekte Speicherzellen und in manchen ausführungsformen Tail-Speicherzellen, die spärliche Arbeitsleistung aufweisen, auf. Während Lese- oder Schreiboperation an der Reihe ist/sind die eine oder mehreren abnormalen Speicherzellen durch den permanenten Zustand identifiziert und ist/sind aus einem ...

VERFAHREN ZUR ÜBERWACHUNG EINES COMPUTER-NETZWERKS.

ELEKTRONISCHE SCHALTUNG

Gemäß verschiedenen Ausführungsformen ist eine elektronische Schaltung beschrieben, die Folgendes umfasst: mehrere Taktgeneratoren, wobei jeder Taktgenerator dazu ausgelegt ist, einen Zählerwert zu speichern, einen Referenztakt zu empfangen, den Zählerwert gemäß dem Referenztakt zu ändern und mindestens ein Taktsignal basierend auf dem Zählerwert zu erzeugen, einen Komparator, der dazu ausgelegt ist, den Zählerwert für jeden von mindestens zwei der mehreren Taktgeneratoren zu empfangen und die empfangenen Zählerwerte zu vergleichen, und eine Fehlerbearbeitungsschaltung, die dazu ausgelegt ist, eine Fehlerbearbeitung basierend auf dem Ergebnis des Vergleichs zu initiieren.

Kommunikationsvorrichtung

Eine Kommunikationsvorrichtung (10) an einem Fahrzeug, die kommunikationsfähig mit zumindest einer anderen Kommunikationsvorrichtung ist, umfasst: eine Erfassungseinheit (S210, S220), die jedes Mal, wenn eine neue Anwendung zu einer Mehrzahl von Anwendungen in zumindest einer der Vorrichtungen, die Kommunikationsvorrichtung und die zumindest eine andere Kommunikationsvorrichtung, hinzugefügt wird, einen Einflussgrad erfasst, der einen Grad an Einfluss auf eine andere der Anwendungen angibt, wenn eine Funktion von zumindest einer der Anwendungen beschränkt ist; eine Reihenfolgefestlegeinheit (S310, S270), die eine Beschränkungsreihenfolge festlegt, die eine Reihenfolge angibt, in der die Funktion der zumindest einen der Anwendungen gemäß dem Einflussgrad beschränkt ist, wenn eine vorgegebene Funktionsbeschränkungsbedingung erfüllt ist; und eine Beschränkungsanweisungseinheit (S370), die zumindest eine der Anwendungen, die in der Funktion zu beschränken ist, anweist, die Funktion gemäß der ...

Schaltungsanordnung zur Gewaehrleistung der Stoersicherheit bei taktpulsgesteuerten Systemen aus Logik- und Speicherelementen

Random access memory recharging method for e.g. command memory, uses subsystem with processor to detect memory error and renew content by an error routine

A RAM e.g. command memory, recharging method, has the RAM as part of a subsystem (SUB2) arranged with a processor (CPU2) on the subsystem so that the occurrence of an error (ERR) in the RAM is detected and the memory content renewed by an error routine controlled by the processor. An independent claim is also included for a subsystem for the above process.

A recovery framework

Method and system for error strategy in a storage system

Insertion of error detection curcuits based on error propagation within intergrated circuits

Methods and systems for batch processing and execution in a process system

Memory management

Reliance control in networks of devices

System error handling in a data processing apparatus

Arbitration and hazard detection for a data processing apparatus

Fault processing for direct memory access address translation

An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

Cooperative error handling system

Multiple trap avoidance mechanism

Notification of faults in redundant devices in a process control system

A process control system for communication in a process control network having a plurality of devices in communication using a bus. The process control system comprises a primary redundant device communicatively linked to the bus, and a secondary redundant device communicatively linked to the bus, and programmed to detect a primary redundant device fault. If the secondary redundant device detects a primary redundant device fault, it publishes a primary redundant device fault message on the bus. A controller deactivates or activates the primary redundant device in response to the publication of a fault or no-fault message. The primary redundant device also performs fault detection. Embodiments disclose the use of input-output (I/O) devices and field devices.

Adaptive SAS PHY configuration

A SAS expander adaptively configures a Serial-Attached-SCSI (SAS) PHY to accommodate varying lengths of a cable coupling the PHY to a remote PHY. The expander (a) configures the SAS PHY with settings of an entry of a table of PHY configuration settings, each entry in the table having different PHY configuration setting values; (b) clears a counter; (c) operates the PHY to communicate with the remote PHY for a monitoring period, after configuring the PHY and clearing the counter; (d) increments the counter when the PHY detects a PHY event during the monitoring period, and otherwise decrements the counter; (e) repeats steps (c) and (d) unless the counter rises above a threshold; and (f) when the counter rises above the threshold, repeats steps (a) through (e), wherein step (a) is performed with the settings of a different entry of the table.

Selectively disabling error repair circuitry in an integrated circuit

Integrated circuit 2 comprises sequential pipeline stages 6, 8 within a processing pipeline, error detection circuitry 10, 12 and error repair circuitry 14. Shadow latch 10 samples and stores an output value of pipeline stage 6 at a time subsequent to the output signal captured by register 4 being applied to pipeline stage 8. When a difference is detected between the output signals stored within register 4 and shadow latch 10, an error is detected and error tolerance circuitry 16 determines, in dependence upon a control parameter, whether to selectively disable error repair circuitry 14. If error repair is performed, an error signal controls multiplexer 14 to switch the value stored in shadow latch 10 for storage in register 4. If a detected error is a tolerable error then error repair circuit 14 remains disabled despite detection of the error. Disabling error repair circuitry may be performed under program control by setting a fault-tolerance mode flag.

Computer system

A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.

Policy-based response to system errors occuring during OS runtime

System for detecting and resetting a device coupled to an inter-integrated circuit router

Embodiments of the present invention provide a system and method for detecting if a device is coupled to an inter-integrated circuit (I2C) router and/or for resetting the device. The I2C router (1605) comprises a first I2C bus port (1620) having a presence line (1660) and/or a reset line (1665). The I2C router (1605) further comprises a control logic (164) coupled to and/or distributed within the first I2C bus port (1620). The control logic (1640) may determine if a device is coupled to the I2C router as a function of a state of the presence line (1660). The control logic (1640) may also determine if a reset condition exists. If a reset condition exists, the control logic (1640) changes the state of the reset line (1665), thereby causing the device to reset itself.

Recovery method management program, recovery method management device, and recovery method management method

Provided are an operation information management storage part (41) for constantly storing operating method information and change-before-and-after-the-operation information for each operation of interest, a recovery method information creation part (33) for creating recovery method information for each of similar operations to be recovered among the operations of interest, a change-before-and-after-the-recovery information creation part (34) for creating the change information before and after the recovery associated with a change in system before and after the recovery for each of the operations to be recovered based on the change-before-and-after-the-operation information being stored, and a recovery method management storage part (42) for managing the recovery method information and the change-before-and-after-the-recovery information for each operation to be recovered. The recovery method information for an unknown failure can be selected based on the operation to be recovered corresponding ...

A monitoring unit as well as method for predicting abnormal operation of time-triggered computer systems

Protected exception handling

Process integrity in a multiple processor system

Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more preferred embodiments of the present invention, an error can be determined while two or more processor cores are processing a first group of two or more work items, and the error can be signaled to an application. The application can determine a state of progress of processing the two or more work items and at least one dependency from the state of progress. In one or more preferred embodiments of the present invention, a second group of two or more work items that are scheduled for processing can be unscheduled, in response to determining the error. In one or more preferred embodiments of the present invention, the application can process at least one work item that caused the error, and the second group of two or more work items can be rescheduled for processing.

Cache control in fault handling in address translation transactions

Cache management circuitry responds to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction. Such that a valid bit associated with each entry in the cache is set to invalid for the address translations, invalid entries being available for update and not forming part of any lookup in the cache. Alternatively, in response to identification of a transaction stall fault to set a stall indicator associated with all address translations in the cache that relate to the context of the faulting transaction. This allows a processor for processing a stream of instructions to use a hierarchical memory system having a cache, where the memory stores tables having virtual to physical address translations, to maintain access to translations for stalled operations, ready for a resume instruction, but invalidate entries where a transaction needs to be terminated.

Livelock recovery circuit

A livelock recovery circuit 104 monitors control signals of a processor 102 and causes the processor to transition to a known safe state when live-lock is detected. The circuit includes detection logic 108 to detect that the processor is in livelock when it has illegally repeated an instruction; and transition logic 110 to cause the processor to transition to a safe state when livelock has been detected. The detection can be based on: the frequency of repetition exceeding a threshold; fetching the same instruction two times within a predetermined number of consecutive fetches; fetching an instruction from the same address between a start and a stop event, e.g. the processor being in an idle state. Known states can be idle states and transitions to them may comprise invoking an interrupt. The processor can be single cycled non pipelineed or pipelined. Uses include system-on-chips (SoCs) implementing complex finite state machines (FSM).

Autonomic parity exchange in data storage systems

A computer-implemented method is provided for increasing the failure tolerance of an array of storage elements in a storage system. The computer-implemented method includes configuring an array to include a plurality of storage elements in n > 1 sets of storage elements. The computer-implemented method also includes configuring an erasure-correcting code such that at least one column of the storage elements of the array stores row parity information, and at least one row of the storage elements of the array stores column parity information. Still yet, the computer-implemented method includes, subsequent to a failure of one of the storage elements storing data, selecting a recipient storage element from the array, and rebuilding at least a portion of the data onto the recipient storage element by performing a parity exchange operation that retains a failure tolerance of the set of storage elements containing the failed storage element.

Memory scanning operation in response to common mode fault signal

Fault Handling in Address Translation Transactions

A monitoring unit as well as method for predicting abnormal operation of time-triggered computer system

Hardware-based sensor analysis

A method of monitoring messages from a sensor (fig.2, 202) using an integrated circuit, the messages comprising data measured by the sensor, the method comprising: reading a first message from interconnect circuitry (fig.2, 206) of the integrated circuit 502, the interconnect circuitry connecting the sensor to a core device configured to process the message; calculating a first hash value for the first message 504; comparing the first hash value to a prior hash value stored in a hash store 506, each prior hash value corresponding to a message read from the interconnect circuitry prior to the first message; and performing a corrective action 510 if the difference between the first hash value and at least one of the prior hash values stored in the hash store is below a predetermined threshold; and a second independent claim to an associated integrated circuit chip. The corrective action may comprise informing a user that the sensor data is unreliable, disactivating components, and activating ...

System comprising an electronics module

A system comprises an electronics module 100 arranged to be removably mechanically coupled to a wearable article 200. The electronics module forms a communicative connection with the wearable article so as to receive measurement data from the wearable article when the electronics module is mechanically coupled to the wearable article. The system also comprises at least one processor operable to analyse measurement data obtained when the electronics module is mechanically coupled with the wearable article to determine whether an anomaly condition is present, wherein the anomaly condition is indicative of an anomaly in the communicative connection between the electronics module and the wearable article, and if the anomaly condition is present, trigger a compensation to be applied to obtained measurement data so as to compensate for the anomaly in the communicative connection between the electronics module and the wearable article. The compensation my be a scaling factor to be applied to the ...

DATA PROCESSING SYSTEM

Method for operating a digital system and digital system incorporating such method

A method of operating a digital system operable in multiple operational states having a digital resource and an event detector that detects events of the digital resource comprises the steps of determining an operational mode of at least one of the system and the digital resource in effect during an interval and accumulating a number of events that occur during the interval. The method further includes the steps of comparing accumulated events against at least one threshold associated with the operational mode and implementing at least one of isolationist, limiting, and corrective action if the comparison indicates an out-of-nominal operation of the digital resource, A digital system incorporating the method is also disclosed.

Blockchain management of provisioning failures

In an approach to blockchain management of cloud service provisioning failures, one or more computer processors capture one or more application programming interface (API) calls associated with a service provision. One or more computer processors submit the captured one or more API calls to a blockchain ledger. One or more computer processors detect a system failure during the service provision. One or more computer processors extract the submitted one or more API calls from the blockchain ledger. Based on the extracted one or more API calls, one or more computer processors identify a problematic system associated with the system failure.

Error information processing method and device, and storage medium

An error information processing method includes, in response to a memory error triggering an interrupt, collecting error information of the memory error that includes a first memory area where the memory error occurs, obtaining a second memory area for writing log information, determining whether the second memory area contains the first memory area, and, in response to determining that the second memory area contains the first memory area, skipping a process of writing the log information into the second memory area.

Ml-based event handling

The invention relates to a computer-implemented method for processing events. The method provides a database comprising original event objects stored in association with canonical event objects. The method executes a learning algorithm on the associated original and canonical event objects for generating a trained ML program adapted to transform an original event object of any one of the one or more original data formats into a canonical event object having the canonical data format and uses the trained machine learning program for automatically transforming original event objects generated by an active IT-monitoring system into canonical event objects processable by an event handling system.

Microservices change management and analytics

Managing microservice changes and performing related analytics can include generating a plurality if process instance representations. Each process instancere presentation can be generated based on a corresponding process path that comprises an ordered sequence of operations that are performed by a process using multiple microservices. a microservices network representation can be constructed based on the plurality of process instance representations, each element of the microservices network corresponding to an interface between a pair of the microservices. Based on the microservices network representation, a relative frequency can be determined for each of the microservices, each relative frequency corresponding to a likelihood that a change in a microservice will affect the performance of at least one process using at least one of the microservices.

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

CHANGED HARVARD ARCHITECTURE PROCESSOR, WITH PROGRAM MEMORY EINGEMAPPTEM DATA MEMORY AND PROTECTION FROM INCORRECT EXECUTION

FENCE MECHANISM FOR CLIENT ERRORS FOR THE FENCE OF NETWORK FILE SYSTEM DATA IN A HOST CLUSTER ENVIRONMENT

MEMORY SYSTEM

MECHANISM FOR THE ENTERPRISE OF A MICROCOMPUTER SYSTEM

SWITCHING CONFIGURATION FOR THE OPERATING SUPERVISION OF MICROPROCESSORS OR MICROCOMPUTERS

PROCEDURE FOR THE SOFTWARE FAULT TREATMENT

MULTIPROCESSOR SYSTEM WITH REPEATED COMMAND SOURCES

INTELLIGENT ERROR ADMINISTRATION

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

PROCEDURE AND COMPUTER-READABLE DATA MEDIUM FOR THE SHOP OF CONTENTS OF A FILE

WATCH-DOG TIMER CIRCUIT

Activity detection in web applications

A computing system includes a web server, client computing devices, a proxy between the web server and the client computing devices, and an analytics server. Each client computing device is operated by an end-user to access an application based on end-user events resulting in representational state transfer (REST) calls to the web server. The proxy passes through the REST calls to the web server and returns responses from the web server, with the return responses corresponding to activities being performed within the web application. The analytics server correlates the end-user events with the corresponding REST calls and return responses from the proxy for each client computing device, and uses vectorization to compare similar activities. The analytics server associates the similar activities with a quality indicator to identify anomalies within the application for corrective action to be taken.

Automated identification of device status and resulting dynamic modification of device operations

Techniques are described for automatically and dynamically modifying ongoing operations of computing devices in device-specific manners, such as based on an automated identification of a computing 5 device's status (e.g., identifying a likely ongoing or imminent failure of a smart phone or other computing device based on a series of observed hardware states of the computing device, and taking automated corrective actions to prevent or otherwise mitigate such device failure, such as by modifying configuration settings on the computing device or on associated 10 systems). The techniques may include, for each of multiple device status outcomes of interest (e.g., device failure versus device non-failure), generating a state-space outcome model representing devices that reach that status outcome within a time period of interest, and using such outcome models to identify a likely ongoing or imminent outcome of a current device, 15 with corresponding automated corrective actions then taken.

Method and system for performing diagnostics or software maintenance for a vehicle

A method and system for performing diagnostics or software maintenance on a vehicle comprises a data processor (71) for performing a particular task. A resource monitor (74) is arranged for determining if resource consumption of the data processor (71) for the respective particular task exceeds a threshold amount of resource consumption. A loop counter (75) is arranged to increment a loop counter (75) in a data storage device (56) associated with the data processor (71) if the resource consumption for the respective particular task exceeds the threshold amount. A poison task module (65) is capable of designating the particular task as a poison message if the data processor (71) has been rebooted a maximum number of times as indicated by the loop counter (75).

Home appliance diagnosis system, and method for operating same

The present invention relates to a home appliance diagnosis system and to a method for operating same, wherein product information is output in a predetermined signal sound by a home appliance product, and the signal sound is transmitted via a communication network connected to a remote service center to enable the service center to easily check the state of the home appliance product. In addition, the product information is encoded into a predetermined format and converted to enable sound to be outputted by the home appliance product, thereby preventing noise or signal errors. The present invention enables stable signal conversion and accurate sound output, and enables the easy recovery of the sound transmitted to the service center via the communication network.

A method, system and apparatus for providing monitoring of electronic transactions

SYSTEM AND METHOD FOR TAKING SEQUENCE OF DYNAMIC RECOVERY ACTIONS FROM NETWORK MANAGEMENT SYSTEM SUPPORTING SNMP PROTOCOL

The present invention relates to a system and method for enabling SNMP (Simple Network Management Protocol) based Network Management System to correlate and control sequence of recovery actions to be performed and dynamically change the recovery action sequence across various systems/platforms/devices. Disclosed is a system for taking sequence of dynamic recovery actions in network management system upon occurrence of a fault, in one aspect of the present invention. The system includes an action definition repository containing a sequence of recovery actions for the fault in a particular business scenario. The action definition repository is initialized and updated for every new scenario. The system further includes an action sequence engine being capable of reading the recovery sequence listed in the action definition repository for the fault in the particular business scenario. The action sequence engine sends a list of enhanced SNMP SET commands to agent module to enable the recovery ...

Asset health scores and uses thereof

Disclosed herein are systems, devices, and methods related to assets and asset operating conditions. In particular, examples involve defining and executing predictive models for outputting health metrics that estimate the operating health of an asset or a part thereof, analyzing health metrics to determine variables that are associated with high health metrics, and modifying the handling of abnormal-condition indicators in accordance with a prediction of a likely response to such abnormal-condition indicators, among other examples.

Information service terminal communication adapter

A method and system for displaying and providing access to data on a monitor

CACHE RESILIENCY IN PROCESSING A VARIETY OF ADDRESS FAULTS

METHOD FOR ELIMINATING AN ERROR IN A DATA PROCESSING UNIT

The invention is characterized in that the data processing unit detects the error and then sends a first coded message to a central data processing facility. The central data processing facility decodes the signal and evaluates information on the error contained in the first message. Depending on the result of said evaluation, the central data processing facility then generates and/or selects an error elimination routine. The central data processing facility issues a program instruction that can be executed by the data processing unit. The program instruction is then coded by the data processing facility and sent to the data processing element as part of a second message.

CLIENT SELECTABLE SERVER-SIDE ERROR RESOLUTION

An illustrative embodiment of a computer-implemented process for client selectable server-side data error resolutions receives a request from a client to perform an action on a server, identifies a data error during performance of the action of the request and generates a response including an error description and a resolution subset for the identified error. The computer-implemented process further sends a response to the client, receives a selected resolution returned from the client, and responsive to a determination the selected resolution associated with the token returned executes on the server, executes the selected resolution, associated with the token returned, on the server to correct the data error.

SECURITY APPLIANCE EXTENSION

Systems and methods are disclosed that receive and characterize security event data. Based upon a customized severity characterized security event data, presentation and/or control actions, such as prioritized presentation and alarm generation are performed.

MALFUNCTION DETECTION SYSTEM FOR A MICROPROCESSOR BASED PROGRAMMABLE CONTROLLER

MALFUNCTION DETECTION SYSTEM FOR A MICROPROCESSOR BASED PROGRAMMABLE CONTROLLER Hardware is employed at the I/O interface racks of a programmable controller to detect fault conditions. An I/O fault line is connected in daisy chain fashion between the I/O interface racks and the controller processor, and when a fault is indicated at any of the I/O interface racks it is communicated to the controller processor. The indicated I/O fault freezes, or holds, the microprocessor in the controller processor, and if the I/O fault persists for a preselected time interval, all operating devices connected to the programmable controller are decontrolled. Means are also provided in the controller processor for detecting malfunction conditions and when such a condition is detected, the operating devices connected to the programmable controller are decontrolled.

MULTI-LEVEL INFORMATION PROCESSING SYSTEM

FAULT DETECTION AND HANDLING ARRANGEMENTS FOR USE IN DATA PROCESSING SYSTEMS

ACTIVITY DETECTION IN WEB APPLICATIONS

A computing system includes a web server, client computing devices, a proxy between the web server and the client computing devices, and an analytics server. Each client computing device is operated by an end-user to access an application based on end-user events resulting in representational state transfer (REST) calls to the web server. The proxy passes through the REST calls to the web server and returns responses from the web server, with the return responses corresponding to activities being performed within the web application. The analytics server correlates the end-user events with the corresponding REST calls and return responses from the proxy for each client computing device, and uses vectorization to compare similar activities. The analytics server associates the similar activities with a quality indicator to identify anomalies within the application for corrective action to be taken.

METHOD AND ARCHITECTURE FOR CRITICAL SYSTEMS UTILIZING MULTI-CENTRIC ORTHOGONAL TOPOLOGY AND PERVASIVE RULES-DRIVEN DATA AND CONTROL ENCODING

The present disclosure relates to novel and advantageous systems and methods of processing and managing data in critical or large-scale systems, such as airliner, automobile, space station, power plant, and healthcare systems. Particularly, the present disclosure relates to a rules-driven data and control method mapped onto complementary physical architecture for a more reliable operational system. By maintaining an algebraic encoding of control and application data at fine granularities, whether static or in transit, it is possible to detect, isolate, and correct many errors that would otherwise go undetected. This more dynamic and precise method addresses cases where deteriorating conditions or cataclysmic events affect much of the system simultaneously, including the control system itself.

VALIDATION OF TEST RESULTS IN NETWORK TESTING

A network testing system includes one or more test devices each including a media-specific testing module and a processing device with a network interface, wherein the processing device is configured to test a network with the media-specific testing module; one or more servers configured to receive test results from the test of the network either directly from the one or more test devices or an intermediate data source communicatively coupled to the one or more test devices; and a validator module executed on the one or more servers configured to perform automated post-processing on the test results to compare the test results to a pre-defined Method of Procedure (MOP), to auto-correct one or more errors in the test results, and to provide a report based on the comparison.

REMOTE SHUTDOWN VIA FIBER

A system and method provide vital shutdown of a remote slave unit linked by a fiber optic connection to a local, checked redundant master unit with two paired computers. Each computer sends a life signal to an associated local vital supervision card (VSC) and copper to fiber converter (C/F converter) for transmission via fiber to a corresponding fiber to copper converter (F/C converter) on the slave unit, then to a corresponding remote VSC. Each local VSC controls power to a corresponding second local VSC-associated C/F converter, and each remote VSC controls power to a corresponding second remote VSC F/C converter. A VSC detecting an incorrect life signal signature removes power to the corresponding controlled converter and, optionally, to a respective local or remote I/O rack, thereby shutting down the slave unit.

SYSTEM AND METHOD FOR DATA CENTER RECOVERY

An improved approach for disaster recovery is provided, along with corresponding systems, methods, and computer readable media. ln the improved approach, a set of applications are assigned one or more application weightings (e.g., based upon asset type, a recovery time objective, a recovery time capability, a criticality to key business functions, vendor hosting, interfaces with other systems), etc. The one or more application weightings are utilized for ranking the applications, and the ranked set of applications is utilized to generate a disaster recovery boot sequence whereby specific recovery tasks and infrastructure device requirements are arranged temporally to achieve one or more recovery time conditions.

SYSTEMS AND METHODS FOR PROTECTION OF COMPONENTS IN ELECTRICAL POWER DELIVERY SYSTEMS

Various embodiments disclosed herein provide protection to monitored equipment at both a local level and a system level, in order to offer more comprehensive protection. In one particular embodiment, the protected equipment may include one or more generators. The protection system may utilize time- synchronized data in order to analyze data provided by systems having disparate sampling rates, that are monitored by different equipment, and/or equipment that is geographically separated. Various embodiments may be configured to utilize a variety of sampling rates.

SYSTEM, METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MOBILE DEVICE SUPPORT SERVICES

A method is provided for providing mobile device support services. The method may include monitoring a mobile device status. The method may additionally include performing device diagnostics based at least in part on captured device status data to identify potential faults that may affect mobile device functionality. A corresponding system, apparatus, and computer program product are also provided.

SYSTEMS AND METHODS FOR CONFIGURATION MANAGEMENT

Aspects of the present disclosure describe systems and methods for automatically configuring, managing, updating, and/or monitoring the configuration of various computing resources and/or network devices within a communications network, such as a telecommunications network. Configuration code may be deployed to a repository for a cluster of computing resources and one or more layers may be defined describing configurable aspects of the cluster. Subsequently, a script may be identified and executed to configure the cluster based on the configuration code.

FAULT-TOLERANT COMPUTER SYSTEM WITH ONLINE REINTEGRATION AND SHUTDOWN/RESTART

FAULT-TOLERANT COMPUTER SYSTEM WITH ONLINE REINTEGRATION AND SHUTDOWN/RESTART A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit of offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. The system employs a pseudo-filesystem to dynamically manage the hardware components. A directory which appears as a standard, hierarchical ...

Message queue management

Various embodiments provide message queue management techniques designed to reduce the likelihood of multi-component applications becoming nonresponsive and enable recovery options for individual components if they do become nonresponsive. In at least some embodiments, a message queue manager detects when a component of an application interface becomes nonresponsive and detaches the component from a shared message queue. The shared message queue can continue to process messages for other responsive components while messaging for the nonresponsive component is managed via a separate queue. The message queue manager can also notify a user regarding the nonresponsive component and provide the user with options to facilitate recovery of the nonresponsive component. Further, in at least some embodiments, the message queue manager can monitor a detached component and reattach the detached component when it becomes responsive again.

Implementing lane shuffle for fault-tolerant communication links

A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.

Server having memory dump function and memory dump acquisition method

A server having a plurality of system boards, comprising: a panic processing unit configured to stop (panic) the server; a system board information storage unit configured to store information to identify a system board having a memory used by a kernel; a system board detaching processing unit configured to detach the system board having the memory used by the kernel before server stoppage; and a reboot processing unit configured to reboot the server using system boards other than the separated system board among the plurality of system boards, after detaching the system board having the memory used by the kernel.

Allocation method and apparatus of moderate memory

An allocation method comprises: partitioning moderate memory into a plurality of physical memory pages having predetermined page size according to the predetermined page size; scanning the moderate memory using the predetermined page size and recording the physical address and damage degree of each physical memory page; obtaining the allocation information of the physical memory pages when a memory request is received and allocating physical memory to the request based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information. A moderate memory is scanned and the physical address and damage degree of each physical memory page are recorded, then the physical memory is allocated based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information.

VIOS Cluster Alert Framework

In a data processing system including a virtual I/O server (VIOS) cluster and multiple logical partitions (LPARs), at least one VIOS of the VIOS cluster performs functions of: receiving first registration information from one or more entities within the VIOS cluster; registering, based on the first registration information, a handler associated with a first message type; responsive to receiving second registration information, registering, based on the second registration information, a listener associated with a second message type; receiving a first message associated with a first alert event of the cluster; determining, based on the first message, that the handler is associated with the first message type; and calling the handler. In one embodiment, the handler is associated with a pointer to a subroutine, and registering the handler includes storing the pointer in a data structure that associates the handler with the first message type.

Systems and methods for controlling and managing personal data communications

Disclosed herein are systems and methods for controlling and managing personal data communications. According to an aspect, a method may be computer-implemented for controlling data communications. The computer-implemented method may include receiving and storing data from at least one electronic device. Further, the computer-implemented method may include controlling access to the data using at least one user control space. The computer-implemented method may also include managing the data using the at least one user control space. Further, the computer-implemented method may include communicating with at least one other electronic device using the at least one user control space.

Memory channel having deskew separate from redrive

A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.

Redundant computing system and redundant computing method

A redundant computing system is composed of two systems: a first arithmetic processing unit (A-system) and a second arithmetic processing unit (B-system) having the same functions. A diagnosis control unit performs diagnosis of one system while the other system is performing arithmetic processing operation. The diagnosis control unit controls the input to the first and second arithmetic processing units by way of an input control unit according to the diagnosis operation, and an output control unit controls the output from the first and second arithmetic processing units according to the diagnosis result. After termination of the diagnosis, a value is copied from a storage unit of the system which has not been diagnosed to a storage unit of the system which has been diagnosed, and the redundant computing system resumes the redundant operation.

System and Method for Self-Supporting Applications

A method and system self-supportable devices and applications are provided. The method and system in one embodiment allows devices and applications to automatically communicate and service themselves, for example, by checking knowledgebase services and other services for instructions on how to handle an exception. In another embodiment, the devices and applications automatically initiate actions needed to handle the exception.

Memory system with interleaved addressing method

Disclosed is a memory system which includes a nonvolatile memory device including a memory cell array having a plurality of word lines including a first set of word lines storing first data having a high bit error rate, and a second set of word lines storing second data having low bit error rate less than the high bit error rate, and a memory controller that during a program operation maps logical addresses for a portion of the first data and a portion of the second data onto a selected word line selected from the plurality of word lines.

Controller Election

A method of controller election includes, upon failure of a master controller within a team comprising a number of controllers, automatically promoting another of the number controllers to serve as an elected master controller and designating the elected master controller as a new master controller if it is determined that the failure of the master controller is not temporary.

Partial fault processing method in computer system

As regards a hardware fault which has occurred in a computer, a hypervisor notifies an LPAR which can continue execution, of a fault occurrence as a hardware fault for which execution can be continued. Upon receiving the notice, the LPAR notifies the hypervisor that it has executed processing to cope with a fault. The hypervisor provides an interface for acquiring a situation of a notice situation. It is made possible to register and acquire a situation of coping with a hardware fault allowing continuation of execution through the interface, and it is made possible to make a decision as to the situation of coping with a fault in the computers as a whole.

Method and system for monitoring a monitoring-target process

A method and system for monitoring a monitoring-target process. A monitored server computer starts a monitoring-target process. After starting the monitoring-target process, the computer ascertains a current operating state of the monitoring-target process which includes utilizing a monitoring condition record included in a monitoring-condition registry. The monitoring-condition registry is a file or database stored in a data storage device in the computer. The monitoring condition record includes monitoring conditions controlling implementation of the monitoring-target process. The monitoring condition record includes a process label that uniquely identifies the monitoring-target process. After ascertaining the current operating state, the computer stops the monitoring-target process.

Real-Time Diagnostics Pipeline for Large Scale Services

Real-time diagnostics may be provided. A plurality of data feeds may be aggregated from at least one of a plurality of nodes. Upon determining that at least one element of at least one of the data feeds meets a trigger condition, an action associated with the trigger condition may be executed.

Cache locking control

Each cache line of a cache has a lockout state that indicates whether an error has been detected for data accessed at the cache line, and also has a data validity state, which indicates whether the data stored at the cache line is representative of the current value of data stored at a corresponding memory location. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. In response to a cache invalidation event, the state of the lockout indicators for each cache line can be maintained so that locked out cache lines remain in the locked out state even after a cache invalidation. This allows memory error management software executing at the data processing device to robustly manage the state of the lockout indicators.

Health monitoring of applications in a guest partition

A health monitoring technique monitors the health and performance of applications executing in a guest partition in a virtualized environment. In an embodiment, a guest integration component interacts with an application through an application programming interface in order for the virtualization platform to monitor the health and performance of the application. In another embodiment, the guest integration component may include a monitoring agent that accesses an event log and/or a performance monitor log to access the health and performance of the application. The health and performance of the application may then be analyzed by the virtualization platform to determine an appropriate remedial action.

Technical support agent and technical support service delivery platform

An embodiment of a method for providing technical support service includes generating a plurality of problem resolutions that are determined to resolve an identified technical problem; attributing weights to each of said plurality of problem resolutions according to frequency of use; and in response to a request to resolve said identified problem, selecting a problem resolution from among said plurality of problem resolutions based at least in part on said attributed weights.

Method for processing data of a control unit in a data communication device

A method for processing data of a control unit in a data communication device, which has a first memory area and a second memory area, and is connected to the control unit through an interface. Data from the control unit is transmitted to the data communication device through the interface. A value is stored identically in the first memory area and in the second memory area. The data communication device tests whether a first trigger is present, and if present, storage in the first memory area is discontinued, or the trigger class of the first trigger is tested and storage in the first memory area is discontinued only in the presence of a predefined trigger class. Subsequently, values of the data are read out from the first memory area, whereby values arriving chronologically after the first trigger are stored in the second memory area by the data communication device.

Protection system for server

A protection system includes a baseboard management controller (BMC), N fans, a power on unit, a power supply, and a switching unit. The switching unit includes an AND gate, a transistor, and a first resistor. During operation the fans each output an operating signal to the BMC. The BMC counts the operating signals received. When the count is less than N, the power-off pin outputs a low level signal, so that the output pin of the AND gate outputs a low level signal, and the transistor turns off. The power supply then receives a high level signal and stops supplying power.

Storage control apparatus

An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first processor to a first guest and a second processor to a second guest from among the plurality of processors, and an interrupt control module that receives an interrupt from the I/O device and transmits the interrupt to any one of the plurality of processors, wherein the virtualization module comprises, a state detection module that detects at least one of a state of the first guest and a state of the first processor, and an interrupt delivery destination control module that switches the interrupt with respect to the first processor to the second processor when at least one of the state of the first guest and the state of the first processor becomes a predetermined state.

System and Method of Performing Remote Diagnostics on a Computing Device

A user's cellular communication device communicates with a peer cellular communication device to perform diagnostic or repair functions on a computer connected to the user's device. The user's device is connected to the computer via a cable. The remote device commands the user's device to query the computer via the cable connection for information about the computer. Based on that information, the remote device generates commands to send to the user's device. Upon receipt, the user's device employs the commands to execute selected diagnostic and repair programs resident on the computer.

Diagnostic and managing distributed processor system

A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

Server cluster and control mechanism thereof

A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node performs an operation system and respectively includes a network port, a network chip and a south bridge chip. The network port is connected to the network switch via a cable. The network chip outputs a power-off signal according to a received power-off packet after the network switch is started. The south bridge chip outputs a shutdown signal to shut down the server node according to the power-off signal when the server node is turned on and the operation system is working normally.

System and Method for Provisioning and Running a Cross-Cloud Test Grid

An automated method for provisioning a grid used to run a load test on a target website includes sending one or more requests in a multi-threaded manner to at least one cloud provider, the one or more requests for an allocation of N load server instances and M result server instances which comprise the grid. Requests received back from the cloud provider are also handled in a multi-threaded manner; any errors occurring during the allocation being corrected automatically. The N load server instances and the M result server instances are then verified to be operational and correctly running software deployed to provide defined test services. Errors identified during the verification are automatically corrected either by attempting to restart a failed instance or allocating a different instance. 123-. (canceled)24. A method of cloud computing comprising:executing a program on a first computing device that allows a user to specify parameters of a computing grid for use in running a load test composition on a target website or web-based application, the parameters including a first number of load server instances and a second number of result server instances;responsive to a first user input, automatically provisioning the computing grid by interacting with an application programming interface (API) of one or more cloud providers to allocate the first number of load server instances and the second number of results server instances, and to deploy software that runs on the load server instances and the result server instances needed to execute the load test composition.25. The method of wherein the automatic provisioning comprises sending one or more requests to the cloud providers an allocation of the first number of load server instances and the second number of result server instances.26. The method of wherein the automatic provisioning further comprises handling responses to the one or more requests received from the cloud providers claim 25 , the handling of the ...

SYSTEMS AND METHODS FOR AUTOMATIC REPLACEMENT AND REPAIR OF COMMUNICATIONS NETWORK DEVICES

Systems and methods for automatic repair, replacement, and/or configuration of various network devices within a communications network are disclosed. The system may receive indication of a failed network device and automatically perform diagnostic on the network device to determine any problems associated with the hardware and/or software components within the network device. Subsequently one or more repair, replacement, and/or configuration procedures may be automatically initiated in an attempt to resolve the problems and restore the failed network device. 1. A method for automatic repair of network devices in a communications network comprising:identifying, at a processor, a network device in a communications network;identifying, in a database, a profile comprising device identification information corresponding to the network device;establishing, using the processor, communication with the network device based on the identification information to determine a status for the network device; andinitiating, using the processor, at least one repair procedure to restore the network device based on the status.2. The method of claim 1 , wherein the status of the network device is unavailable.3. The method of claim 2 , wherein the at least one repair procedure comprises a replacement procedure to replace at least one component in the network device or a repair procedure for the network device.4. The method of claim 1 , wherein the status of the network device is available claim 1 , the method further comprising:accessing, at the processor, the network device to obtain state information for the network device;parsing, at the processor, the state information to identify at least one application executable by the network device; andrestoring, at the processor, the at least one application to an acceptable state on the network device, wherein initiating the at least one repair procedure to repair the network device is based on the state information and the at least one ...

Asics having programmable bypass of design faults

A relatively small amount of programmable logic may be included in a mostly ASIC device such that the programmable logic can be used as a substitute for a fault-infected ASIC block. This substitution may occur permanently or temporarily. When an ASIC block is temporarily substituted, faulty outputs of the ASIC block are disabled just at the time they would otherwise propagate an error. The operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed programmable logic. Thus, a fault-infected ASIC block that operates improperly 1% of the time can continue to be gainfully used for the 99% of the time when its operations are fault free. This substitution can be activated in various stages of the ASIC block's life including after: initial design; pilot production; and mass production. This provides for cost saving and faster time-to-market, repair, and maintenance even years after installation and use.

Method for processing booting errors

A method for processing booting errors for a computer having multiple voltage regulator downs (VRDs) includes reading a boot sequence including multiple power-on stages, and each power-on stage corresponds to a boot voltage and one of the VRDs; performing the power-on stages according to the boot sequence, and determining whether an output voltage of the VRD corresponding to each power-on stage is equal to the corresponding boot voltage; and when the output voltage of any one of the VRDs is not equal to the corresponding boot voltage, performing a debugging procedure.

Voltage control

An apparatus for controlling a supply voltage to an electronic processing arrangement comprising a processor or a memory element, the apparatus being configured to receive an output of the electronic processing arrangement and comprising: error detection means for detecting errors in an output of the electronic processing arrangement; and means for adaptively varying the supply voltage to the electronic processing arrangement based on an analysis of errors detected in the output of the electronic processing arrangement. The apparatus may further comprise means for correcting errors detected in the output of the electronic processing arrangement.

Preventing Disturbance Induced Failure in A Computer System

A method to prevent failure on a server computer due to internally and/or externally induced shock and/or vibration. The method includes acquiring, by at least one sensor, analog acceleration data of components in a server computer. The data is then converted to digital format and stored within a motor drive assembly processor memory unit. The processor analyzes the stored data for existence of machine degradation. In response to detecting the existence of machine degradation, the motor drive assembly processor initiates remediation procedures. The remediation procedures include controlling rotating speed of moving devices or performing a complete system shut down. 1) A method to prevent failure on a server computer due to disturbance , the method comprising:acquiring, by at least one sensor, analog acceleration data of at least one component in a server computer;converting, by a computer processor, the analog acceleration data to digital form;storing the converted data within a motor drive assembly processor memory unit;analyzing said stored data for existence of machine degradation; andin response to detecting the existence of machine degradation, initiating, by the motor drive assembly processor, remediation procedures.2) The method of claim 1 , wherein the sensors comprise tri-axial accelerometers imbedded in motor drives assemblies of rotating components within the computer.3) The method of claim 1 , wherein analyzing comprises an action selected from the group comprising: periodic monitoring and comparing of peak acceleration data points against a peak of a “known good” component acceleration claim 1 , periodic monitoring and comparing a FFT (Fast Fourier Transform) acceleration data against a FFT of a “known good” component acceleration claim 1 , and periodic monitoring and comparing a Kurtosis of acceleration data.4) The method of claim 1 , wherein initiating remediation measures comprises an action selected from the group comprising: slowing down at least ...

UNFUSING A FAILING PART OF AN OPERATOR GRAPH

Techniques for managing a fused processing element are described. Embodiments receive streaming data to be processed by a plurality of processing elements. Additionally, an operator graph of the plurality of processing elements is established. The operator graph defines at least one execution path and wherein at least one of the processing elements of the operator graph is configured to receive data from at least one upstream processing element and transmit data to at least one downstream processing element. Embodiments detect an error condition has been satisfied at a first one of the plurality of processing elements, wherein the first processing element contains a plurality of fused operators. At least one of the plurality of fused operators is selected for removal from the first processing element. Embodiments then remove the selected at least one fused operator from the first processing element. 1. A method of managing a processing element , comprising:receiving streaming data to be processed by a plurality of processing elements, the processing elements processing at least a portion of the received data by operation of one or more computer processors;establishing an operator graph of the plurality of processing elements, the operator graph defining at least one execution path and wherein at least one of the processing elements of the operator graph is configured to receive data from at least one upstream processing element and transmit data to at least one downstream processing element;detecting an error condition has been satisfied at a first one of the plurality of processing elements, wherein the first processing element contains a plurality of fused operators;selecting at least one of the plurality of fused operators for removal from the first processing element; andremoving the selected at least one fused operator from the first processing element.2. The method of claim 1 , wherein selecting at least one of the plurality of fused operators further ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

A semiconductor memory device includes, a memory cell array configured to include a plurality of memory cells each having a plurality of logic pages, an error detector configured to detect a recovery target data among the data stored in the memory cell array, and output a logic page information of the recovery target data, a data recoverer configured to recover the recovery target data by using adjustment of a read reference voltage in response to the logic page information of the recovery target data, and a page buffer configured to read the recovery target data output from the memory cell array and write a recovered data output from the data recoverer in the memory cell array. 1. A semiconductor memory device , comprising:a memory cell array configured to include a plurality of memory cells each having a plurality of logic pages;an error detector configured to detect a recovery target data among the data stored in the memory cell array, and output a logic page information of the recovery target data;a data recoverer configured to recover the recovery target data by using adjustment of a read reference voltage in response to the logic page information of the recovery target data; anda page buffer configured to read the recovery target data output from the memory cell array and write a recovered data output from the data recoverer in the memory cell array.2. The semiconductor memory device of clai wherein the data recoverer includes:a voltage control unit for increasing the read reference voltage for reading a lower-bit logic page when the recovery target data is a lower-bit logic page data; anda data transform unit for transforming the recovery target data by using the increased read reference voltage.3. The semiconductor memory device of claim 2 , wherein the voltage control unit includes a counter configured to control a level of the increased read reference voltage.4. The semiconductor memory device of claim 1 , wherein the error detector includes an Error ...

MEMORY CIRCUIT INCORPORATING RADIATION-HARDENED MEMORY SCRUB ENGINE

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry. 1. An integrated circuit comprising:a first memory array comprising a first plurality of data groups, each such data group including a respective plurality of data bits;a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array, said first EDAC circuit comprising spatially redundant circuitry; anda first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein, said first scrub circuit comprising spatially redundant circuitry.2. The integrated circuit as recited in wherein:the first EDAC circuit and the first scrub circuit each includes buried guard ring (BGR) structures.3. The integrated circuit as recited in wherein:the first EDAC circuit and the first scrub circuit each includes parasitic isolation device (PID) structures.4. The integrated circuit as recited in wherein:the spatially redundant circuitry comprises dual interlocked storage cell (DICE) circuits.5. The integrated circuit as recited in ...

HOME/BUILDING FAULT ANALYSIS SYSTEM USING RESOURCE CONNECTION MAP LOG AND METHOD THEREOF

Provided are a home/building fault analysis system and method using a resource connection map log which compares and analyzes a previous integrated resource state and a current resource state using resource connection map logging information based on a standard resource management model when a fault is generated, provides state information of the resource in which information having high association with a fault resource is mainly changed, and performs an effective fault analysis and process by restoring to the previous resource state, as necessary. According to the prevent invention, when the fault is generated, a synthetic state of resources within a home/building as well as a state of an individual resource may be known from the resource connection map. 1. A home/building fault analysis system comprising:a plurality of resources that include at least one of a plurality of devices, networks, and services; anda home/building log-based fault management device that is connected with each of the resources via a network to thereby collect information of each of the resources, generates and maintains a resource connection map based on the collected information of each of the resources, compares and analyzes, when a fault is generated, a previous integrated resource state and a current resource state using resource connection map logging information to thereby provide, to a user, state information of the resource in which information having high association with a fault resource is mainly changed, and performs an effective fault analysis and process by restoring the current resource state to the previous resource state, as necessary.2. The home/building fault analysis system of claim 1 , wherein the home/building log-based fault management device includesa plurality of resource information collection modules that are connected with the plurality of resources via the network to thereby periodically collect the information of each of the resources,a home/building resource ...

SELF-HEALING OF NETWORK SERVICE MODULES

Methods, systems, and devices are described for managing virtual network services provided to a network. A number of processors in a self-contained network services module may execute a number of separate network service application instances associated with providing network services to the network. State information for each network service application instance may be stored within a shared memory, and a fault in one of the network service application instances may be identified based on the stored state information. The identified fault may be dynamically remedied in the one of the network service application instances. 1. A method of managing network services , comprising:providing network services for a network at a self-contained network services module comprising a number of processors, the processors executing a number of separate network service application instances;storing state information for each network service application instance within a shared memory;identifying a fault in one of the network service application instances based on the state information stored within the shared memory; anddynamically remedying the identified fault in the one of the network service application instances.2. The method of claim 1 , further comprising:discontinuing deliverance of tasks to the identified one of the network service application instances in response to the identified fault.3. The method of claim 2 , further comprising:restarting the identified one of the network service application instances in response to the identified fault.4. The method of claim 3 , further comprising:restoring a state of the identified one of the network service application instances to the restarted network service application instance based on the state information stored within the shared memory.5. The method of claim 4 , further comprising:resuming delivery of tasks to the restarted network service application instance.6. The method of claim 2 , further comprising:launching a ...

Controlling a Solid State Disk (SSD) Device

A mechanism is provided for controlling a solid state disk. A failure detector detects a failure in the solid state disk. Responsive to failure detector detecting a failure, a status degrader sets a degraded status indicator for the solid state disk. Responsive to the degraded status indicator, a degraded status controller maintains the solid state disk in operation in a degraded operation mode.

Method in a Gaming Machine for Providing Data Recovery

Disclosed is a gaming machine capable of data restoration. 1. In a gaming machine , including a memory for storing gaming data , divided into first and second equal-sized banks each storing copies of gaming data and each including error detecting data , a method for providing data recovery , comprising: writing the data set to the first bank then updating error detecting data associated with the data set after the data set is completely written;', 'writing the data set to the second bank then updating error detecting data associated with the data set after the data set is completely written; and, 'writing a data set by [ reading the data set;', 'reading error detecting data associated with the data set; and', 'calculating error detecting data associated with the read data set and comparing it to the read error detecting data and if they are different, detecting an error in the first bank;, 'in the first bank, reading the data set from the second bank;', 'reading error detecting data associated with the data set from the second bank; and', 'calculating error detecting data associated with the read data set and comparing it to the read error detecting data and if they are different, detecting an error in the second bank;, 'in the second bank], 'reading a data set byif no errors are detected, returning the data set read from one of the first and second banks;if errors are detected in both the first and second banks, reporting an unrecoverable error;if an error is detected in the first bank, copying the data set and error detecting data associated with the data set from the second bank to the first bank and returning the data set read from the second bank; andif an error is detected in the second bank, copying the data set and error detecting data associated with the data set from the first bank to the second bank and returning the data set read from the first bank.2. The method of wherein the error detecting data is a cyclical redundancy check (CRC) code.3. The method ...

FLASH MEMORY SYSTEM AND READ METHOD OF FLASH MEMORY SYSTEM

A read method in a flash memory system containing a flash memory and a memory controller includes updating a selected one of indexes of a selected one of blocks of the flash memory, in a wear-out table for indexing each of the blocks of the flash memory, and setting a start read level to start read retry on the selected block by referring to a read retry table corresponding to a wear-out degree included in the selected index when a current request of read retry on the selected block is received. 1. A method of operating a nonvolatile memory device , comprising:reading a first plurality of nonvolatile memory cells within a first block of the nonvolatile memory device using a first plurality of read voltage levels to assess the program states of the first plurality of nonvolatile memory cells;identifying at least one error in first data obtained from said reading a first plurality of nonvolatile memory cells; andrereading the first plurality of nonvolatile memory cells using a first plurality of updated read voltage levels derived from a first selected index in a read retry table that corresponds to a wear-out degree associated with the first block of the nonvolatile memory device.2. The method of claim 1 , further comprising identifying at least one error in second data obtained from said rereading the first plurality of nonvolatile memory cells using a first plurality of updated read voltage levels; and rereading the first plurality of nonvolatile memory cells using a second plurality of updated read voltage levels derived from a second selected index in the read retry table claim 1 , which differ at least partially from the first plurality of updated read voltage levels.3. The method of claim 2 , further comprising identifying at least one error in third data obtained from said reading a first plurality of nonvolatile memory cells using a second plurality of updated read voltage levels; and then correcting the at least one error in the third data using a low ...

SYSTEMS, METHODS, AND APPARATUS FOR SIGNAL PROCESSING-BASED FAULT DETECTION, ISOLATION AND REMEDIATION

Certain embodiments of the invention may include systems, methods, and apparatus for signal processing-based fault detection, isolation and remediation. According to an example embodiment of the invention, a method is provided for detecting and remediating sensor signal faults. The method may include monitoring data received from one or more sensors; determining confidence values for one or more parameters associated with the one or more sensors based at least in part on the monitored data; determining a combined confidence for each of the one or more sensors; and outputting a remediated value and status based at least in part on the monitored data and the combined confidences. 1. A method for detecting and remediating sensor signal faults , comprising:monitoring data received from one or more sensors;determining confidence values for one or more parameters associated with the one or more sensors based at least in part on the monitored data;determining a combined confidence for each of the one or more sensors; andoutputting a remediated value and status based at least in part on the monitored data and the combined confidences.2. The method of claim 1 , wherein the one or more parameters comprise one or more of availability status; spike; shift; stuck; noise; disagreement; or drift.3. The method of claim 1 , wherein the one or more sensors are redundant sensors.4. The method of claim 1 , further comprising outputting the remediated value based at least in part on a sensor model.5. The method of claim 1 , further comprising identifying sensor faults based at least in part on the one or more parameters.6. The method of claim 1 , wherein outputting the remediated value and status comprises outputting one or more protective logicals when confidence values are below a pre-determined threshold for at least one of the one or more sensors or when monitored data from two or more of the one or more sensors differs by more than a predetermined amount.7. The method of claim 1 , ...

Heterogeneous recovery in a redundant memory system

Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing based on the removing any stale data being complete.

Detection, diagnosis, and mitigation of software faults

A computational geometry technique is utilized to detect, diagnose, and/or mitigate fault detection during the execution of a software application. Runtime measurements are collected and processed to generate a geometric enclosure that represents the normal, non-failing, operating space of the application being monitored. When collected runtime measurements are classified as being inside or on the perimeter of the geometric enclosure, the application is considered to be in a normal, non-failing, state. When collected runtime measurements are classified as being outside of the geometric enclosure, the application is considered to be in an anomalous, failing, state. In an example embodiment, the geometric enclosure is a convex hull generated in N-dimensional Euclidean space. Appropriate action (e.g., restart the software, turn off access to a network port) can be taken depending on where the measurement values lie in the space.

METHOD AND SYSTEM FOR PROVIDING A SMART MEMORY ARCHITECTURE

A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The processor may include a common address/data/control memory bus that is configured to provide an asynchronous handshaking interface between the memory array and the memory processor. The processor can offload error data from the memory chip for analysis, and can store poor retention bit address information for memory refreshing in a non-volatile error retention memory. Program logic can also be included for memory address re-configuration. Power management logic can also be included, which may have a process-voltage-temperature compensation voltage generator for providing stable and constant read currents. An asynchronous handshaking interface is provided between the memory array and the memory processor. Write error tagging and write verification circuits can also be included. 1. A smart memory system comprising:a memory comprising one or more memory arrays;a memory processor;a common memory bus configured to provide an asynchronous handshaking interface between the one or more memory arrays and the memory processor to provide verification of read and write operation success or failures; anda non-volatile error retention memory configured to receive address information from the memory processor relating to memory locations exhibiting errors,wherein said memory processor is configured to perform one or more error-correction processes on the memory locations whose addresses are stored in the non-volatile error retention memory.2. The smart memory system of claim 1 , further comprising:control logic configured to receive at least one of a read signal or a write signal; andan address line configured to receive a memory address,wherein the control logic is configured to cause a first transition of a logic state of an acknowledgment signal responsive to the memory address.3. The smart memory system of claim 2 , wherein: ...

FAULT MONITORING DEVICE, FAULT MONITORING METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

A fault monitoring device includes: a controller that is implemented in a computer and controls the computer; a monitored object operated by the computer; a monitor that monitors a fault of the controller and a fault of the monitored object; and a switcher that alternately switches a monitored target by the monitor. 1. A fault monitoring device comprising:a controller that is implemented in a computer and controls the computer;a monitored object operated by the computer;a monitor that monitors a fault of the controller and a fault of the monitored object; anda switcher that alternately switches a monitored target by the monitor.2. The fault monitoring device as claimed in claim 1 , further comprising a watchdog timer that performs countdown;wherein the switcher alternately repeats first operation and second operation at fixed intervals when the controller and the monitored object are normal, the first operation being operable to switch the monitored target to the controller and reset the watchdog timer depending on an instruction received from the monitored object, and the second operation being operable to switch the monitored target to the monitored object and reset the watchdog timer depending on an instruction received from the controller.3. The fault monitoring device as claimed in claim 2 , wherein when the switcher does not receive a reset instruction of the watchdog timer from any one of the controller and the monitored object claim 2 , and the watchdog timer is not reset even when the countdown of the watchdog timer reaches a predetermined first threshold value claim 2 , the switcher notifies any one of the controller and the monitored object of occurrence of the fault in another one of the controller and the monitored object transmitting no reset instruction of the watchdog timer claim 2 , andthe any one of the controller and the monitored object that is notified of the occurrence of the fault stores information indicating the occurrence of the fault into ...

Controller and control method for a controller

A controller and a control method for a controller can simplify application development and can improve the performance of device control processes. When a request is received from an application 1 and the received process request is an initialization request, whether or not the received request is the first initialization request received after the application 1 started running is determined. If the received initialization request is the first initialization request, the request is passed to the device driver 3 and initialization settings information describing the configuration of the device driver 3 after the initialization process ends is stored. If an error has occurred in the device driver 3 when the device driver 3 status is detected, an error handling process is executed according to the device driver 3 state. When the device driver 3 has recovered, a request for setting the device driver 3 state to the state based on the initialization settings information is asserted.

Error Location Specification Method, Error Location Specification Apparatus and Computer-Readable Recording Medium in Which Error Location Specification Program is Recorded

A method for specifying an error location by an information processing apparatus that includes a plurality of devices connected to each other through a transmission path includes deciding, when an interrupt is generated, whether the interrupt is a periodic interrupt or an error interrupt, and storing, where the generated interrupt is a periodic interrupt, history information of errors of each of the devices, but analyzing, where the generated interrupt is an error interrupt, the stored history information of errors of the devices to specify a suspect location of the error. 1. A method for specifying an error location by an information processing apparatus that includes a plurality of devices connected to each other through a transmission path , comprising:deciding, when an interrupt is generated, whether the interrupt is a periodic interrupt or an error interrupt; andstoring, where the generated interrupt is a periodic interrupt, history information of errors of each of the devices; butanalyzing, where the generated interrupt is an error interrupt, the stored history information of errors of the devices to specify a suspect location of the error.2. The method according to claim 1 , wherein the error that is stored where the generated interrupt is a periodic interrupt is a recoverable error while the error that is analyzed where the generated interrupt is an error interrupt is an unrecoverable error.3. The method according to claim 2 , wherein claim 2 , in the analysis of the history of errors claim 2 , the number of times of occurrence of a recoverable error for each location at which there is the possibility that an error may occur is counted for each of the devices claim 2 , and a location at which a maximum counted value is exhibited is specified as the suspect location.4. The method according to claim 3 , wherein claim 3 , where a plurality of candidates for the suspect location at which a maximum counted value is exhibited are found claim 3 , a suspect location ...

METHOD AND APPARATUS FOR RESTARTING COMMUNICATION AFTER REGISTRATION OF SUBSCRIBER IDENTITY MODULE SIM CARD FAILS

Disclosed in the present invention are a method and an apparatus for restarting communication after registration of a subscriber identity module SIM card fails, which belongs to the field of mobile communications. The method includes: acquiring failure information about registration of the SIM card; displaying the failure information and prompt information on an interface, and receiving confirmation information that is replied by a user according to the prompt information; and restarting, according to the confirmation information, a communication processor under the condition of not turning off an application processor or not restarting the application processor, so as to re-register the SIM card. 1. A method for restarting communication after registration of a subscriber identity module SIM card fails , comprising:acquiring failure information about registration of the SIM card;displaying the failure information and prompt information on an interface, and receiving confirmation information that is replied by a user according to the prompt information; andrestarting, according to the confirmation information, a communication processor under a condition of not turning off an application processor or not restarting the application processor, so as to re-register the SIM card.2. The method according to claim 1 , wherein the confirmation information comprises immediate restart information claim 1 , and the restarting claim 1 , according to the confirmation information claim 1 , the communication processor comprises:restarting the communication processor according to the immediate restart information.3. The method according to claim 1 , wherein the confirmation information comprises restart delay information claim 1 , and the restarting claim 1 , according to the confirmation information claim 1 , the communication processor comprises:starting a timer according to the restart delay information; andrestarting the communication processor when the timer reaches a set time.4 ...

MONITORING SYSTEM AND METHOD

A remote computer monitors virtual machines in cloud servers of a data center. The remote computer sends a monitoring program to cloud servers according to a configuration file and consists of a cloud server cluster using the monitoring program. The remote computer obtains parameters of each cloud server from the cloud server cluster by the monitoring program. The remote computer searches for an image file corresponding to a virtual machine installed in the cloud server from the remote computer, if the cloud server works abnormally. The remote computer sends the searched image file to another cloud server in the cloud server cluster and installs the virtual machine in another cloud server according to the searched image file. 1. A remote computer , the remote computer in communication with cloud servers of a data center , the remote computer comprising:a storage system storing a configuration file and one or more image files;at least one processor; andone or more programs stored in the storage system and being executable by the at least one processor, the one or more programs comprising:a sending module sends the monitoring program to the cloud servers according to the configuration file and consists of a cloud server cluster using the monitoring program;an obtaining module obtains parameters of each cloud server in the cloud server cluster by the monitoring program;a determination module determines if the cloud server in the cloud server cluster works abnormally according to the parameters;a search module searches for an image file corresponding to a virtual machine installed in the cloud server from the remote computer, if the cloud server works abnormally; anda sending module sends the searched image file to another cloud server in the cloud server cluster and installs the virtual machine in another cloud server according to the searched image file.2. The remote computer of claim 1 , wherein the configuration file comprises serial numbers of the cloud servers.3. ...

DESKEW APPARATUS AND METHOD FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS

Disclosed herein are a deskew apparatus and method for Peripheral Component Interconnect (PCI) Express for compensating for a skew. The deskew apparatus includes a lane data input unit, a lane data alignment unit, and a lane data detection unit. The lane data input unit receives 18-bit data from each of lanes of the PCI Express. The lane data alignment unit aligns the 18-bit data using a COM symbol. The lane data detection unit detects a change in a state of alignment of the 18-bit data attributable to deletion or addition of an SKP symbol when the 18-bit data is aligned, and to perform synchronization between the lanes. 1. A deskew apparatus for Peripheral Component Interconnect (PCI) Express for compensating for a skew , the deskew apparatus comprising:a lane data input unit configured to receive 18-bit data from each of lanes of the PCI Express;a lane data alignment unit configured to align the 18-bit data using a COM symbol; anda lane data detection unit configured to detect a change in a state of alignment of the 18-bit data attributable to deletion or addition of an SKP symbol when the 18-bit data is aligned, and to perform synchronization between the lanes.2. The deskew apparatus of claim 1 , wherein the lane data alignment unit comprises:a 9-bit lower data input unit configured to receive 9-bit data, including the COM symbol, which is selected from the 18-bit data;a 9-bit upper data input unit configured to receive 9-bit data, including a symbol other than the COM symbol, which is selected from the 18-bit data;a 9-bit lower data register configured to store content of the 9-bit lower data input unit;a 9-bit upper data register configured to store content of the 9-bit upper data input unit;an alignment signal output unit configured to output an alignment signal by determining whether the pieces of received 9-bit data have been aligned; anda data control unit configured to control output of the pieces of 9-bit data based on results of the determination.3. The ...

Systems and Methods for Providing Fault Detection and Management

Methods and systems for providing fault detection and management are disclosed. A system includes a web-based interface that allows a user to access all elements of a customer service network, which spans multiple networks, departments, and external partners. The system, and thereby the user, is able to manage almost all aspects of the network, thereby giving the user end-to-end customer experience issue management. Real time and archived events are utilized, in some embodiments, for root cause analysis and/or process and/or performance improvement. Events from differing transport, platform, technology and OSI model levels are correlated for optimal customer experience monitoring alarming and analysis. 1. A method comprising:receiving, at a network management system, an instruction to gather network operational data;gathering, at a network management system, the network operational data, wherein gathering the network operational data comprises monitoring a network element executing a synthetic transaction to determine if the network element completes the synthetic transaction correctly;storing the network operational data at a storage location associated with the network management system;obtaining access control list data associated with the network element;comparing the access control list data to historical access control list data associated with the network element to determine if the access control list data and the historical access control list data are the same, the historical access control list data being stored at a data storage location associated with the network management system;determining if a network error exists, wherein the network error comprises a determination that the access control list data and the historical access control list data are not the same; andin response to determining that the network error exists, examining preferences and settings associated with the network management system to determine if the network management system is ...

Reconfigurable recovery modes in high availability processors

A method for performing error recovery that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.

Read only memory (rom) with redundancy

A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.

CODE-ASSISTED ERROR-DETECTION TECHNIQUE

A circuit, wherein an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. An error-detection circuit coupled to the encoder circuit generates and stores error-detection information associated with the set of M symbols, facilitating subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. A receiver circuit receives feedback information from the other circuit, which includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Control logic performs remedial action based on the feedback information. 1. (canceled)2. A method of operation in memory device , the method comprising:receiving write data from a memory controller that is encoded via a dynamic-bus-inversion (DBI) code;detecting errors in the write data based on constraints associated with the DBI encoding; andcommunicating error information associated with the detected errors to the memory controller.3. The method according to claim 2 , further comprising:storing the error information in a memory prior to communicating the error information to the memory controller.4. The method according to claim 2 , wherein the DBI encoding constraints are applied to minimize states.5. The method according to claim 2 , wherein the DBI-encoded write data is further encoded via a cyclic-redundancy-check (CRC) code.6. A memory device comprising:receiver circuitry to receive write data from a memory controller that is encoded via a dynamic-bus-inversion (DBI) code;a DBI decoder coupled to the receiver circuitry to decode the write data consistent with a DBI coding constraint;error detection circuitry operative to indicate an error in the ...

Automated Fault and Recovery System

A mechanism is provided for handling incidents occurring in a managed environment. An incident is detected in a resource in the managed environment. A set of incident handling actions are identified based on incident handling rules for an incident type of the incident. From the set of incident handling actions, one incident handling action is identified to be executed based on a set of impact indicators associated with the set of incident handling rules. The identified incident handling action is then executed to address the failure of the resource. 1. A method , in a data processing system , for handling incidents occurring in a managed environment , the method comprising:detecting, by a processor, an incident in a resource in the managed environment;identifying, by the processor, a set of incident handling actions based on incident handling rules for an incident type of the incident;from the set of incident handling actions, identifying, by the processor, one incident handling action to be executed based on a set of impact indicators associated with the set of incident handling rules; andexecuting, by the processor, the identified incident handling action to address the failure of the resource.2. The method of claim 1 , further comprising:from the set of incident handling actions, identifying, by the processor, a subset of incident handling actions based on the set of incident handling rules;excluding, by the processor, the subset of incident handling actions from consideration when identifying the one incident handling action to be executed;from a remaining set of incident handling actions, identifying, by the processor, the one incident handling action to be executed based on impact indicators associated with the set of incident handling rules; andexecuting, by the processor, the identified incident handling action to address the failure of the resource.3. The method of claim 1 , further comprising:qualifying, by the processor, the failure as an incident by ...

METHOD FOR FAULT HANDLING IN A DISTRIBUTED IT ENVIRONMENT

An improved method provides fault handling in a distributed IT environment. The distributed IT environment executes at least one workflow application interacting with at least one application by using interface information about the at least one application. The method comprises: storing at least one fault handling description in a implementation-independent meta language associated with the at least one application; associating the interface information with the at least one fault handling description based on at least one defined fault handling policy, created based on at least one service definition; and the workflow application if a fault response from the at least one application is received: retrieving at least one associated fault handling description based on at least one fault handling policy, and interpreting and executing a particular meta language code of the at least one associated fault handling description in order to continue the defined workflow application. 12104040. A method for fault handling in a distributed IT environment that executes at least one workflow application () interacting with at least one application () by using interface information about said at least one application () , [{'b': 9', '40, 'storing at least one fault handling description () in an implementation-independent meta language associated with said at least one application ();'}, {'b': 40', '9', '7', '5, 'associating said interface information about said at least one application () with said at least one fault handling description () based on at least one defined fault handling policy (), which is created based on at least one service definition ();'}, {'b': 40', '210, 'claim-text': [{'b': 9', '7', '7, 'retrieving at least one associated fault handling description () based on at least one fault handling policy (, ′), and'}, {'b': 9', '210, 'interpreting and executing a particular meta language code of said at least one associated fault handling description () in order to ...

MONITORING AND RESOLVING DEADLOCKS, CONTENTION, RUNAWAY CPU AND OTHER VIRTUAL MACHINE PRODUCTION ISSUES

Resolving virtual machine (VM) issues, by executing VM and operating system (OS) diagnostic monitors, including, monitoring a set of VM and OS health status metrics of a system at a first level, analyzing data of the monitored health status metrics to determine that an instability has occurred when the data exceeds defined bounds for the health status metrics, responding to the instability by monitoring additional VM and OS health status metrics, whereby a level of monitoring of the system is increased from the first level to a second level, greater than the first level, identifying the instability, repairing the system by taking corrective action based on the identified instability; and removing at least one of the set of monitoring and profiling tools to reduce the level of monitoring to a third level once the instability has been resolved, wherein the third level is less than the second level. 1. A computer-implemented method for resolving a computing system issue , comprising:monitoring a set of computing system health status metrics of a system at a first level;analyzing data of the monitored computing system health status metrics to determine that an instability has occurred when the data exceeds defined bounds for the computing system health status metrics;responding to the instability by monitoring additional computing system health status metrics, whereby a level of monitoring of the system is increased from the first level to a second level, greater than the first level;identifying the instability;repairing the computing system by taking corrective action based on the identified instability; andremoving at least one of the set of monitoring and profiling tools to reduce the level of monitoring to a third level once the instability has been resolved, wherein the third level is less than the second level.2. The computer-implemented method of claim 1 , wherein a user defines the sets of computing system health status metrics to be monitored and the bounds ...

HYBRID TRANSACTIONAL MEMORY (HYBRID TM)

Embodiments related to a hardware transactional memory (HTM). An aspect includes setting a mode register of a processor core of a computer to indicate a HTM mode. Another aspect includes executing a plurality of transactions by the processor core in the HTM mode based on the mode register. Another aspect includes determining whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode. Yet another aspect includes, based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transitioning the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode. 1. A computer system for a hardware transactional memory (HTM) , the system comprising: set a mode register of the processor core of a computer to indicate a HTM mode;', 'execute a plurality of transactions by the processor core in the HTM mode based on the mode register;', 'determine whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode; and', 'based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transition the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode., 'a processor core configured to2. The system of claim 1 , wherein determining that the first transaction exceeds the failure limit of the processor core in the HTM mode comprises:initializing a failure counter; and aborting and discarding the results of the first transaction;', 'incrementing the failure counter based on the aborting of the first transaction;, 'based on detecting an error during execution the first transactioncomparing the failure counter to a failure count limit of the processor core; andbased on determining that the failure counter exceeds the ...

NONVOLATILE MEMORY CONTROLLER AND A NONVOLATILE MEMORY SYSTEM

A nonvolatile memory (NVM) controller that includes a command decoder that receives a command from a host and outputs an index in response to the command, a program memory that stores a command mapping table including address information for accessing a program corresponding to the command and a processor that receives an index from the command decoder and controls the address information to be output in response to the index. 1. A nonvolatile memory (NVM) controller , comprising:a command decoder that receives a command from a host and outputs an index in response to the command;a program memory that stores a command mapping table comprising address information for accessing a program corresponding to the command; anda processor that receives the index from the command decoder and controls the address information to be output in response to the index.2. The NVM controller of claim 1 , wherein the program memory stores at least one program performed by the processor claim 1 ,wherein the processor performs a program corresponding to the address information output from the program memory.3. The NVM controller of claim 1 , wherein the program memory stores an error handling program that handles an error in the command claim 1 ,wherein when the command has the error, the index output from the command decoder is an index of the command mapping table enabling access to the error handling program.4. The NVM controller of claim 1 , wherein the command is a command set that comprises a first command and a second command which are sequentially received at the command decoder claim 1 ,wherein the command decoder outputs an index in response to the command set.5. The NVM controller of claim 4 , wherein the command set comprises an address of an NVM device claim 4 ,wherein the command decoder extracts the address of the NVM device from the command set.6. The NVM controller of claim 5 , wherein the command decoder comprises a first memory that stores addresses of a plurality of ...

Method and system for detecting symptoms and determining an optimal remedy pattern for a faulty device

Computer-implemented systems, methods, and computer-readable media electronic for detecting symptoms and determining an optimal remedy pattern for one or more faulty components of a device is disclosed. First the symptoms of the faulty device are detected and associated faulty components of the device are identified. Different tests are performed to confirm the status of the faulty components. Based on the historical data, cost information and remedy cost function an optimal remedy pattern is determined.

FORECASTING WORKLOAD TRANSACTION RESPONSE TIME

Reliability testing can include determining a transaction time for each of a plurality of transactions to a system under test during the reliability test, wherein the plurality of transactions are of a same type. Forecasts of transaction times can be calculated for the transaction type. The forecasts can be compared with a threshold time using a processor. A remedial action can be implemented responsive to at least one of the forecasts exceeding the threshold time. 124-. (canceled)25. A method , comprising:determining a transaction time for each of a plurality of transactions to a system under test during a reliability test, wherein the plurality of transactions are of a same transaction type;calculating a forecast of transaction times for the transaction type;comparing the forecast with a threshold time using a processor; andimplementing a remedial action responsive to the forecast exceeding the threshold time.26. The method of claim 25 , wherein the forecast of the transaction times uses average transaction times.27. The method of claim 25 , wherein the transaction type is selected from a plurality of different transaction types and the threshold time is specific to the transaction type.28. The method of claim 25 , wherein the plurality of transactions are conducted over a network.29. The method of claim 25 , wherein the forecast is calculated for a user selected amount of time into the future.30. The method of claim 25 , wherein each transaction type is associated with one of a plurality of different criticality levels claim 25 , wherein the remedial action performed is selected according to the criticality level of the transaction type.31. The method of claim 25 , wherein implementing a remedial action comprises:providing a notification that the forecast exceeds the threshold time.32. The method of claim 25 , wherein implementing a remedial action comprises:changing an amount of the transactions of the transaction type that are issued during the reliability test ...

SYSTEM, METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MOBILE DEVICE SUPPORT SERVICES

A method is provided for providing mobile device support services. The method may include monitoring a mobile device status. The method may additionally include performing device diagnostics based at least in part on captured deice status data to identify potential faults that may affect mobile device functionality. A corresponding system, apparatus, and computer program product are also provided. 126-. (canceled)27. An apparatus comprising at least one processor and at least one memory having program code instructions embodied therein , the at least one memory and program code instructions being configured to , with the at least one processor , direct the apparatus to at least:receive device status data from a mobile device;determine one or more potential faults related to the mobile device based at least in part on the device status data; andcause information regarding the one or more potential faults related to the mobile device to be provided to the mobile device.2849-. (canceled)50. A computer program product comprising a non-transitory computer-readable storage medium having program code portions stored therein , the program code portions being configured to , upon execution , direct an apparatus to at least:receive device status data from a mobile device;identify one or more potential faults related to the mobile device based at least in part on the device status data; andcause information regarding the one or more potential faults related to the mobile device to be provided to the mobile device.51. The computer program product of claim 50 , wherein the one or more potential faults comprise at least one predicted fault.52. The computer program product of claim 50 , wherein the one or more potential faults comprise at least one present fault.53. The computer program product of claim 50 , wherein the determining the one or more potential faults comprises determining at least one an application profile.54. The computer program product of claim 50 , wherein the ...

Methods for providing for correcting data and associated apparatus

The apparatus and methods allow for correcting data from a sensor due to changes in relative speed of that sensor. The methods and apparatus described use a determined entropy from data associated with across a direction of travel of the sensor together with a determined entropy from data associated with in a direction of travel of the sensor. The determined entropies allow for providing for correcting the data for changes in the relative speed of the sensor. Also, described are methods and apparatus for correcting data from at least first and second sensors of a measurement device, whereby features are correlated from datasets taken from both sensors to determine one or more corresponding signatures. These signatures can then be used to correct the data from first and second sensors.

ADVANCED CONVERTERS FOR MEMORY CELL SENSING AND METHODS

A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output. 119-. (canceled)20. A non-volatile memory device , comprising:a counter for generating a counter output responsive to an input interval and a clock signal, the counter output to serve as one or more most significant bits of digital data;a delay device for receiving the clock signal and generating phase outputs responsive to the clock signal;a latch for latching the phase outputs to serve as one or more least significant bits of the digital data; andan error corrector at least for identifying an at least potential error in the digital data based at least in part on the clock signal and an input interval endpoint of the input interval.21. A method for reading a memory cell in a non-volatile memory device , comprising:sensing a level in the memory cell and generating an input interval in response thereto;generating a clock signal during the input interval, the clock signal having a clock period defined by clock transitions;counting the clock periods during the input interval and generating a counter output in response thereto, the counter output serving as one or ...

Computer system

There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU# 0 through VCPU# 2 each operate different OS's. VCPU# 0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU# 0 regardless of an execution sequence stored in schedule register A. VCPU# 0 reinitializes a bus where an error occurred.

Configurable and scalable storage system

The system utilizes a plurality of layers to provide a robust storage solution. One layer is the RAID engine that provides parity RAID protection, disk management and striping for the RAID sets. The second layer is called the virtualization layer and it separates the physical disks and storage capacity into virtual disks that minor the drives that a target system requires. A third layer is a LUN (logical unit number) layer that is disposed between the virtual disks and the host. By using this approach, the system can be used to represent any number, size, or capacity of disks that a host system requires while using any configuration of physical RAID storage.

COMPUTING DEVICE AND METHOD FOR PROCESSING SYSTEM EVENTS OF COMPUTING DEVICE

In a method for processing system events of a computing device, the computing device includes a basic input and output system (BIOS) and a baseboard management controller (BMC). The method allocates revised storage blocks in the BMC, for storing normal system events of the computing device, and a backup storage block in the BMC for storing error system events of the computing device. The method detects a error system event via the BMC, and records the error system event into the backup storage block of the BMC. The method obtains the error system event from the backup storage block of the BMC via the BIOS when the computing device is rebooted, and processes the error system event to reboot the computing device using a normal system event stored in the revised storage blocks of the BMC. 1. A computing device , comprising:a basic input and output system (BIOS);a baseboard management controller (BMC);at least one processor; anda storage device storing one or more computer-readable programs, which when executed by the at least one processor, causes the at least one processor to:allocate a revised storage block in the BMC that stores normal system events of the computing device, and allocate a backup storage block in the BMC that stores error system events of the computing device;detect if the computing device generates an error system event via the BMC, and record the error system event into the backup storage block of the BMC when the BIOS sends an intelligent platform management interface (IPMI) command to the BMC; andobtain the error system event from the backup storage block of the BMC via the BIOS when the computing device reboots, and reboot the computing device using a normal system event stored in the revised storage block of the BMC.2. The computing device according to claim 1 , wherein the error system event is a system event indicating that a multi-bit error has occurred in a component of the computing device.3. The computing device according to claim 1 , ...

REMOTE ACCESS DIAGNOSTIC MECHANISM FOR COMMUNICATION

A method for diagnosing and correcting errors at a data processing system is disclosed includes detecting at a first device of the system, such as a network interface device, an error at a second device of the system, such as a data processor. In response to detecting the error, the first device communicates a help request via a network. In response to the help request, the first device receives diagnostic and error correction routines from a remote system. The first device executes the routines and provides information to the remote system to diagnose and correct errors at the second device. 1. A method , comprising:detecting, at a data processing device, an error at a first system of a network, wherein the first system includes the data processing device; transmitting a help request from the data processing device to a second system of the network;', 'authenticating the second system at the data processing device based, at least in part, on authentication information received from the second system after transmitting the help request;', 'receiving an error correction routine from the second system, in response to said authenticating the second system and based, at least in part, on diagnostic information associated with the first system;', 'executing the error correction routine at the data processing device to resolve the error at the first system; and, 'in response to detecting the error at the first system,'} 'disabling an operation for authenticating the second system at the data processing device.', 'in response to detecting that the error at the first system is resolved,'}2. The method of claim 1 , further comprising:enabling the operation for authenticating the second system at the data processing device, in response to detecting the error at the first system.3. The method of claim 1 , further comprising:executing a diagnostic routine at the data processing device to determine the diagnostic information associated with the first system, in response to ...

Method and system for automatically detecting and resolving infrastructure faults in cloud infrastructure

Systems and methods are provided for any party in a cloud ecosystem (cloud providers of such resources, the intermediate management software for such resources, and the end user of such resources) to detect and resolve faulty resources synchronously or asynchronously, before said faults adversely affect the users' workloads. The system requests a service or set of one or more resources within a cloud, automatically checking the infrastructure for various faults that would cause it to be non-functional, including pre-defined and user-defined checks, and resolving them before including the infrastructure in the working service cluster of resources. The system presents an API to the user that returns only functional, production-quality resources that are not in a faulty state. An API that tests and resolves bad infrastructure can be registered during the request or a preceding/subsequent API call, removing the need for the end-user to deal with various types of infrastructure faults.

METHOD AND SYSTEM FOR MANAGING A COMMUNICATION NETWORK

Embodiments of the present invention described herein, discloses a method and system for managing a communication network using any loop avoidance or mitigation technology. The restoration of network under fault, or sub-optimal network condition, maintenance and improvement of network connectivity and network behaviour is based upon GET and POST commands. In one embodiment of the present invention, the restoration mechanism is used to maintain or improve network connectivity and network behaviour or function upon receipt of command from management plane or control plane to build optimal network condition (e.g: minimum hops, maximum bandwidth, etc.) for data traffic, within a communication network of any topology. 1. A method for restoring a network due to link (or node) fault between a pair of nodes associated to the link (or node) , maintaining and improving network connectivity and network behaviour within a communication network of any topology using any loop avoidance or mitigation technology , the method comprising:identifying membership with an existing tree or loop-free topology within the network;identifying occurrence of fault in any link or node of the tree;obtaining information from neighboring nodes of the associated-nodes under fault, operator command or to build optimal network condition for traffic; andusing the information for updating previous information having with the associated nodes thereby restoring the fault link, maintaining and improving network connectivity and network behaviour;wherein the restoration of network under fault, maintenance and improvement of network connectivity and network behaviour is based upon GET and POST commands.2. The method as in claim 1 , further comprising:checking if a GET message or command is received by a node, thereby checking if the information is available and upon availability of the information, enabling the receiver node to respond to the sender node the requested information with POST command; ...

Defect Management in Memory Systems

Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.

System and method for facilitating recovery from a document creation error

A system and method for facilitating recovery from an error occurring during creation or alteration of a target document from a form or template. The method may involve gathering some or all input collateral (e.g., the document template, input data, instructions for creating the document) and adding it to the target document. If the target document is not created, the input collateral may be placed in an error document. The target or error document is dispatched to the user and may also be sent to support personnel (e.g., help desk, technical support personnel) or forward to such personnel by the user. Capturing the document creation conditions and parameters in the target or error document allows the support personnel (or user) to diagnose and/or recover from the error without expending the time and effort that would be required to gather the separate input collateral items, log files, configuration parameters, etc. 1. An automated method of facilitating recovery from an error encountered during creation of a document from a template , the method comprising:receiving from a requestor a request to create a first document;receiving a template for the first document;identifying data to be merged with the template to create the first document;initiating creation of the first document;detecting an error in creation of the first document before the first document is returned to the requestor; and if the first document is created, automatically adding to the first document input collateral used during the merger, including the template or an identifier of the template; and', 'if the first document is not created, automatically generating a second document to contain said input collateral., 'in response to detection of the error2. The method of claim 1 , further comprising:if the first document is created, forwarding the first document with the input collateral to the requestor; andif the first document is not created, forwarding the second document with the input ...

COMPUTER PRODUCT, COUNTERMEASURE SUPPORT APPARATUS, AND COUNTERMEASURE SUPPORT METHOD

A computer-readable recording medium stores a countermeasure support program that causes a computer to execute a process that includes calculating a time period elapsing from an occurrence timing of a message that is of a predetermined type and related to an operation of an apparatus in a monitored system, until an occurrence timing of a fault; and outputting the calculated elapsed time period. 1. A non-transitory computer-readable recording medium stores a countermeasure support program that causes a computer to execute a process comprising:calculating a time period elapsing from an occurrence timing of a message that is of a predetermined type and related to an operation of an apparatus in a monitored system, until an occurrence timing of a fault; andoutputting the calculated elapsed time period.2. The non-transitory computer-readable recording medium according to claim 1 , the process further comprising:searching among messages occurring in the system, for a message that is of a predetermined type, is a sign of a specific fault, and occurs before occurrence of the specific fault;identifying an occurrence time point of the specific fault by referring to a database that stores occurrence time points of faults occurring in the system;calculating a time period from a time when a sign of the specific fault occurs until a time when the specific fault occurs, based on an occurrence time point of the retrieved message of the predetermined type and the identified occurrence time point of the specific fault; andoutputting a calculation result acquired at the calculating.3. The non-transitory computer-readable recording medium according to claim 2 , of the process further comprisingdetecting the message of the predetermined type occurring in the system, whereinthe outputting includes outputting when the message of the predetermined type is detected, the calculated time period that is from occurrence of the sign of the specific fault until occurrence of the specific fault.4. ...

Supervisor System Resuming Control

Embodiments herein relate to a computing device ( 100 ) including a supervisor system ( 112 ) and an operating system ( 122 ). In an embodiment, the supervisor system is to launch and monitor the operating system. The supervisor system is to resume control of the computing device when a crash occurs in the operating system of the computing device.

INFORMATION PROCESSING APPARATUS AND METHOD FOR GENERATING PSEUDO FAILURE

A controller that obtains data from an object device in obedience to an obtaining request from the processor includes an error setter that sets, when a pseudo failure mode that spuriously generates a failure is active, an error associated with a failure type of a pseudo failure to be generated in the data obtained from the object device in obedience to the obtaining request; and an error processor that notifies, when detecting an error in the data under a state where the pseudo failure mode is active, the processor of the failure response corresponding to the failure type associated with the detected error. 1. An information processing apparatus comprising a processor and a controller that obtains data from an object device in obedience to an obtaining request from the processor ,the controller comprising:an error setter that sets, when a pseudo failure mode that spuriously generates a failure is active, an error associated with a failure type of a pseudo failure to be generated in the data obtained from the object device in obedience to the obtaining request; andan error processor that notifies, when detecting an error in the data under a state where the pseudo failure mode is active, the processor of the failure response corresponding to the failure type associated with the detected error.2. The information processing apparatus according to claim 1 , the error processor comprising:an error corrector that corrects, when the detected error is correctable, the correctable error; anda pseudo failure processor that prevents, when the error is detected in the data under a state where the pseudo failure mode is active, the error corrector from correcting the error detected in the data, and notifies the processor of a failure response corresponding to the failure type associated with the detected error.3. The information processing apparatus according to claim 1 , the error processor further comprising an error detector that performs error check on the data to detect ...

MESSAGE SEQUENCE GENERATION METHOD AND MESSAGE SEQUENCE GENERATION DEVICE

A message sequence generation method and a message sequence generation device, by which a message sequence with an error handling added thereto can be efficiently generated. The method includes setting an action for a specific phenomenon in the phenomenon causal relationship model, associating each element included in the message sequence information with each phenomenon to generate element/phenomenon correspondence information, storing the element/phenomenon correspondence information into a memory device, and acquiring the action set for the phenomenon corresponding to each element and the action set for another phenomenon caused by the phenomenon, from the element/phenomenon correspondence information, and adding the actions to the element as an error handling. 1. A message sequence generation method comprising the steps of:(a) preparing message sequence information indicating a normal procedure of a communication protocol by using a message sequence diagram, for data processing;(b) preparing a phenomenon causal relationship model describing a plurality of phenomena including a phenomenon which requires an error handling together with a causal relationship thereof, for data processing;(c) setting an action for a specific phenomenon in said phenomenon causal relationship model, said action being performed when said specific phenomenon occurs;(d) associating each element in said message sequence information with each of said phenomena to generate element/phenomenon correspondence information;(e) storing said element/phenomenon correspondence information into a memory device; and(f) acquiring said action set for said phenomenon corresponding to said each element and said action set for another phenomenon caused by said phenomenon, from said element/phenomenon correspondence information, and adding said actions to said each element as an error handling,wherein said steps are executed through data processing by a computer.2. The message sequence generation method ...

Test Case Crash Recovery

A safe operating region of a complex integrated circuit may be determined by selecting an operating point for the integrated circuit (IC) at a first voltage and first frequency. A test program is executed by a central processing unit (CPU) comprised within the IC to test a portion of the IC. Communication activity between the IC and a host system is recorded to form a data log while the test program is being executed. A crash is detected by storing and examining the data log periodically, and assuming that the test program has crashed when any one of a predetermined set of crash conditions is detected during examination of the data log. The operating point may be iteratively changed and execution of the test program repeated while continuing to check for a crash until a crash is detected.

HANDLING INTERMITTENT RECURRING ERRORS IN A NETWORK

Embodiments relate to a computer for transmitting data in a network. The computer includes at least one data transmission port configured to be connected to at least one storage device via a plurality of paths of a network. The computer further includes a processor configured to detect recurring intermittent errors in one or more paths of the plurality of paths and to disable access to the one or more paths based on detecting the recurring intermittent errors. 1. A method for transmitting data in a network , comprising:initiating, by a processor, a data transmission operation from the processor to a storage device via a network, the network including a plurality of paths between the processor and the storage device;detecting, by the processor, a recurring intermittent error in one or more paths of the plurality of paths; anddisabling access to the one or more paths based on detecting the recurring intermittent error.2. The method of claim 1 , further comprising:determining a burden on a data transmission capability of the processor caused by disabling access to the one or more paths, and disabling access to the one or more paths based on a determination that the burden is less than a threshold burden.3. The method of claim 1 , wherein detecting the recurring intermittent error includes determining whether the one or more paths have suffered at least a predetermined number of errors within a predetermined duration of time claim 1 , the predetermined number of errors being a number greater than one.4. The method of claim 1 , wherein the recurring intermittent error is a time-out on the one or more paths.5. The method of claim 1 , wherein detecting the recurring intermittent error includes determining whether the one or more paths have suffered at least a predetermined number of errors claim 1 , the predetermined number of errors being a number greater than one. This is a continuation application of and claims priority from U.S. application Ser. No. 13/586,405, filed ...

AUTOMATIC CLASSIFICATION ADJUSTMENT OF RECORDED ACTIONS FOR AUTOMATION SCRIPT

A method for automatic revision of an automation script includes obtaining a sequence of at least one classified recorded action and an automation script, the automation script including a sub-sequence of the sequence of classified recorded actions, wherein each action is included in the automation script in accordance with the classification of that action. At least a portion of the automation script is executed. Upon failure of an action of the portion of the automation script to execute, an action of the sequence of classified recorded actions is reclassified, it is verified if the action that failed to execute executes successfully after the reclassifying, and the automation script is revised. Relating computer program product and data processing system are also disclosed. 1. A method for automatic revision of automation script , the method comprising:obtaining a sequence of at least one classified recorded action and an automation script, the automation script including a sub-sequence of said sequence of at least one classified recorded action, wherein each action is included in the automation script in accordance with the classification of that action;executing at least a portion of the automation script;upon failure of an action of said at least a portion of the automation script to execute, reclassifying an action of said sequence of at least one classified recorded action.verifying that the action that failed to execute executes successfully after the reclassifying; andrevising the automation script.2. The method of claim 1 , performed iteratively.3. The method of claim 1 , wherein the classification of an action of said at least one classified recorded action comprises classifying that action as either relevant or irrelevant to attaining a result claim 1 , and including that action in the automation script if that action is classified as relevant.4. The method of claim 1 , wherein the classification comprises an interpretation of an action of said at least ...

PERIPHERAL DEVICE SHARING IN MULTI HOST COMPUTING SYSTEMS

The present subject matter discloses methods and systems of sharing of peripheral devices in multi host computing systems (). In one implementation, the method of sharing a peripheral device () amongst a plurality of hosts of the multi-host computing system () comprises receiving a request to switch the peripheral device () from a first operating system running on a first host from amongst the plurality of hosts to a second operating system running on a second host from amongst the plurality of hosts; generating a request for the first operating system to relinquish control of the peripheral device (); determining the status of the relinquishment based on response generated by the first operating system; initiating a request for the second operating system to install a device driver for the peripheral device () upon determining successful relinquishment; and transferring ownership of the peripheral device () to the second operating system. 1116100. A method of sharing a peripheral device () amongst a plurality of hosts in a multi-host computing system () , the method comprising:{'b': 120', '158', '116, 'receiving a switching request from at least one amongst the plurality of hosts, by at least one of a peripheral and interface virtualization unit (PIVU) () and a switching module (), to switch the peripheral device () from a first operating system running on a first host from amongst the plurality of hosts to a second operating system running on a second host from amongst the plurality of hosts;'}{'b': '116', 'generating a request based on ownership configuration for the first operating system to relinquish ownership of the peripheral device () at a safe transaction boundary;'}determining the status of the relinquishment based in part on response generated by the first operating system;{'b': '116', 'initiating a request for the second operating system to install a device driver for the peripheral device () upon determining successful status of the relinquishment; and ...

Management system for managing computer system comprising multiple monitoring-target devices

A management system manages a computer system including multiple monitoring-target devices. A storage device of the management system stores a general rule, general plan information, unresolved information, and configuration information. A control device of the management system creates multiple expanded rules based on the general rule and the configuration information, and if an event related to any of the multiple monitoring-target devices has occurred, identifies, based on the multiple expanded rules, a first conclusion event constituting a candidate for the cause of the occurred event, creates, based on the general plan information, one or more expanded plans, which are recovery plans that can be implemented if the first conclusion event is a cause, identifies an unresolved event based on the unresolved information, identifies a risk site based on the identified unresolved event, and displays data showing the first conclusion event, expanded plan, and risk site.

Remediating events using behaviors

Remediating events of components using behaviors via an administrator system and an administrator client. The administrator system receives an event from a component of an information technology (IT) environment. A behavior is determined at least partly from the event. The behavior is determined to be an anomalous behavior at least partly from a group of previously received events. A coefficient is calculated, via a calculation, for the anomalous behavior at least partly from a weight. The administrator system sends a description of the anomalous behavior and a group of options to the administrator client. The description is at least partly based on the calculation. The administrator system receives a severity indication from the administrator client. The weight, the calculation, and the description are updated based on the severity indication.

SYSTEMS AND METHODS FOR USING A CORRECTIVE ACTION AS DIAGNOSTIC EVIDENCE

Methods, systems and computing devices are provided for using a completed corrective action as evidence of a fault. The methods, systems and computing devices receive equipment status evidence and determine an equipment fault based on the equipment status evidence. The methods, systems and computing devices also create and rank a list of potential failure modes based at least in part on the determined equipment fault, recommend a corrective action to correct the equipment fault based at least in part on the ranking of the potential failure modes and receiving additional equipment status evidence indicating that the recommended corrective action failed to correct the equipment fault. The methods, systems and computing devices then associate a detection probability and a false negative rate with the failed corrective action to create additional status evidence, and re-rank the list of potential failure modes for subsequent performance based on the additional status evidence. 1. A method using a completed corrective action as evidence of a fault by a diagnostic reasoner , comprising:receiving equipment status evidence;determining an equipment fault based on the equipment status evidence;creating and ranking a list of potential failure modes based at least in part on the determined equipment fault;recommending a corrective action to correct the equipment fault based at least in part on the ranking of the potential failure modes;receiving additional equipment status evidence indicating that the recommended corrective action failed to correct the equipment fault;associating a detection probability and a false negative rate with the failed corrective action to create additional status evidence wherein the false negative rate is equal to a ratio, wherein the numerator of the ratio is equal to the number of times the corrective action was performed on a valid equipment fault minus the number of times the corrective action corrected the valid equipment fault, and the ...

METHOD AND SYSTEM FOR FIXING LOOPHOLES

The present invention discloses method and system for debugging, and a non-transitory computer-readable medium that stores instructions of debugging. The method includes when a loophole is detected, determining whether a network is online; if yes, fixing the loophole; otherwise, prompting a user to make the network online, and fixing the loophole when the network is online, so as to avoid debugging failure caused by a failure of patch downloading when the network is offline, thereby reducing the failure rate of debugging. 1. A method for debugging , comprising:when a loophole is detected, determining whether a network is online;if yes, fixing the loophole; andotherwise, prompting a user to make the network online, and fixing the loophole when the network is online.2. The method according to claim 1 , prior to the step of determining whether the network is online claim 1 , further comprising:generating a loophole notification according to the detected loophole, and displaying the loophole notification,wherein the step of prompting the user to make the network online comprises prompting, on the loophole notification, the user to make the network online.3. The method according to claim 1 , prior to the step of determining whether the network is online claim 1 , further comprising:generating a loophole notification according to the detected loophole, and displaying the loophole notification; andtriggering a debugging process when a debugging instruction sent by the user is received.4. The method according to claim 1 , wherein the step of fixing the loophole when the network is online comprises:detecting an online status of the network periodically according to a preset time period; andfixing the loophole when it is detected that the network is online.5. The method according to claim 4 , after the step of detecting the online status of the network periodically according to a preset time period claim 4 , further comprising:if timing reaches a preset time threshold and the ...

Systems and Methods for Repairing System Files

Systems and methods are provided for repairing system files. For example, a list of system files including file information of one or more first repairable system files are updated in real time; file information of a target file sent from a terminal is received; whether the target file is in need of repair is detected based on at least information associated with the list of system files; in response to the target file being in need of repair, a first repair strategy for the target file is determined based on at least information associated with a predetermined database of repair strategies and a file type of the target file; and the target file is repaired based on at least information associated with the first repair strategy. 1. A method for repairing system files , the method comprising:updating in real time a list of system files including file information of one or more first repairable system files;receiving file information of a target file sent from a terminal;detecting whether the target file is in need of repair based on at least information associated with the list of system files; determining a first repair strategy for the target file based on at least information associated with a predetermined database of repair strategies and a file type of the target file; and', 'repairing the target file based on at least information associated with the first repair strategy., 'in response to the target file being in need of repair,'}2. The method of claim 1 , wherein:the list of system files includes a predetermined database of scanning strategies and the database of repair strategies;the predetermined database of scanning strategies classifies one or more second system files into three levels of importance: highly risky, important and general, the second system files of different levels of importance corresponding to different scanning strategies;the database of repair strategies is used to determine a second repair strategy corresponding to a file type of a ...

TECHNOLOGIES FOR RE-PROGRAMMABLE HARDWARE IN AUTONOMOUS VEHICLES

Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect. 1. An apparatus , comprising:a vehicle controller having a plurality of physical logic units, the vehicle controller to:aggregate data observed from each of a plurality of sensors;detect a trigger indicative of a defect in a first physical logic unit of the plurality of physical logic units, the defect identified as a function of the aggregated data; andperform, in response to the trigger, a reconfiguration action in the plurality of physical logic units to activate a second physical logic unit of the plurality of physical logic units in place of the first physical logic unit.2. The apparatus of claim 1 , wherein to aggregate the data observed from each of the plurality of sensors comprises to:receive data from each of the plurality of sensors; andformat the data for transmission to one or more services.3. The apparatus of claim 2 , wherein to format the data for transmission to the one or more services comprises to format the data for transmission to a service of the one or more services claim 2 , the data being formatted based on permissions specified for the service of the one or more services.4. The apparatus of claim 2 , wherein the vehicle controller is further to transmit the aggregated data to the one or more services.5. The apparatus of claim 4 , wherein to transmit the aggregated data comprises to transmit the aggregated data to a service of ...

Inaccessibility status indicator

Processing within a computing environment is facilitated by use of an inaccessibility status indicator. A processor determines whether a unit of memory to be accessed is inaccessible in that default data is to be used for the unit of memory. The determining is based on an inaccessibility status indicator in a selected location accessible to the processor. Based on the determining indicating the unit of memory is inaccessible, default data is provided to be used for a request associated with the unit of memory.

Error and solution tracking in a software development environment

In an approach for error and solution tracking a processor identifies that a first occurrence of a first error is present in code. A processor tracks a first set of actions made to the code which affect the first occurrence of the first error. A processor determines that the first occurrence of the first error has been resolved. A processor records the first error and the first set of actions to the code. A processor identifies that a second occurrence of the first error is present in the code. A processor determines that the first error has previously occurred. A processor retrieves the first set of actions. A processor causes the first set of actions to be made to the code to affect the second occurrence of the first error.

METHOD, APPARATUS AND SYSTEM FOR HANDLING DATA ERROR EVENTS WITH A MEMORY CONTROLLER

Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform. 1. A memory controller comprising:scrubber logic comprising circuitry to perform a first patrol scrub of a plurality of active segments of a memory, and to perform a second patrol scrub of one or more segments of the platform while the one or more segments are each available as a spare segment for the plurality of active segments; andsparer logic comprising circuitry to receive an indication of a first uncorrectable error event detected based on the first patrol scrub, wherein, of a first handler process and a second handler process, the sparer logic to signal only the first handler process in response to the indication of the first uncorrectable error event, the sparer logic further to receive an indication of a second uncorrectable error event detected based on the second patrol scrub, wherein, of the first handler process and the second handler process, the sparer logic to signal only the second handler process in response to the indication of the second uncorrectable error event.2. The memory controller of claim 1 , ...

PROBLEM MANAGEMENT SOFTWARE

Computer systems are managed by providing systems programmers with visual displays and user interfaces that identify certain issues and allow the system programmer to readily apply fixes, patches, and other updates without tediously sifting through a mountain of information and manually addressing those issues. The systems herein, provide a more streamlined approach for the system programmer by reducing the possibility of overlooking a particular issue that may adversely affect the system. 1. In a mainframe system , a machine-executable process comprising:receiving data from at least one error record;parsing the received data for a first set of errors in a mainframe system and a second set of errors in the mainframe system; an issue section comprising an issue indicator being indicative of an issue that impacts the mainframe system; and', 'a status section comprising a status indicator corresponding to the issue indicator, the status indicator being indicative of a status of the issue;, 'outputting, to a first segment of a graphical user interface, a first ordered listing of entries indicative of the first set of errors in the mainframe system, the first segment comprisingoutputting, to a second segment of the graphical user interface that is separate from the first segment, a second ordered listing of entries indicative of the second set of errors in the mainframe system, the second set of errors having a different impact on the mainframe system than the first set of errors;querying a support database in response to a user selecting an entry associated with an error in the mainframe system from either the first segment or second segment;determining whether a solution to the mainframe system error associated with the user selected entry exists in the support database; anddownloading the solution from the support database in response to determining that the solution exists in the support database.2. The process of claim 1 , further comprising:determining whether a ...

SALVAGING HARDWARE TRANSACTIONS WITH INSTRUCTIONS

A transactional memory system salvages a hardware transaction. A processor of the transactional memory system executes a salvage indicator instruction, such execution including obtaining a salvage indication information specified by the salvage indicator instruction, and saving the salvage indication information comprising a salvage indication. Based on a pending point of failure being detected, the processor uses the saved salvage indication information to avoid aborting a hardware transaction, wherein absent salvage indication information, the pending point of failure causes a hardware transaction to abort. The processor detects the point of failure, and based on the detecting, determines whether the salvage indication has been recorded. Based on determining that the salvage indication has been recorded, the processor executes an about-to-fail handler, and based on determining that the salvage indication has not been recorded, the processor aborts the transactional execution of the code region. 1. A method for salvaging a hardware transaction , the method comprising: a) obtaining a salvage indication information specified by the salvage indicator instruction; and', 'b) saving, by the processor, the salvage indication information comprising a salvage indication; and, 'executing, by a processor, a salvage indicator instruction, the execution comprising a) and b)based on a pending point of failure being detected by the processor, using the saved salvage indication information to avoid aborting a hardware transaction, wherein absent salvage indication information, the pending point of failure causes a hardware transaction to abort.2. The method of claim 1 , further comprising:detecting, by the processor, the pending point of failure in a code region during transactional execution of the code region;based on the detecting, determining, by the processor, whether the salvage indication has been saved;based on determining, by the processor, that the salvage indication has ...

SALVAGING HARDWARE TRANSACTIONS WITH INSTRUCTIONS

A transactional memory system salvages a hardware transaction. A processor of the transactional memory system executes a first salvage checkpoint instruction in a code region during transactional execution of the code region, and based on the executing the first salvage checkpoint instruction, the processor records transaction state information comprising an address of the first salvage checkpoint instruction within the code region. The processor detects a pending point of failure in the code region during the transactional execution, and based on the detecting, determines that the transaction state information been recorded, and further based on the detecting, executes an about-to-fail handler. Based on executing the about-to-fail handler, the processor returns to the execution of the code region of the transaction at the address of the checkpoint instruction. 1. A method for salvaging a hardware transaction , the method comprising:executing, by a processor, a first salvage checkpoint instruction in a code region during transactional execution of the code region of a hardware transaction;based on the executing the first salvage checkpoint instruction, recording, by the processor, transaction state information comprising an address of the first salvage checkpoint instruction within the code region;detecting, by the processor, a pending point of failure in the code region during the transactional execution;based on the detecting, determining, by the processor, that transaction state information has been recorded; andbased on the detecting, transferring control to an about-to-fail handler; andbased on executing the about-to-fail handler, returning to the execution of the code region of the transaction at the address of the first salvage checkpoint instruction.2. The method of claim 1 , wherein the detecting claim 1 , by the processor claim 1 , the pending point of failure in the code region during the transactional execution includes evaluating a next instruction to ...

Controller device with retransmission upon error

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Storage apparatus and storage apparatus control method

A storage controller stores, for each of a plurality of storage devices, a usable capacity, which is a capacity usable by the storage controller in a logical storage area, configures a first RAID group using a first storage device group among the plurality of storage devices, and allocates, on the basis of a request from a host computer, one of a plurality of pages of the logical storage area in the first RAID group to a virtual volume. The storage controller reduces, when receiving first failure information indicating a failure in a first storage device in the first storage device group from the first storage device, a usable capacity of the first storage device on the basis of the first failure information.

Salvaging lock elision transactions

A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system executes a lock-acquire instruction in an HLE environment and records information about a lock elided to begin HLE transactional execution of a code region. The processor detects a pending point of failure in the code region during the HLE transactional execution. The processor stops HLE transactional execution at the point of failure in the code region. The processor acquires the lock using the information, and based on acquiring the lock, commits the speculative state of the stopped HLE transactional execution. The processor starts non-transactional execution at the point of failure in the code region.

IMPLEMENTING COHERENT ACCELERATOR FUNCTION ISOLATION FOR VIRTUALIZATION

A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy. 1. A system for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter comprising:a processor;a hypervisor managing functions associated with the hardware I/O adapter;the I/O adapter comprising a coherent accelerator including an interface services layer providing Partitionable Endpoint (PE) functions and multiple accelerator function units (AFUs);each AFU being enabled to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor; each AFU having access to system memory bound to the application software and each AFU being adapted to make copies of memory within AFU memory-cache in the AFU; and each of the AFU memory-cache and processor memory-cache being adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy for memory coherency domain.2. The system of claim 1 , further comprising a Peripheral Component Interconnect Express (PCIE) host bridge (PHB) providing coherent accelerator PE (Partitionable Endpoint) support including an adapter PE and an AFU PE;wherein ...

IMPLEMENTING COHERENT ACCELERATOR FUNCTION ISOLATION FOR VIRTUALIZATION

A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy. 1. A method for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system , said computer system including a processor; and a hypervisor managing functions associated with the hardware I/O adapter; said method comprising:providing the I/O adapter with a coherent accelerator including an interface services layer providing Partitionable Endpoint (PE) functions and multiple accelerator function units (AFUs) ;enabling each AFU to operate independently of the other AFUs to perform a computing task;enabling each AFU to access system memory bound to an application and to make one or more copies of said system memory bound to the application within the AFU;enabling each AFU to maintain synchronization between AFU memory-cache and processor memory-cache.2. The method of claim 1 , further comprising:enabling individual ones of said AFUs to operate as Peripheral Component Interconnect Express (PCIE) endpoint functions, and using a PCIE root port to associate Memory-mapped IO (MMIO) address ranges, Direct Memory Access (DMA) address ranges, and Message Signaled Interrupt (MSI) address ranges with PCIE requester IDs ( ...

HANDLING MEMORY ERRORS IN MEMORY MODULES THAT INCLUDE VOLATILE AND NON-VOLATILE COMPONENTS

In one example in accordance with the present disclosure, a system for handling memory errors includes a memory module having volatile components and non-volatile components. The system includes a BIOS chip having BIOS code and a BIOS non-volatile (NV) memory. The BIOS NV memory stores error data associated with the memory module that was stored prior to a power-on or reset of the system. The system includes a processor to execute the BIOS code to, after the power-on or reset of the system end before an operating system is loaded; (1) read, from the BIOS NV memory, the error data; and (2) determine, based on the error data, whether to take a corrective action with respect to the memory module. 1. A system for handling memory errors , the system comprising:a memory module having volatile components and non-volatile components;a BIOS chip having BIOS code and a BIOS non-volatile (NV) memory, wherein the BIOS NV memory stores error data associated with the memory module that was stored prior to a power-on or reset of the system; and read, from the BIOS NV memory, the error data; and', 'determine, based on the error data, whether to take a corrective action with respect to the memory module., 'a processor to execute the BIOS code to, after the power-on or reset of the system and before an operating system is loaded2. The system of claim 1 , wherein the processor executes the BIOS code further to take the corrective action which is to cause data in the memory module to be reinitialized.3. The system of claim 2 , wherein causing data in the memory module to be reinitialized includes causing the volatile components in the memory module to be reinitialized claim 2 , and wherein the memory module claim 2 , upon reset claim 2 , power-down claim 2 , power loss or power failure claim 2 , causes data in the volatile components to be copied to the non-volatile components.4. The system of claim 1 , wherein fie processor executes the BIOS code further to take the corrective action ...

DATA PROCESSING

Provided are a data processing method and an apparatus thereof. The method includes: when data writing is to be performed for a target Trunk Group (TKG), determining whether the target TKG is available (S); when the target TKG is available, performing data writing for the target TKG (S); and, when the target TKG is unavailable, repairing the target TKG, and performing data writing for the repaired target TKG (S). 1. A data processing method , comprising:when data writing is to be performed for a target Trunk Group (TKG), determining whether the target TKG is available, wherein in an initial state, one TKG comprises N Trunks for storing raw data and M Trunks for storing check data, any M Trunks in the N+M Trunks belong to at least K storage nodes, where N≥M, N>1, and 0≤K≤M;when the target TKG is available, performing data writing for the target TKG; andwhen the target TKG is unavailable, repairing the target TKG, and performing data writing for the repaired target TKG.2. The method according to claim 1 , wherein repairing the target TKG comprises:determining whether a first repair scheme by which the target TKG is repaired to have N+M available Trunks with any M Trunks belonging to the at least K storage nodes exists according to available Trunk resources; andwhen the first repair scheme exists, repairing the target TKG according to the first repair scheme.3. The method according to claim 2 , wherein repairing the target TKG further comprises:when the first repair scheme does not exist and K>0, letting K=K−1 and repeating the above determining block until it is determined that the first repair scheme exists or K=0; andwhen K=0, determining whether a second repair scheme by which the target TKG is repaired to have N+M available Trunks exists according to the available Trunk resources;when the second repair scheme exists, repairing the target TKG according to the second repair scheme; andwhen the second repair scheme does not exist and M>0, letting M=M−1, and ...

OUT-OF-BOUNDS RECOVERY CIRCUIT

Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic. 1. An out-of-bounds recovery circuit for an electronic device having at least a first operating state having first non-allowable memory addresses and a second operating state having second non-allowable memory addresses , the out-of-bounds recovery circuit comprising: monitor one or more control and/or data signals of the electronic device,', 'detect an out-of-bounds violation in the electronic device, when the detection logic determines, based on the one or more control and/or data signals of the electronic device, that the electronic device is in the first operating state and a processing element of the electronic device has fetched an instruction from one of the first non-allowable memory addresses, and', 'detect an out-of-bounds violation in the electronic device, when the detection logic determines, based on the one or more control and/or data signals of the electronic device, that the electronic device is in the second operating state and the processing element of the electronic device has fetched an instruction from one of the second non-allowable memory addresses; and, 'detection logic configured totransition logic configured to, in response to the detection logic detecting an out-of-bounds violation, cause the electronic device to transition to a predetermined ...

Application aware input/output fencing

Disclosed herein are methods, systems, and processes to perform application aware input/output (I/O) fencing operations. Performing such an application aware I/O fencing operation includes installing an identifier that identifies an instance of an application with a node on which the instance of the application is executing, on coordination points. A weight assigned to the instance of the application is determined, and the instance of the application is terminated based on the weight.

Method and System to Automate Troubleshooting and Resolution of Customer Device Issues

Aspects of the subject disclosure may include, for example, a method in which a processing system installs on a controlling device user interface automation software provided by a customer care server separated from the controlling device; the controlling device communicates with the customer care server over a communication network. The system receives information from equipment of a customer care agent regarding a customer care issue associated with a communication device coupled to the controlling device by a communication link separate from the communication network. The method includes effecting, responsive to the information and without action by a user of the communication device, an input to the user interface via the communication link to initiate a resolution procedure for the customer care issue; the resolution procedure can include resetting network settings, enabling a network service, collecting information regarding the network settings, and/or providing new network settings. Other embodiments are disclosed. 1. A method , comprising:installing, by a processing system including a processor of a controlling device, user interface automation software provided by a customer care server, the controlling device communicating with the customer care server over a communication network, the customer care server being separate from the controlling device;receiving, by the processing system over the communication network, information from equipment of a customer care agent regarding a customer care issue associated with a communication device, the communication device coupled to the controlling device by a communication link separate from the communication network; andeffecting, by the processing system responsive to the information and without action by a user of the communication device, an input to the user interface via the communication link to initiate a resolution procedure for the customer care issue,the resolution procedure comprising resetting network ...

IDENTIFYING DEFECTIVE FIELD-REPLACEABLE UNITS THAT INCLUDE MULTI-PAGE, NON-VOLATILE MEMORY DEVICES

A method for managing hardware within a computing system. The method includes at least one computer processors identifying a plurality of field-replaceable units (FRUs) within a computing system that respectively include a non-volatile memory device. The method further includes determining a status corresponding to a FRU of the identified plurality of FRUs. The method further includes responding to determining a non-functional status of the FRU of the identified plurality of FRUs, by determining a response related to the non-functional FRU. The method further includes initiating an action on the computing system based on the determined response related to the non-functional FRU. 1. A method for managing hardware within a computing system , the method comprising:identifying, by one or more computer processors, a plurality of field-replaceable units (FRUs) within a computing system that respectively include a non-volatile memory device;determining, by one or more computer processors, a status corresponding to a FRU of the identified plurality of FRUs;in response to determining a non-functional status of the FRU of the identified plurality of FRUs, determining, by one or more computer processors, a response related to the non-functional FRU; andinitiating, by one or more computer processors, an action on the computing system based on the determined response related to the non-functional FRU.2. The method of claim 1 , wherein the non-volatile memory device of an identified FRU is a multi-page non-volatile memory device that stores at least vital product data (VPD) related to a FRU.3. The method of claim 1 , wherein determining the status corresponding to the FRU further comprises:initiating, by one or more computer processors, a read operation to obtain data stored within a respective non-volatile memory device of the FRU utilizing a hardware bus that facilitates communication between the plurality of FRUs and a management program of the computing system; andin response ...