VERFAHREN UND VORRICHTUNG ZUM REDUZIEREN VON MIKROBONDHÜGELN FÜR EINE DOUBLE-DATA RATE (DDR)-ÜBERTRAGUNG ZWISCHEN DIES

Es wird ein Regime zur Datenübertragung mit doppelter Datenrate (Double Data Rate, DDR) zwischen Dies bereitgestellt. Insbesondere verwendet das Datenübertragungsregime ein Fehlerkorrekturcode (Error Correction Code, ECC)-Codierregime, das sich die DDR-Eigenschaft zunutze macht, dass ein einzelner Mikrobondhügeldefekt nur vier mögliche Fehlerszenarien ergeben kann. Ein spezialisiertes Single Error Correcting-, Double Error Detecting- and Double Adjacent Error Correcting (SEC-DED-DAEC)-Codierregime, das mindestens vier einschränkende Bedingungen für eine Paritätsprüfungsmatrix auferlegt, kann verwendet werden. Auf diese Weise konfiguriert und betrieben, ist eine geringere Anzahl von Paritätsprüfbits erforderlich, um Datenbitfehler zu detektieren, die mit einem einzelnen defekten Mikrobondhügel verknüpft sind.

NICHTFLÜCHTIGER HALBLEITERSPEICHER MIT ZYKLUSZÄHLWERTE SPEICHERNDEN GROSSEN LÖSCHBLÖCKEN

VERSCHIEBUNG AUFEINANDER FOLGENDER SEKTOREN INNERHALB EINES DATENBLOCKS IN EINEM FLASH-MASSENSPEICHER

Verfahren zur Steuerung einer Operation einer nichtflüchtigen Speichervorrichtung unter Verwendung von Maschinenlernen und Speichersystem

Nach einem Verfahren zur Steuerung einer Operation einer nichtflüchtigen Speichervorrichtung unter Verwendung von Maschinenlernen werden Operationsbedingungen der nichtflüchtigen Speichervorrichtung durch Durchführen einer Ableitungsoperation unter Verwendung eines Maschinenlernmodells bestimmt. Trainingsdaten, die basierend auf Merkmalsinformationen und Fehlerinformationen erzeugt werden, werden gesammelt, wobei die Fehlerinformationen Ergebnisse einer Fehlerkorrekturcode(ECC)-Dekodierung der nichtflüchtigen Speichervorrichtung angeben. Das Maschinenlernmodell wird durch Durchführen einer Lernoperation basierend auf den Trainingsdaten aktualisiert. Optimierte Operationsbedingungen für individuelle Benutzerumgebungen werden durch Sammeln von Trainingsdaten im Speichersystem und Durchführen der Lernoperation und der Ableitungsoperation basierend auf den Trainingsdaten vorgesehen.

Ausgleich nachlassender Funktionsfähigkeit von Halbleiterdatenträgern auf der Grundlage der von einer RAID-Steuereinheit empfangenen Daten- und Paritätsnutzungsinformationen

Verfahren, das folgende Schritte umfasst:Konfigurieren einer Vielzahl von Halbleiterdatenträgern (solid state disks) als redundante Anordnung unabhängiger Datenträger/Laufwerke (RAID), wobei in der Vielzahl von Halbleiterdatenträgern eine Vielzahl von Blöcken gespeichert sind und wobei die geschätzte Lebenserwartung von Speicherbereichen der Vielzahl von Halbleiterdatenträgern, die mindestens einigen der Vielzahl von Blöcken entsprechen, unterschiedlich hoch ist;Einbeziehen einer Anzeige durch eine Steuereinheit in Datenstrukturen, die einem in den Speicherbereichen der Vielzahl von Halbleiterdatenträgern zu speichernden Block zugehörig sind, dass der Block der RAID entsprechende Paritätsinformationen enthält, wobei die Paritätsinformationen Informationen umfassen, die einem Fehlerkorrekturmechanismus zum Schutz vor Datenträgerausfall entsprechen; undSenden der Datenstrukturen durch die Steuereinheit an die Vielzahl von Halbleiterdatenträgern,wobei die Vielzahl von Halbleiterdatenträgern ...

EEPROM-MATRIX MIT EINEM, DEM "FLASH"-SPEICHER ÄHNLICHEN, KERN

Method for initiating a refresh operation in a solid-state nonvolatile memory device

Data management in solid state storage systems

Data encoding in solid-state storage apparatus

PROCEDURE FOR THE DATA PROTECTION AND EQUIPMENT FOR ITS EXECUTION

COPY BAKING OPTIMIZATION FOR A MEMORY SYSTEM

PROCEDURE AND DEVICE FOR THE ERROR CORRECTION AFTER THE DELETE'S NUMBER OF A SOLID MEMORY

PROCEDURE AND DEVICE FOR THE MULTI-LEVEL ERROR CORRECTION

PROCEDURE FOR COPYING DATA WITHIN A REPROGRAMMABLE NON VOLATILE MEMORY

DETECTION OF BEING APPROACHING BAD BLOCKS

SEMICONDUCTOR MEMORY ARRANGEMENT WITH ERROR DETECTION AND - CORRECTION

NON-VOLATILE SEMICONDUCTOR MEMORY WITH LARGE ERASE BLOCKS STORING CYCLE COUNTS

DIRECT MEMORY SWAPPING BETWEEN NAND FLASH AND SRAM WITH ERROR CORRECTION CODING

Error management processes for flash eeprom memory arrays

WEAR MANAGEMENT FOR FLASH MEMORY DEVICES

A machine-implemented method for managing a flash storage system includes receiving a command for a data operation. The method includes determining a projected life value for each of a plurality of flash memory devices in the flash storage system, wherein the projected life value for at least one of the plurality of flash memory devices is higher than the projected life value for at least another one of the plurality of flash memory devices. The method also includes selecting a flash memory block on one of the plurality of flash memory devices for the data operation based on the respective projected life values for the plurality of flash memory devices.

Processing a target memory

SEMICONDUCTOR STORAGE DEVICE

Storage device and method, data processing device and method and electronic device

Selection of data for redundancy calculation in three dimensional nonvolatile memory

INTEGRATED ERROR CHECKING AND CORRECTION (ECC) IN MEMORY DEVICES WITH FIXED BANDWIDTH INTERFACES

Nonvolatile memory apparatus, memory controller, and memory system

Soft decoding for quantizied channel

METHOD AND APPARATUS FOR CONTROL OF FLASH MEMORY.

DEVICE AND A METHOD FOR READING A DATA WORD AND DEVICE AND METHOD FOR STORING A STORAGE BLOCK

Reprogrammable microprocessor correcting method for e.g. airbag system, involves verifying integrity of corrected application routine using verification code, and accepting correction when integrity of corrected routine is confirmed

Procédé de correction d'un microprocesseur reprogrammable comprenant les étapes suivantes: utiliser le microprocesseur avec une mémoire semi conductrice non volatile reprogrammable, mémoriser au moins une routine d'application dans la mémoire, fournir un code de correction pour la routine d'application, fournir un code de vérification pour la routine d'application, vérifier l'intégrité de la routine à l'aide du code de vérification, effectuer une correction à l'aide du code de correction s'il n'y a pas intégrité de la routine d'application, la correction se faisant dans la mémoire, vérification de l'intégrité de la routine d'application corrigée du code de vérification, et accepter une correction réussie si l'intégrité de la routine d'application corrigée est confirmée.

Encoding scheme for 3D vertical flash memory

L'invention concerne des techniques de codage de données pour systèmes de stockage en mémoire non volatile. Dans un mode de réalisation particulier, ces techniques peuvent être mises en œuvre sous la forme d'un procédé, consistant par exemple à écrire des premières données dans la mémoire, à lire les premières données depuis la mémoire, à analyser les premières données lues de telle manière que l'analyse consiste à déterminer si les données lues comportent une erreur, à coder des deuxièmes données sur la base de l'analyse des premières données de telle manière que les deuxièmes données soient codées afin qu'elles soient écrites à une position adjacente à l'erreur lorsqu'il est déterminé que les données lues comportent l'erreur, et à écrire les deuxièmes données codées dans la mémoire à ladite position.

SOLID STATE DISK CONTROLLER APPARATUS

SEMICONDUCTOR MEMORY DEVICE AND FAIL BIT TEST METHOD THEREOF

Solid State Storage System with High Speed and Controlling Method thereof

에러 교정을 기초로 디폴트 판독 신호를 설정하기 위한 방법 및 장치

... 본 발명은 에러 교정을 기초로 디폴트 판독 신호를 설정하는 것과 관련된 장치 및 방법을 포함한다. 복수의 방법은 제 1 이산 판독 신호에 의해 메모리 셀의 그룹으로부터 데이터의 페이지를 판독하는 단계 및 상기 제 1 이산 판독 신호에 의해 판독된 데이터의 페이지의 적어도 하나의 코드워드를 에러 교정하는 단계를 포함한다. 방법은 상기 제 1 이산 판독 신호와 상이한 제 2 이산 판독 신호에 의해 메모리 셀의 그룹으로부터 데이터의 페이지를 판독하는 단계 및 상기 제 2 이산 판독 신호에 의해 판독된 데이터의 페이지의 적어도 하나의 코드워드를 에러 교정하는 단계를 포함할 수 있다. 제 1 이산 판독 신호 및 제 2 이산 판독 신호 중 하나가 각각의 에러 교정을 적어도 부분적으로 기초로 하여 디폴트 판독 신호로서 설정될 수 있다.

FLASH MEMORY SYSTEM AND ERROR CORRECTION METHOD THEREOF

ERASED SECTOR DETECTION MECHANISMS

ENCODING METHOD AND MEMORY APPARATUS

TEST EQUIPMENT AND TEST METHOD

STORAGE DEVICE AND READ METHOD FOR READING SAME

A method for reading a storage device according to the embodiment of the present invention includes: a step of performing a first reading operation based on a time-read level lookup table which indicates a read level change degree according to program elapse time and a time stamp table which stores program time; a step of determining whether the time-read level lookup table needs to be controlled according to the performance result of the first reading operation; a step of controlling the time-read level lookup table by a valley search operation when the time-read level lookup table needs to be controlled; and a step of performing a second reading operation based on the controlled time-read level lookup table and the time stamp table. COPYRIGHT KIPO 2016 ...

OPERATING METHOD OF FLASH MEMORY SYSTEM

The present invention relates to an operating method of a flash memory system, to set an optimal reference voltage to raise a quantization level. According to the present technology, the method comprises the following steps: a first step of performing soft decision decoding for data which is decoded in a message block unit formed by line codes and column codes by a block-wise concatenated Bose-Chaudhuri and Hochquenghem (BC-BCH) schema and is stored in a memory device; a second step of calculating a reference voltage for the message block including an error among the message blocks of the data when the soft decision decoding is failed; and a third step of performing the soft decision decoding by using the calculated reference voltage. COPYRIGHT KIPO 2016 (AA) Start (BB) End (S501) Read data (S503) Perform hard decision decoding (S505) Is hard decision decoding successful? (S507) Calculate position and the number of error blocks (S509) Calculate reference voltage l = argmasE[n_fe¦dF] x ( ...

METHOD AND DEVICE FOR SELECTIVELY REFRESHING A REGION OF A MEMORY OF A DATA STORAGE DEVICE

NON-REGULAR PARITY DISTRIBUTION DETECTION VIA METADATA TAG

MEMORY DATA ERROR CORRECTION METHOD

According to the present invention, a memory data error correction method comprises: a step of receiving a burst-specific content from each of multiple bursts of a memory module; a step of storing the burst-specific content from each of the multiple bursts; and a step of using all error correction code (ECC) beats received as a part of a single error correction double error detection (SECDED) code from at least one of the multiple bursts to correct at least one error included in the first predetermined number of beats of burst-specific data. The burst-specific content includes the first predetermined number of beats of the burst-specific data as well as corresponding beats of a burst-specific ECC. According to the present invention, error correction performance can be improved even by using existing SECDED circuitry. COPYRIGHT KIPO 2016 ...

LOW LATENCY READ OPERATION FOR MANAGED NON-VOLATILE MEMORY

가변 코드 레이트 고체-상태 드라이브

... 장치(100)뿐만 아니라 이를 위한 방법(200) 및 시스템(400)은 일반적으로 정보를 저장하는 것에 관한 것이다. 이러한 장치에서, 메모리 제어기(110)는 코드 레이트(112)를 제공하기 위한 것이다. 인코더(120)는 인코딩된 데이터(121)를 제공하기 위해 코드 레이트(112) 및 입력 데이터(111)를 수신하기 위한 것이다. 고체-상태 저장소(130)는, 저장된 데이터(133)로서, 인코딩된 데이터(121)를 수신 및 저장하기 위한 것이다. 디코더(140)는, 저장된 데이터(133)에 액세스하고, 그리고 액세스되는 저장된 데이터(133)의 디코딩된 데이터(141)를 제공하기 위해 코드 레이트(112)를 수신하기 위한 것이다. 디코딩된 데이터(141)는 소프트 판정들로서 제공된다. 메모리 제어기(110)는, 디코딩된 데이터(141)의 확률들에 대한 응답으로 코드 레이트(112)를 조정하기 위해, 디코딩된 데이터(141)를 수신하기 위한 것이다.

OPTION(SETTING) DATA STORAGE CIRUIT, NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

PURPOSE: A set data storage circuit, a nonvolatile memory device including the same, and a memory system are provided to improve reliability by rewriting set data or changing a page for reading the set data. CONSTITUTION: A set data storage block(120) stores set data. An access unit accesses the set data of the set data storage block. An error sensing unit(140) senses set data errors. An error correcting unit(150) corrects errors of the set data storage block when the error sensing unit senses errors. The set data is equally stored in two or more regions of the set data storage block. COPYRIGHT KIPO 2013 [Reference numerals] (110_0) Normal data storage block 0; (110_1) Normal data storage block 1; (110_N) Normal data storage block N; (140) Error sensing unit; (150) Error correcting unit; (160) Counter; (170) Control circuit; (AA) Set data storage block; (BB) Page buffer array; ...

반도체 메모리 장치의 에러 정정 회로, 반도체 메모리 장치 및 메모리 시스템

... 메모리 셀 어레이를 포함하는 반도체 메모리 장치의 에러 정정 회로는 생성 매트릭스로 표현되는 에러 정정 코드(error correction code, 이하 'ECC') 및 ECC 엔진을 포함한다. 상기 ECC 엔진은 상기 ECC를 이용하여, 복수의 데이터 비트들을 포함하는 메인 데이터에 기초하여 패리티 데이터를 생성하고, 상기 패리티 데이터를 이용하여 상기 메인 데이터의 에러를 정정한다. 상기 데이터 비트들은 복수의 서브 코드워드 그룹들로 분할되고, 상기 ECC는 상기 서브 코드워드 그룹들에 상응하는 복수의 코드 그룹들로 분할되는 복수의 칼럼 벡터들을 포함하고, 상기 칼럼 벡터들은 상기 메인 데이터의 에러 비트들에 의한 오정정 비트가 발생하는 서브 코드워드 그룹의 위치를 제약하는 원소들을 가진다.

SIMULTANEOUS EXTERNAL READ OPERATION DURING INTERNAL PROGRAMMING IN A FLASH MEMORY DEVICE

A system (300) and method for performing a simultaneous external read operation during internal programming of a memory device (301) is described. The memory device is configured to store data randomly and includes a source location (305), a destination location (303), a data register (307), and a cache register (309). The data register (307) is configured to simultaneously write data to the destination (303) and to the cache register (309). The system (300) further includes a processing device (107) (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device (107) is additionally configured to provide for error correction if the received data are inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location (303). © KIPO & WIPO 2007 ...

ECC CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

Semiconductor storage device

As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

Storage device for refreshing data pages of flash memory based on error correction code and method for the same

A storage device for refreshing data pages of a flash memory includes an error correction code (ECC) detector and a controller. The flash memory includes a plurality of data pages each having a data area for storing data and a spare area for storing ECC corresponding to the stored data. The ECC detector is used for detecting used bits of ECC stored in the spare area of each data page. The controller is used for storing data and ECC of a data page to another new data page when the used bits of the ECC are less than a predetermined value.

Architecture and method for storing data

In a data storage architecture, any of the data sector bytes is stored next to and contiguous to a data correction byte calculated with the data sector byte in a flash memory, thereby improving data access efficiency. In a data storage method, a data correction byte consisting of at least two sets of data correction codes is generated in response to one of data sector bytes, thereby reducing data error coverage rate.

Apparatuses and methods for staircase code encoding and decoding for storage devices

An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndorme for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codeword span two or more rows and two or more columns of the codeword.

DATA STORAGE DEVICE AND DATA STORAGE METHOD FOR DETECTING CURRENTLY-USED LOGICAL PAGES

Data storage device and operating method thereof

Semiconductor memory device and method of controlling the same

Memory device, memory system and method for data protection across multiple memory blocks

Architecture and method for storing data

In a data storage architecture, any of the data sector bytes is stored next to and contiguous to a data correction byte calculated with the data sector byte in a flash memory, thereby improving data access efficiency. In a data storage method, a data correction byte consisting of at least two sets of data correction codes is generated in response to one of data sector bytes, thereby reducing data error coverage rate.

Flash memory device, system and method with random

DATA RESTORATION METHOD FOR A NON-VOLATILE MEMORY

A method and apparatus for selectively restoring data in a non- volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data.

SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

FLASH MEMORY WITH CODING AND SIGNAL PROCESSING

A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.

MOVING SEQUENTIAL SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE

A method and apparatus are disclosed for increasing the system performance of a digital system having a controller for controlling nonvolatile devices for storing blocks of information, each block having a group of sectors. When sectors within a block are being rewritten in sequential order, the controller writes the new sector information into a sector location of another block without the need to move any of the sectors within the original block thereby reducing the number of read and write cycles needed to avoid erase-before-write operations. A "moved" flag (1042), stored in the sector location of each block, indicates that the sector has been transferred to another block or, alternatively, a move locator word (170) maintains status information regarding the position of the sectors within the blocks that have been moved.

SYSTEM AND METHOD FOR DETECTING COPYBACK PROGRAMMING PROBLEMS

In a method for detecting problems related to copyback programming, after the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page.

APPARATUSES AND METHODS FOR CORRECTING ERRORS AND MEMORY CONTROLLERS INCLUDING THE APPARATUSES FOR CORRECTING ERRORS

An error correction apparatus may be provided. The error correction apparatus may be configured to perform a scrambling operation before an error correction code (ECC) operation is performed.

METHOD OF OPERATION FOR A NONVOLATILE MEMORY SYSTEM AND METHOD OF OPERATING A MEMORY CONTROLLER

A method of operating a nonvolatile memory system including a memory device having a plurality of memory blocks includes selecting a source block among the plurality of memory blocks in the nonvolatile memory system, and performing a reclaim operation for the source block based on the number of program and erase cycles which have been performed on the source block. 1. A method of operating a nonvolatile memory device including a plurality of memory blocks , the method comprising:selecting a source block from among the plurality of memory blocks upon detecting that a number of error bits, equal to or greater than a reference value, has occurred during a read operation on the source block; anddetermining a number of program/erase cycles (P/E cycles) of the source block, if the number of P/E cycles being greater than a first value, then starting a first reclaim operation on the source block at first read count, and, if the number of P/E cycles being equal to or smaller than the first value, then starting a second reclaim operation on the source block at second read count,wherein the first read count and the second read count are numbers of read operations performed on the nonvolatile memory device, and the first read count is smaller than the second read count.2. The method of claim 1 , wherein the first read count and the second read count are set based on the number of P/E cycles of the source block and a number of error bits occurred during the read operation performed on the source block.3. The method of claim 3 , wherein a first number of error bits occurred during a first read operation performed at the first read count is substantially same with a second number of error bits occurred during a second read operation performed at the second read count.4. The method of claim 1 , wherein the first reclaim operation is completed in a first reclaim execution period claim 1 , and the second reclaim operation is completed in a second reclaim execution period which is ...

DECODING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE

A decoding method, a memory controlling circuit unit and a memory storage device are provided. The decoding method includes: performing a first type decoding operation for a first frame including a first codeword to obtain a second codeword. The method also includes: recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation. The method further includes: updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition; and performing a second type decoding operation for a block code including the first frame.

Write mapping to mitigate hard errors via soft-decision decoding

An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

DISPOSABLE PARITY

Devices and techniques for disposable parity are described herein. First and second portions of data can be obtained, and respective parity values stored in adjacent memory locations. An entry mapping the respective parity values to the first and second portions of data is updated when the parity values are stored. If an error occurs when writing a portion of data, the mapping entry is used to retrieve the parity data to correct the error. Otherwise, the parity data is discarded.

NONVOLATILE MEMORY DEVICE

A nonvolatile memory device includes a memory cell region having a first metal pad and a peripheral circuit region having a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a a memory cell array in the memory cell region and an address decoder in the peripheral circuit region. The memory cell array includes memory blocks, and each memory block includes memory cells coupled to word-lines respectively. The word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selectable by a sub-block unit smaller than one memory block of the plurality of memory blocks. The address decoder applies an erase voltage to each of sub-blocks in a first memory block of the plurality of memory blocks through the first metal pad and the second metal pad.

Data writing method and system

A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased.

SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

System and method for providing data integrity in a non-volatile memory system

An invention is provided for ensuring data integrity in a non-volatile memory system, including boot block data integrity during Power On Reset. The invention includes loading data into a buffer, such as a flash buffer, and generating an error detection code for the data utilizing a check code generator located in the memory controller. The error detection code is compared to a previously stored error detection code associated with the data. Then, when the error detection code is different from the previously stored error detection code, a correction pattern is calculated and applied to the data directly in the buffer for the non-volatile memory.

Memory systems and methods of correcting errors in the memory systems

A memory system includes a Reed-Solomon (RS) decoder, a reliability tracking circuit, and an erasure control circuit. The RS decoder performs an error correction decoding operation of ‘K’-number of symbols outputted from a memory medium. The reliability tracking circuit generates and stores information on a reliability of the symbols, error occurrence possibilities of which are distinguished into a plurality of different levels according to the error correction decoding operation performed by the RS decoder. The erasure control circuit controls the RS decoder such that the symbols are erased in order of the reliability of the symbols from a low reliable symbol to a high reliable symbol and the error correction decoding operation is performed according to the information on the reliability of the symbols stored in the reliability tracking circuit.

Analog Interface for a Flash Memory Die

A flash disk controller includes an input operable to receive analog signals from a flash memory die. The flash memory die includes multiple flash memory cells. The analog signals represent data values stored in the flash memory cells. An analog-to-digital conversion module is coupled to the input to convert received analog signals into digital data. A control module selects memory cells from which the input receives analog signals.

Method for reliably storing non-data fields in a flash EEPROM memory array

A method for utilizing a cyclical redundancy check value with an identification field stored in memory which is constantly changing between testing of the cyclical redundancy check value. In order to allow the use of a cyclical redundancy check value with a field which constantly varies as does the field in a flash EEPROM memory array, various portions of the field are masked to the cyclical redundancy check and additional reliability checks are utilized to assure that those portions which are masked remain reliable.

Flash eeprom system with defect handling

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Flash EEprom system

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Implementation of keeping data integrity in multiple dimensions

Techniques for Implementation of keeping data integrity in multiple dimensions are described. A single but relatively complicated engine is used to encode a line of original data bits in one dimension once and for all, while a linear array of simple engines are used in another dimension to keep revising sets of redundant data bits for successive lines of original data bits, where the redundant data bits become final when a last line of original data bits is accessed.

FIELD PROGRAMMABLE GATE ARRAY (FPGA) WITH AUTOMATIC ERROR DETECTION AND CORRECTION FUNCTION FOR PROGRAMMABLE LOGIC MODULES

A field programmable gate array (FPGA) with an automatic error detection and correction function for programmable logic modules includes an error checking and correction device. A check code generation circuit in the error checking and correction device performs error correcting code (ECC) encoding according to input data of corresponding programmable logic registers to generate a check code, and refreshes and writes the check code into a check code register according to a clock signal. A check circuit checks outputs of the programmable logic registers and check code registers to generate syndromes for implementing checking. A decoding circuit generates upset signals corresponding to the syndromes according to a trigger enable pulse of a trigger circuit to control a fault register to directly and asynchronously upset content to correct the error. A circuit area is greatly reduced by using the FPGA, thereby improving a degree of integration of the circuit.

Semiconductor storage apparatus

A semiconductor storage apparatus is provided which can be used as a primary storage apparatus and a secondary storage apparatus and which allows both high accessibility and non-volatile storage of information. A volatile RAM section is a semiconductor memory adapted to load information to be stored and can be accessed at a high speed from the outside by way of a central control section. A non-volatile RAM section is another semiconductor memory into which information can be electrically reloaded and which does not require a power supply for holding stored contents. Under the control of a save/reload control section of the central control section, a memory mutual access control section is activated and saving/reloading of stored information is performed between the volatile RAM section and the non-volatile RAM section by a volatile RAM access control section and a non-volatile RAM access control section.

Method and apparatus for flexible RAID in SSD

A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

Semiconductor memory device and memory system having the same

Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.

MEMORY SYSTEM AND OPERATION METHOD THEREOF

A memory system comprising: a nonvolatile memory device including a plurality of pages, and suitable for performing one among a first program operation of performing program and verify operations according to an incremental step pulse programming (ISPP) scheme and a second program operation of first performing a verify operation and then performing program and verify operations according to the ISPP scheme when the program operation is to be performed to each of the plurality of pages; and a controller suitable for controlling the nonvolatile memory device to perform the second program operation when a target page meets an operation condition of a reprogram, and to perform the first program operation when the target page does not meet the operation condition of the reprogram.

Flash memory device and method

An improved flash memory device and method for improving the performance and reliability of a flash memory device is provided. According to one embodiment, a method for writing data to a memory device may include writing the data to a temporary storage location within the memory device before the data is copied to another location within the memory device, incrementing a count value to indicate that the data has been copied, and repeating the step of writing, if the count value is less than a threshold value. If the count value is greater than or equal to the threshold value, the method may write the data to an external memory controller, where the data is checked for errors and corrected if an error is found, before the data is copied to the other location within the memory device.

Storage device

The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only "1s", the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof "0", followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.

Semiconductor memory device

An ECC circuit ( 103 ) is located between I/O terminals ( 104 ₀ -104 ₇) and page buffers ( 102 ₀ -102 ₇). The ECC circuit ( 103 ) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas ( 101 ₀ -101 ₇), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas ( 101 ₀ -101 ₇). The ECC circuit ( 103 ) allocates a set of 40 check bits (ECC) to an information bit length of 4224=(528x8) bits to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area ( 101 _j).

Method and device for multi phase error-correction

Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

Controller, semiconductor memory system and operating method thereof

An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.

Memory controller storing data in approximate memory device based on priority-based ECC, non-transitory computer-readable medium storing program code, and electronic device comprising approximate memory device and memory controller

A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.

Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory

A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Memory buffer having accessible information after a program-fail

A memory device, and a method of operating same, utilize a first memory buffer associated with a first memory array and a second memory buffer associated with a second memory array to maintain information subsequent to a program-fail event associated with the first memory array and to provide the information to the second memory array.

SYSTEMS AND METHODS FOR ULTRA FAST ECC WITH PARITY

Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

ADAPTIVE TARGETING OF READ LEVELS IN STORAGE DEVICES

A storage device may include a controller and a plurality of memory devices logically divided into a plurality of pages. Each page in the plurality of pages may include a plurality of bits. The controller may be configured to: apply a read level to a control gate of a transistor for each respective bit in the plurality of bits; determine, based on an amount of current that flows through the transistor, a respective value for each bit from the respective plurality of bits; determine, based on the respective values for the respective plurality of bits, an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value; and adjust, based on the error ratio, the read level.

Method and apparatus for data encoding and decoding using a standardized data storage and retrieval protocol

A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device encodes the data specified in the encode command, thus relieving the host processor of performing the encoding/decoding and freeing the host processor for other tasks.

Semiconductor memory device with error correction

This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

Systems and methods for averaging error rates in non-volatile devices and storage systems

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

Memory for accessing multiple sectors of information substantially concurrently

A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently.

Data processing method and semiconductor integrated circuit

A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string.

Method and memory controller for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory

An exemplary method for reading data stored in a flash memory includes: controlling the flash memory to perform a plurality of read operations upon each of a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from each of the memory cells as one of the bit sequences by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Nonvolatile semiconductor memory device

The disclosed invention provides a technique for efficiently avoiding read disturbance. A nonvolatile semiconductor memory device includes a nonvolatile memory unit and a controller that can control refresh processing for rewriting data in a block of blocks assumed to be erasable units in the nonvolatile memory unit into anther block different from the block. The controller sets up a first area and a second area different from the first area in the nonvolatile memory unit and, each time a refresh trigger occurs, executes refresh processing for the first area and the second area, such that a refresh frequency of data in the first area will become higher than a refresh frequency of data in the second area. Thereby, it is possible to efficiently avoid read disturbance when read access is repeated.

Semiconductor memory device and method of controlling the same

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Copyback Optimization for Memory System

In a copyback or read operation for a non-volatile memory subsystem, data page change indicators are used to manage transfers of data pages between a register in non-volatile memory and a controller that is external to the non-volatile memory.

Methods, devices, and systems for data sensing

The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

Data management in solid state storage systems

Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords.

Memory controller, semiconductor memory apparatus and decoding method

A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

System and method for detecting copyback programming problems

Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page.

Flash storage wear leveling device and method

A flash storage device performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data.

Refresh architecture and algorithm for non-volatile memories

Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

Lifetime mixed level non-volatile memory system

A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

System and method of copying data

A method of copying data includes receiving a command instructing copying of data from a source location in the memory die to a destination location in the memory die. The method includes determining if a criterion is met, including comparing a predefined parameter to a dynamic threshold. In response to determining that the criterion is met, the method includes executing the copying by moving the data from the source location in the memory die to the controller die and, after moving the data to the controller die, moving an error-corrected version of the data from the controller die to the destination location in the memory die. In response to determining that the criterion is not met, the method includes executing the copying by moving the data inside the memory die source location to the destination location without moving the data to the controller die.

Setting data storage for semiconductor devices including memory devices and systems

A setting data storage circuit includes a setting data storage block configured to store setting data; an access unit configured to access the setting data of the setting data storage block; an error detection unit configured to detect an error in the setting data; and an error recovery unit configured to recover an error in the setting data storage block when the error detection unit detects an error.

Non-volatile memory with extended error correction protection

Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.

SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND

A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device. 1. A method , comprising:receiving an activate signal at a serial peripheral interface Not AND (NAND) controller;receiving a timing signal at the serial peripheral interface NAND controller;receiving a serial data in signal at the serial peripheral interface NAND controller; andtransmitting the serial in data signal from the serial peripheral interface NAND controller without translation into standard NAND format.2. The method of claim 1 , comprising receive the serial data in signal transmitted from the serial peripheral interface NAND controller at a NAND memory.3. The method of claim 1 , comprising storing data transmitted between the serial peripheral interface NAND controller and a NAND memory in a cache memory.4. The method of claim 3 , comprising performing error correction on the data stored in the cache memory.5. The method of claim 4 , wherein performing error correction on the data stored in the cache memory comprises:reading data in the cache memory;detecting errors in the data; andupdating an error correction status register.6. The method of claim 4 , wherein performing error correction on data stored in the cache memory comprises:reading data in the cache memory;detecting errors in the data;correcting at least one error in the data; andupdating an error correction status register.7. The method of claim 4 , ...

Data partitioning scheme for non-volatile memories

Systems and methods are disclosed for partitioning data for storage in a non-volatile memory (“NVM”), such as flash memory. In some embodiments, a priority may be assigned to data being stored, and the data may be logically partitioned based on the priority. For example, a file system may identify a logical address within a first predetermined range for higher priority data and within a second predetermined range for lower priority data, such using a union file system. Using the logical address, a NVM driver can determine the priority of data being stored and can process (e.g., encode) the data based on the priority. The NVM driver can store an identifier in the NVM along with the data, and the identifier can indicate the processing techniques used on the associated data.

SYSTEMS AND METHODS FOR ADAPTIVE DATA STORAGE

A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising two or more solid-state storage elements. The data segments may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The data arrangement may determine input/output performance characteristics. An optimal adaptive data storage configuration may be based on read and/or write patterns of storage clients, read time, stream time, and so on. Data of failed storage elements may be reconstructed by use of parity data and/or other ECC codewords stored within the array. 1. A method , comprising:managing storage operations on a plurality of solid-state storage elements;generating an ECC codeword comprising data for storage on the solid-state storage elements; andstoring portions of the ECC codeword on two or more of the solid-state storage elements.2. The method of claim 1 , further comprising:generating a first set of ECC codewords comprising data of a first storage request;generating a second set of ECC codewords comprising data of a second storage request;storing the first set of ECC codewords in a first set of one or more solid-state storage elements; andstoring second set of ECC codewords in a second, different set of one or more solid-state storage elements.3. The method of claim 2 , further comprising reading ECC codewords comprising the data of the first storage request from the first set of solid-state storage elements and ECC codewords comprising the data of the second storage request from the second set of solid-state storage elements in a single read operation.4. The method of claim 1 , further comprising:dividing the plurality of solid-state storage elements into a plurality of independent channels, each independent channel comprising a respective subset of solid-state storage elements; andstoring ECC codewords corresponding to respective ...

DECODING IN SOLID STATE MEMORY DEVICES

In a solid state memory device, codewords stored in a unit of the memory device are decoded using an error correcting iterative decoding process. An average number of iterations needed for successfully decoding codewords of the unit is determined, and the average number of iterations is monitored. The average number of iterations can be taken as a measure of wear of the subject unit. 1. A method for controlling a solid state memory device , comprising:decoding codewords stored in a unit of the memory device using an error correcting iterative decoding process,determining an average number of iterations needed for successfully decoding codewords of the unit, andmonitoring the average number of iterations.2. A method according to claim 1 , wherein subject to the average number of iterations at least one of the following activities is triggered:modifying a mode the unit is operated in;applying a wear-levelling routine;no longer operating the unit;preventing loss of data with respect to the unit;modifying one or more parameters used in the decoding process, and continue running the decoding process with the modified parameters.3. A method according to claim 1 ,wherein the monitoring of the average number of iterations includes comparing the average number of iterations to a threshold, andwherein at least one activity is triggered when the average number of iterations exceeds the threshold.4. A method according to claim 3 , wherein the unit is marked when the average number of iterations exceeds the threshold.5. A method according to claim 3 ,wherein one of a maximum latency and a maximum number of iterations is defined after which the decoding process for decoding a codeword is terminated at latest, andwherein the maximum latency or the maximum number of iterations respectively is increased when the average number of iterations exceeds the threshold.6. A method according to claim 1 ,wherein a maximum user bit error rate is defined with the user bit error rate being the ...

MEMORY MANAGEMENT IN A NON-VOLATILE SOLID STATE MEMORY DEVICE

A non-volatile solid state memory device and method for balancing write/erase cycles among blocks to level block usage. The non-volatile solid state memory device includes a memory unit having data stored therein and a controller with logic for programming the memory unit according to a monitored occurrence of an error during a read operation. The method includes monitoring an occurrence of an error during a read operation in a memory unit of the device and programming the memory unit according to the monitored occurrence of the error. 1. A non-volatile solid state memory device comprising:a memory unit having (i) stored data which is readable using a read operation;and (ii) an error-correcting code for correcting a potential error in said data; anda controller with a logic for programming said memory unit according to a monitored occurrence of said error during said read operation.2. The device according to claim 1 , wherein said read operation comprises monitoring the rate of errors.3. The device according to claim 1 , wherein said memory unit is subdivided into die claim 1 , each comprising at least one block claim 1 , wherein said read operation is carried out for each block in each die by maintaining a per-block counter of said occurrence of said error.4. The device according to claim 1 , wherein said read operation comprises monitoring an error in a window of a maximum of w consecutive read operations.5. The device according to claim 1 , wherein:said memory unit maintains a per-block counter of write-erase data; andsaid controller logic is carried out in response to both error monitored and write-erase data maintained.6. The device according to claim 1 , wherein said memory unit is subdivided into dice claim 1 , each die comprising at least one block.7. The device according to claim 6 , wherein said memory is configured to set apart a writable block of said memory unit claim 6 , and implement wear-leveling for a block that is distinct from said writable block ...

SEMICONDUCTOR STORAGE DEVICE

According to an embodiment, a semiconductor storage device includes an error correction processing unit that executes encoding process related data to be dispersedly written over a plurality of memory areas and decoding process related data dispersedly written over the plurality of memory areas. A transfer management unit determines whether or not data related to the data transfer request is a target of the error correction process and causes the error correction processing unit to execute the error correction process only with respect to the data determined as the target of the error correction process. 1. A semiconductor storage device , comprising:a non-volatile semiconductor memory including a plurality of memory areas which can be independently operated respectively;a plurality of memory interfaces that execute an access to data in the plurality of memory areas and output data transfer requests;a temporary memory buffer that temporarily stores data;a transfer management unit that manages a data transfer order between the temporary memory buffer and the plurality of memory interfaces, based on the contents of the data transfer requests from the plurality of memory interfaces;an error correction processing unit that executes encoding process related data to be dispersedly written over the plurality of memory areas and decoding process related data dispersedly written over the plurality of memory areas, using data that is being transferred between the temporary memory buffer and the plurality of memory interfaces; anda control unit that controls the plurality of memory interfaces such that data and an encoding result of the error correction process are dispersedly written over the plurality of memory areas, andwherein the transfer management unit determines whether or not data related to the data transfer request is a target of the error correction process and causes the error correction processing unit to execute the error correction process only with respect to ...

Storage device

A storage device is provided which includes a nonvolatile memory device and a controller configured to write meta information, indicating that a transfer of unit data is completed, in a buffer memory when the unit data is transferred to the buffer memory from the nonvolatile memory device.

MITIGATING INTER-CELL COUPLING EFFECTS IN NON VOLATILE MEMORY (NVM) CELLS

A system, computer readable medium and a method of operating a non volatile memory (NVM) array that comprises multiple NVM cells, the method comprises: receiving input data to be written to the non volatile memory; performing constraint coding on the input data to provide encoded data; wherein the constraint coding prevents the encoded data from comprising forbidden combinations of values; wherein the forbidden combinations of values are defined based on expected inter-cell coupling induced errors resulting from coupling between NVM cells; and writing the encoded data to the non volatile memory. 1. A method of operating a non volatile memory (NVM) array that comprises multiple NVM cells , the method comprises:receiving input data to be written to the non volatile memory;performing constraint coding on the input data to provide encoded data; wherein the constraint coding prevents the encoded data from comprising forbidden combinations of values; wherein the forbidden combinations of values are defined based on expected inter-cell coupling induced errors resulting from coupling between NVM cells; andwriting the encoded data to the non volatile memory.2. The method according to claim 1 , wherein the performing of the constraint coding comprises preventing the encoded data from comprising forbidden combinations of values based on magnitudes of inter-cell coupling induced errors; wherein a certain NVM cell is read to provide an estimate of a threshold voltage of the certain NVM cell; and wherein a magnitude of an inter-cell coupling induced error associated with a certain NVM cell represents a difference between (a) a desired threshold value of the certain NVM cell—assuming a lack of inter-cell coupling and (b) the estimate of the threshold voltage of the certain NVM cell.3. The method according to claim 2 , wherein the performing of the constraint coding comprises preventing the encoded data from comprising forbidden combination of values that are expected to cause an ...

ARCHITECTURE FOR STORAGE OF DATA ON NAND FLASH MEMORY

Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (AUs) and a parity AU. Error correction decoding is applied to each of the plurality of data AUs to produce a plurality of decoded data AUs. It is determined whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs. The plurality of decoded data AUs are output in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs. 1. A system for processing data from a storage medium , the system comprising:read circuitry configured to read a stripe of data stored on the storage medium, the stripe comprising a plurality of data allocation units (AUs) and a parity AU;decoding circuitry configured to apply error correction decoding to each of the plurality of data AUs to produce a plurality of decoded data AUs;parity check circuitry configured to determine whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs; anddata transfer circuitry configured to output the plurality of decoded data AUs in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs.2. The system of claim 1 , comprising data check circuitry configured to determine whether a data AU in the plurality of data AUs is unreadable.3. The system of claim 1 , wherein the read circuitry comprises a plurality of data transfer channels and wherein the read circuitry is configured to read a first portion of the stripe of data using a first data transfer channel in the plurality of data transfer channels and a second portion of the stripe of data using a second transfer channel in the plurality of data transfer channels.4. The system of claim 1 , wherein a data AU in the ...

SENDING FAILURE INFORMATION FROM A SOLID STATE DRIVE (SSD) TO A HOST DEVICE

A system, method, and computer program product are provided for sending failure information from a solid state drive (SSD) to a host device. In operation, an error is detected during an operation associated with a solid state drive. Additionally, a command is received for failure information from a host device. Further, the failure information is sent from the solid state drive to the host device, the failure information including failure information associated with the solid state drive. 1. (canceled)2. A method , comprising:detecting an error during an operation associated with a solid state drive (SSD);receiving from a host device a command to return failure information; andsending the failure information from the SSD to the host device in response to the receiving, the failure information comprising information relevant to the SSD being comprised of flash memory as a storage media.3. The method of claim 2 , wherein the information relevant to the SSD being comprised of flash memory as a storage media comprises a specific storage media location of the flash memory where the error occurred.4. The method of claim 3 , wherein the information relevant to the SSD being comprised of flash memory as a storage media further comprises information indicating whether the specific storage media location of the flash memory is associated with corrupt data.5. The method of claim 2 , wherein the information relevant to the SSD being comprised of flash memory as a storage media comprises information indicating that the SSD was unable to free up a storage media location of the flash memory in which to write data for the operation.6. The method of claim 2 , further comprising:wherein subsequent to a determination that the error is associated with a reoccurring event, the information relevant to the SSD being comprised of flash memory as a storage media comprises a persistent failure indication; andwherein prior to the determination, the information relevant to the SSD being ...

DATA ACCESSING METHOD FOR FLASH MEMORY MODULE

A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet. 1. A data accessing method , suitable for a flash memory module , and the data accessing method comprising:performing an error correction encoding for a data packet to be stored in the flash memory module to generate a sequence data code containing the data packet and a corresponding error correction code of the data packet, wherein the data packet comprises user data and system data related to the user data;converting the sequence data code into a non-sequence data code, wherein the user data, the system data, and the error correction code are dispersed in the non-sequence data code; andtransmitting the non-sequence data code to the flash memory module.2. The data accessing method as claimed in claim 1 , further comprising:reading the non-sequence data code from the flash memory module; andconverting the non-sequence data code for restoring the sequence data code; andperforming an error correction for the data packet within the sequence data code according to the error correction code within the sequence data code.3. The data accessing method as claimed in claim 1 , further comprising encrypting and decrypting the ...

FABRIC-BASED SOLID STATE DRIVE ARCHITECTURE

Embodiments of apparatus, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory. 1. A solid state drive comprising:a fabric coupled through a plurality of ports to one or more controllers, a host, one or more error correcting code (ECC) engines, a volatile memory, and one or more RAID engines, the one or more channel controllers coupled to a memory array where data is written and saved; anda scheduler coupled to the fabric and operable to schedule data and header to be transferred through the fabric, the plurality of ports asynchronously and optionally encoded and decoded while being transferred through the fabric,wherein the data and header are selectably decoupled from each other and are transferred to through the fabric independently of one another.2. The solid state drive of claim 1 , wherein the host is notified asynchronously of the completion of data transfer through the fabric.3. The solid state drive of claim 1 , wherein information transferred through the fabric includes control claim 1 , further wherein the data and control through the fabric are decoupled.4. The solid state drive of claim 1 , wherein the fabric is non- ...

MEMORY MANAGEMENT METHOD, STORAGE DEVICE, AND COMPUTER WITH THE SAME

A storage device includes a nonvolatile memory, a volatile memory, and a memory controller. The volatile memory includes a free block management table, and a worn block management table. If the number of free blocks is equal to or larger than a threshold value 1, and errors of the number of equal to or larger than a threshold value 2 but smaller than a threshold value 3 are included in the data read from the nonvolatile memory, the memory controller registers the block in the worn block management table as a worn block. If the number of free blocks becomes smaller than the threshold value 1, the memory controller registers the worn block registered in the worn block management table in the free block management table as the free block. 1. A memory management method in which a memory includes a plurality of blocks which is an erasure unit , and the plurality of blocks in the memory is divided into a plurality of data blocks , a plurality of free blocks , and a worn block in use ,conducting data check when reading data from the memory, continuously using the data block that retains the data as the data block if the number of errors in the read data is smaller than a threshold value 2, and discarding the data block that retains the data if the number of errors in the read data is equal to or larger than a threshold value 3, andtreating the data block that retains the data as the worn block if the number of free blocks is equal to or larger than a threshold value 1, and the errors equal to or larger than the threshold value 2 and smaller than the threshold value 3 are included in the read data, and using the worn block as the free block if the number of free blocks is lower than the threshold value 1, and the errors equal to or larger than the threshold value 3 are included in the read data.2. The memory management method according to claim 1 ,wherein the worn block in which the number of generated errors is smaller is preferentially used when the worn block is used as ...

Operating Method of Controller Controlling Nonvolatile Memory Device and Mapping Pattern Selecting Method of Selecting Mapping Pattern Mapping Polar Coded Code Word with Multi Bit Data of Nonvolatile Memory Device

An operating method of a nonvolatile memory device controller includes generating a code word through polar encoding of information bits, reading a mapping pattern, generating a repeated mapping pattern through iteration of the mapping pattern, and mapping each bit of the code word onto a specific bit of multi-bit data of the nonvolatile memory device, based upon the repeated mapping pattern.

Method and System For Error Correction in Flash Memory

A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

Zero-one balance management in a solid-state disk controller

An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

LOW-DENSITY PARITY-CHECK DECODER DISPARITY PREPROCESSING

Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has not reached a predetermined threshold, the media controller decodes the read data and provides the decoded data to the host device. 1. A method of error correcting , by a media controller , user data stored in a solid-state media , the method comprising:by the media controller:receiving a read operation from a host device coupled to the media controller, the read operation corresponding to one or more given read units of the solid-state media;reading data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages;determining if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has reached a predetermined threshold; decoding the read data; and', 'providing the decoded data to the host device., 'only if the disparity has not reached the predetermined threshold2. The method of claim 1 , further comprising: adjusting the one or more read threshold voltages of the solid-state media, based at least partly on the determined disparity;', 're-reading data for the corresponding read units from the solid-state media employing the adjusted one or more read threshold voltages;', 'determining if the disparity between an actual number of bits at a given logic level included in the re-read data and the ...

Resiliency to memory failures in computer systems

A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.

METHOD FOR PROCESSING A NON-VOLATILE MEMORY, IN PARTICULAR A MEMORY OF THE EEPROM TYPE, FOR THE STORAGE THEN THE EXTRACTION OF INFORMATION, AND CORRESPONDING MEMORY DEVICE

Method for processing a non-volatile memory designed to store words containing data bits and control bits allowing an error correction with an error correction code, the method comprising the storage of information in the memory plane comprising an operation for writing in the memory plane at least one digital word modified with respect to at least one initial digital word not having any erroneous bit, said at least one modified digital word containing a bit having a modified value with respect to the value of this bit in said at least one initial digital word, the other bits of the modified digital word having values identical to those of these same bits in the initial digital word, the position of the modified bit in said at least one modified digital word defining the value of the digital information. 1. A method for processing a non-volatile memory designed to store words containing data bits and control bits allowing error correction with an error correction code , the method comprising:storing information in a memory plane including writing in the memory plane at least one modified digital word modified with respect to at least one initial digital word not having any erroneous bit, said at least one modified digital word containing a bit having a modified value with respect to the value of a corresponding bit in the at least one initial digital word, other bits of the at least one modified digital word having values identical to corresponding bits in the initial digital word, the position of the modified bit in said at least one modified digital word defining a value of digital information.2. The method according to claim 1 , in which the bit of the at least one modified digital word having the modified value is a data bit and control bits of the at least one modified digital word have values determined based on the values of the data bits of said at least one initial digital word.3. The method according to claim 1 , in which storing information in the memory ...

INFORMATION PROCESSING APPARATUS, CONTROL METHOD

An information processing apparatus includes a memory, and a processor that executes a process in the memory. The process includes detecting a sign of a fault of a storage device that prohibits write access to a storage area of the storage device and permits read access to the storage area during a fault, and storing a copy of data to be written to the storage device as first copy data in the memory when the sign of a fault is detected. 1. An information processing apparatus comprising:a memory; anda processor that executes a process includingdetecting a sign of a fault of a storage device that prohibits write access to a storage area of the storage device and permits read access to the storage area during a fault, andstoring a copy of data to be written to the storage device as first copy data in the memory when the sign of a fault is detected.2. The information processing apparatus according to claim 1 ,wherein the process further includesdetecting occurrence of a fault in the storage device, andstoring a copy of the first copy data as second copy data in another storage device when the occurrence of a fault is detected.3. The information processing apparatus according to claim 2 ,wherein the process further includes outputting the first copy data in response to a request for reading data stored in the storage device when the occurrence of a fault is detected.4. The information processing apparatus according to claim 2 ,wherein the detecting occurrence of a fault includes detecting the occurrence of a fault based on a result of comparison between data read from the storage device and the first copy data.5. The information processing apparatus according to claim 2 ,wherein the process further includes creating data that is to be written to the storage device before the occurrence of the fault based on data read from the storage device and the second copy data.6. The information processing apparatus according to claim 1 ,wherein the process further includes ...

Apparatus, system, and method for managing solid-state storage reliability

A storage controller may be configured to assess the reliability of a solid-state storage medium. The storage controller may be further configured to project, forecast, and/or estimate storage reliability at a future time. The projection may be based on a currently reliability metric of the storage and a reliability model. The portions or sections of the solid-state storage media may be retired in response the projected reliability metric failing to satisfy a reliability threshold. The reliability threshold may be based on data correction and/or reconstruction characteristics. The projected reliability metrics of a plurality of erase blocks of a storage division may be combined, and one or more of the erase blocks may be retired in response to determining that the combined reliability metric projection fails to satisfy the reliability threshold.

Storage device including non-volatile memory device and repair method

Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page of the memory block.

METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE AND/OR RELIABILITY OF A SOLID-STATE DRIVE

A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page. 111-. (canceled)12. An apparatus comprising:one or more memory modules; anda controller coupled to the one or more memory modules to dynamically adjust a strength of an Error Correcting Code (ECC) of data to be stored in the one or memory modules.13. The apparatus of claim 12 , wherein the controller to dynamically adjust the strength of the ECC of the data to be stored in the one or more memory modules is to dynamically adjust the strength of the ECC of the data to be stored in the one or memory modules based on at least one of a Bit Error Rate (BER) associated with a location in the one or more memory modules that is to store the data and an erase count of a physical band of the one or more memory modules that is to store the data.14. The apparatus of claim 12 , wherein the data is to be partitioned into one or more data chunks to be stored in a memory page of the one or more memory modules claim 12 , and wherein the controller to dynamically adjust the strength of the ECC of the data to be stored in the one or memory modules is to:select one of the one or more data chunks;perform an exclusive OR (XOR) operation on all data chunks except the selected data chunks to obtain a XOR data chunk; andreplace the ...

Integrity of a data bus

A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An external controller generates error correction data in response to associated data to be transmitted. The error correction data is divided into multiple data packets and appended to the corresponding data for transmission over the data bus. The memory device can use the ECC data, if the feature is enabled, to attempt to correct the corresponding data and store both the corrected data and the ECC data.

Defect Management in Memory Systems

Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.

ERROR RECOVERY FOR FLASH MEMORY

A set of data associated with a page in flash storage is received. Error correction decoding is performed on the set of data; if event error correction decoding fails, it is determined whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. If it is determined the page is a MSB page, one or more MSB read thresholds are adjusted and the is re-read page using the adjusted MSB read threshold(s). If it is determined the page is a LSB page, one or more LSB read thresholds are adjusted and the page is re-read using the adjusted LSB read threshold(s). 1. A method , comprising:receiving a set of data associated with a page in flash storage;using an error correction decoder to perform error correction decoding on the set of data; and determining whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page;', adjusting one or more MSB read thresholds; and', 're-reading the page using the one or more adjusted MSB read thresholds; and, 'in the event it is determined the page is a MSB page, adjusting one or more LSB read thresholds; and', 're-reading the page using the one or more adjusted LSB read thresholds., 'in the event it is determined the page is a LSB page], 'in the event error correction decoding fails2. The method of claim 1 , further comprising: receiving a page number associated with the page claim 1 , wherein determining whether the page is a MSB page or a LSB page includes providing the page number to a lookup table and receiving a page type from the lookup table.3. The method of claim 1 , further comprising: in the event error correction decoding fails and it is determined the page is a MSB page claim 1 , using the error correction decoder to perform error correction decoding on a second set of data associated with re-reading the page using the one or more adjusted MSB read thresholds.4. The method of claim 3 , further comprising: in the event error correction decoding fails and it is determined ...

Split data error correction code circuits

Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.

Storage control apparatus and error correction method

A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group. In a case where the result of this determination is affirmative, the controller corrects the fixed value, in which there is an error, to a correct fixed value, and in a case where the number of errors included in the data group is equal to or less than the number of errors correctable by the guarantee code, uses the guarantee code to correct errors in the data group.

SOFT DECODING FOR QUANTIZIED CHANNEL

Systems, methods, and other embodiments associated with soft decoding for a quantized channel are described. According to one embodiment, a method includes repetitively controlling the soft decoder to attempt to decode the signal based, at least in part, on a reliability measure selected from a pre-determined collection of reliability measures. When the soft decoder fails to decode the signal, the method includes computing a new reliability measure and repetitively controlling the soft decoder to attempt to decode the signal based, at least in part, on the new reliability measure. When the soft decoder decodes the signal with the new reliability measure, the method includes adding the new reliability to the pre-determined collection of reliability measures. 1. An apparatus , comprising:a soft decoder configured to decode a signal received from a quantized channel based, at least in part, on one or more log likelihood ratios (LLRs);a reliability memory configured to store one or more known LLRs, wherein the known LLRs are stored in the reliability memory prior to the soft decoder receiving the signal to be decoded; and repetitively and selectively provide the soft decoder with known LLRs chosen from the reliability memory,', 'control the soft decoder to decode the signal, and', to compute one or more new LLRs;', 'to repetitively and selectively provide the soft decoder with the new LLRs; and', 'store the new LLRs as known LLRs in the reliability memory upon determining that the soft decoder successfully decoded the signal with the new LLRs., 'when the soft decoder fails to decode the signal with the known LLRs], 'a controller configured to2. The apparatus of claim 1 , wherein the one or more known LLRs stored in the reliability memory include one or more of claim 1 , a default LLR claim 1 , one or more LLRs previously used by the soft decoder to successfully decode a signal previously received from the quantized channel claim 1 , and one or more LLRs computed from ...

METHOD FOR READING DATA FROM BLOCK OF FLASH MEMORY AND ASSOCIATED MEMORY DEVICE

A method for reading data from a block of a flash memory is provided, where the block includes a plurality of pages and at least one parity page, each of the pages includes a plurality of sectors used for storing data and associated row parities, each of the sectors of the parity page is used to store a column parity. The method includes: reading data from a specific page of the pages; decoding the data of the specific page; and when a specific sector of the specific page fails to be decoded, sequentially reading all original data of the pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the original data of the pages and the parity page corresponding to the specific sector. 1. A method for reading data from a block of a flash memory , wherein the block comprises a plurality of pages and at least one parity page , each of the pages comprises a plurality of sectors used for storing data and associated row parities , and each of the sectors of the parity page is used to store a column parity which is generated in accordance with a sector of each of the pages; the method comprising:reading data from a specific page of the pages;decoding the data of the specific page; andwhen a specific sector of the specific page fails to be decoded successfully, sequentially reading all original data of the pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the original data of the pages and the parity page corresponding to the specific sector.2. The method of claim 1 , further comprising:after performing error correction upon the specific sector, decoding corrected data of the specific sector.3. The method of claim 1 , wherein the step of sequentially reading all original data of the pages and the parity page claim 1 , and performing error correction upon the specific sector according to the at least a portion of the original data of the pages and ...

INFORMATION PROCESSING SYSTEM, SHARED MEMORY DEVICE, AND METHOD FOR SAVING MEMORY DATA

An information processing system includes a plurality of clusters and a shared memory device having a shared memory shared by computer programs that operate on the clusters. The shared memory device includes an operating system (OS) stop detecting unit and a solid state drive (SSD) control unit. The OS stop detecting unit detects stop of computer programs that operate on all the clusters allocated to a certain storage area among storage areas of the shared memory shared by the clusters during an operation of the system. The SSD control unit saves, when the OS stop detecting unit detects the stop of the computer programs that operate on all the clusters allocated to the certain storage area, data stored in the certain storage area to a nonvolatile storage area. The information processing system can reduce time required to save data stored in the shared memory device when a power failure occurs. 1. An information processing system comprising:a plurality of information processing apparatuses; anda shared memory device including a shared memory shared by computer programs that operate on the information processing apparatuses, wherein a detecting unit that detects stop of computer programs that operate on all information processing apparatuses allocated to a certain storage area among storage areas of the shared memory shared by the information processing apparatuses during an operation of the information processing system; and', 'a saving unit that saves, when the detecting unit detects the stop of the computer programs that operate on all the information processing apparatuses allocated to the certain storage area, data stored in the certain storage area to a nonvolatile storage area., 'the shared memory device includes2. The information processing system according to claim 1 , wherein when a power failure occurs claim 1 , the saving unit supplies power to the shared memory device by a backup power supply and saves data stored in a storage area different from the ...

Memory block identified by group of logical block addresses, storage device with movable sectors, and methods

In an embodiment, only one sector of a plurality of sectors in a physical block of a plurality of physical blocks has a sector status location configured to store information that indicates a move status of an other sector of the plurality sectors of the physical block of the plurality of physical blocks, where the only one sector of the plurality of sectors in the physical block of the plurality of physical blocks is configured to store a sector of data in addition to the information that indicates the move status.

METHOD FOR MANAGING DATA STORED IN FLASH MEMORY AND ASSOCIATED MEMORY DEVICE AND CONTROLLER

A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result. 1. A method for managing data stored in a flash memory , wherein the flash memory comprises a plurality of blocks; the method comprising:providing a program list, wherein the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks;detecting quality of a first block of the plurality of blocks to generate a first detection result, wherein the first block is a programmed block that has an earliest write time in the program list; andreferring to the first detection result to determine whether to move contents of the first block to a blank block and delete the contents of the first block.2. The method of claim 1 , wherein the step of detecting the quality of the first block of the plurality of blocks to generate the first detection result comprises:detecting a bit error rate or a bit error amount of at least a portion of data of the first block to generate the first detection result.3. The method of claim 2 , wherein the step of determining whether to move the contents of the first block to the blank block and delete the contents of the first block comprises:when the first detection result indicates that the bit error rate or the bit error amount of the at least a portion of data of the first block is higher than a threshold, moving the contents of the ...

Mixed granularity higher-level redundancy for non-volatile memory

Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead.

CYCLING ENDURANCE EXTENDING FOR MEMORY CELLS OF A NON-VOLATILE MEMORY ARRAY

Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program. 1. A method comprising:determining a current program/erase cycle count for one or more memory cells of a non-volatile memory array;comparing the current program/erase cycle to a first target program/erase cycle count; andimplementing one or more cycling endurance extending schemes based on whether the current program/erase cycle count exceeds the first target program/erase cycle count or based on whether a failure trigger associated with the one or more memory cells has been reached, the one or more cycling endurance extending schemes to include at least one of a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program.2. The method of claim 1 , comprising the failure trigger to include a maximum bit error rate for the one or more memory cells and implementing the gradual read window expansion cycling endurance extending scheme based on the one or more memory cells having a measured bit error rate that exceeds the maximum bit error rate.3. The method of claim 1 , comprising the failure trigger to include a block fail trigger point for the one or more memory cells and implementing the gradual read window expansion cycling endurance extending scheme based on a memory block associated with the one or more memory cells reaching the block fail trigger point.4. The method of claim 1 , comprising the failure trigger to include a first block erase verify failure for a memory block associated with the one or more memory cells and implementing the erase blank check ...

FLASH MEMORY SYSTEM HAVING ABNORMAL WORDLINE DETECTOR AND ABNORMAL WORDLINE DETECTION METHOD

A flash memory controller for a flash memory system includes an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal. 1. A flash memory system comprising:a flash memory having a memory cell array, and a memory controller configured to control operation of the flash memory, wherein the memory controller comprises:an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data;an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate; anda control unit that controls operation of the flash memory in response to the abnormal wordline detection signal.2. The flash memory system of claim 1 , wherein the abnormal wordline detector operates in response to an enable signal provided by the control unit.3. The flash memory system of claim 1 , wherein the first page data is read from first flash memory cells connected to a first wordline claim 1 , and the second page data is read from second flash memory cells connected to a second wordline different from the first wordline.4. The flash memory system of claim 3 , wherein ...

ERROR CORRECTING FOR IMPROVING RELIABILITY BY COMBINATION OF STORAGE SYSTEM AND FLASH MEMORY DEVICE

According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an FET which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger. 1. A storage system comprising:a plurality of flash memory devices, each of the plurality of flash memory devices including a plurality of flash memories, each of the plurality of flash memories including a plurality of blocks, each of the plurality of blocks being a unit of data deletion and including a plurality of sectors, and each of the plurality of sectors being a unit of reading/writing data;a memory controller coupled to the plurality of flash memories and storing data with error correction codes in each of the plurality of sectors; anda storage controller configured to control the plurality of flash memory devices as a redundant configuration by storing data in each of the plurality of flash memory devices,wherein a first memory controller of a first flash memory device is configured to:read data stored in a sector of a block;detect an error contained in the read data,wherein if the error contained in the read data is correctable, the memory controller corrects the read data by decoding the error correcting codes and stores the corrected data into a sector of another block of the plurality of blocks, andwherein ...

DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE

Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed. 130-. (canceled)31. An apparatus comprising:memory controller logic to apply a first trim profile to a flash memory storage device; andthe first trim profile to dynamically cause a program-erase window to vary by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the flash memory storage device based on a current cycle count value,wherein the memory controller logic is to apply a second trim profile to the flash memory storage device in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition.32. The apparatus of claim 31 , wherein the occurrence of the failure condition is to be detected based on a ECC (Error Correcting Code) event.33. The apparatus of claim 31 , wherein the occurrence of the failure condition is to be detected based on a Block Fail Rate (BFR) value.34. The apparatus of claim 31 , further comprising a storage device or register to store the current cycle count value.35. The apparatus of claim 31 , wherein the flash memory storage device comprises a NAND storage device.36. The apparatus of claim 31 , wherein the program-erase window corresponds to a Multi Level Cell (MLC) window.37. The ...

Techniques Associated with a Read and Write Window Budget for a Two Level Memory System

Examples are disclosed for techniques associated with a read and write window budget for a two level memory (2LM) system. In some examples, a read and write window budget may be established for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory. Other examples are described and claimed. 1. A method comprising:establishing a read and write window budget for a two level memory (2LM) system including a first level memory and a second level memory, the read and write window budget including a combination of a first set of memory addresses and a second set of memory addresses of the second level memory, the first set of memory addresses associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses;receiving a write request to write data to the 2LM system; andcausing the data to be written to the second level memory based on the read and write window budget.2. The method of claim 1 , comprising the non-volatile memory cells associated with the first set of memory addresses to store the data via use of a foreground write process that includes no error correction.3. ...

FLASH MEMORY AND ACCESSING METHOD THEREOF

A flash memory and an accessing method thereof are provided. The accessing method includes steps of receiving a plurality of contiguous accessing commands, sequentially selecting a plurality of word lines corresponding to the accessing commands, and accessing a plurality of memory cells on each of the word lines according to the accessing commands sequentially. Here, any two of the contiguously selected word lines do not neighbor with each other. 1. An accessing method of a flash memory , comprising:receiving a plurality of contiguous accessing commands;sequentially selecting a plurality of word lines corresponding to the accessing commands and accessing a plurality of memory cells on each of the word lines according to each of the accessing commands sequentially,wherein any two of the contiguously selected word lines do not neighbor with each other.2. The accessing method as recited in claim 1 , wherein the step of sequentially selecting the word lines corresponding to the accessing commands and accessing the memory cells on each of the word lines according to each of the accessing commands sequentially comprises:dividing the flash memory into a plurality of memory groups;selecting one memory group as a selected memory group from the memory groups according to one of the accessing commands; andaccessing the memory cells on one of the word lines of the selected memory group,wherein each of the selected memory groups contiguously selected according to one of the contiguous accessing commands is different from one another.3. The accessing method as recited in claim 2 , wherein the step of selecting one memory group as the selected memory group from the memory groups according to one of the accessing commands comprises:selecting each of the selected memory groups respectively corresponding to one of the accessing commands according to a block selection order.4. The accessing method as recited in claim 3 , wherein the block selection order is determined by a number ...

METHOD AND APPARATUS FOR TREATMENT OF STATE CONFIDENCE DATA RETRIEVED FROM A NON-VOLATILE MEMORY ARRAY

An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed. 119-. (canceled)20. An apparatus , comprising:a controller to retrieve data from a non-volatile memory; andan error correction module operable on the controller to:read a memory cell of the memory at a first set of sense conditions comprising a multiplicity of sense conditions; andset a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.21. The apparatus of claim 20 , the non-volatile memory comprising a NAND memory claim 20 , and the error correction module operable on the controller to apply a low density parity check (LDPC) correction to determine bit errors in the non-volatile memory.22. The apparatus of claim 20 , the first set of bits corresponding to a result of application of multiple sense conditions that include the application of at least one sense reference voltage that lies between a first threshold voltage representing a nominal ...

ERROR ESTIMATION MODULE AND ESTIMATION METHOD THEREOF FOR FLASH MEMORY

The present invention relates to the field of data storage, and more particularly to an estimation technology in an error correction process of a flash memory. The present invention provides an error estimation module and an error estimation method thereof for a flash memory. The estimation module mainly includes a timer, a quantification index table, a storage page table, and an error index table. The error estimation method of a flash memory includes: creating rewriting and programming error a priori data, and estimating an error rate of the flash memory by using special physical signals in a flash memory device to provide proper error estimation for an error correction algorithm of the flash memory. The present invention is applicable to a solid-state hard disk controller, a flash memory controller, and the like, where the flash memory device is used as a storage medium, so that the reliability of the flash memory device is improved. 1. An error estimation module for a flash memory , mainly comprising a timer , a quantification index table , a storage page table , and an error index table , wherein ,the timer is used to record a programming time or an erasing time of the flash memory, wherein the programming time or the erasing time collected by the timer serves as an input as a quantification index;the quantification index table is used to record a mapping between a programming level and a programming time and a mapping between an erasing level and an erasing time, wherein the erasing level represents a life state of a flash memory block corresponding to a physical address, and the programming level represents a life state of a page inside the flash memory block;the storage page table comprises several continuous storage units, wherein each continuous storage unit is used to record an erasing level and a programming level of one flash memory block, the erasing level of the flash memory block is saved at the beginning of the continuous storage unit, and the ...

BIT ERROR RATE BASED WEAR LEVELING FOR SOLID STATE DRIVE MEMORY

According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count. 1. A system for bit error rate (BER) based wear leveling in a solid state drive (SSD) , the system comprising:a program/erase (PE) cycle adjustment module and a plurality of blocks comprising solid state memory, the system configured to perform a method comprising:determining a block-level BER value for a block of the plurality of blocks;incrementing or decrementing an adjusted PE cycle count for the block based on the block-level BER value by the PE cycle adjustment module; andperforming wear leveling in the SSD based on the adjusted PE cycle count.2. The system of claim 1 , wherein determining the block-level BER statistics for the block comprises collecting error correcting code (ECC) data from one or more read events of one or more pages in the block claim 1 , and wherein determining the adjusted PE cycle count for the block based on the block-level BER value is preformed in response to an erase event in the block.3. The system of claim 1 , wherein determining the adjusted PE cycle count for the block based on the block-level BER value comprises comparing the block-level BER value and the adjusted PE cycle count of the block to a lookup table claim 1 , wherein the lookup table comprises a plurality of ranges of expected PE cycle count values claim 1 , each of the plurality of ranges of expected PE cycle count values being mapped to a respective BER value.4. The system of claim 3 , wherein the lookup table is modified based on observed actual PE cycle count values received from the plurality of blocks by the PE cycle adjustment module.5. The system of claim 3 , wherein the adjusted PE ...

MEMORY DEVICE WITH PARITY DATA SYSTEM AND METHOD

Apparatus and methods are disclosed, including a memory device with circuitry to generate an amount of parity data, and to store at least a portion of the parity data within a dummy data location. Selected examples include storing meta data with the parity data to further facilitate data recovery. Selected examples include a memory device with circuitry to generate one or more parity data index entries that map protected data to parity data. 1. A memory device , comprising:at least one flash memory storage;circuitry in the memory device to write an amount of dummy data in the flash memory storage;circuitry in the memory device to generate parity data for an amount of protected data;circuitry in the memory device to store the parity data in a parity entry that is included as at least part of the dummy data.2. The memory device of claim 1 , wherein the circuitry in the memory device to write an amount of dummy data includes circuitry to write the dummy data along with partial page data to make a full page in the flash memory storage.3. The memory device of claim 1 , further including circuitry in the memory device to write a full page of dummy data that includes parity data.4. The memory device of claim 1 , wherein the parity entry includes a protected data location header.5. The memory device of claim 1 , further including a buffer claim 1 , and wherein the circuitry in the memory device to generate parity data is configured to store an amount of parity data in the buffer at a first time claim 1 , and wherein the circuitry in the memory device to store the parity data is configured to write the amount of parity data from the buffer to at least part of the dummy data at a second time different from the first time.6. The memory device of claim 1 , further including circuitry configured to write a parity data index block cataloging a location of one or more parity entries.7. The memory device of claim 1 , further including circuitry configured to stitch together ...

METHOD OF EQUALIZING BIT ERROR RATES OF MEMORY DEVICE

Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER. 167-. (canceled)68. A memory system comprising:a memory device including a control circuit and a memory cell array that includes a plurality of memory cells disposed at intersections between a plurality of word lines and a plurality of bit lines; anda memory controller configured to control the memory device and including an error correction code (ECC) circuit that is configured to perform an ECC encoding on write data and an ECC decoding on read data,wherein the ECC circuit is configured to perform the ECC encoding on the write data to generate a codeword including a first sector and a second sector, and to provide the codeword to the memory device,the control circuit is configured to perform an ECC interleaving operation on the codeword such that the first sector is written to a first portion of the memory cell array and the second sector is written to a second portion of the memory cell array, andthe first portion of the memory cell array has a first bit error rate (BER) and the second portion of the memory cell array has a second bit error rate (BER) that is lower than the first BER.69. The memory system of claim 68 , wherein the first portion of the memory cell array includes memory cells connected to a first word line among the plurality of word ...

Machine Learning For Temperature Compensation

A method of temperature compensation to read a flash memory device includes determining a state of the flash memory device. An action is selected with a maximum Q-value from a Q-table for the current state during exploitation. A read operation of a code word from the flash memory device is conducted using one or more parameters according to the selected action. The code word is decoded with an error correction code (ECC) process. 1. A method of temperature compensation to read a flash memory device , comprising:determining a current state of the flash memory device;selecting an action with a maximum Q-value from a Q-table for the current state during exploitation, the Q-table comprising a plurality of actions for each of a plurality of states of the flash memory device;conducting a read operation of a code word from the flash memory device using one or more parameters according to the selected action; anddecoding the code word with an error correction code (ECC) process.2. The method of claim 1 , further comprising selecting an action with a non-maximum Q-value using a probability of p=1−ε from the Q-table during exploration.3. The method of claim 1 , further comprising:determining an estimated BER of the code word from the read operation, wherein the decoding the code word with the ECC process occurs if the estimated BER is at or below a decoding limit; andselecting another action from the Q-table for the current state to conducted another read operation of the code word from the flash memory device using one or more parameters according to the selected another action.4. The method of claim 1 , wherein determining the current state of the flash memory device is a previous read access state in a sequential or a random read operation of the flash memory device claim 1 , wherein the selecting the action determines a next state of the flash memory device.5. The method of claim 1 , wherein a triggering event selected from a group consisting of a temperature difference ...

VARIABLE CODE RATE SOLID-STATE DRIVE

An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data. 1. A method for managing reliability of a solid-state storage , comprising:reading encoded data stored in the solid-state storage;decoding the encoded data accessed to provide decoded data as soft decisions representing probabilities of the decoded data;assessing the probabilities of the decoded data; andadjusting a code rate of an encoder and a decoder responsive to the assessment.2. The method according to claim 1 , wherein the code rate is for a linear error correcting code.3. The method according to claim 2 , wherein the solid-state storage comprises memory cells selected from a group consisting of multi-level cells claim 2 , binary cells claim 2 , triple-level cells claim 2 , and single-level cells for storage of the encoded data.4. The method according to claim 2 , wherein:the encoder is a Low-Density Parity-Check encoder; andthe decoder is an LDPC decoder.5. The method according to claim 1 , further comprising:encoding input data with the encoder to provide the encoded data; andwriting the encoded data to the solid-state storage.6. The method according to claim 5 , wherein the accessing comprises reading a predefined amount of the encoded data from the solid-state storage.7. The method according to claim 6 , wherein the ...

ERROR CORRECTION BASED ON THERMAL PROFILE OF FLASH MEMORY DEVICE

Systems and methods to manage a memory device by executing program code to determine a temperature profile associated with a region of the memory device. The temperature profile may be one of many temperature profiles each associated with a respective region of the memory device. A correction capability may be determined based on the thermal profile and an error in the memory region may be corrected using the determined correction capability. 113.-. (canceled)14. An apparatus comprising:a memory device storing data and program code;a temperature sensor configured to sense a temperature of the memory device; and determine a temperature profile associated with a region of the memory device, wherein the temperature profile is one of a plurality of temperature profiles each associated with a respective region of a plurality of regions of the memory device;', 'determine a correction capability based on the thermal profile; and', 'correct an error in the memory region using the determined correction capability., 'a controller in communication with the memory and the temperature sensor, the controller configured execute the program code to15. The apparatus of claim 14 , further comprising a logical-to-physical address table maintaining information associating the plurality of temperature profiles with the plurality of regions.16. The apparatus of claim 14 , wherein the controller is further configured to generate a bias vector indicative of the correction capability.17. The apparatus of claim 14 , wherein the controller is further configured to associate the plurality of regions with a plurality of correction capabilities.18. The apparatus of claim 14 , wherein the controller is further configured to set a plurality of set points based on a plurality of changing temperature bounds.19. The apparatus of claim 14 , wherein the thermal profile is determined at runtime claim 14 , and wherein the correction capability is set at system startup to a highest supported error- ...

CONTROLLER FOR A SOLID-STATE DRIVE, AND RELATED SOLID-STATE DRIVE

A controller for a solid state drive is proposed. The solid state drive comprises memory cells each one for storing a symbol among a plurality of possible symbols that the memory cell is designed to store. The controller comprises: 1. A controller for a solid state drive comprising memory cells each one for storing a symbol among a plurality of possible symbols that the memory cell is designed to store , wherein the controller comprises:an encoding unit for encoding information bits into encoded bits;a mapping unit for mapping the encoded bits into said symbols, wherein said symbols are determined based on a plurality of allowed symbols that the memory cells are allowed to store, said plurality of allowed symbols being a subset of the plurality of the possible symbols such that a plurality of forbidden symbols not allowed to be stored in the memory cells are defined among the plurality of the possible symbols,a demapping unit for demapping read symbols and for providing an indication of the reliability of the read symbols based on said plurality of forbidden symbols, anda soft decoding unit for soft decoding the read symbols according to said indication of the reliability of the read symbols thereby obtaining said information bits.2. The controller according to claim 1 , wherein said indication of the reliability of the read symbols comprises claim 1 , for each read symbol equal to a forbidden symbol of said plurality of forbidden symbols claim 1 , an indication that the read symbol read from a memory cell is different from an original symbol originally stored in that memory cell.3. The controller according to claim 2 , wherein said indication of the reliability of the read symbols further comprises claim 2 , for each read symbol equal to a forbidden symbol of said plurality of forbidden symbols claim 2 , an indication of the probability that the original symbol is one of the plurality of the allowed symbols.4. The controller according to claim 3 , wherein the ...

SYSTEMS AND METHODS FOR PROVIDING ERROR CODE DETECTION USING NON-POWER-OF-TWO FLASH CELL MAPPING

Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array. 1. A method providing error detection or correction with flash cell mapping , the method comprising:generating raw page data for a physical page in a main array of a flash memory device, the raw page data comprising less than a capacity of the physical page using a non-power-of-two flash cell mapping;generating one or more parity bits for the raw page data using an error detection or correction scheme; andstoring the raw page data and the one or more parity bits in the physical page in the main array.2. The method of claim 1 , wherein the error detection or correction scheme comprises an error code correction (ECC) algorithm.3. The method of claim 2 , wherein the one or more parity bits generated by the ECC algorithm comprises an inner ECC generated for the raw page data and an outer ECC generated for a combination of the raw page data and the inner ECC.4. The method of claim 3 , wherein the inner ECC is stored in the physical page with the raw page data claim 3 , and the outer ECC is stored in a spare array associated with the physical page.5. The method of claim 2 , further comprising concatenating a plurality of ECC codes generated by the ECC algorithm.6. The method of claim 1 , wherein the non-power-of-two flash cell mapping comprises a quinary mapping scheme for transforming binary data in one or more logical pages to a plurality of quinary bits.7. The method of claim 6 , wherein the ...

Memory array and link error correction in a low power memory sub-system

A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

Flash memory system and operating method thereof

An operation method of a flash memory system includes: obtaining first syndrome values to a codeword; obtaining locations of errors and the number of the locations of errors based on the first syndrome values; error-correcting the codeword by flipping bit values of error bits of the codeword based on the locations of errors to generate an error-corrected codeword; obtaining second syndrome values to the error-corrected codeword; determining whether an error is found in the error-corrected codeword based on the second syndrome values; changing the first syndrome values when it is determined that no error is found in the error-corrected codeword; and restoring the error-corrected codeword to the codeword by re-flipping the flipped bit values when it is determined that an error is found in the error-corrected codeword.

MEMORY DEVICE WITH DIFFERENT PARITY REGIONS

The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode. 1. A controller for a semiconductor memory device , the device including a memory cell array including a plurality of pages , the controller comprising:a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information; andan error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.2. The controller of claim 1 ,wherein the parity-related information includes information about sizes of parity-data regions, andwherein each of the parity-data regions corresponds to one of the plurality of pages.3. The controller of claim 1 ,wherein the parity-related information includes information about the plurality of operation modes, andwherein each of the plurality of operation modes corresponds to one of the plurality of pages.4. The controller of claim 1 , further comprising a storage module suitable for storing therein the parity-related information.5. The controller of claim 1 , wherein the plurality of operation modes respectively correspond to numbers of bits of the parity-data for each of the plurality of pages.6. The ...

SYSTEMS AND METHODS FOR ENHANCED DATA RECOVERY IN A SOLID STATE MEMORY SYSTEM

Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location. 1. A data processing system , the system comprising:a solid state memory device; and a soft information calculation circuit operable to calculate soft information indicating a probability that one or more elements of the data set derived from the solid state memory device represent data originally stored to the solid state memory device; and', 'a data decoding circuit operable to apply a data decoding algorithm to the data set derived from the solid state memory device guided by the soft information., 'a data processing circuit to access a data set from the solid state memory device, the data processing circuit including2. The data processing system of claim 1 , wherein the data decoding algorithm is a low density parity check decoding algorithm.3. The data processing system of claim 1 , wherein the data processing circuit further comprises:a limited location re-read request circuit operable to identify a subset of elements of the data set derived from the solid state memory device exhibiting an increased likelihood of error, wherein identifying the subset of elements of the data set is based at least in part on selecting one or more locations from the subset of elements in the data set exhibiting one or more highest voltage variances from a first location to a subsequent location.4. The data processing system of claim 3 , wherein identifying the subset of elements of the data set derived from the solid state memory device exhibiting an increased likelihood of error is based at least ...

STORAGE DEVICE AND READ METHODS THEREOF

A read method of a storage device includes performing a first read operation on a nonvolatile memory device based on a time stamp table storing a program time and a time-read level look-up table indicating a read level shift due to a program lapsed time. A determination is made whether to adjust the time-read level look-up table based on a result of the first read operation. As a consequence of determining to adjust the time-read level look-up table, adjusting the time-read level look-up table through a valley search operation and performing a second read operation on the nonvolatile memory device based on the time stamp table and the adjusted time-read level look-up table. 1. A read method of a storage device which includes at least one nonvolatile memory device including a plurality of strings formed of pillars penetrating word lines stacked between bit lines and a common source line in a direction perpendicular to a substrate; and a memory controller to control the at least one nonvolatile memory device , the read method comprising:performing a first read operation on the at least one nonvolatile memory device based on a time stamp table storing program time and a time-read level look-up table indicating a read level shift due a program elapsed time;determining whether to adjust the time-read level look-up table based on a result of the first read operation;as a consequence of determining that an adjustment of the time-read level look-up table is required, adjusting the time-read level look-up table through a valley search operation; andperforming a second read operation on the at least one nonvolatile memory device based on the time stamp table and the adjusted time-read level look-up table.2. The read method of claim 1 , wherein an adjustment of the time-read level look-up table is determined to be required when errors of data read during the first read operation are uncorrectable.3. The read method of claim 1 , wherein a read voltage for each of the first and ...

Controller device with retransmission upon error

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

METHODS AND APPARATUS TO READ FROM A NONVOLATILE MEMORY DEVICE

A disclosed apparatus to access a nonvolatile memory includes a physical geometry selector to select a first assumed physical geometry of a nonvolatile memory from among a plurality of assumed physical geometries supported by a memory controller, an information supplier to supply information about the first physical geometry to a set of registers, and a boot up controller to cause the memory controller to access data in the nonvolatile memory. The memory controller to access data in the nonvolatile memory uses the information supplied to the set of registers. Example disclosed apparatus further include a feedback input to receive feedback from the memory controller. 2. An apparatus as defined in claim 1 , wherein the feedback input receives feedback from the memory controller indicating whether accessing the data in the nonvolatile memory resulted in an error.3. An apparatus as defined in claim 2 , wherein the physical geometry selector is further to select a second assumed physical geometry of the nonvolatile memory from among the plurality of assumed physical geometries when the feedback input receives feedback indicating that accessing the data resulted in an error.4. An apparatus as defined in claim 1 , further including a lookup table containing the information identifying the plurality of assumed physical geometries.5. An apparatus as defined in claim 4 , wherein the information identifying the plurality of assumed physical geometries includes claim 4 , for corresponding ones of the assumed physical geometries claim 4 , an error correction code correction level and an error correction code byte offset claim 4 , a page size claim 4 , a main area size and a spare area size.6. An apparatus as defined in claim 1 , wherein the nonvolatile memory is a NAND flash memory and the memory controller is a NAND flash memory controller.7. At least one tangible machine readable medium comprising instructions claim 1 , the instructions claim 1 , when executed claim 1 , to ...

NAND TEMPERATURE-AWARE OPERATIONS

Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written. 1. A device for NAND temperature-aware operations , the device comprising:a NAND array including a NAND component; and receive a command to write data to the NAND component;', 'obtain a temperature corresponding to the NAND component in response to receipt of the command; and', 'execute the command to write data to the NAND component, wherein to execute the command, the controller writes the temperature into a management portion of the NAND device that is separate from a user portion of the NAND device to which the data is written., 'a controller configured to2. The device of claim 1 , wherein the controller is configured to read the data from the NAND component and to read the temperature in response to a read error metric being over a threshold claim 1 , the read error metric computed by the controller for the NAND component.3. The device of claim 2 , wherein claim 2 , to read the data and the temperature claim 2 , the controller is configured to:compare the temperature to a second threshold; andperform a cross-temperature read-recovery operation in response to the temperature being beyond the threshold.4. The device of claim 1 , wherein the management portion is on the NAND component.5. The device of claim 4 , wherein the NAND component is a page.6. The device of claim 5 , wherein the management portion is flag bytes of the page.7. The device of claim 6 , wherein the management portion is programmed using a single-level cell (SLC) encoding claim 6 ...

ERROR CORRECTION CODE EVENT DETECTION

Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node. 1. A method of operating an electronic memory apparatus , comprising:identifying a codeword from a read operation of the electronic memory apparatus;detecting an error in the codeword based at least in part on an error correction code (ECC) operation associated with the codeword; andtransmitting a signal indicative of the error detection to a node of the electronic memory apparatus.2. The method of claim 1 , wherein the error comprises a one bit error or a two bit error.3. The method of claim 1 , further comprising:selecting a type of error to be detected in response to a user input.4. The method of claim 3 , wherein the type of error comprises a one bit error or a two bit error claim 3 , or both.5. The method of claim 1 , further comprising:enabling an error detection mode, wherein the error in the codeword is detected based at least in part on enabling the error detection mode.6. The method of claim 1 , wherein the read operation comprises:applying a first voltage to a set of memory cells associated with the codeword; anddetermining a voltage or current corresponding to each memory cell of the set of memory cells based at least in part on the application of the first voltage, wherein the codeword is identified based at least in part on the determination of the voltages or currents corresponding to each memory cell.7. The method of claim 1 , further comprising:storing an indication of the detected ...

Low-Overhead Mechanism to Detect Address Faults in ECC-Protected Memories

Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory. 1. An apparatus comprising:a memory array;an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; andan ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values;wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory array.2. The apparatus of claim 1 , further comprising a first bus for address values claim 1 , a second bus for data values claim 1 , and a third bus for ECC values claim 1 , wherein the ECC encoder and ECC decoder are to read values from both the first bus and the second bus.3. The apparatus of claim 1 , wherein the ECC decoder is to generate an error location vector to indicate a bit position of each detected error in the address value.4. The apparatus of claim 4 , wherein the apparatus is to generate an address fault signal based on a value of the error location vector.5. The apparatus of claim 1 , further comprising an address scrubber to read data from a plurality of addresses of the memory array to detect errors in addresses for the memory array based on the ECC values claim 1 , address values claim 1 , and data values stored in the memory array.6. The apparatus of claim 1 , wherein the ...

LINKED-LIST INTERLINEATION OF DATA

In one embodiment, linked-list interlineation of data in accordance with the present description includes inserting a subsequent set of data in a linked-list data structure within an initial data structure. The linked-list data structure includes a sequence of linked-list entries interspersed with the initial data of the initial data structure. To insert the subsequent data, a pattern of data within the initial data structure is replaced with data of the subsequent set of data in a sequence of linked-list entries of the linked-list data structure. Other aspects are described herein. 1. An apparatus , comprising:a memory having memory locations configured to store data in data structures; and store a subsequent set of data in a linked-list data structure within the initial data structure, the linked-list data structure having a subset of the initial set of memory locations and a sequence of linked-list entries stored in the subset of the initial set of memory locations, wherein the linked-list interlineation logic includes pattern recognition logic configured to identify a subset of memory locations within the initial set of memory locations of the initial data structure, as a function of at least the first pattern of data wherein the memory locations of the subset of memory locations are interspersed with other memory locations of the initial set of memory locations; and, data replacement logic configured to', 'replace the first pattern of data stored in a memory location of the subset of memory locations with data of the subsequent set of data, to store in the subset of memory locations, the subsequent set of data in a linked-list data structure in a sequence of linked-list entries of the linked-list data structure., 'memory control logic configured to control input/output operations to the memory wherein the memory control logic is further configured to store an initial set of data which includes at least a first pattern of data, in an initial data structure ...

Methods for Error Correction with Resistive Change Element Arrays

Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data. 1. A method of error correction for a resistive change element array comprising: a plurality of resistive change elements, each of said plurality of resistive change elements capable of adjusting between at least two non-volatile resistive states responsive to applied electrical stimuli, wherein one of said non-volatile resistive states is an initialized state;', 'wherein said plurality of resistive change elements within said array are organized into a plurality of subsections, each of said subsections including a plurality of resistive change elements assigned as data cells and at least one resistive change element assigned as a flag cell, said data cells further organized into a plurality of data subsets, each of said data subsets having at least two data cells;, 'providing a resistive change element array, said resistive change element array comprisingreceiving input data to be programmed into at least one of said subsections;initializing all of said data cells and said flag cells within at least one of said subsections into said initialized state;reading said data cells within said at least one subsection to ...

FAIL INFORMATION CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME, AND FAIL INFORMATION CONTROL METHOD OF SEMICONDUCTOR APPARATUS

A fail information control circuit may include: a comparison circuit configured to generate a comparison result signal by comparing read data and write data; a fail bit discrimination circuit configured to generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value and a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal; and a fail bit counter configured to generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal. 1. A fail information control circuit comprising:a comparison circuit configured to generate a comparison result signal by comparing read data and write data; generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value; and', 'generate a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal; and, 'a fail bit discrimination circuit configured toa fail bit counter configured to generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal.2. The fail information control circuit according to claim 1 , further comprising: output, as a first counting correction signal, a signal obtained by resetting levels of remaining bits, except for a most significant bit among high level bits of the first counting signal, to a low level; and', 'output, as a second counting correction signal, a signal obtained by resetting levels of remaining bits, except for a most significant bit among high level bits of the second counting signal, to a low level., 'a counting signal correction circuit configured to3. The fail information control circuit ...

SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, MEMORY SYSTEM, AND OPERATION METHOD THEREOF

Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed. 1. An operation method of a semiconductor memory device comprising:during a read operation of the semiconductor memory device,receiving first data and a parity output from selected memory cells of a memory cell array;generating a syndrome based on the first data and the parity;generating second data and a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome; andoutputting the second data and the DSF to an external device outside of the semiconductor memory device,wherein a number of bits of the first data is the same as a number of bits of the second data.2. The operation method of the semiconductor memory device of claim 1 , further comprising:during a write operation of the semiconductor memory device,receiving third data from the external device;generating the parity; andoutputting fourth data and the parity to the selected memory cells,wherein a number of bits of the third data is the same as a number of bits of the fourth data.3. The operation method of the semiconductor memory device of claim 2 , wherein the generating of the parity comprises:performing an exclusive OR (XOR) operation on each of row vectors of a first H matrix and on the third data and then perform a modulo 2 operation thereon to generate the parity, ...

SYSTEMS AND METHODS FOR ULTRA FAST ECC WITH PARITY

Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels. 1. A method for storing and retrieving data stored in a non-volatile storage device , comprising:transmitting M+F data pieces to M+F channels of the non-volatile storage device for each of the M+F data pieces to be stored in a different channel of the M+F channels, wherein the M+F data pieces include M error correction code (ECC) codewords generated from M data chunks and F ECC parity block(s) generated from F parity block(s), and M is an integer larger than one and F is an integer equal to or larger than one;reading M data pieces in parallel from M channels, wherein the M data pieces include a subset of the M ECC codewords and at least one of the F ECC parity block(s);decoding the M data pieces to generate a subset of the M data chunks and at least one of the F parity block(s); andobtaining at least one data chunk of the M data chunks that is not included in the subset of the M data chunks by at least one parity operation on the at least one of F parity block(s) and the subset of the M data chunks.2. The method of claim 1 , wherein each channel of the non-volatile storage device comprises a plurality of dies claim 1 , and each of the M+F data pieces is stored in a different die of a different channel.3. The method of claim 1 , wherein the non-volatile storage device is one of: a NAND flash memory claim 1 , a NOR flash memory claim 1 , a magnetoresistive random Access Memory (MRAM) claim 1 ...

Storage drive error-correcting code-assisted scrubbing for dynamic random-access memory retention time handling

encoding, at the storage device, the data with a second encoding to generate a second parity portion; aligning, by the storage device, the data, the first parity portion, and the second parity portion according to a predefined alignment scheme, the aligning generating aligned data; and writing, by the storage device, the aligned data to the memory device.

STAGGERED GARBAGE COLLECTION UNIT (GCU) ALLOCATION ACROSS DIES

Apparatus and method for managing a non-volatile memory (NVM) such as a flash memory in a solid-state drive (SSD). In some embodiments, the NVM is arranged as a plurality of semiconductor memory dies coupled to a controller circuit using a plurality of channels. The controller circuit divides the plurality of dies into a succession of garbage collection units (GCUs). Each GCU is independently erasable and allocatable for storage of user data. The GCUs are staggered so that each GCU is formed from a different subset of the dies in the NVM. In further embodiments, the dies are arranged into NVM sets in accordance with the NVMe (Non-Volatile Memory Express) specification with each NVM set addressable by a different user for storage of data in a separate set of staggered GCUs. 1. A method comprising:providing a non-volatile memory (NVM) having a plurality of semiconductor memory dies coupled to a controller circuit using a plurality of channels; anddividing the plurality of dies into a succession of garbage collection units (GCUs) each independently erasable and allocatable for storage of user data, each GCU in the succession of GCUs formed from a different subset of the dies.2. The method of claim 1 , wherein a total N dies are present in the NVM claim 1 , wherein each GCU spans less than all of the N dies claim 1 , and each die nominally shares a portion of a common number of the GCUs.3. The method of claim 1 , wherein a first GCU is formed from a first subset of the dies claim 1 , and each of a succession of additional GCUs is formed by removing a die from the first subset of dies and adding a die to the first subset of dies.4. The method of claim 1 , wherein each GCU is formed by assigning at least one erasure block from each of the dies in the subset of dies that form the GCU.5. The method of claim 4 , wherein each die has at least two planes that support simultaneous access commands to an erasure block in each plane claim 4 , and wherein at least one erasure block ...

DETERMINING SOFT DATA

The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell. 120-. (canceled)21. An apparatus , comprising:an array of memory cells; anda controller configured to operate sense circuitry to determine soft data associated with a data state of a memory cell of the array by applying a single stepped sensing signal to the memory cell.22. The apparatus of claim 21 , wherein the soft data associated with the data state of the memory cell includes at least two soft data values.23. The apparatus of claim 21 , wherein the controller is configured to operate the sense circuitry to apply the single stepped sensing signal to the memory cell as part of a single stepped sense operation.24. The apparatus of claim 21 , wherein the controller is configured to operate the sense circuitry to determine the data state of the memory cell by applying the single stepped sensing signal to the memory cell.25. The apparatus of claim 21 , wherein the controller includes an error correction component configured to correct an error associated with the data state of the memory cell using the determined soft data.26. The apparatus of claim 21 , wherein the soft data associated with the data state of the memory cell indicates:a location of a threshold voltage associated with the memory cell within a threshold voltage distribution associated with the data state of the memory cell; anda probability of whether the threshold voltage associated with the memory cell corresponds to the data state of the memory cell.27. The apparatus of claim 21 , wherein the memory cell is a multilevel memory cell.28. A method for operating memory claim 21 , comprising:determining soft data associated with a data state of a memory cell by applying a single stepped sensing ...

Multi-Device Storage System with Hosted Services on Peer Storage Devices

Example multi-device storage systems, storage devices, and methods provide hosted services on peer storage devices. Storage devices include local memory resources, such as operating memory, remotely addressable memory, or logical mapping memory, and compute resources, such as a processor or coding engine. Each storage device is configured to communicate with a plurality of peer storage devices over an interconnect fabric. The storage devices identify requested hosted services from service host requests received through the interconnect fabric. The storage devices store a plurality of hosted services are to enable access to local memory resources and local compute resources for data management operations for the plurality of peer storage devices. 1. A storage device , comprising:a processor;an operating memory;a remotely addressable memory;a fabric interface configured to communicate with a plurality of peer storage devices over an interconnect fabric between the fabric interface and the plurality of peer storage devices;a service request handler stored in the operating memory and executable by the processor to identify a requested hosted service from a service host request received through the fabric interface; and stored in the operating memory and executable by the processor to access local memory resources and local compute resources for data management operations for the plurality of peer storage devices; and', 'including the requested hosted service., 'a plurality of hosted services2. The storage device of claim 1 , wherein:the remotely addressable memory is configured to allocate a transfer buffer space in the remotely addressable memory; andthe requested hosted service includes a data transfer between the transfer buffer space and at least one of the plurality of peer storage devices.3. The storage device of claim 2 , further comprising an erasure coding engine claim 2 , wherein the requested hosted service further comprises an erasure coding operation using ...

ASYMMETRIC LLR GENERATION USING ASSIST-READ

A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages. 1070. A method of operating a storage system , the storage system including memory cells and a memory controller coupled to the memory cells for controlling operations of the memory cells , wherein each memory cell is a 3-bit tri-level cell (TLC) , wherein the memory cells are arranged in LSB (least significant bit) pages , CSB (center significant bit) pages , and , MSB (most significant bit) pages , wherein each of the memory cells comprises eight programmed voltage (PV) levels (PV-PV) , wherein PV is an erased state , the method comprising:{'b': 1', '7', '11', '5', '2', '4', '6', '3', '7, 'performing a read operation on the memory cells in response to a read command from a host, wherein performing the soft read operation comprises reading the memory cells using seven read threshold values (Vr-Vr) to determine the programmed voltages of the memory cells, including using threshold values Vr and Vr for MSB, using threshold values Vr, Vr, and Vr for CSB, and using threshold values Vr and Vr for LSB;'}determining initial LLR (log likelihood ratio) values for the memory cells based ...

MEMORY MODULE, ERROR CORRECTION METHOD OF MEMORY CONTROLLER CONTROLLING THE SAME, AND COMPUTING SYSTEM INCLUDING THE SAME

A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other. 1. An error correction method of a memory controller configured to control a memory module including first memory chips , each having a first input/output width , and configured to store data and at least one second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data , the error correction method comprising:determining whether the data, received from the memory module, includes an error that is correctable;determining whether physical replacement of a memory cell storing the data is required;selecting a first error correction mode when the error is correctable and the physical replacement is required;selecting a second error correction mode when the error is correctable and the physical replacement is not required; andperforming an error correction operation on the data according to the selected error correction mode.2. The error correction method of claim 1 , further comprising:receiving the data from the first memory chip through first lanes when the first error correction mode is selected;receiving the error correction code from the at least one second memory chip through second lanes when the first error correction mode is selected; andperforming the error correction operation on the data using the received error correction code.3. The error correction mode of claim 1 , further ...

METHODS AND APPARATUS TO DETECT AND CORRECT ERRORS IN DESTRUCTIVE READ NON-VOLATILE MEMORY

In described examples, data are stored in a destructive read non-volatile memory (DRNVM). The DRNVM includes an array of DRNVM cells organized as rows of data. The rows of data are subdivided into columns of code word symbols. Each column of code word symbols is encoded to store an error correction code symbol for each column of code word symbols. 1. A destructive read non-volatile memory (DRNVM) comprising:an array of DRNVM cells organized as rows of data, the rows of data being subdivided into columns of code word symbols;read-restore logic, coupled to the array of DRNVM cells, to destructively read data from an addressed row of the DRNVM cells and to restore the data to the addressed row; anderror correction logic, coupled to the read-restore logic, to correct an error in a row of the DRNVM cells, by correcting the error per column in the row, based on the code word symbols in a same column of other rows of the DRNVM cells.2. The DRNVM of claim 1 , further comprising:power control logic, coupled to the array of DRNVM cells, to remove power from the array of DRNVM cells in response to a power-off command only after the read-restore logic has completed any pending read-restore cycle;status logic, coupled to the power control logic, to store a first power-off signature during operation of the array of DRNVM cells and to store a second power-off signature in response to completion of a power-off command; andcontrol logic, coupled to the error correction logic, to detect when power is applied to the array of DRNVM cells and to cause the error correction logic to perform an error correction on each column of code word symbols in the array of DRNVM cells in response to power being applied to the array of DRNVM cells when the power-off status is the first power-off signature.3. The DRNVM of claim 1 , further comprising encoding logic claim 1 , coupled to the read-restore logic claim 1 , to create an error correction code symbol for each of the columns of code word ...

MEMORY SYSTEM FOR CONTROLLING NONVOLATILE MEMORY

According to one embodiment, a memory system copies content of a first logical-to-physical address translation table corresponding to a first region of a nonvolatile memory to a second logical-to-physical address translation table corresponding to a second region of the nonvolatile memory. When receiving a read request specifying a logical address in the second region, the memory system reads a part of the first data from the first region based on the second logical-to-physical address translation table. The memory system detects a block which satisfies a refresh condition from a first group of blocks allocated to the first region, corrects an error of data of the detected block and writes the corrected data back to the detected block. 1. A memory system connectable to a host computing device , the memory system comprising:a nonvolatile memory including a plurality of blocks; anda controller electrically connected to the nonvolatile memory and configured to:manage a plurality of regions in the nonvolatile memory, the regions including a first region storing first data referred to by another region and a second region referring to the first data;copy content of a first logical-to-physical address translation table corresponding to the first region to a second logical-to-physical address translation table corresponding to the second region in response to a request from the host computing device;when receiving a read request specifying a logical address in the second region from the host computing device, read a part of the first data from the first region based on the second logical-to-physical address translation table, and return the read data to the host computing device;when receiving a write request specifying a logical address in the second region from the host computing device, write, to the second region, second data to be written, and update the second logical-to-physical address translation table such that a physical address indicating a physical storage ...

ACCELERATED ERASURE CODING SYSTEM AND METHOD

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data. 1a processing core for executing computer instructions and accessing data from a main memory; anda non-volatile storage medium for storing the computer instructions, a data matrix for holding original data in the main memory;', 'a check matrix for holding check data in the main memory;', 'an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and', a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor; and', 'a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data., 'a thread for executing on the processing core and comprising], 'wherein the processing core, the storage medium, and the computer instructions are configured to implement an erasure coding system comprising. A system for accelerated error-correcting code (ECC) processing comprising: This application is a continuation of U.S. patent ...

PARTIAL PARITY ECC CHECKING MECHANISM WITH MULTI-BIT HARD AND SOFT ERROR CORRECTION CAPABILITY

Embodiments of the inventive concept include a system and method for computing a partial parity error correcting code. Check bits are computed from subsets of the data bits and stored. When the data bits are read, the check bits can be recomputed from the read data bits and compared with the stored check bits to generate a syndrome value. The syndrome value can identify which data bits and/or check bits are in error and correct for the errors. 1105. A memory module () , comprising:{'b': '115', 'storage () for data bits;'}{'b': '125', 'storage () for check bits;'}{'b': 120', '130, 'check bit circuitry (, ) to compute the check bits from the data bits; and'}{'b': '140', 'an XOR gate () to compute a syndrome from the check bits,'}wherein the syndrome is capable of identifying and correcting at least two bit errors.2105. A memory module () according to claim 1 , wherein the syndrome includes at least E bits set to 1 if at least one data bit is read from the memory incorrectly claim 1 , where E is greater than the number of bits the method is intended to correct.3105120130. A memory module () according to claim 1 , wherein the check bit circuitry ( claim 1 , ) computes the check bits using XOR gates on unique subsets of the data bits.4105. A memory module () according to claim 3 , wherein each of the data bits is used in at least E of the first set of partial parity check bits claim 3 , where E is greater than a number of bit errors the method is intended to correct.5105. A memory module () according to claim 1 , wherein the syndrome is capable of indicating one of the following results: no errors claim 1 , one data bit error claim 1 , one check bit error claim 1 , one data bit err and one check bit error claim 1 , two data bit errors claim 1 , and two check bit errors.6105. A memory module () according to claim 1 , further comprising:{'b': '145', 'correction vector circuitry () to generate a correction vector from the syndrome value; and'}{'b': '135', 'a second XOR gate ...

METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY

A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences. 1. A memory controller for reading data stored in a flash memory , comprising:a control logic, for performing a plurality of read operations upon a plurality of memory cells of the flash memory, wherein the read operations utilizes a plurality of control gate voltages to read bits from memory cells; anda receiving circuit, for obtain a plurality of bit sequences from the flash memory in response to the plurality of read operations;wherein the control logic refers to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a first control gate voltage and a second control gate voltage of the plurality of control gate voltages, to generate a first value; and the control logic refers to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between the second control gate voltage and a third control gate voltage of the plurality of control gate voltages, to generate a second value; and the control logic updates a control gate voltage of the plurality of control gate voltages according to the first value and the second value.2. The memory controller of claim 1 , wherein the first control gate voltage is lower than the second control gate voltage claim 1 , and the second control gate voltage is lower than the third control gate voltage.3. The memory controller of claim 2 , wherein the first ...

Single and double chip spare

Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

NONVOLATILE MEMORY AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a first memory cell suitable for storing a validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information. 1. A nonvolatile memory , comprising: a first memory cell suitable for storing a validity signal indicating data validity of the corresponding memory set; and', 'second memory cells suitable for storing multi-bit data or one or more-bit defect information., 'a plurality of memory sets, wherein each of the memory sets comprises2. The nonvolatile memory of claim 1 , wherein in an unused defective memory set among the plurality of memory sets claim 1 ,the first memory cell is not programmed, but one or more of the second memory cells are programmed.3. The nonvolatile memory of claim 2 , wherein in an unused normal memory set among the plurality of memory sets claim 2 ,the first memory cell and the second memory cells are not programmed.4. The nonvolatile memory of claim 3 , wherein in a used memory set among the plurality of memory sets claim 3 ,the first memory cell is programmed, and the second memory cells are programmed according to multi-bit data.5. A semiconductor device comprising:a nonvolatile memory comprising a plurality of memory sets;a control unit suitable for controlling read operations to be sequentially performed on the plurality of memory sets during a boot-up operation;a usable address storage unit suitable for selectively storing addresses of the plurality of memory sets using read data of the plurality of memory sets outputted from the nonvolatile memory during the boot-up operation;a register unit suitable for storing the read data of the plurality of memory sets outputted from the nonvolatile memory during the boot-up operation; andan internal circuit suitable for operating by using the read data of the plurality of memory sets stored in ...

FLASH MEMORY APPARATUS, MEMORY CONTROLLER AND METHOD FOR CONTROLLING FLASH MEMORY

A flash memory apparatus, a memory controller and a method for controlling a flash memory are provided. The memory controller includes a damaged-column manager, an error checking and correcting decoder (ECC decoder) and a damaged-column decision circuit. The damaged-column manager logs a damaged-column address information in the flash memory. The ECC decoder receives a read data read by the flash memory and generates an error information according to whether or not the read data has error. The damaged-column decision circuit receives the error-column address and counts the number of accumulated generated times corresponding to the error-column address. The damaged-column decision circuit updates the damaged-column address information according to an error information. 1. A memory controller , configured to control a flash memory and comprising:a damaged-column manager, storing a damaged-column address information in the flash memory;an error checking and correcting decoder, receiving a read data read from the flash memory, performing decoding on the read data and generating an error information according to the read data; anda damaged-column decision circuit, coupled to the error checking and correcting decoder and coupled to the damaged-column manager, wherein the damaged-column decision circuit receives the error information and updates the damaged-column address information according to the error information.2. The memory controller as claimed in claim 1 , wherein the error checking and correcting decoder judges whether or not the read data has error and outputs an error-column address corresponding to the read data with generated errors to serve as the error information.3. The memory controller as claimed in claim 2 , wherein the damaged-column decision circuit counts a number of accumulated generated times of the error-column address and delivers the error-column address to the damaged-column manager according to the number of accumulated generated times.4. The ...

Methods for Error Correction with Resistive Change Element Arrays

Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.

Low ber hard-decision ldpc decoder

A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.