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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 349. Отображено 189.
12-02-2013 дата публикации

Method and device for multi phase error-correction

Номер: US0008375272B2
Автор: Simon Litsyn, Eran Sharon, Idan Alrod, Menahem Lasser, LITSYN SIMON, SHARON ERAN, ALROD IDAN, LASSER MENAHEM
Принадлежит: Ramot at Tel Aviv University Ltd., UNIV RAMOT, LITSYN SIMON, SHARON ERAN, ALROD IDAN, LASSER MENAHEM, RAMOT AT TEL AVIV UNIVERSITY LTD.

Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

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Номер записи: 1
04-02-2020 дата публикации

Single-port memory with opportunistic writes

Номер: US0010553285B2
Автор: Ran Zamir, David Avraham, Eran Sharon, Idan Alrod, ZAMIR RAN, AVRAHAM DAVID, SHARON ERAN, ALROD IDAN, Zamir, Ran, Avraham, David, Sharon, Eran, Alrod, Idan
Принадлежит: Western Digital Technologies, Inc., WESTERN DIGITAL TECH INC, WESTERN DIGITAL TECHNOLOGIES, INC.

An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.

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Номер записи: 2
24-02-2015 дата публикации

Probabilistic error correction in multi-bit-per-cell flash memory

Номер: US0008966342B2
Автор: Simon Litsyn, Idan Alrod, Eran Sharon, Mark Murin, Menahem Lasser, LITSYN SIMON, ALROD IDAN, SHARON ERAN, MURIN MARK, LASSER MENAHEM
Принадлежит: Ramot at Tel Aviv University Ltd., LITSYN SIMON, ALROD IDAN, SHARON ERAN, MURIN MARK, LASSER MENAHEM, UNIV RAMOT, RAMOT AT TEL AVIV UNIVERSITY LTD.

Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

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Номер записи: 3
13-01-2011 дата публикации

GAIN CONTROL FOR READ OPERATIONS IN FLASH MEMORY

Номер: US20110007573A1
Автор: Idan Alrod, Eran Sharon
Принадлежит:

A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach, M-quantized threshold voltage values are multiplied by a gain to obtain gain-adjusted threshold voltage values, which are quantized by an L-level quantizer, where L Подробнее

Номер записи: 4
02-12-2021 дата публикации

DATA SHAPING FOR INTEGRATED MEMORY ASSEMBLY

Номер: US20210373993A1
Автор: Eran Sharon, Idan Alrod
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly comprises a memory die bonded to a control die with bond pads. The control die includes one or more control circuits for controlling the operation of the memory die. The one or more control circuits are configured to receive data to be programmed into the memory die, select a number of parity bits, encode the data to add error correction information and form a codeword that includes the number of parity bits, shape the codeword, and program the shaped codeword into the memory die.

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Номер записи: 5
30-11-2010 дата публикации

Method and device for multi phase error-correction

Номер: US0007844877B2
Автор: Simon Litsyn, Eran Sharon, Idan Alrod, Menahem Lasser, LITSYN SIMON, SHARON ERAN, ALROD IDAN, LASSER MENAHEM
Принадлежит: Ramot at Tel Aviv University Ltd., UNIV RAMOT, RAMOT AT TEL AVIV UNIVERSITY LTD.

Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

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Номер записи: 6
29-04-2014 дата публикации

Non-volatile memory and method having efficient on-chip block-copying with controlled error rate

Номер: US0008713380B2
Автор: Chris Nga Yee Avila, Jianmin Huang, Lee M. Gavens, Idan Alrod, AVILA CHRIS NGA YEE, HUANG JIANMIN, GAVENS LEE M, ALROD IDAN, GAVENS LEE M.
Принадлежит: Sandisk Technologies, Inc., AVILA CHRIS NGA YEE, HUANG JIANMIN, GAVENS LEE M, ALROD IDAN, SANDISK TECHNOLOGIES INC, GAVENS LEE M., SANDISK TECHNOLOGIES, INC.

A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.

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Номер записи: 7
12-10-2010 дата публикации

Soft decoding of hard and soft bits read from a flash memory

Номер: US0007814401B2
Автор: Idan Alrod, Eran Sharon, Simon Litsyn, Menahem Lasser, ALROD IDAN, SHARON ERAN, LITSYN SIMON, LASSER MENAHEM
Принадлежит: Ramot at Tel Aviv University Ltd., UNIV RAMOT, RAMOT AT TEL AVIV UNIVERSITY LTD.

To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimated probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.

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Номер записи: 8
25-08-2015 дата публикации

System and method to reduce read latency of a data storage device

Номер: US0009116824B2
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: SANDISK TECHNOLOGIES INC., SANDISK TECHNOLOGIES INC

A data storage device includes a memory and a controller. The controller is configured to receive a read request that indicates a logical address. The controller is further configured to perform a first read operation to retrieve a representation of an entry of a logical mapping table from the memory, and perform a second read operation to retrieve a representation of a codeword from the memory. The controller is further configured to decode the representation of the codeword to determine whether an error exists at the entry, and, prior to completion of decoding, to initiate a third read operation to retrieve first read data from a first physical address corresponding to the logical address as determined based on the representation of the entry.

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Номер записи: 9
16-04-2019 дата публикации

Command sequence for first read solution for memory

Номер: US0010262743B2
Автор: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik, ALROD IDAN, SHARON ERAN, EYAL ALON, PANG LIANG, MEKHANIK EVGENY, Alrod, Idan, Sharon, Eran, Eyal, Alon, Pang, Liang, Mekhanik, Evgeny
Принадлежит: SanDisk Technologies LLC, SANDISK TECHNOLOGIES LLC

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.

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Номер записи: 10
08-08-2017 дата публикации

Method and device for iteratively updating read voltages

Номер: US0009728263B2
Автор: Eran Sharon, Evgeny Mekhanik, Idan Alrod, SHARON ERAN, MEKHANIK EVGENY, ALROD IDAN, Sharon Eran, Mekhanik Evgeny, Alrod Idan
Принадлежит: SANDISK TECHNOLOGIES LLC, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A value of the first read voltages is selected based on error correction coding (ECC) related information related to the multiple representations of the data. In another embodiment, storage elements of the memory are sensed using a set of candidate read voltages to generate sensing data that is transferred to a memory accessible to the controller. The multiple representations of data may be generated based on the sensing data to emulate results of reading the storage elements using a different combination of candidate reading voltages.

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Номер записи: 11
28-10-2014 дата публикации

Systems and methods of storing data

Номер: US0008874994B2
Автор: Eran Sharon, Idan Alrod, Simon Litsyn, SHARON ERAN, ALROD IDAN, LITSYN SIMON
Принадлежит: Sandisk Technologies Inc., SHARON ERAN, ALROD IDAN, LITSYN SIMON, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A method of storing data includes receiving data including a first group of bits and a second group of bits and initiating a shaping encoding operation on the second group of bits to generate a third group of bits. The third group of bits has more bits than the second group of bits. The shaping encoding operation is configured to produce a non-uniform probability distribution of bit values in the third group of bits. The first group of bits and first error correction coding (ECC) parity bits corresponding to the first group of bits are stored to a first logical page that is within a physical page of a MLC memory and the third group of bits and second ECC parity bits corresponding to the third group of bits are stored to a second logical page that is within the physical page of the MLC memory.

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Номер записи: 12
11-08-2016 дата публикации

Adaptive Data Shaping in Nonvolatile Memory

Номер: US20160232983A1
Автор: Bhuvan Khurana, Niles Yang, Jianmin Huang, Ting Luo, Idan Alrod, KHURANA BHUVAN, YANG NILES, HUANG JIANMIN, LUO TING, ALROD IDAN, Khurana Bhuvan, Yang Niles, Huang Jianmin, Luo Ting, Alrod Idan
Принадлежит:

A nonvolatile memory block experiences multiple write-erase cycles during which data is subject to a shaping operation prior to storage. In response to a write-erase cycle count reaching a predetermined number, a polling cycle occurs during which shaping is disabled and data is collected that indicates a condition of the block. Subsequently, shaping is reenabled for subsequent cycles.

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Номер записи: 13
21-07-2016 дата публикации

Selective Online Burn-In with Adaptive and Delayed Verification Methods for Memory

Номер: US20160211035A1
Автор: Ofer Shapira, Eran Sharon, Idan Alrod, SHAPIRA OFER, SHARON ERAN, ALROD IDAN
Принадлежит:

A memory is released for use without pre-verification of its memory blocks as being defect free. Some memory blocks are subjected to a verification process when the computer memory is in use in order to verify a minimum number of memory blocks required for high performance program operation as being defect free. The verification process continues as the computer memory is in use in order to maintain the minimum number of memory blocks required for high performance operation in the verified defect free state. A verification mode of either no verification, delayed verification, or immediate verification is applied to memory blocks used for regular performance program operation. Delayed verification is maintained until an ability to recover the stored data is going to be lost. Immediate verification can be performed using bit error rate analysis. Some verification processes are performed using aggressive programming trim and/or multiple word line sensing for faster programming.

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Номер записи: 14
08-06-2021 дата публикации

Non-volatile storage system with data shaping memory partitions

Номер: US0011029872B2
Автор: Ariel Navon, Eran Sharon, Idan Alrod, Alex Bazarsky, NAVON ARIEL, SHARON ERAN, ALROD IDAN, BAZARSKY ALEX, Navon, Ariel, Sharon, Eran, Alrod, Idan, Bazarsky, Alex
Принадлежит: Western Digital Technologies, Inc., WESTERN DIGITAL TECH INC, WESTERN DIGITAL TECHNOLOGIES, INC.

A non-volatile storage apparatus comprises a non-volatile storage and a control circuit connected to the non-volatile storage. The non-volatile storage structure is organized into multiple partitions. Each partition is preassigned to a different data shaping level. Data to be stored in the non-volatile storage is shaped based on its entropy. The control circuit is configured to write shaped data to a partition of the multiple partitions that is preassigned to a same shaping level as the shaped data.

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Номер записи: 15
08-06-2021 дата публикации

Soft bit read mode selection for non-volatile memory

Номер: US0011029889B1
Автор: Eran Sharon, Alex Bazarsky, Idan Alrod, SHARON ERAN, BAZARSKY ALEX, ALROD IDAN, Sharon, Eran, Bazarsky, Alex, Alrod, Idan
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC., WESTERN DIGITAL TECH INC, Western Digital Technologies, Inc.

Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times.

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Номер записи: 16
26-03-2009 дата публикации

Post-Facto Correction For Cross Coupling In A Flash Memory

Номер: US20090080259A1
Автор: Idan Alrod, Eran Sharon
Принадлежит: SANDISK IL LTD.

A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that data are read from the cells by measuring those values. One of the cells and its neighbors are read. The data stored in the cell are estimated, based on the measurements and on respective extents to which the neighbors disturb the reading. Preferably, the method also includes determining those respective extents to which the neighbors disturb the reading, for example based on the measurements themselves.

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Номер записи: 17
23-10-2008 дата публикации

ADAPTIVE DYNAMIC READING OF FLASH MEMORIES

Номер: US20080263266A1
Автор: Eran Sharon, Idan Alrod, Mark Shlick
Принадлежит: SanDisk IL Ltd.

Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. A histogram is constructed by determining how many of some or all of the cells have threshold voltages in each of two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on estimated values of shape parameters of the histogram. Alternatively, the cells are read relative to reference voltages that define m≧2 threshold voltage intervals that span the threshold voltage window, to determine numbers of at least a portion of the cells whose threshold voltages are in each of two or more of the threshold voltage intervals. Respective threshold voltage states are assigned to the cells based on the numbers without re-reading the cells.

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Номер записи: 18
06-08-2013 дата публикации

Using damping factors to overcome LDPC trapping sets

Номер: US0008504895B2
Автор: Eran Sharon, Simon Litsyn, Idan Alrod, SHARON ERAN, LITSYN SIMON, ALROD IDAN
Принадлежит: Ramot At Tel Aviv University Ltd., SHARON ERAN, LITSYN SIMON, ALROD IDAN, UNIV RAMOT, RAMOT AT TEL AVIV UNIVERSITY LTD.

To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between N bit nodes and N-K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules.

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Номер записи: 19
24-04-2018 дата публикации

First read solution for memory

Номер: US0009952944B1
Автор: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik, ALROD IDAN, SHARON ERAN, EYAL ALON, PANG LIANG, MEKHANIK EVGENY, Alrod, Idan, Sharon, Eran, Eyal, Alon, Pang, Liang, Mekhanik, Evgeny
Принадлежит: SanDisk Technologies LLC, SANDISK TECHNOLOGIES LLC

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

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Номер записи: 20
23-06-2016 дата публикации

MULTI-STAGE DECODER

Номер: US20160179620A1
Автор: Alexander Bazarsky, Ran Zamir, Eran Sharon, Idan Alrod, BAZARSKY ALEXANDER, ZAMIR RAN, SHARON ERAN, ALROD IDAN
Принадлежит:

An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit. 1. An apparatus comprising:a memory die including a group of storage elements and one or more unallocated redundant columns, wherein a number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die; anda controller coupled to the memory, the controller configured to receive data and redundancy information associated with the data from the memory, the data including a first bit and the redundancy information including a second bit, the redundancy information sensed from the one or more unallocated redundant columns and having a size that is based on the number of one or more bad columns,wherein the controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.2. The apparatus of claim 1 , further comprising a second memory die including a second set of one or more bad columns claim 1 , wherein a number of the second set of one or more bad columns is different than the number of unallocated redundant columns of the memory die.3. The apparatus of claim 2 , wherein the second memory die further includes a second set of one or more unallocated ...

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Номер записи: 21
02-01-2020 дата публикации

SYSTEM AND METHOD FOR PREDICTIVE READ OF RANDOM DATA

Номер: US20200004430A1
Автор: Ariel Navon, Eran Sharon, Idan Alrod, NAVON ARIEL, SHARON ERAN, ALROD IDAN, Navon, Ariel, Sharon, Eran, Alrod, Idan
Принадлежит:

Systems and methods for predicting read commands and pre-fetching data when a memory device is receiving random read commands to non-sequentially addressed data locations are disclosed. A limited length sequence of prior read commands are generated and compared to a read command history datastore. When a prior pattern of read commands is found corresponding to the search sequence, a next read command that previously followed that search sequence may be used as a predicted next read command and data pre-fetched based on the read command data location information associated with that prior read command that is being used as the predicted read command. 1. A non-volatile memory system comprising:a non-volatile memory;a volatile memory; and receive a current read command comprising read command data location information for data to be read from the non-volatile memory;', 'generate, in the volatile memory, a read command search sequence comprising a list of read command data location information for the current read command and for each of a predetermined number of read commands received sequentially prior to the current read command;', 'compare the generated read command search sequence to a prior read command datastore, the prior read command datastore comprising a list of prior read commands arranged in chronological order of receipt; and', 'responsive to a sequential portion of the list of prior read commands matching the generated read command sequence, retrieve predicted data location information from a next more-recent prior read command in the prior read command datastore located after the sequential portion., 'a controller in communication with the non-volatile memory and the volatile memory, the controller configured to2. The non-volatile memory system of claim 1 , wherein the controller is further configured to pre-fetch data from the non-volatile memory into the volatile memory based on the predicted data location information.3. The non-volatile memory system ...

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Номер записи: 22
25-07-2013 дата публикации

APPARATUS AND METHOD FOR ENHANCING FLASH ENDURANCE BY ENCODING DATA

Номер: US20130191579A1
Автор: Eran Sharon, Simon Litsyn, Idan Alrod
Принадлежит: Ramot At Tel Aviv University Ltd.

Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance. 1. A method of storing a first plurality of input bits in a plurality of memory cells , comprising:(a) providing a first mapping of bit patterns to cell states of the memory cells;(b) mapping the first plurality of input bits to a first plurality of transformed bits that is larger in number than the first plurality of input bits, using a first shaping encoding that has a downward asymptotic bias with respect to the first mapping of bit patterns to cell states;(c) programming at least a portion of the first sub-plurality of the memory cells to store the first plurality of transformed bits according to the first mapping of bit patterns to cell states; and(d) erasing the at least portion of the first sub-plurality of the memory cells before programming the at least portion of the first sub-plurality of the memory cells to store any other bits.2. The method of claim 1 , wherein the first shaping encoding has a downward asymptotic bias towards a lower half of the cell states.3. The method of claim 1 , wherein the first shaping encoding is non-linear.4. The method of claim 3 , wherein the first shaping encoding is a variable length encoding.5. The method of claim 4 , wherein the variable length encoding is a prefix encoding.6. The method of claim 5 , wherein the prefix encoding is a reverse Huffman encoding.7. The method of claim 3 , wherein the first shaping encoding is a reverse enumerative source encoding.8. The method of claim 1 , wherein the first shaping encoding is a trellis shaping encoding.9. The method of claim ...

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Номер записи: 23
04-11-2014 дата публикации

Systems and methods of storing data

Номер: US0008880977B2
Автор: Eran Sharon, Idan Alrod, Simon Litsyn, SHARON ERAN, ALROD IDAN, LITSYN SIMON
Принадлежит: SanDisk Technologies Inc., SHARON ERAN, ALROD IDAN, LITSYN SIMON, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page.

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Номер записи: 24
20-10-2011 дата публикации

MULTIPLE PROGRAMMING OF FLASH MEMORY WITHOUT ERASE

Номер: US20110258370A1
Автор: Eran SHARON, Idan Alrod, Simon Litsyn, Ishai Ilani, SHARON ERAN, ALROD IDAN, LITSYN SIMON, ILANI ISHAI
Принадлежит: Ramot At Tel Aviv University Ltd.

To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.

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Номер записи: 25
05-08-2014 дата публикации

Endurance enhancement coding of compressible data in flash memories

Номер: US0008799559B2
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: Sandisk Technologies Inc., SHARON ERAN, ALROD IDAN, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

Methods described in the present disclosure may be based on a direct transformation of original data to shaped data. In a particular example, a method comprises generating a first portion of output data by applying a mapping of input bit sequences to output bit sequences to a first portion of input data, updating the mapping of the input bit sequences to the output bit sequences based on the first portion of the input data to generate an updated mapping, reading a second portion of the input data, and generating a second portion of the output data by applying the updated mapping of the input bit sequences to the output bit sequences to the second portion of the input data.

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Номер записи: 26
11-07-2017 дата публикации

Self-detecting a heating event to non-volatile storage

Номер: US0009704595B1
Автор: Alon Eyal, Idan Alrod, Eran Sharon, Ishai Ilani, Mark Murin, David Rozman, Wei-Cheng Lien, Deepanshu Dutta, Changyuan Chen, EYAL ALON, ALROD IDAN, SHARON ERAN, ILANI ISHAI, MURIN MARK, ROZMAN DAVID, LIEN WEI-CHENG, DUTTA DEEPANSHU, CHEN CHANGYUAN, Eyal Alon, Alrod Idan, Sharon Eran, Ilani Ishai, Murin Mark, Rozman David, Lien Wei-Cheng, Dutta Deepanshu, Chen Changyuan
Принадлежит: SanDisk Technologies LLC, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES LLC, SanDisk Technologies Inc.

Techniques are provided for non-volatile storage self-detecting that a heating event has occurred to the non-volatile storage. One example of the heating event is an Infrared (IR) reflow process. In one aspect, a block of memory cells in a memory device are put through a number of program/erase cycles. A group of the memory cells in the cycled block are programmed to a reference threshold voltage distribution. Some time may pass after programming the cycled block. The memory device self-detects that there has been a heating event in response to a shift in the reference VT distribution being more than an allowed amount. The memory device may switch from a first programming mode to a second programming mode in response to detecting that the heating event has occurred.

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Номер записи: 27
08-11-2022 дата публикации

Toggle mode (TM) coding with circuit bounded array memory

Номер: US0011494126B1
Автор: Julian Vlaiko, Idan Alrod, Tien-Chien Kuo, Nimrod Hermesh, Eran Sharon
Принадлежит: Western Digital Technologies, Inc.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.

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Номер записи: 28
23-12-2014 дата публикации

Systems and methods of storing data

Номер: US0008918698B2
Автор: Eran Sharon, Idan Alrod, Simon Litsyn
Принадлежит: Sandisk Technologies Inc.

A method of writing data includes receiving data pages to be stored in a data storage device and generating codewords corresponding to the received data pages. The codewords are stored to physical pages of a first memory portion of the data storage device. A first portion of a particular codeword that corresponds to a particular data page is stored at a first physical page of the first memory portion. A second portion of the particular codeword is stored at a second physical page of the first memory portion. The codewords are copied from the physical pages of the first memory portion to a physical page of a second memory portion of the data storage device.

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Номер записи: 29
02-01-2014 дата публикации

FLASH MEMORY WITH RANDOM PARTITION

Номер: US20140006898A1
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит:

A system and method for partitioning data in long term memory of a flash memory device is disclosed. The method may include the steps of identifying a type of data that has been received and routing the data to one of at least two partitions in the long term memory array. One partition of the flash memory device may be optimized for random data while another is optimized for sequential data. The method includes identifying the type of data and routing the data to the appropriate partition. Data may be analyzed and routed upon receipt or initially stored in a default partition and later analyzed and routed to another partition. The partition for random data may be configured for storing data using a first level of ECC protection while the second may be configured for storing data using a second, stronger level of ECC protection. 1. A method for implementing at least two data partitions in a long term memory array of a flash memory device: receiving data from a host;', 'determining a data type for the received data; and', applying a first level of error correction code (ECC) protection to the received data; and', 'storing the received data having the first level of ECC protection in a first partition of the flash memory;, 'if the data type for the received data is determined to be a first data type], 'in a controller of the flash memory device, the controller applying a second level of ECC protection to the received data; and', 'storing the received data encoded with the level of ECC protection in a second partition of the flash memory., 'if the data type for the received data is determined to be a second data type, 'and'}2. The method of claim 1 , wherein the first data type comprises data optimized for random access and the second data type comprises data optimized for sequential access.3. The method of claim 2 , wherein applying the first level of ECC protection and storing the received data the first partition comprises encoding the received data with an ECC ...

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Номер записи: 30
12-05-2015 дата публикации

Systems and methods of storing data

Номер: US0009032269B2
Автор: Eran Sharon, Idan Alrod, Simon Litsyn, SHARON ERAN, ALROD IDAN, LITSYN SIMON
Принадлежит: Sandisk Technologies Inc., SHARON ERAN, ALROD IDAN, LITSYN SIMON, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A method of writing data includes receiving data pages to be stored in a data storage device and generating codewords corresponding to the received data pages. The codewords are stored to physical pages of a first memory portion of the data storage device. A first portion of a particular codeword that corresponds to a particular data page is stored at a first physical page of the first memory portion. A second portion of the particular codeword is stored at a second physical page of the first memory portion. The codewords are copied from the physical pages of the first memory portion to a physical page of a second memory portion of the data storage device.

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Номер записи: 31
03-09-2019 дата публикации

Memory health monitoring

Номер: US0010402117B2
Автор: Nian Niles Yang, Idan Alrod, YANG NIAN NILES, ALROD IDAN, Yang, Nian Niles, Alrod, Idan
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC., WESTERN DIGITAL TECH INC, Western Digital Technologies, Inc.

A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.

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Номер записи: 32
07-09-2017 дата публикации

MULTI-TYPE PARITY BIT GENERATION FOR ENCODING AND DECODING

Номер: US20170255512A1
Автор: Ran Zamir, Alexander Bazarsky, Eran Sharon, Idan Alrod, ZAMIR RAN, BAZARSKY ALEXANDER, SHARON ERAN, ALROD IDAN, Zamir Ran, Bazarsky Alexander, Sharon Eran, Alrod Idan
Принадлежит: SanDisk Technologies LLC

A non-volatile memory system may be configured to generate a codeword with first-type parity bits and one or more second-type parity bits. If a storage location in which the codeword is to be stored includes one or more bad memory cells, the bit sequence of the codeword may be arranged so that at least some of the second-type parity bits are stored in the bad memory cells. During decoding, a first set of syndrome values may be determined for a first set of check nodes and a second set of syndrome values may be determined for a second set of check nodes. In some examples, a syndrome weight used for determining if convergence is achieved may be calculated using check nodes that are unassociated with the second-type parity bits.

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Номер записи: 33
31-08-2017 дата публикации

NON-VOLATILE MEMORY WITH CORRUPTION RECOVERY

Номер: US20170249207A1
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN, Sharon Eran, Alrod Idan
Принадлежит: SANDISK TECHNOLOGIES INC.

A non-volatile storage system is provided that includes a mechanism to restore data that has been corrupted beyond the limits of traditional error correction. The system creates first level parity information for each subset of data to form multiple sets of programmable data, with each set of programmable data including a subset of data and corresponding first level parity. Separate second level parity is created for each set of programmable data. The system creates combined second level parity information based on a function of separate second level parity information for the multiple sets of programmable data. If a set of programmable data is found to be corrupt, the corrupt subset of data is recovered using the corrupt subset of data read from the non-volatile storage system, the corresponding first level parity read from the non-volatile storage system and the combined second level parity information.

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Номер записи: 34
30-05-2019 дата публикации

SINGLE-PORT MEMORY WITH OPPORTUNISTIC WRITES

Номер: US20190164610A1
Автор: Ran Zamir, David Avraham, Eran Sharon, Idan Alrod, ZAMIR RAN, AVRAHAM DAVID, SHARON ERAN, ALROD IDAN, Zamir, Ran, Avraham, David, Sharon, Eran, Alrod, Idan
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data. 1. An apparatus , comprising:a first single-port memory;a second single-port memory; andone or more control circuits in communication with the first single-port memory and in communication with the second single-port memory, the one or more control circuits configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and configured to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.2. The apparatus of further comprising a table that indicates the physical location of the stored data in either the first single-port memory or the second single-port memory.3. The apparatus of wherein the one or more control circuits are configured to update the table with a physical location of the fresh data.4. The apparatus of further comprising a plurality of stored initial table entries to initialize the table claim 3 , the one or more control circuits configured to write data at locations indicated by the plurality of stored initial table entries on initial clock cycles.5. The apparatus of further comprising an iterative decoder and wherein the stored data and the fresh data represent iterations of a decoding operation.6. The apparatus of further comprising a set of non- ...

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Номер записи: 35
09-12-2021 дата публикации

PEAK POWER CONTROL IN AN INTEGRATED MEMORY ASSEMBLY

Номер: US20210382804A1
Автор: Idan Alrod, Eran Sharon, Alexander Bazarsky
Принадлежит: Western Digital Technologies, Inc.

Power regulation in an integrated memory assembly having control semiconductor dies and memory semiconductor is disclosed herein. A master control die regulates power usage by the integrated memory assembly. Each control die reports information about its expected power usage to the master control die. The master control die determines a plan that meets a power criterion for the integrated memory assembly. The plan may maximize the power usage in each time period, while staying within a power budget. The plan can include selecting which of the memory dies perform a memory operation (or phase of a memory operation) during a given time period. The master control die may send a die scheduling plan to each of the other control dies. Each die scheduling plan indicates when memory operations and/or phases of memory operations are to be performed.

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Номер записи: 36
19-04-2016 дата публикации

Systems and methods of storing data

Номер: US0009318166B2
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: SANDISK TECHNOLOGIES, INC., SHARON ERAN, ALROD IDAN, SANDISK TECHNOLOGIES INC

A method of reading data in a data storage device with a controller and a memory includes generating, in the memory, a set of bits corresponding to a particular storage element of the memory. The set of bits indicates a group of threshold voltage intervals. A threshold voltage of the particular storage element corresponds to one of the threshold voltage intervals within the group. At least one threshold voltage interval within the group is separated from another threshold voltage interval within the group by an intervening threshold voltage interval that is not within the group. The method also includes sending the set of bits to the controller. The set of bits includes a first hard bit that corresponds to a value read from the particular storage element and a first soft bit that corresponds to a reliability measure.

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Номер записи: 37
11-06-2013 дата публикации

Method and apparatus for error correction according to erase counts of a solid-state memory

Номер: US0008464134B2
Автор: Idan Alrod, Eran Sharon, Menahem Lasser, ALROD IDAN, SHARON ERAN, LASSER MENAHEM
Принадлежит: SanDisk IL Ltd, ALROD IDAN, SHARON ERAN, LASSER MENAHEM, SANDISK IL LTD

Embodiments of the present invention relate to methods and devices where an erase count is maintained for at least one block of solid state memory. Errors are corrected in data read from the solid state memory in accordance with the associated erase count of the memory block. In some embodiments, one or more of the following error-correction operations may be effected according to the associated erase count of a memory block from which the data is read: (i) a decoder and/or decoder mode is selected; (ii) a decision to attempt correcting errors using a lighter-weight weight decoder (mode) and/or heavier weight decoder (mode) and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii) a mode transition and/or error correction attempt resource budget is determined; (iv) a number of soft bits is determined; and (v) a decoding bus width size is selected.

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Номер записи: 38
13-10-2011 дата публикации

AUXILIARY PARITY BITS FOR DATA WRITTEN IN MULTI-LEVEL CELLS

Номер: US20110252288A1
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: SANDISK IL LTD.

Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.

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Номер записи: 39
18-10-2011 дата публикации

Gain control for read operations in flash memory

Номер: US0008040737B2
Автор: Idan Alrod, Eran Sharon, ALROD IDAN, SHARON ERAN
Принадлежит: SanDisk IL Ltd., SANDISK IL LTD, SANDISK IL LTD.

A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach, M-quantized threshold voltage values are multiplied by a gain to obtain gain-adjusted threshold voltage values, which are quantized by an L-level quantizer, where L Подробнее

Номер записи: 40
09-12-2021 дата публикации

ECC IN INTEGRATED MEMORY ASSEMBLY

Номер: US20210383886A1
Автор: Idan Alrod, Eran Sharon
Принадлежит: SanDisk Technologies LLC

Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory controller. By not sending the parity bits to the memory controller, substantial bandwidth is saved. Also, substantial power may be saved. For example, the interface between the control die and the memory controller could be a high speed interface.

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Номер записи: 41
30-06-2015 дата публикации

Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling

Номер: US0009070472B2
Автор: Idan Alrod, Eron Sharon, Toru Miwa, Gerrit Jan Hemink, Nima Mokhlesi, ALROD IDAN, SHARON ERON, MIWA TORU, HEMINK GERRIT JAN, MOKHLESI NIMA
Принадлежит: SANDISK IL LTD, SANDISK IL LTD.

A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as Direct-Lookahead (DLA).

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Номер записи: 42
11-03-2014 дата публикации

Method and system for adaptive coding in flash memories

Номер: US0008671327B2
Автор: Simon Litsyn, Eran Sharon, Idan Alrod, LITSYN SIMON, SHARON ERAN, ALROD IDAN
Принадлежит: SanDisk Technologies Inc., LITSYN SIMON, SHARON ERAN, ALROD IDAN, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

To store bits in one or more cells, an adaptive mapping of bits to ranges of a physical parameter of the cell(s) is provided, in accordance with respective initial values of the physical parameter, by steps including encoding the bits as a codeword by partitioning the bits into subsets and finding a factor bit string such that the codeword is a concatenation of the factor bit string and separate Galois field products of all the subsets with the factor bit string. The initial values of the physical parameter are adjusted accordingly as needed.

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Номер записи: 43
20-01-2015 дата публикации

Error correction decoding by trial and error

Номер: US0008938664B2
Автор: Idan Alrod, Eran Sharon, Simon Litsyn, ALROD IDAN, SHARON ERAN, LITSYN SIMON
Принадлежит: Ramot at Tel Aviv University Ltd., ALROD IDAN, SHARON ERAN, LITSYN SIMON, UNIV RAMOT, RAMOT AT TEL AVIV UNIVERSITY LTD.

A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.

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Номер записи: 44
09-01-2014 дата публикации

OPTIMIZED FLASH MEMORY WITHOUT DEDICATED PARITY AREA AND WITH REDUCED ARRAY SIZE

Номер: US20140013033A1
Автор: Eran Sharon, Idan Alrod, Simon Litsyn, SHARON ERAN, ALROD IDAN, LITSYN SIMON
Принадлежит: SANDISK IL LTD.

A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells. 166.-. (canceled)67. A method for storing a plurality of data bits , the method comprising the steps of:(a) encoding the plurality of data bits to generate at least one parity bit;(b) providing a plurality of memory cells, wherein each memory cell is programmable to a plurality of cell states; and(c) programming the plurality of memory cells to represent the plurality of data bits and the at least one parity bit by placing each memory cell in one of the plurality of cell states, wherein every memory cell is programmed to represent at least one of the plurality of data bits.68. The method of wherein the plurality of cell states are threshold voltage states.69. The method of wherein a number of the plurality of memory cells is an integer factor of a number of the plurality of data bits.70. The method of wherein each memory cell is programmed to represent exactly one parity bit.71. The method of wherein each memory cell is programmed to represent at least one parity bit.72. The method of wherein each memory cell is programmed to represent an equal number of the data bits.73. The method of wherein the encoding generates a plurality of parity bits.74. The method of wherein each memory cell is programmed to represent an equal number of the parity bits.75. The method of wherein each memory cell is programmed to represent an equal number of the data bits.76. The method of wherein a sum of the ...

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Номер записи: 45
23-08-2016 дата публикации

Optimized flash memory without dedicated parity area and with reduced array size

Номер: US0009424178B2
Автор: Eran Sharon, Idan Alrod, Simon Litsyn, SHARON ERAN, ALROD IDAN, LITSYN SIMON, Sharon Eran, Alrod Idan, Litsyn Simon
Принадлежит: Sandisk IL Ltd., SHARON ERAN, ALROD IDAN, LITSYN SIMON, SANDISK IL LTD, Sharon Eran, Alrod Idan, Litsyn Simon

A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.

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Номер записи: 46
24-11-2015 дата публикации

Method of data storage in non-volatile memory

Номер: US0009195537B2
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: SANDISK TECHNOLOGIES INC., SHARON ERAN, ALROD IDAN, SANDISK TECHNOLOGIES INC

A method of storing a set of metadata bits associated with each of multiple data words includes combining the set of metadata bits with each of the multiple data words to generate multiple extended data words. The method includes encoding each of the multiple extended data words to generate multiple codewords and puncturing each of the multiple codewords to generate multiple punctured codewords, where in each of the punctured codewords the set of metadata bits is removed. The method includes storing the multiple punctured codewords, transforming the set of metadata bits to generate a set of transformed metadata bits, and storing the set of transformed metadata bits.

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Номер записи: 47
12-06-2018 дата публикации

Temperature variation compensation

Номер: US0009996281B2
Автор: Eran Sharon, Nian Niles Yang, Idan Alrod, Evgeny Mekhanik, Mark Shlick, Joanna Lai, SHARON ERAN, YANG NIAN NILES, ALROD IDAN, MEKHANIK EVGENY, SHLICK MARK, LAI JOANNA, Sharon, Eran, Yang, Nian Niles, Alrod, Idan, Mekhanik, Evgeny, Shlick, Mark, Lai, Joanna
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC., WESTERN DIGITAL TECH INC, Western Digital Technologies, Inc.

A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

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Номер записи: 48
02-05-2017 дата публикации

Rewritable multibit non-volatile memory with soft decode optimization

Номер: US0009640253B2
Автор: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod, CONLEY KEVIN MICHAEL, CERNEA RAUL-ADRIAN, SHARON ERAN, ALROD IDAN, Conley Kevin Michael, Cernea Raul-Adrian, Sharon Eran, Alrod Idan
Принадлежит: SanDisk Technologies LLC, SANDISK TECHNOLOGIES LLC

A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

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Номер записи: 49
19-04-2007 дата публикации

Method of error correction in MBC flash memory

Номер: US20070089034A1
Автор: Simon Litsyn, Idan Alrod, Eran Sharon, Mark Murin, Menahem Lasser
Принадлежит: M-SYSTEMS FLASH DISK PIONEERS, LTD.

A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

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Номер записи: 50
28-04-2009 дата публикации

Probabilistic error correction in multi-bit-per-cell flash memory

Номер: US0007526715B2
Автор: Simon Litsyn, Idan Alrod, Eran Sharon, Mark Murin, Menahem Lasser, LITSYN SIMON, ALROD IDAN, SHARON ERAN, MURIN MARK, LASSER MENAHEM
Принадлежит: Ramot at Tel Aviv University Ltd., UNIV RAMOT, RAMOT AT TEL AVIV UNIVERSITY LTD.

Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

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Номер записи: 51
01-11-2018 дата публикации

STORAGE SYSTEM AND METHOD FOR BAD BLOCK RECYCLING

Номер: US20180315487A1
Автор: DUDY Avraham, Ran Zamir, Idan Alrod, Eran Sharon, AVRAHAM DUDY, ZAMIR RAN, ALROD IDAN, SHARON ERAN, Avraham, DUDY, Zamir, Ran, Alrod, Idan, Sharon, Eran
Принадлежит: Western Digital Technologies, Inc.

A storage system is provided comprising a controller and a memory. The controller is configured to identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline; identify which wordlines in the at least two physical blocks of memory are defective; and create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.

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Номер записи: 52
12-08-2014 дата публикации

Interruption criteria for block decoding

Номер: US0008806307B2
Автор: Idan Alrod, Eran Sharon, Simon Litsyn
Принадлежит: Ramot at Tel Aviv University Ltd.

While decoding a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, by updating estimates of the codeword bits in a plurality of iterations, the iterations are interrupted upon satisfaction of an interruption criterion that is either an order-dependent interruption criterion or an interruption criterion that includes an estimate of mutual information of the codeword and a vector that is used in the decoding iterations. Either the iterations are terminated or the iterations are resumed after one or more elements of one or more vectors used in the iterations is/are modified.

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Номер записи: 53
02-02-2021 дата публикации

CAM storage schemes and CAM read operations for detecting matching keys with bit errors

Номер: US0010910057B2
Автор: Idan Alrod, Eran Sharon, Alon Marcu, Yan Li, ALROD IDAN, SHARON ERAN, MARCU ALON, LI YAN, Alrod, Idan, Sharon, Eran, Marcu, Alon, Li, Yan
Принадлежит: Western Digital Technologies, Inc., WESTERN DIGITAL TECH INC

A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

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Номер записи: 54
30-06-2015 дата публикации

Data coding using divisions of memory cell states

Номер: US0009070427B2
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: SANDISK TECHNOLOGIES INC., SHARON ERAN, ALROD IDAN, SANDISK TECHNOLOGIES INC

Data storage devices and methods to encode and decode data using divisions of memory cell states are disclosed. A method includes dividing data bits into disjoint multiple groups of data bits and storing the data bits into a plurality of memory cells. The storing is done by setting each of the plurality of memory cells to a corresponding state selected from at least three ordered states. For each of the multiple groups of data bits, when a request is received for reading a particular group of the data bits, the request is serviced by selecting a disjoint division of the at least three ordered states of the memory cells into a first set of states and a second set of states. Each of the states in the first set of states has a higher position than any of the states in the second set of states according to the order of the states. For each cell of the plurality of memory cells, a determination is made whether the cell is in the first set of states or the second set of states. Based on the determination ...

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Номер записи: 55
20-06-2013 дата публикации

Systems and Methods for Managing Data in a Device for Hibernation States

Номер: US20130159599A1
Автор: Shahar Bar-Or, Eran Sharon, Idan Alrod
Принадлежит:

The present application is directed to systems and methods for managing data in a device for hibernation states. In one implementation, the device includes an interface and a processor. The interface is coupled with a first memory and a second memory. The processor is in communication with the first and second memories via the interface. The processor is configured to read first data from the first memory, generate image data of the data stored in the first memory based on the first data, and write to the second memory prior to the device entering an initial hibernation state the image data of the data stored in the first memory. The processor is further configured to, after the device awakes from the initial hibernation state, read the image data from the second memory, reconstruct the first data based on the image data, and write the first data to the first memory. 1. A method for managing data storage in conjunction with hibernation of a device , the method comprising: reading first data from the first memory;', 'generating image data of the data stored in the first memory based on the first data;', 'writing to the second memory prior to the device entering an initial hibernation state the image data of the data stored in the first memory; and', reading the image data from the second memory;', 'reconstructing the first data based on the image data; and', 'writing the first data to the first memory., 'after waking from the initial hibernation state], 'in a controller of a device operatively coupled with a first memory and a second memory2. The method of claim 1 , wherein the first memory comprises DRAM memory and the second memory comprises NAND memory.3. The method of claim 1 , further comprising: reading second data from the first memory; and', 'comparing the second data to at least a portion of data reconstructed from the image data stored on the second memory to determine whether data stored in the first memory has changed since the device awoke from the ...

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Номер записи: 56
22-05-2018 дата публикации

Partial soft bit read

Номер: US0009978462B2
Автор: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Abhijeet Manohar, Idan Alrod, RAVIMOHAN NARENDHIRAN CHINNAANANGUR, JAYARAMAN MURALITHARAN, MANOHAR ABHIJEET, ALROD IDAN, Ravimohan, Narendhiran Chinnaanangur, Jayaraman, Muralitharan, Manohar, Abhijeet, Alrod, Idan
Принадлежит: SanDisk Technologies LLC, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES LLC, SANDISK TECHNOLOGIES INC.

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.

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Номер записи: 57
02-05-2017 дата публикации

System and method of processing of duplicate data at a data storage device

Номер: US0009639461B2
Автор: Yarden Eitan, Udi Agami, Eran Sharon, Idan Alrod, EITAN YARDEN, AGAMI UDI, SHARON ERAN, ALROD IDAN, Eitan Yarden, Agami Udi, Sharon Eran, Alrod Idan
Принадлежит: SANDISK TECHNOLOGIES LLC, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A data storage device includes a memory and a controller. A method may be performed at the data storage device. The method includes receiving a request to write data, generating a signature of the data, and searching a signature table to determine if the generated signature is in the signature table. The signature table includes at least one signature table entry that includes a signature of stored data and a physical address of the stored data.

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Номер записи: 58
06-10-2015 дата публикации

Storage module and low-complexity methods for assessing the health of a flash memory device

Номер: US0009152488B2
Автор: Noam Presman, Idan Alrod, Eran Sharon, PRESMAN NOAM, ALROD IDAN, SHARON ERAN
Принадлежит: SanDisk Technologies Inc., PRESMAN NOAM, ALROD IDAN, SHARON ERAN, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A storage module and low-complexity methods for assessing the health of a flash memory device are disclosed. In one embodiment, data is written to a subset of memory cells in a memory of a storage module. Error statistics for the subset of memory cells are determined, and cell error rate parameters for the memory are estimated by fitting the determined error statistics for the subset of memory cells with a parametric statistical model. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

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Номер записи: 59
10-06-2014 дата публикации

Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures

Номер: US0008750042B2
Автор: Eran Sharon, Yan Li, Dana Lee, Idan Alrod, SHARON ERAN, LI YAN, LEE DANA, ALROD IDAN
Принадлежит: SanDisk Technologies Inc., SHARON ERAN, LI YAN, LEE DANA, ALROD IDAN, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.

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Номер записи: 60
10-10-2017 дата публикации

Error detection and handling for a data storage device

Номер: US0009785501B2
Автор: Idan Alrod, Eran Sharon, ALROD IDAN, SHARON ERAN, Alrod Idan, Sharon Eran
Принадлежит: SANDISK TECHNOLOGIES LLC, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A data storage device includes a non-volatile memory and a controller. A method includes writing a first logical page to a physical page of the non-volatile memory. In response to a multistate error indication satisfying a threshold, the method further includes rewriting the first logical page at the non-volatile memory. The multistate error indication is determined based on the first logical page.

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Номер записи: 61
12-02-2013 дата публикации

Compact decoding of punctured block codes

Номер: US0008375278B2
Автор: Eran Sharon, Idan Alrod, Simon Litsyn, SHARON ERAN, ALROD IDAN, LITSYN SIMON
Принадлежит: Ramot At Tel Aviv University Ltd., UNIV RAMOT, SHARON ERAN, ALROD IDAN, LITSYN SIMON, RAMOT AT TEL AVIV UNIVERSITY LTD.

... k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n Подробнее

Номер записи: 62
04-06-2024 дата публикации

On-chip non-volatile memory (NVM) search

Номер: US0012002508B2
Автор: Eran Sharon, Alon Marcu, Shay Benisty, Judah Gamliel Hahn, Idan Alrod, Alexander Bazarsky, Ariel Navon, Ran Zamir
Принадлежит: Western Digital Technologies, Inc.

The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

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Номер записи: 63
25-09-2018 дата публикации

Word line defect detection and handling for a data storage device

Номер: US0010083069B2
Автор: Seungjune Jeon, Idan Alrod, Eran Sharon, Dana Lee, JEON SEUNGJUNE, ALROD IDAN, SHARON ERAN, LEE DANA, Jeon, Seungjune, Alrod, Idan, Sharon, Eran, Lee, Dana
Принадлежит: SanDisk Technologies LLC, SANDISK TECHNOLOGIES LLC

A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.

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Номер записи: 64
20-08-2013 дата публикации

Compact decoding of punctured block codes

Номер: US0008516351B2
Автор: Eran Sharon, Idan Alrod, Simon Litsyn, SHARON ERAN, ALROD IDAN, LITSYN SIMON
Принадлежит: Ramot at Tel Aviv University Ltd., SHARON ERAN, ALROD IDAN, LITSYN SIMON, UNIV RAMOT, RAMOT AT TEL AVIV UNIVERSITY LTD.

... k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n' Подробнее

Номер записи: 65
21-06-2022 дата публикации

CAM storage schemes and CAM read operations for detecting matching keys with bit errors

Номер: US0011367485B2
Автор: Idan Alrod, Eran Sharon, Alon Marcu, Yan Li
Принадлежит: Western Digital Technologies, Inc.

A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

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Номер записи: 66
19-06-2018 дата публикации

Preliminary ready indication for memory operations on non-volatile memory

Номер: US0010002649B1
Автор: Ronen Golan, Roie Shpaizman, Alex Bazarsky, Eli Elmoalem, Grishma Shah, Idan Alrod, GOLAN RONEN, SHPAIZMAN ROIE, BAZARSKY ALEX, ELMOALEM ELI, SHAH GRISHMA, ALROD IDAN, Golan, Ronen, Shpaizman, Roie, Bazarsky, Alex, Elmoalem, Eli, Shah, Grishma, Alrod, Idan
Принадлежит: SANDISK TECHNOLOGIES LLC, SanDisk Technologies LLC

Apparatuses, systems, methods, and computer program products are disclosed for providing a preliminary ready indication for non-volatile memory. A non-volatile memory element initiates a write operation for one or more storage cells of the non-volatile memory element. The non-volatile memory element determines whether a progress threshold is satisfied for the write operation. The non-volatile memory element provides a preliminary ready indication, indicating that the progress threshold is satisfied.

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Номер записи: 67
12-06-2018 дата публикации

Memory health monitoring

Номер: US0009996299B2
Автор: Nian Niles Yang, Idan Alrod, YANG NIAN NILES, ALROD IDAN, Yang, Nian Niles, Alrod, Idan
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC, WESTERN DIGITAL TECH INC, Western Digital Technologies, Inc.

A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.

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Номер записи: 68
31-12-2009 дата публикации

PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY

Номер: US20090327841A1
Автор: Simon LITSYN, Idan Alrod, Eran Sharon, Mark Murin, Menahem Lasser
Принадлежит: Ramot At Tel Aviv University Ltd.

Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

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Номер записи: 69
02-07-2020 дата публикации

ON-CHIP NON-VOLATILE MEMORY (NVM) SEARCH

Номер: US20200211640A1
Автор: Eran Sharon, Alon Marcu, Shay Benisty, Judah Gamliel Hahn, Idan Alrod, Alexander Bazarsky, Ariel Navon, Ran Zamir, SHARON ERAN, MARCU ALON, BENISTY SHAY, HAHN JUDAH GAMLIEL, ALROD IDAN, BAZARSKY ALEXANDER, NAVON ARIEL, ZAMIR RAN, Sharon, Eran, Marcu, Alon, Benisty, Shay, Hahn, Judah Gamliel, Alrod, Idan, Bazarsky, Alexander, Navon, Ariel, Zamir, Ran
Принадлежит:

The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

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Номер записи: 70
04-08-2020 дата публикации

Optimistic read operation

Номер: US0010732847B2
Автор: Alexander Bazarsky, Grishma Shah, Idan Alrod, Eran Sharon, BAZARSKY ALEXANDER, SHAH GRISHMA, ALROD IDAN, SHARON ERAN, Bazarsky, Alexander, Shah, Grishma, Alrod, Idan, Sharon, Eran
Принадлежит: SanDisk Technologies LLC, SANDISK TECHNOLOGIES LLC

A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

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Номер записи: 71
30-06-2015 дата публикации

Systems and methods of updating read voltages

Номер: US0009070479B2
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: SANDISK TECHNOLOGIES INC., SANDISK TECHNOLOGIES INC

A method includes, in a data storage device that includes a non-volatile memory, reading data from the non-volatile memory using a first read voltage. The method includes determining a first count of errors in the data having a first error type and a second count of errors in the data having a second error type. A value of the first read voltage is selectively updated based on a comparison of the first count to the second count.

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Номер записи: 72
27-04-2017 дата публикации

SYSTEMS AND METHODS TO COMPENSATE FOR THRESHOLD VOLTAGE SHIFTS

Номер: US20170117053A1
Автор: Eran Sharon, Idan Alrod, Deepanshu Dutta, SHARON ERAN, ALROD IDAN, DUTTA DEEPANSHU, Sharon Eran, Alrod Idan, Dutta Deepanshu
Принадлежит:

A data storage device includes a memory including multiple storage elements. The data storage device also includes circuitry configured to determine, for a particular storage element of the multiple storage elements, an indicator associated with a threshold voltage temperature dependence (TVTD) of the particular storage element. 1. A data storage device comprising:a memory including multiple storage elements; andcircuitry configured to determine, for a particular storage element of the multiple storage elements, an indicator associated with a threshold voltage temperature dependence (TVTD) of the particular storage element.2. The data storage device of claim 1 , wherein the circuitry is configured to determine the indicator during a read operation associated with a word line that includes the particular storage element.3. The data storage device of claim 1 , wherein the circuitry is configured to determine the indicator responsive to a determination that a first temperature of at least a portion of the memory at a time of programming the particular storage element satisfies a threshold.4. The data storage device of claim 1 , wherein the circuitry is configured to determine a temperature difference between a first temperature at a first time of programming the particular storage element and a second temperature at a second time of reading the particular storage element claim 1 , and wherein the circuitry is configured to determine the indicator in response to determining that the temperature difference is greater than or equal to a threshold.5. The data storage device of claim 1 , wherein the circuitry is configured to determine the indicator based on a determined drain induced barrier lowering value associated with the particular storage element.6. The data storage device of claim 1 , wherein the circuitry is configured to determine the indicator by:causing a first bit line voltage to be applied to a first bit line associated with the particular storage element; ...

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Номер записи: 73
22-02-2022 дата публикации

Die memory operation scheduling plan for power control in an integrated memory assembly

Номер: US0011256591B2
Автор: Idan Alrod, Eran Sharon, Alexander Bazarsky
Принадлежит: Western Digital Technologies, Inc.

Power regulation in an integrated memory assembly having control semiconductor dies and memory semiconductor is disclosed herein. A master control die regulates power usage by the integrated memory assembly. Each control die reports information about its expected power usage to the master control die. The master control die determines a plan that meets a power criterion for the integrated memory assembly. The plan may maximize the power usage in each time period, while staying within a power budget. The plan can include selecting which of the memory dies perform a memory operation (or phase of a memory operation) during a given time period. The master control die may send a die scheduling plan to each of the other control dies. Each die scheduling plan indicates when memory operations and/or phases of memory operations are to be performed.

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Номер записи: 74
05-01-2010 дата публикации

Multi-bit-per-cell flash memory device with non-bijective mapping

Номер: US0007643342B2
Автор: Simon Litsyn, Eran Sharon, Idan Alrod, LITSYN SIMON, SHARON ERAN, ALROD IDAN
Принадлежит: Ramot at Tel-Aviv University Ltd., UNIV RAMOT, RAMOT AT TEL-AVIV UNIVERSITY LTD.

To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an "into" generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

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Номер записи: 75
08-03-2011 дата публикации

Adaptive dynamic reading of flash memories

Номер: US0007903468B2
Автор: Simon Litsyn, Idan Alrod, Eran Sharon, LITSYN SIMON, ALROD IDAN, SHARON ERAN
Принадлежит: Ramot At Telaviv University Ltd., UNIV RAMOT, RAMOT AT TELAVIV UNIVERSITY LTD.

Each of a plurality of flash memory cells is programmed to a respective one of L2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells.

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Номер записи: 76
17-01-2012 дата публикации

Non-volatile memory and methods with reading soft bits in non uniform schemes

Номер: US0008099652B1
Автор: Idan Alrod, Eran Sharon, Toru Miwa, Gerrit Jan Hemink, Yee Lih Koh, ALROD IDAN, SHARON ERAN, MIWA TORU, HEMINK GERRIT JAN, KOH YEE LIH
Принадлежит: Sandisk Corporation, ALROD IDAN, SHARON ERAN, MIWA TORU, HEMINK GERRIT JAN, KOH YEE LIH, SANDISK CORP, SANDISK CORPORATION

A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.

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Номер записи: 77
03-06-2010 дата публикации

Post-Facto Correction for Cross Coupling in a Flash Memory

Номер: US20100135074A1
Автор: Idan Alrod, Eran Sharon, ALROD IDAN, SHARON ERAN
Принадлежит:

A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that data are read from the cells by measuring those values. One of the cells and its neighbors are read. The data stored in the cell are estimated, based on the measurements and on respective extents to which the neighbors disturb the reading. Preferably, the method also includes determining those respective extents to which the neighbors disturb the reading, for example based on the measurements themselves.

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Номер записи: 78
02-01-2020 дата публикации

ERROR CORRECTION DECODING WITH REDUNDANCY DATA

Номер: US20200004627A1
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN, Sharon, Eran, Alrod, Idan
Принадлежит: Western Digital Technologies Inc

Enhanced error correction for data stored in storage devices are presented herein. An error correction circuit decodes an encoded data segment retrieved from a storage media. This decode uses a selected error correction scheme having an error correction limit. The error correction circuit tracks a number of bit corrections made to the encoded data segment during decode. A detection circuit sends a redundant version of the encoded data segment to the error correction circuit in response to the number of bit corrections satisfying a threshold limit set below the error correction limit to mitigate undetected errors in decoding the encoded data segment. An output circuit can transfer resultant data decoded by the error correction circuit to other systems, such as a host device.

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Номер записи: 79
04-10-2018 дата публикации

USE OF MULTIPLE CODEBOOKS FOR PROGRAMMING DATA IN DIFFERENT MEMORY AREAS OF A STORAGE DEVICE

Номер: US20180287634A1
Автор: Rami Rom, Idan Goldenberg, Alexander Bazarsky, Eran Sharon, Ran Zamir, Idan Alrod, Stella Achtenberg, ROM RAMI, GOLDENBERG IDAN, BAZARSKY ALEXANDER, SHARON ERAN, ZAMIR RAN, ALROD IDAN, ACHTENBERG STELLA, Rom, Rami, Goldenberg, Idan, Bazarsky, Alexander, Sharon, Eran, Zamir, Ran, Alrod, Idan, Achtenberg, Stella
Принадлежит: SanDisk Technologies LLC

A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

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Номер записи: 80
19-09-2023 дата публикации

On-chip-copy for integrated memory assembly

Номер: US0011763911B2
Автор: Eran Sharon, Idan Alrod
Принадлежит: Western Digital Technologies, Inc., WESTERN DIGITAL TECHNOLOGIES, INC.

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data.

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Номер записи: 81
27-01-2011 дата публикации

COMPACT DECODING OF PUNCTURED CODES

Номер: US20110022927A1
Автор: Eran Sharon, Idan Alrod, Simon Litsyn
Принадлежит: RAMOT AT TEL AVIV UNIVERSITY LTD.

... k information bits are encoded according to a code with which is associated a parity check matrix H that has n columns. The entire resulting codeword is stored in a storage medium. At least n′ Подробнее

Номер записи: 82
19-07-2018 дата публикации

FIRST READ SOLUTION FOR MEMORY

Номер: US20180203763A1
Автор: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
Принадлежит: SanDisk Technologies LLC

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

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Номер записи: 83
26-05-2015 дата публикации

Detecting effect of corrupting event on preloaded data in non-volatile memory

Номер: US0009043678B2
Автор: Seungjune Jeon, Idan Alrod, Qing Li, Xiaoyu Yang, JEON SEUNGJUNE, ALROD IDAN, LI QING, YANG XIAOYU
Принадлежит: Sandisk Technologies Inc., SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.

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Номер записи: 84
02-05-2017 дата публикации

System and method of using multiple read operations

Номер: US0009640270B2
Автор: Idan Alrod, Eran Sharon, ALROD IDAN, SHARON ERAN, Alrod Idan, Sharon Eran
Принадлежит: SANDISK TECHNOLOGIES LLC, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

Systems and methods are described for reading a storage element of a memory. In a particular embodiment, a method, in a data storage device including a controller and a non-volatile memory, where the non-volatile memory includes a plurality of storage elements, includes performing multiple read operations at a storage element of the non-volatile memory. Each read operation of the multiple read operations is performed using the same reading voltage. The method further includes determining a read value of the storage element based on the multiple read operations.

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Номер записи: 85
31-12-2009 дата публикации

GAIN CONTROL FOR READ OPERATIONS IN FLASH MEMORY

Номер: US20090323422A1
Автор: Idan Alrod, Eran Sharon
Принадлежит:

A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach, M-quantized threshold voltage values are multiplied by a gain to obtain gain-adjusted threshold voltage values, which are quantized by an L-level quantizer, where L Подробнее

Номер записи: 86
12-04-2016 дата публикации

Systems and methods of storing data

Номер: US0009311969B2
Автор: Eran Sharon, Idan Alrod, Menahem Lasser, SHARON ERAN, ALROD IDAN, LASSER MENAHEM
Принадлежит: SANDISK TECHNOLOGIES INC., SHARON ERAN, ALROD IDAN, LASSER MENAHEM, SANDISK TECHNOLOGIES INC

A method of writing data is performed in a data storage device with a controller and a memory. The memory includes latches and multiple storage elements and is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements. The method includes loading data bits into the latches within the memory and generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations. The method also includes storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping. The designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states. The second mapping is different than the first mapping.

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Номер записи: 87
22-09-2022 дата публикации

Storage System and Method for Using Subcodes and Convolutional-Based LDPC Interleaved Coding Schemes with Read Threshold Calibration Support

Номер: US20220300369A1
Автор: Eran Sharon, Idan Goldenberg, Idan Alrod, Ran Zamir, Alexander Bazarsky
Принадлежит: Western Digital Technologies, Inc.

A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern. 1. A storage system comprising:a memory; and store each subcode of a plurality of subcodes in a different page of a word line in the memory; and', 'generate a low-density parity check (LDPC) code from the plurality of subcodes stored in the different pages of the word line in the memory., 'a controller coupled to the memory and configured to2. The storage system of claim 1 , wherein the plurality of subcodes are stored in a same plane in the memory.3. The storage system of claim 1 , wherein the plurality of subcodes are stored in different planes in the memory.4. The storage system of claim 3 , wherein the plurality of subcodes are stored in a checkerboard pattern in the different planes in the memory.5. The storage system of claim 1 , wherein the controller is further configured to calibrate a read threshold for a page of the memory.6. The storage system of claim 5 , wherein the calibration is done using a subcode stored on the page being calibrated claim 5 , and wherein the calibration is done based on subcode bits that are stored on the page and a set of parity check equations that involve solely the subcode bits.7. The storage system of claim 5 , wherein the calibration is done using a histogram.8. The storage system of claim 1 , wherein the controller is further configured to store interleaved codewords and non-interleaved codewords in the memory.9. The storage system of claim 8 , wherein the interleaved codewords and the non-interleaved codewords are stored in different word lines claim 8 , different word line zones claim 8 , or different blocks in the memory.10. The storage system of claim 8 , wherein ...

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Номер записи: 88
12-04-2022 дата публикации

Data shaping for integrated memory assembly

Номер: US0011301321B2
Автор: Eran Sharon, Idan Alrod
Принадлежит: Western Digital Technologies, Inc., WESTERN DIGITAL TECHNOLOGIES, INC.

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly comprises a memory die bonded to a control die with bond pads. The control die includes one or more control circuits for controlling the operation of the memory die. The one or more control circuits are configured to receive data to be programmed into the memory die, select a number of parity bits, encode the data to add error correction information and form a codeword that includes the number of parity bits, shape the codeword, and program the shaped codeword into the memory die.

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Номер записи: 89
19-01-2016 дата публикации

Systems and methods for managing data in a system for hibernation states

Номер: US0009239610B2
Автор: Yair Baram, Hanan Borukhov, Idan Alrod, Eran Sharon, BARAM YAIR, BORUKHOV HANAN, ALROD IDAN, SHARON ERAN
Принадлежит: SanDisk Technologies Inc., BARAM YAIR, BORUKHOV HANAN, ALROD IDAN, SHARON ERAN, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor. The processor is configured to manage data storage in conjunction with hibernation of the memory device. The processor is in communication with the controller memory, the main memory and the buffer, and is configured to read data from the controller memory; write at least a portion of the data read from the controller memory into the buffer prior to the memory device entering a hibernation state; and after writing the at least a portion of the data read from the controller memory into the buffer and prior to the memory device entering the hibernation state, reduce an amount of power provided to the buffer of the to a reduced power level.

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Номер записи: 90
14-03-2017 дата публикации

Resistance-based memory with auxiliary redundancy information

Номер: US0009595353B2
Автор: Idan Alrod, Eran Sharon, ALROD IDAN, SHARON ERAN, Alrod Idan, Sharon Eran
Принадлежит: SANDISK TECHNOLOGIES LLC, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A data storage device includes a resistance-based memory. A method includes storing a codeword into a first set of storage elements of the resistance-based memory. The codeword represents data to be stored, and the codeword includes first redundancy information associated with the data. The method further includes storing auxiliary redundancy information into a second set of storage elements of the resistance-based memory. The auxiliary redundancy information is associated with the data. The method further includes discarding the auxiliary redundancy information from the second set of storage elements while retaining the first redundancy information at the first set of storage elements.

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Номер записи: 91
12-08-2014 дата публикации

Multi-bit-per-cell flash memory device with non-bijective mapping

Номер: US0008804423B2
Автор: Simon Litsyn, Eran Sharon, Idan Alrod
Принадлежит: Ramot at Tel-Aviv University Ltd.

To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

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Номер записи: 92
27-01-2022 дата публикации

ON-CHIP-COPY FOR INTEGRATED MEMORY ASSEMBLY

Номер: US20220028475A1
Автор: Eran Sharon, Idan Alrod
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data. 1. A method , comprising:transferring codewords that are stored in non-volatile memory cells on a memory die to a control die bonded to the memory die, the codewords are stored in the non-volatile memory cells on the memory die as single bit per memory cell data;on the control die, decoding the transferred codewords to identify one or more errors;on the control die, fixing the identified errors in the codewords; andafter fixing the identified errors in the codewords, programming the codewords to the memory die as multiple bit per memory cell data such that multiple non-volatile memory cells of the memory die store data from multiple codewords.2. The method of claim 1 , wherein:the programming the codewords comprises programming using a multi-pass programming process;the multi-pass programming process comprises programming a first subset of the codewords during a first pass of the multi-pass programming process and programming a second subset of the codewords during a later pass of the multi-pass programming process that is subsequent to the first pass; andthe decoding the transferred codewords comprises decoding the second subset of the codewords on the ...

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Номер записи: 93
24-05-2016 дата публикации

System and method of storing redundancy data

Номер: US0009348695B2
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: SANDISK TECHNOLOGIES INC., SANDISK TECHNOLOGIES INC

A data storage device includes a controller operatively coupled to a non-volatile memory. The non-volatile memory includes a plurality of blocks. When the controller is configured to operate according to a first mode, a portion of a first redundancy block of the plurality of blocks stores first redundancy data corresponding to a first group of multiple data portions. The multiple data portions stored in multiple blocks of the plurality of blocks. When the controller is configured to operate according to a second mode, the portion of the first redundancy block stores second redundancy data corresponding to a single block of the plurality of blocks.

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Номер записи: 94
20-11-2012 дата публикации

Device and method to read data subject to a disturb condition

Номер: US0008315091B2
Автор: Eran Sharon, Idan Alrod, SHARON ERAN, ALROD IDAN
Принадлежит: Sandisk IL Ltd., SHARON ERAN, ALROD IDAN, SANDISK IL LTD, SANDISK IL LTD.

A storage device includes a plurality of memory elements and a controller. The controller is configured to receive measured characteristics of the memory elements. The measured characteristics correspond to a plurality of values including a first value stored at a first memory element of the plurality of memory elements and a second value stored at a second memory element of the plurality of memory elements. The controller is configured to test whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the first memory element. The controller is configured to provide a data value corresponding to the first memory element, where the data value is determined at least in part based on a result of the test.

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Номер записи: 95
27-08-2009 дата публикации

PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY

Номер: US20090217131A1
Автор: Simon LITSYN, Idan Alrod, Eran Sharon, Mark Murin, Menahem Lasser
Принадлежит: Ramot At Tel Aviv University Ltd.

Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

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Номер записи: 96
04-02-2014 дата публикации

Multi-phase ECC encoding using algebraic codes

Номер: US0008645789B2
Автор: Eran Sharon, Idan Alrod, Simon Litsyn, SHARON ERAN, ALROD IDAN, LITSYN SIMON
Принадлежит: Sandisk Technologies Inc., SHARON ERAN, ALROD IDAN, LITSYN SIMON, SANDISK TECHNOLOGIES INC, SANDISK TECHNOLOGIES INC.

A method includes a first encoding operation associated with a first algebraic error correcting code generating a first set of first parity bits corresponding to a first set of information bits and a second set of first parity bits corresponding to a second set of information bits. A second encoding operation associated with a second algebraic error correcting code generates a first set of second parity bits corresponding to the first set of information bits and a second set of second parity bits corresponding to the second set of information bits. A third encoding operation generates a set of joint parity bits. The first set of information bits, the second set of information bits, the first set of first parity bits, the second set of first parity bits, and the joint parity bits may be stored in a data storage device as a single codeword.

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Номер записи: 97
22-10-2002 дата публикации

Method for increasing information content in a computer memory

Номер: US0006469931B1
Автор: Amir Ban, Simon Litsyn, Idan Alrod, BAN AMIR, LITSYN SIMON, ALROD IDAN
Принадлежит: M-Systems Flash Disk Pioneers Ltd., MILSYS LTD, M-SYSTEMS FLASH DISK PIONEERS LTD.

A method for increasing information capacity in nominally m-bit-per-cell Flash technology, using advanced coding techniques and changes in the Flash array interface, without increasing the basic cell size or the bit read failure rate. The increase in information capacity is obtained by using a number n, greater than 1, of memory cells, each cell having a respective adjustable parameter, setting the parameters to collectively represent a binary number of b bits, b being greater than nm, measuring the parameters and decoding the measured parameters collectively to recover the number.

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Номер записи: 98
12-11-2019 дата публикации

Soft bit techniques for a data storage device

Номер: US0010474525B2
Автор: Eran Sharon, Ariel Navon, Idan Alrod, Alexander Bazarsky, SHARON ERAN, NAVON ARIEL, ALROD IDAN, BAZARSKY ALEXANDER, Sharon, Eran, Navon, Ariel, Alrod, Idan, Bazarsky, Alexander
Принадлежит: SANDISK TECHNOLOGIES LLC

A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.

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Номер записи: 99
25-10-2022 дата публикации

ECC in integrated memory assembly

Номер: US0011482296B2
Автор: Idan Alrod, Eran Sharon
Принадлежит: SanDisk Technologies LLC

Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory controller. By not sending the parity bits to the memory controller, substantial bandwidth is saved. Also, substantial power may be saved. For example, the interface between the control die and the memory controller could be a high speed interface.

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Номер записи: 100
29-03-2012 дата публикации

METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES

Номер: US20120079178A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит:

To store bits in one or more cells, an adaptive mapping of bits to ranges of a physical parameter of the cell(s) is provided, in accordance with respective initial values of the physical parameter, by steps including encoding the bits as a codeword by partitioning the bits into subsets and finding a factor bit string such that the codeword is a concatenation of the factor bit string and separate Galois field products of all the subsets with the factor bit string. The initial values of the physical parameter are adjusted accordingly as needed. 1. A method of storing a plurality of bits in at least one memory cell , comprising:(a) providing, in accordance with a respective initial value of a physical parameter of each of the at least one memory cell, an adaptive mapping of the bits to physical parameter ranges for storing the bits in the at least one memory cell, by steps including encoding the bits as a codeword by partitioning the bits into a plurality of subsets and finding a factor bit string such that the codeword is a concatenation of the factor bit string and separate Galois field products of all the subsets with the factor bit string; and(b) for each of the at least one memory cell, if, according to the adaptive mapping, the respective initial value of the physical parameter of the each memory cell needs to be adjusted in order for the bits to be stored in the at least one memory cell: adjusting the respective initial value of the physical parameter of the each memory cell in accordance with the adaptive mapping.2. The method of claim 1 , wherein the physical parameter is a threshold voltage.3. The method of claim 1 , wherein the adjusting of the respective value of the physical parameter of the each memory cell includes adjusting the respective value of the physical parameter of the each memory cell so that the each memory cell stores a respective at least portion of the codeword.4. The method of claim 1 , wherein all the subsets have equal numbers of the ...

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Номер записи: 101
28-06-2012 дата публикации

Method For Page- And Block Based Scrambling In Non-Volatile Memory

Номер: US20120163605A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит:

A method and system for programming and reading data with reduced read errors in a memory device. In one approach, date to be written to the memory device is scrambled using a first pseudo random number which is generated based on a number of a page of the memory device to which the data is to be written and a second pseudo random number which is generated based on a number of a block of the memory device to which the data is to be written. This avoids bit line-to-bit line and block-to-block redundancies which can result in read errors. The data may also be scrambled based on a number of a section within a page. 1. A method of writing data into a page of a flash memory device , where the pages of the flash memory device are grouped into blocks that are each erasable as a single unit , the method comprising:receiving data to be stored in the page;generating a first number that depends on a block number of the block containing the page;generating a second number that depends on a number of the page within the block containing the page;scrambling the data to generate scrambled data, where the scrambling depends on the first number and the second number; andwriting the scrambled data into the page.2. The method of claim 1 , wherein the scrambled data is an XOR of the received data claim 1 , the first number and the second number.3. The method of claim 1 , wherein the first number depends on the block number of the block containing the page claim 1 , but not on the page number within the block.4. The method of claim 1 , wherein the second number depends nonlinearly on the number of the page within the block containing the page.5. The method of claim 1 , wherein the page comprises multiple sections claim 1 , and the scrambling depends on a number of a section within the page.6. The method of claim 5 , wherein the dependency on the number of the section within the page is nonlinear.7. The method of claim 1 , wherein the first and second numbers are pseudo random numbers. ...

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Номер записи: 102
06-09-2012 дата публикации

System and method of decoding data from memory based on sensing information and decoded data of neighboring storage elements

Номер: US20120224421A1
Автор: Eran Sharon, Idan Alrod, Simon Litsyn
Принадлежит: SanDisk Technologies LLC

Systems and methods to decode data stored in a data storage device are disclosed. Data bits stored in a first group of storage elements are decoded using data in a second group of storage elements together with physical characteristics of the second group of storage elements to aid in the decoding of the first group of storage elements.

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Номер записи: 103
01-11-2012 дата публикации

METHOD OF DATA STORAGE IN NON-VOLATILE MEMORY

Номер: US20120278687A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: SANDISK IL LTD.

A method of storing a set of metadata bits associated with each of multiple data words includes combining the set of metadata bits with each of the multiple data words to generate multiple extended data words. The method includes encoding each of the multiple extended data words to generate multiple codewords and puncturing each of the multiple codewords to generate multiple punctured codewords, where in each of the punctured codewords the set of metadata bits is removed. The method includes storing the multiple punctured codewords, transforming the set of metadata bits to generate a set of transformed metadata bits, and storing the set of transformed metadata bits. 1. A method of storing a set of metadata bits associated with each of multiple data words , the method comprising:combining the set of metadata bits with each of the multiple data words to generate multiple extended data words;encoding each of the multiple extended data words to generate multiple codewords;puncturing each of the multiple codewords to generate multiple punctured codewords, wherein in each of the punctured codewords the set of metadata bits is removed;storing the multiple punctured codewords at a storage device;transforming the set of metadata bits to generate a set of transformed metadata bits; andstoring the set of transformed metadata bits at the storage device.2. The method of claim 1 , wherein a transformation is applied to at least one of the multiple extended data words claim 1 , and wherein the transformation is a function of said set of metadata bits.3. The method of claim 2 , wherein the transformation is a scrambling transformation claim 2 , and wherein the set of metadata bits or a function of said set of metadata bits is a seed for the scrambling transformation.4. The method of claim 1 , wherein the transforming of the set of metadata bits includes encoding the set of metadata bits with an error correction code.5. The method of claim 1 , wherein the transforming of the set of ...

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Номер записи: 104
24-01-2013 дата публикации

SYSTEMS AND METHODS OF STORING DATA

Номер: US20130024605A1
Автор: ALROD IDAN, LASSER MENAHEM, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method of writing data is performed in a data storage device with a controller and a memory. The memory includes latches and multiple storage elements and is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements. The method includes loading data bits into the latches within the memory and generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations. The method also includes storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping. The designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states. The second mapping is different than the first mapping. 1. A method of writing data , the method comprising: loading data bits into the latches within the memory;', 'generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations; and', 'storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping,', 'wherein the designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states, the second mapping different than the first mapping., 'in a data storage device with a controller and a memory, wherein the memory includes latches and multiple storage elements and wherein the memory is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements, performing2. The method of claim 1 , wherein the latches and the storage elements are within a memory die that is configured to apply the first mapping as a built-in mapping and wherein the second mapping is ...

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Номер записи: 105
24-01-2013 дата публикации

SYSTEMS AND METHODS OF STORING DATA

Номер: US20130024743A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method of reading data in a data storage device with a controller and a memory includes generating, in the memory, a set of bits corresponding to a particular storage element of the memory. The set of bits indicates a group of threshold voltage intervals. A threshold voltage of the particular storage element corresponds to one of the threshold voltage intervals within the group. At least one threshold voltage interval within the group is separated from another threshold voltage interval within the group by an intervening threshold voltage interval that is not within the group. The method also includes sending the set of bits to the controller. The set of bits includes a first hard bit that corresponds to a value read from the particular storage element and a first soft bit that corresponds to a reliability measure. 1. A method of reading data , the method comprising: generating, in the memory, a set of bits corresponding to a particular storage element, wherein the set of bits indicates a group of threshold voltage intervals, wherein a threshold voltage of the particular storage element corresponds to one of the threshold voltage intervals within the group, and wherein at least one threshold voltage interval within the group is separated from another threshold voltage interval within the group by an intervening threshold voltage interval that is not within the group; and', 'sending the set of bits to the controller, wherein the set of bits includes a first hard bit that corresponds to a value read from the particular storage element and a first soft bit that corresponds to a reliability measure., 'in a data storage device with a controller and a memory, the memory including multiple storage elements, performing'}2. The method of claim 1 , wherein the particular storage element is within a physical page of the memory claim 1 , wherein the physical page includes a first logical page and a second logical page claim 1 , and wherein a state of the particular storage ...

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Номер записи: 106
24-01-2013 дата публикации

MEMORY-EFFICIENT LDPC DECODING

Номер: US20130024745A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит: RAMOT AT TEL AVIV UNIVERSITY LTD.

To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes. 1. A memory controller comprising:(a) an encoder for encoding K information bits as a codeword of N>K codeword bits; and(b) a decoder including:(i) a read/write memory; and(ii) at least one processor for decoding the representation of the codeword by executing an algorithm for, in a graph that includes N bit nodes and N−K check nodes, each bit node being connected to at least one check node by a respective edge, there being E edges in total, exchanging messages between the bit nodes and the check nodes that are so connected to each other, while storing fewer than E of the messages in the read/write memory at any time during the exchanging of the messages.2. The memory controller of claim 1 , further comprising:(c) circuitry for storing at least a portion of the codeword in a main memory and for retrieving a representation of the at least portion of the codeword from the main memory.3. The memory controller of claim 2 , wherein the circuitry stores all of the codeword in the main memory and retrieves a representation of all of the codeword from the main memory.4. The memory controller of claim 2 , wherein the circuitry stores only a portion of the ...

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Номер записи: 107
24-01-2013 дата публикации

SYSTEMS AND METHODS OF STORING DATA

Номер: US20130024746A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method of storing data includes receiving data including a first group of bits and a second group of bits and initiating a shaping encoding operation on the second group of bits to generate a third group of bits. The third group of bits has more bits than the second group of bits. The shaping encoding operation is configured to produce a non-uniform probability distribution of bit values in the third group of bits. The first group of bits and first error correction coding (ECC) parity bits corresponding to the first group of bits are stored to a first logical page that is within a physical page of a MLC memory and the third group of bits and second ECC parity bits corresponding to the third group of bits are stored to a second logical page that is within the physical page of the MLC memory. 1. A method of writing data , the method comprising: receiving data including a first group of bits and a second group of bits;', 'initiating a shaping encoding operation on the second group of bits to generate a third group of bits, wherein the third group of bits has more bits than the second group of bits and wherein the shaping encoding operation is configured to produce a non-uniform probability distribution of bit values in the third group of bits; and', 'storing the first group of bits and first error correction coding (ECC) parity bits corresponding to the first group of bits to a first logical page that is within a physical page of the MLC memory and storing the third group of bits and second ECC parity bits corresponding to the third group of bits to a second logical page that is within the physical page of the MLC memory., 'in a data storage device with a flash multi-level cell (MLC) memory, performing2. The method of claim 1 , wherein the first logical page is associated with a first error rate and the second logical page is associated with a second error rate that is less than the first error rate.3. The method of claim 1 , wherein the first ECC parity bits include ...

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Номер записи: 108
24-01-2013 дата публикации

SYSTEMS AND METHODS OF STORING DATA

Номер: US20130024747A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page. 1. A method of writing data , the method comprising: receiving a data page to be stored in the data storage device;', 'initiating an encode operation to encode the data page, wherein the encode operation generates first encoded data;', 'storing a first portion of the first encoded data to the first physical page;', 'initiating storage of a second portion of the first encoded data to the second physical page; and', 'initiating a decode operation to recover the data page, wherein the decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page., 'in a data storage device with multiple physical pages including a first physical page and a second physical page, performing2. The method of claim 1 , wherein the data page is received from a host device while the data storage device is operatively coupled to the host device.3. The method of claim 2 , further comprising sending a message to the host device in response to storing the first portion of the first encoded data claim 2 , the message indicating that the data page has been successfully stored at the data storage device claim 2 , and wherein the message is sent prior to completing storage of ...

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Номер записи: 109
24-01-2013 дата публикации

SYSTEMS AND METHODS OF STORING DATA

Номер: US20130024748A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method of writing data includes receiving data pages to be stored in a data storage device and generating codewords corresponding to the received data pages. The codewords are stored to physical pages of a first memory portion of the data storage device. A first portion of a particular codeword that corresponds to a particular data page is stored at a first physical page of the first memory portion. A second portion of the particular codeword is stored at a second physical page of the first memory portion. The codewords are copied from the physical pages of the first memory portion to a physical page of a second memory portion of the data storage device. 1. A method for writing data , the method comprising: receiving data pages to be stored in the data storage device;', 'generating codewords corresponding to the received data pages;', 'storing the codewords to physical pages of a first memory portion of the data storage device, wherein a first portion of a particular codeword that corresponds to a particular data page is stored at a first physical page of the first memory portion and wherein a second portion of the particular codeword is stored at a second physical page of the first memory portion; and', 'copying the codewords from the physical pages of the first memory portion to a physical page of a second memory portion of the data storage device., 'in a data storage device, performing2. The method of claim 1 , wherein the particular codeword is a concatenated codeword that includes multiple sub-codes and joint parity of the multiple sub-codes.3. The method of claim 2 , wherein each of the multiple sub-codes includes a sub-code data portion and a sub-code parity portion claim 2 , wherein the first portion of the particular codeword includes the sub-code data portions and wherein the second portion of the particular codeword includes the joint parity.4. The method of claim 3 , wherein generating and storing the multiple sub-codes and the joint parity enables ...

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Номер записи: 110
31-01-2013 дата публикации

Simultaneous Sensing of Multiple Wordlines and Detection of NAND Failures

Номер: US20130028021A1
Автор: ALROD IDAN, Lee Dana, Li Yan, SHARON ERAN
Принадлежит:

Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed. 1. A method of operating a memory device including a plurality of memory cells formed along word lines and bit lines , the method comprising:performing a write operation including the programming of a plurality of memory cells along a corresponding plurality of selected word lines and one or more selected bit lines; and concurrently applying a plurality of first sensing voltages to distinguish between levels of programming to the corresponding plurality of selected word lines; and', 'concurrently performing, for each of the one or more selected bit lines, a first combined sensing operation of the corresponding plurality of memory cells along the plurality of selected word lines while the plurality of first sensing voltages are applied thereto, where the result of the first combined sensing operation is dependent upon the state of the plurality of memory cells along the selected bit line., 'subsequently performing a composite sensing operation, including2. The method of claim 1 , further comprising:performing a comparison of the result of the composite sensing operation with an expected result; andbased upon the comparison, making a determination of the integrity of the sensed memory cells.3. The method of claim 2 , wherein ...

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Номер записи: 111
31-01-2013 дата публикации

Data Recovery for Defective Word Lines During Programming of Non-Volatile Memory Arrays

Номер: US20130031429A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит:

The recovery of data during programming, such as in the case of a broken word-line, is considered. The arrangement described assumes that k pages may be corrupted when the system finishes programming a block. Then these corrupted pages can be recovered using an erasure code. In order to recover any k pages, the system will compute and temporarily store k parity pages in the controller. These k parity pages may be computed on-the-fly as the data pages are received from the host. Once programming of the block is finished, a post-write read may be done in order to validate that the data is stored reliably. If no problem is detected during EPWR, then the parity pages in the controller may be discarded. In case a problem is detected, and data in up to k pages is corrupt on some bad word-lines, then the missing data is recovered using the k parity pages that are stored in the controller and using the other non-corrupted pages that are read from the block of the memory array and decoded. Once the recovery is complete the block can be reprogrammed and the temporary parity pages in the controller may be discarded upon successfully reprogramming. 1. A method of operating a memory system including an array of flash memory cells formed along a plurality of word lines each capable of storing one or more pages of data , the method comprising:receiving a first data page;storing the received first data page in a first buffer;writing the first data page from the first buffer into a corresponding word line of the flash memory;generating a page of parity data for the received first page of data;storing the page of parity data in a second buffer;subsequent to receiving the first data page, sequentially receiving one or more additional pages of data, and for each of additional received page of data;overwriting the preceding page of received data in the first buffer therewith;writing the page of data from the first buffer into a corresponding word line of the flash memory; andupdating ...

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Номер записи: 112
31-01-2013 дата публикации

Post-Write Read in Non-Volatile Memories Using Comparison of Data as Written in Binary and Multi-State Formats

Номер: US20130031431A1
Автор: Eran Sharon, Idan Alrod
Принадлежит: SanDisk Technologies LLC

Techniques for a post-write read are presented. In an exemplary embodiment, host data is initially written into the non-volatile memory in binary form, such as a non-volatile binary cache. It is then subsequently written from the binary section into a multi-state non-volatile section of the memory. After being written in multi-state format, pages of data from a multi-state block can then be checked against there source pages in the binary section to verify the quality of the multi-state write. This process can be performed on the memory device itself, without transferring the pages out to the controller.

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Номер записи: 113
31-01-2013 дата публикации

CHECKSUM USING SUMS OF PERMUTATION SUB-MATRICES

Номер: US20130031440A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method for encoding data bits includes computing checksum parity bits based on the data bits. A set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense parity-check matrix. The dense parity-check matrix comprises sums of permutation sub-matrices. 1. A method comprising: 'computing checksum parity bits based on data bits, wherein a set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense parity-check matrix and wherein the dense parity-check matrix comprises sums of permutation sub-matrices.', 'at a coding unit of a data storage device, performing2. The method of claim 1 , further comprising computing error correction coding (ECC) parity bits based on the data bits and the checksum parity bits claim 1 , wherein a second set of equations satisfied by the data bits claim 1 , the checksum parity bits claim 1 , and the ECC parity bits corresponds to a sparse parity-check matrix.3. The method of claim 1 , wherein the dense parity-check matrix has a density corresponding to a ratio of a number of non-zero elements of the dense parity-check matrix as compared to a total number of elements of the dense parity-check matrix claim 1 , and wherein the ratio exceeds a density threshold.4. The method of claim 3 , wherein the density threshold is approximately 0.4.5. The method of claim 4 , wherein the ratio is less than approximately 0.6.7. The method of claim 6 , further comprising encoding the first encoded data bits using a parity check matrix H claim 6 , wherein H comprises sub-matrices Hof order z×z claim 6 , wherein each of the sub-matrices His either a 0 matrix or a matrix of the form Aand wherein nis an integer.8. The method of claim 6 , wherein A is generated by applying a cyclic permutation to rows or columns of the identity matrix of order z×z.9. The method of claim 6 , wherein lis greater than or equal to c·z and wherein c is a predefined number greater than or equal to 0.4.10. The method ...

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Номер записи: 114
31-01-2013 дата публикации

FAST DETECTION OF CONVERGENCE OR DIVERGENCE IN ITERATIVE DECODING

Номер: US20130031447A1
Автор: ALROD IDAN, FAINZILBER Omer, LITSYN SIMON, NAVON Ariel, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate. 2. The method of claim 1 , further comprising:(c) if the testing of the termination indication indicates that the algorithm has converged, terminating the decoding.3. The method of claim 1 , further comprising:(c) if the testing of the termination indication indicates that the algorithm is likely to not converge, terminating the decoding.4. The method of claim 1 , wherein claim 1 , during each of the at least one iteration claim 1 , the testing of the termination indication is effected whenever a respective estimate of a codeword bit is flipped.5. The method of claim 1 , wherein the computing of the termination indication includes OR-ing all of a plurality of bits of an error correction syndrome.6. The method of claim 1 , wherein the termination indication includes a weight of an error correction syndrome claim 1 , of the estimates of the bits of the codeword claim 1 , that includes a plurality of error correction syndrome bits claim 1 , and wherein the testing includes comparing the weight of the error correction syndrome to a threshold.7. The method of claim 6 , wherein the threshold is zero.8. The method of claim 6 , wherein the computing of the termination indication includes claim 6 , in response to ...

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Номер записи: 115
28-02-2013 дата публикации

System and method of copying data

Номер: US20130055047A1
Автор: Eran Sharon, Idan Alrod
Принадлежит: SanDisk Technologies LLC

A method of copying data includes receiving a command instructing copying of data from a source location in the memory die to a destination location in the memory die. The method includes determining if a criterion is met, including comparing a predefined parameter to a dynamic threshold. In response to determining that the criterion is met, the method includes executing the copying by moving the data from the source location in the memory die to the controller die and, after moving the data to the controller die, moving an error-corrected version of the data from the controller die to the destination location in the memory die. In response to determining that the criterion is not met, the method includes executing the copying by moving the data inside the memory die source location to the destination location without moving the data to the controller die.

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Номер записи: 116
25-04-2013 дата публикации

METHOD FOR SCRAMBLING SHAPED DATA

Номер: US20130101111A1
Автор: ALROD IDAN, NAVON Ariel, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method includes, in a data storage device, receiving data having a particular proportion of zero values and one values and scrambling the data to generate scrambled data that has the particular proportion of zero values and one values. 1. A method comprising: receiving data having a particular proportion of zero values and one values; and', 'scrambling the data to generate scrambled data that has the particular proportion of zero values and one values., 'in a data storage device, performing2. The method of claim 1 , wherein for any received data claim 1 , the scrambled data has the same proportion of zero values and one values as the received data.3. The method of claim 1 , wherein the data has a length Q and wherein scrambling the data includes copying bits at non-sequential bit positions in the data to sequential bit positions in the scrambled data.4. The method of claim 3 , wherein a distance P between the non-sequential bit positions is prime to Q.5. The method of claim 4 , wherein each bit position k in the scrambled data has a same bit value as a bit position (k−1)P (mod Q) in the data.6. The method of claim 4 , further comprising selecting a particular value of the distance P and selecting a starting bit position in the data.7. The method of claim 1 , wherein scrambling the data includes copying a first group of bits from a first group position in the data to a second group position in the scrambled data claim 1 , wherein the first group position is different from the second group position.8. The method of claim 7 , wherein scrambling the data includes copying a second group of bits from the data to the scrambled data claim 7 , wherein the first group of bits and the second group of bits are copied from non-sequential group positions in the data to sequential group positions in the scrambled data.9. The method of claim 7 , wherein scrambling the data further includes shifting bits within the first group of bits.10. The method of claim 7 , wherein scrambling ...

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Номер записи: 117
25-04-2013 дата публикации

ENDURANCE ENHANCEMENT CODING OF COMPRESSIBLE DATA IN FLASH MEMORIES

Номер: US20130103891A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

Methods described in the present disclosure may be based on a direct transformation of original data to “shaped” data. The disclosed methods may be performed “on-the-fly” and the disclosed methods may utilize an inherent redundancy in compressible data in order to achieve endurance enhancement and error reduction. In a particular example, a method comprises generating a first portion of output data by applying a mapping of input bit sequences to output bit sequences to a first portion of input data, updating the mapping of the input bit sequences to the output bit sequences based on the first portion of the input data to generate an updated mapping, reading a second portion of the input data, and generating a second portion of the output data by applying the updated mapping of the input bit sequences to the output bit sequences to the second portion of the input data. 1. A method of storing data , the method comprising: selecting, in accordance with an input string of multiple m-tuples of bits, a substitution transformation to apply to the input string, wherein m is an integer greater than 1;', 'applying the selected substitution transformation to the input string to generate a transformed string of multiple output m-tuples of bits; and', 'programming K storage elements of the memory to store the transformed string in the K storage elements, each of the K storage elements storing L bits, wherein L is not equal to m., 'in a data storage device including a memory, performing2. The method of claim 1 , wherein the memory includes a flash memory claim 1 , and wherein each of the K storage elements is a memory cell of the flash memory.3. The method of claim 1 , wherein the memory is operative to selectively program each of the K storage elements to represent each binary number from 0 through 2−1 as a respective one of 2states of each of the K storage elements claim 1 , and wherein the substitution transformation is selected to cause a distribution of respective states of ...

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Номер записи: 118
23-05-2013 дата публикации

INTERRUPTION CRITERIA FOR BLOCK DECODING

Номер: US20130132791A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит: RAMOT AT TEL AVIV UNIVERSITY LTD.

While decoding a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, by updating estimates of the codeword bits in a plurality of iterations, the iterations are interrupted upon satisfaction of an interruption criterion that is either an order-dependent interruption criterion or an interruption criterion that includes an estimate of mutual information of the codeword and a vector that is used in the decoding iterations. Either the iterations are terminated or the iterations are resumed after one or more elements of one or more vectors used in the iterations is/are modified. 122.-. (canceled)23. A method of decoding a representation of a codeword that encodes K information bits as N>K codeword bits , the method comprising:(a) importing the representation of the codeword from a channel;(b) in a plurality of decoding iterations, updating estimates of the codeword bits; and(c) interrupting the decoding iterations if an interruption criterion, that includes an estimate of mutual information between the codeword and a vector that is used in the decoding iterations, is satisfied.24. The method of claim 23 , wherein the updating includes claim 23 , in a graph that includes N bit nodes and N−K check nodes claim 23 , exchanging messages between the bit nodes and the check nodes.25. The method of claim 24 , wherein the interrupting includes modifying at least one element of at least one vector associated with the decoding and then resuming the decoding iterations.27. The method of claim 23 , wherein the updating includes claim 23 , in a parity check matrix that includes N−K rows and N columns claim 23 , exchanging messages between the rows and the columns.28. The method of claim 27 , wherein the interrupting includes modifying at least one element of at least one vector associated with the decoding and then resuming the decoding iterations.29. The method of claim 23 , wherein the interrupting is terminating the decoding ...

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Номер записи: 119
27-06-2013 дата публикации

USING ECC ENCODING TO VERIFY AN ECC DECODE OPERATION

Номер: US20130166986A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method includes initiating a decoding operation of a first portion of a codeword to generate a set of data bits. The first portion includes first parity bits and is associated with a first error correcting code. The method includes initiating an encoding operation of the set of data bits according to a second error correcting code to generate computed parity bits. The method includes comparing the computed parity bits to a second portion of the codeword to determine a number of bits that differ between the computed parity bits and the second portion of the codeword. The method also includes generating an indication of successful decoding in response to the number of bits that differ being less than a threshold value. 1. A method comprising: initiating a decoding operation of a first portion of a codeword representation to generate a set of data bits, wherein the first portion includes first parity bits and wherein the first portion is associated with a first error correcting code;', 'initiating an encoding operation of the set of data bits according to a second error correcting code to generate computed parity bits;', 'comparing the computed parity bits with a second portion of the codeword representation to determine a number of bits that differ between the computed parity bits and the second portion of the codeword representation; and', 'generating one of an indication of successful decoding and an indication of unsuccessful decoding, wherein the indication of successful decoding is generated in response to the number of bits that differ being less than a threshold value, and wherein the indication of unsuccessful decoding is generated in response to at least one of the decoding operation failing and the number of bits that differ equaling or exceeding the threshold value., 'at a data storage device, performing2. The method of claim 1 , wherein the threshold value is a predefined value.3. The method of claim 2 , wherein the threshold value is greater than one.4. ...

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Номер записи: 120
27-06-2013 дата публикации

MULTI-PHASE ECC ENCODING USING ALGEBRAIC CODES

Номер: US20130166988A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method includes a first encoding operation associated with a first algebraic error correcting code generating a first set of first parity bits corresponding to a first set of information bits and a second set of first parity bits corresponding to a second set of information bits. A second encoding operation associated with a second algebraic error correcting code generates a first set of second parity bits corresponding to the first set of information bits and a second set of second parity bits corresponding to the second set of information bits. A third encoding operation generates a set of joint parity bits. The first set of information bits, the second set of information bits, the first set of first parity bits, the second set of first parity bits, and the joint parity bits may be stored in a data storage device as a single codeword.

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Номер записи: 121
07-11-2013 дата публикации

READING DATA FROM MULTI-LEVEL CELL MEMORY

Номер: US20130294157A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method at a data storage device includes determining a first hard bit of a first logical page, the first hard bit corresponding to a particular cell of the MLC memory. A second hard bit of a second logical page is sensed. The second hard bit corresponds to the particular cell. The first hard bit is used as a soft bit of the second logical page to provide reliability information during a decode operation of the second logical page. 1. A method comprising: determining a first hard bit of a first logical page, the first hard bit corresponding to a particular cell of the MLC memory;', 'sensing a second hard bit of a second logical page, the second hard bit corresponding to the particular cell; and', 'using the first hard bit as a soft bit of the second logical page to provide reliability information during a decode operation of the second logical page., 'in a data storage device having a multi-level cell (MLC) memory, performing2. The method of claim 1 , wherein using the first hard bit as the soft bit of the second logical page includes determining a reliability indicator for the second hard bit as a function of a value of the first hard bit.3. The method of claim 2 , wherein the reliability indicator is determined by using the value of the first hard bit as an index to a table lookup operation.4. The method of claim 2 , wherein the reliability indicator is determined according to a logical function of one or more hard bit values of the particular cell.5. The method of claim 2 , wherein the reliability indicator is determined at least partially based on a difference between a sensed value of the first hard bit and a decoded value of the first hard bit.6. The method of claim 1 , further comprising:sensing a third hard bit of a third logical page, the third hard bit corresponding to the particular cell; andusing the first hard bit as a soft bit of the third logical page.7. The method of claim 1 , wherein the first hard bit is determined prior to initiating the decoding ...

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Номер записи: 122
21-11-2013 дата публикации

NON-VOLATILE MEMORY AND METHODS WITH SOFT-BIT READS WHILE READING HARD BITS WITH COMPENSATION FOR COUPLING

Номер: US20130308381A1
Автор: ALROD IDAN, Hemink Gerrit Jan, Miwa Toru, Mokhlesi Nima, Sharon Eron
Принадлежит: SANDISK IL LTD.

A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”. 1. In a nonvolatile memory have memory cells accessible by word lines , said memory cells individually having threshold voltages each programmable into one of a first set of threshold voltage bands in a threshold window partitioned by a first set of reference thresholds , the first set of threshold voltage bands codable by a first set of bits , a method of reading a current group of memory cells on a current word line , comprising:sensing the programmed threshold voltages of an adjacent group of memory cells on an adjacent word line to determine coupling levels due to charges stored in neighboring memory cells on individual memory cells in the current group on the current word line, the coupling levels including a nominal coupling level corresponding to insignificant charges from neighboring memory cells;sensing the current group of memory cells by permuting a current word line voltage selected from the first set of reference thresholds and an adjacent word line voltage selected from a set of bias voltages obtained as a function of different associated coupling levels;obtaining the first set of bits when the bias voltage during the permutation corresponds to a nominal coupling level;obtaining a second set of bits when the bias voltage during the permutation corresponds to other than the nominal coupling level.2. The method as in ...

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Номер записи: 123
06-03-2014 дата публикации

DIRECT MULTI-LEVEL CELL PROGRAMMING

Номер: US20140063939A1
Автор: ALROD IDAN, Li Yan, Marcu Alon, Oshinsky Hadas, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage. 1. A method comprising: sending data from the controller to the non-volatile memory;', 'storing first bits corresponding to a first portion of the data into the group of storage elements during a first write stage, wherein each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage;', 'sending second bits corresponding to a second portion of the data to a second memory without sending the first bits to the second memory; and', 'retrieving the second bits from the second memory and storing at least the second bits into the group of storage elements during a second write stage., 'in a data storage device that includes a controller coupled to a non-volatile memory, the non-volatile memory including a group of storage elements, wherein each storage element is configured to store multiple data bits, performing2. The method of claim 1 , further comprising claim 1 , after storing the first bits into the group of storage elements claim 1 , sending third bits corresponding to a third portion of the data to a third memory without sending the first bits to ...

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Номер записи: 124
13-03-2014 дата публикации

NON-VOLATILE STORAGE WITH JOINT HARD BIT AND SOFT BIT READING

Номер: US20140071761A1
Автор: ALROD IDAN, Koh Yee Lih, Kuo Tien-Chien, Li Yan, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A system is disclosed for reading hard bit information and soft bit information from non-volatile storage. Some of the hard bit information and/or soft bit information is read concurrently by using different bit line voltages, different integration times, different sense levels within the sense amplifiers, or other techniques. A method is disclosed for determining the hard bits and soft bits in real time based on sensed hard bit information and soft bit information. 1. A method for reading hard bits and soft bits from non-volatile storage , comprising:applying a set of word line voltages to a word line connected to a plurality of non-volatile storage elements, each word line voltage is associated with a plurality of comparison voltages that are lower than comparison voltages for higher word line voltages and higher than comparison voltages for lower word line voltages;while applying each of the word line voltages to the word line, sensing the plurality of non-volatile storage elements at comparison voltages associated with the applied word line voltage before applying a next word line voltage of the set; andcomputing hard bits and soft bits as a function of the sensing.2. The method of claim 1 , wherein sensing the plurality of non-volatile storage elements at comparison voltages associated with the applied word line voltage comprises:sensing at least two comparison voltages concurrently.3. The method of claim 2 , wherein sensing at least two comparison voltages concurrently comprises:sensing a first subset of the non-volatile storage elements connected to the word line for a first comparison voltage while a first voltage is applied to bit lines for the first subset of the non-volatile storage elements and a particular word line voltage is applied to the word line; andsensing a second subset of the non-volatile storage elements connected to the word line for a second comparison voltage while a second voltage is applied to bit lines for the second subset of the non- ...

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Номер записи: 125
02-01-2020 дата публикации

SYSTEM AND METHOD FOR PREDICTION OF READ COMMANDS TO NON-SEQUENTIAL DATA

Номер: US20200004432A1
Автор: ALROD IDAN, NAVON Ariel, SHARON ERAN
Принадлежит:

Systems and methods for predicting read commands and pre-fetching data when a memory device is receiving random read commands to non-sequentially addressed data locations are disclosed. A limited length sequence of prior read commands is generated and that search sequence is then converted into an index value in a predetermined set of index values. A history pattern match table having entries indexed to that predetermined set of index values contains prior read commands that have previously followed the search sequence represented by the index value. The index value is obtained via application of a many-to-one algorithm to the search sequence. The index value obtained from the search sequence may be used to find, and pre-fetch data for, a next read command in the table that previously followed a search sequence having that index. 1. A method for predicting random read commands , the method comprising:receiving, at a memory device, a current read command for data located at a starting address discontiguous with an address range associated with a last read command received prior to the current read command;generating, with a controller of the memory device, a search sequence comprising a plurality of prior read commands including at least the current read command and the last read command;calculating, with the controller, based on the search sequence, an index value within a predetermined range of index values, the calculated index value representative of the search sequence;retrieving, from an entry in a prior read command data structure stored in a first memory of the memory device and indexed by the calculated index value, data representative of a historical next read command associated with the calculated index value; andpre-fetching data from a second memory of the memory device to the first memory of the memory device based on the retrieved data representative of the historical next read command.2. The method of claim 1 , further comprising the controller claim ...

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Номер записи: 126
02-01-2020 дата публикации

System and method for prediction of multiple read commands directed to non-sequential data

Номер: US20200004540A1
Автор: Ariel Navon, Eran Sharon, Idan Alrod
Принадлежит: Western Digital Technologies Inc

Systems and methods for predicting read commands and pre-fetching data when a memory device is receiving random read commands to non-sequentially addressed data locations are disclosed. A limited length search sequence of prior read commands is generated and that search sequence is then converted into an index value in a predetermined set of index values. A history pattern match table having entries indexed to that predetermined set of index values contains a plurality of read commands that have previously followed the search sequence represented by the index value. The index value is obtained via application of a many-to-one algorithm to the search sequence. The index value obtained from the search sequence may be used to find, and pre-fetch data for, a plurality of next read commands in the table that previously followed a search sequence having that index value.

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Номер записи: 127
02-01-2020 дата публикации

GROWN DEFECT DETECTION AND MITIGATION USING ECC IN MEMORY SYSTEMS

Номер: US20200004629A1
Автор: ALROD IDAN, SHARON ERAN, Zamir Ran
Принадлежит:

A controller may detect unreliable bits of data, memory cells, or bit lines during an error correction process of a read operation based on an error correction code used to generate parity bits for the data. In some embodiments, the controller may use the error correction code to determine a distribution of unsatisfied checks. Based on the distribution, the controller may detect group(s) of bits that more closely resemble a defective group of bits rather than a non-defective group of bits. Based on the detection, the controller may set reliability metrics to values that indicate low levels or reliability, which in turn may increase the probability of successfully correcting the errors and reduce the amount of work the controller needs to do in order to complete the error correction process. 1. A circuit comprising:a memory array comprising a plurality of memory cells; and receive a bit group of data stored in the memory array;', 'generate an empirical distribution for the bit group based on an error correction code;', 'compare the empirical distribution for the bit group with an expected distribution; and', 'in response to the comparison, identify that the bit group is unreliable., 'a controller configured to2. The circuit of claim 1 , wherein the controller is configured to:calculate a statistical similarity between the empirical distribution and the expected distribution to compare the empirical distribution with the expected distribution.3. The circuit of claim 2 , wherein the controller is further configured to:calculate a score based on the statistical similarity; andidentify that the bit group is unreliable based on the score.4. The circuit of claim 3 , wherein the controller is configured to identify that the bit group is unreliable in response to the score satisfying a threshold.5. The circuit of claim 3 , wherein the controller is configured to identify that the bit group is unreliable in response to the score being one of a predetermined number of highest ...

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Номер записи: 128
01-01-2015 дата публикации

STORAGE DEVICE AND METHOD USING PARAMETERS BASED ON PHYSICAL MEMORY BLOCK LOCATION

Номер: US20150006800A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит:

A method includes determining a block identifier of a physical block of a memory array that is to be accessed. The method further includes determining a word line index of a first word line that is to be accessed within the physical block based on the block identifier and further based on a first position of the first word line within the physical block. The method further includes selecting a first value of a first parameter according to a first group of word lines that is associated with the word line index and accessing the first word line using the first value of the first parameter. 1. A method comprising:determining a block identifier of a physical block of a memory that is to be accessed;determining a word line index of a first word line that is to be accessed within the physical block based on the block identifier and further based on a first position of the first word line within the physical block, wherein the word line index is associated with a physical location of the first word line within the memory;selecting a first value of a first parameter according to a first group of word lines that is associated with the word line index; andaccessing the first word line using the first value of the first parameter, wherein the first group of word lines includes the first word line and also includes a second word line within a second physical block, wherein a second group of word lines includes a third word line within the physical block and also includes a fourth word line at the first position within the second physical block, and wherein the second group of word lines corresponds to a second value of the first parameter that is different than the first value of the first parameter.2. The method of claim 1 , wherein the first word line includes a first indicator corresponding to the first value of the first parameter.3. The method of claim 2 , wherein the first word line includes a second indicator corresponding to a first value of a second parameter.4. The ...

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Номер записи: 129
01-01-2015 дата публикации

WORD LINE DEFECT DETECTION AND HANDLING FOR A DATA STORAGE DEVICE

Номер: US20150006975A1
Автор: ALROD IDAN, JEON SEUNGJUNE, Lee Dana, SHARON ERAN
Принадлежит:

A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset. 1. A method comprising: detecting a condition associated with a defect in the word line;', 'determining a first subset of the plurality of storage elements and a second subset of the plurality of storage elements based on an estimated location of the defect; and', 'determining a first read threshold for the first subset and a second read threshold for the second subset., 'in a data storage device including a non-volatile memory and a controller, wherein the non-volatile memory includes a word line coupled to a plurality of storage elements, performing by the controller2. The method of claim 1 , wherein reading data from the second subset using the second read threshold results in fewer errors than reading the data from the second subset using the first read threshold.3. The method of claim 1 , wherein the defect corresponds to a physical break in the word line.4. The method of claim 1 , wherein the defect corresponds to a process variation of a width of the word line.5. The method of claim 1 , further comprising reading first data from the first subset using the first read threshold and reading second data from the second subset using the second read threshold.6. The method of claim 5 , further comprising decoding the first data using a first log-likelihood ratio (LLR) associated with the first subset and decoding the second data using a second LLR associated with the second subset.7. The method of claim 1 , further comprising ...

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Номер записи: 130
01-01-2015 дата публикации

WORD LINE DEFECT DETECTION AND HANDLING FOR A DATA STORAGE DEVICE

Номер: US20150006976A1
Автор: ALROD IDAN, JEON SEUNGJUNE, Lee Dana, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory and circuitry associated with operation of memory cells of the 3D memory. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset. 1. A method comprising: detecting a condition associated with a defect in the word line;', 'determining a first subset of the plurality of storage elements and a second subset of the plurality of storage elements based on an estimated location of the defect; and', 'determining a first read threshold for the first subset and a second read threshold for the second subset., 'in a data storage device including a controller, a non-volatile memory that includes a three-dimensional (3D) memory, and circuitry associated with operation of memory cells of the 3D memory, wherein the non-volatile memory includes a word line coupled to a plurality of storage elements, each storage element including a memory cell of the 3D memory, performing by the controller2. The method of claim 1 , wherein reading data from the second subset using the second read threshold results in fewer errors than reading the data from the second subset using the first read threshold.3. The method of claim 1 , wherein the defect corresponds to a physical break in the word line.4. The method of claim 1 , wherein the defect corresponds to a process variation of a width of the word line.5. The method of claim 1 , further comprising reading first data from the first subset using the first read threshold and reading second data from the second subset using the second read ...

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Номер записи: 131
03-02-2022 дата публикации

ON-CHIP NON-VOLATILE MEMORY (NVM) SEARCH

Номер: US20220036945A1
Автор: ALROD IDAN, Bazarsky Alexander, Benisty Shay, HAHN JUDAH GAMLIEL, Marcu Alon, NAVON Ariel, SHARON ERAN, Zamir Ran
Принадлежит:

The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data. 1. An apparatus , comprising:a non-volatile memory (NVM) die; and send a scrambling pattern to the NVM die that is a function of a storage unit index;', 'control the NVM die to search for information stored on the NVM die while using the scrambling pattern that is the function of the storage unit index; and', 'receive search results from the NVM die., 'a processor configured to2. The apparatus of claim 1 , wherein the NVM die is configured to search within data that has been scrambled using the scrambling pattern.3. The apparatus of claim 2 , wherein the NVM die comprises a scrambler and a latch claim 2 , and wherein the processor is further configured to control the NVM die to use the scrambler to descramble the data as the data is sensed from an array of the NVM and stored in the latch.4. The apparatus of claim 1 , wherein the storage unit index is one or more of a wordline index or a page index.5. The apparatus of claim 1 , wherein the processor is further configured to send non- ...

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Номер записи: 132
22-01-2015 дата публикации

DIRECT MULTI-LEVEL CELL PROGRAMMING

Номер: US20150023099A1
Автор: ALROD IDAN, Li Yan, Marcu Alon, Oshinsky Hadas, SHARON ERAN
Принадлежит:

A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage. 1. A data storage device comprising:a non-volatile memory including a group of storage elements;a set of latches configured to store data to be programmed to the group of storage elements during each particular stage of a multi-stage write operation; anda second memory configured to store bits corresponding to one or more portions of the data during a time period between stages of the multi-stage write operation,wherein the second memory is configured to receive the bits corresponding to the one or more portions of the data from the latches without receiving bits corresponding to a first portion of the data that is programmed to the group of storage elements during a first stage of the multi-stage write operation, andwherein the latches are configured to receive the bits corresponding to the one or more portions of the data from the second memory and to receive the bits corresponding to the first portion of the data from the group of storage elements during a subsequent stage of the multi-stage write operation.2. The data storage device of claim 1 , further comprising mapping circuitry coupled to the latches claim 1 , ...

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Номер записи: 133
25-01-2018 дата публикации

BAD COLUMN HANDLING IN FLASH MEMORY

Номер: US20180024880A1
Автор: ALROD IDAN, Altshuler Michael, Kotagiri Madhuri, Nagabhirava Rajeev, SHARON ERAN, Yurzola Damian
Принадлежит:

In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns. 1. A nonvolatile memory system comprising:a memory array having a plurality of columns, each of the plurality of columns comprising one or more bit lines; anda soft-input error correction code decoder configured to receive hard data and soft data for at least one bad column of the plurality of columns and further configured to decode the hard data in combination with the soft data to generate decoded data,wherein the soft data comprises compressed information including indication of locations of bad data within the at least one bad column, andwherein the locations of bad data are replaced by indications of low likelihood.2. The nonvolatile memory system of claim 1 , wherein the at least one bad column comprises at least one defective bit line.3. The nonvolatile memory system of claim 1 , wherein the compressed information comprises compressed bit line location information.4. The nonvolatile memory system of claim 1 , wherein the compressed information is obtained by dividing the plurality of columns into a plurality of sections and aggregating the plurality of sections into a folded page.5. The nonvolatile memory system of claim 4 , wherein a folded page column within the folded page is indicated as a bad column based upon a location of the folded page column corresponding to a bad column location in any of the plurality of sections.6. The nonvolatile memory system of claim 1 , wherein the memory array is a NAND flash memory array.7. The nonvolatile memory system of claim 1 , wherein the plurality of columns comprise a plurality of non-redundant columns having the at least one bad column claim 1 , and one or more redundant columns ...

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Номер записи: 134
28-01-2021 дата публикации

CAM STORAGE SCHEMES AND CAM READ OPERATIONS FOR DETECTING MATCHING KEYS WITH BIT ERRORS

Номер: US20210027838A1
Автор: ALROD IDAN, Li Yan, Marcu Alon, SHARON ERAN
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors. 1. A circuit comprising: generate a keyword for a key to be stored in a memory array according to a content addressable memory (CAM) storage scheme, the keyword comprising a plurality of information bits of the key and a plurality of parity bits determined from the plurality of information bits;', 'generate an inverse keyword based on the keyword; and', 'program the keyword and the inverse keyword according to the CAM storage scheme., 'a controller configured to2. The circuit of claim 1 , wherein the controller is further configured to:bias a plurality of word lines coupled to the memory array according to a plurality of modified word line bias settings, each modified from an initial word line bias setting that corresponds to a target keyword or an inverse target keyword and based on a bit error number associated with storage of the keyword; anddetermine that the keyword matches the target keyword in response to the bias.3. The circuit of claim 2 , wherein the controller is configured to bias a word line of the plurality of word lines at a low voltage level according to the initial word line bias setting claim 2 , and is configured to bias the word line at the high voltage level according to a modified word ...

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Номер записи: 135
30-01-2020 дата публикации

MEMORY CONTROLLER ASSISTED ADDRESS MAPPING

Номер: US20200034307A1
Автор: ALROD IDAN, Duzly Yacov, Li Yan
Принадлежит:

An apparatus includes a storage controller, a non-volatile memory die comprising a set of memory elements and a memory die controller associated with the non-volatile memory die. The memory die controller is configured to identify a portion of the non-volatile memory die for mapping logical addresses, read a header of a sub-portion of the identified portion, for a logical address, map a physical address corresponding to the logical address of the sub-portion to a physical-to-logical mapping and transmit the physical-to-logical mapping to the storage controller. 1. An apparatus comprising:a non-volatile memory die; and read a logical address from a header of a sub-portion of memory;', 'map a physical address corresponding to the logical address of the sub-portion within a physical-to-logical mapping; and', 'transmit the physical-to-logical mapping to the storage controller., 'a memory die controller associated with the non-volatile memory die and in response to a mapping request from a storage controller configured to2. The apparatus of claim 1 , wherein:the storage controller is configured to send a mapping request to the memory die controller, the mapping request configured to return the physical-to-logical mapping.3. The apparatus of claim 1 , wherein the mapping request identifies a physical address of a block of memory and a number of sub-pages to map in the block of memory.4. The apparatus of claim 1 , wherein the storage controller is further configured to correct data errors in the physical-to-logical mapping.5. The apparatus of claim 4 , wherein the storage controller is further configured to:determine that a logical address in the physical-to-logical mapping is corrupted;retrieve error correction information corresponding to the corrupted logical address; andgenerate a corrected value of the determined corrupted logical address, using the error correction information.6. An apparatus comprising:a storage controller coupled to a host;a non-volatile memory die ...

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Номер записи: 136
05-02-2015 дата публикации

SYSTEMS AND METHODS OF STORING DATA

Номер: US20150039970A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит:

A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page. 1. A method of writing data , the method comprising: receiving a data page to be stored in the data storage device, wherein the data page is received from a host device;', 'initiating an encode operation at the ECC engine to encode the data page, wherein the encode operation generates first encoded data;', 'storing at least a portion of the first encoded data to the first physical page at the memory die;', reading a representation of the portion of the first encoded data from the first physical page; and', 'generating redundant data at the memory die based on the representation of the portion of the first encoded data; and, 'generating, at the memory die, second encoded data by, 'storing the second encoded data to the second physical page., 'in a data storage device with a controller and a memory die, wherein the controller includes an error correction coding (ECC) engine and wherein the memory die includes multiple physical pages including a first physical page and a second physical page, performing2. The method of claim 1 , wherein the redundant data is generated at the memory die by copying at least part of the representation of the portion of the first encoded data.3. The method of claim 2 , wherein the first encoded data includes a first portion and a ...

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Номер записи: 137
12-02-2015 дата публикации

SYSTEMS AND METHODS OF STORING DATA

Номер: US20150043276A1
Автор: ALROD IDAN, LITSYN SIMON, SHARON ERAN
Принадлежит:

A method includes, when using a binary cache in an multi-level cell (MLC) flash memory splitting a codeword corresponding to a data page into multiple data pages and storing the multiple data pages into multiple single level cell (SLC) pages of the binary cache for subsequent storage into a single wordline of the MLC flash memory.

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Номер записи: 138
18-02-2016 дата публикации

System and method of using multiple read operations

Номер: US20160049203A1
Автор: Eran Sharon, Idan Alrod
Принадлежит: SanDisk Technologies LLC

Systems and methods are described for reading a storage element of a memory. In a particular embodiment, a method, in a data storage device including a controller and a non-volatile memory, where the non-volatile memory includes a plurality of storage elements, includes performing multiple read operations at a storage element of the non-volatile memory. Each read operation of the multiple read operations is performed using the same reading voltage. The method further includes determining a read value of the storage element based on the multiple read operations.

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Номер записи: 139
16-02-2017 дата публикации

Soft bit techniques for a data storage device

Номер: US20170046220A1
Автор: Alexander Bazarsky, Ariel Navon, Eran Sharon, Idan Alrod
Принадлежит: SanDisk Technologies LLC

A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.

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Номер записи: 140
01-03-2018 дата публикации

COLUMN-LAYERED MESSAGE-PASSING LDPC DECODER

Номер: US20180062666A1
Автор: ALROD IDAN, ALTERMAN SANEL, Bazarsky Alexander, FAINZILBER Omer, SHARON ERAN, Zamir Ran, Zhang Xinmiao
Принадлежит:

In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message. 1. A decoder comprising: a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node; and', 'a hard-decision lookup table circuit configured to output a hard-decision value corresponding to a variable node; and, 'a variable node unit (VNU) comprisinga check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.2. The decoder of claim 1 , wherein:the VNU is included in a VNU stage that comprises a first number of VNUs corresponding to a column layer of a parity check matrix,the CNU is included in a CNU stage that comprises a second number of CNUs corresponding to a multiple of a column weight of the parity check matrix, andthe VNU stage and the CNU stage are configured to operate according to a column-layered decoding schedule.3. The decoder of claim 1 , wherein the VNU includes:inputs configured to receive check-to-variable messages corresponding to the variable node; anda plurality of variable-to-check lookup table circuits that includes the variable-to-check lookup table circuit.4. The decoder of claim 3 , wherein the variable-to-check lookup table circuit is configured to receive check-to-variable messages from at least two of the inputs.5. The decoder of claim 4 , wherein each of the check-to-variable messages includes a two-bit message.6. The decoder of claim 3 , wherein the VNU comprises a one-hot decoder circuit configured to generate ...

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Номер записи: 141
05-06-2014 дата публикации

STORAGE AND RETRIEVAL OF SHAPED DATA

Номер: US20140157086A1
Автор: ALROD IDAN, FAINZILBER Omer, NAVON Ariel, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

Systems and methods of encoding and decoding shaped data include determining a bit representation corresponding to a bit in a representation of a codeword that is read from a non-volatile memory of a data storage device. A soft metric corresponding to the bit representation is determined at least partially based on an amount of shaping of data. 1. A method comprising: receiving a representation of a codeword that is read from the non-volatile memory;', 'determining a shaping level of a set of one or more bits of the representation of the codeword;', 'determining a soft metric of each bit of the one or more bits of the representation of the codeword based on a value of the bit in the received representation and based on the shaping level; and', 'initiating a decoding operation of the codeword based on the soft metrics., 'in a data storage device including a non-volatile memory, performing2. The method of claim 1 , wherein the shaping level is determined based on stored side information.3. The method of claim 1 , wherein the shaping level is determined as a function of read values of the representation of the codeword read from the non-volatile memory.4. The method of claim 3 , wherein the shaping level is determined as a function of a number of occurrences of each of the read values within the set of one or more bits.5. The method of claim 1 , wherein determining the soft metric of each bit comprises:determining an initial soft metric of each bit based on a read value of the bit;determining a correction value to the initial soft metric of each bit, wherein the correction value is at least partially based on the shaping level; andgenerating the soft metric of each bit by applying the correction value to the initial soft metric.6. The method of claim 5 , wherein the correction value is computed further based on received bit reliability information.7. The method of claim 1 , further comprising estimating an error correction capability of decoding the representation of ...

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Номер записи: 142
05-06-2014 дата публикации

Bad Column Handling in Flash Memory

Номер: US20140157087A1
Автор: ALROD IDAN, Altshuler Michael, Kotagiri Madhuri, Nagabhirava Rajeev, SHARON ERAN, Yurzola Damian Pablo
Принадлежит: SANDISK TECHNOLOGIES, INC.

In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns. 1. A method of operating a memory array that includes at least one bad column , comprising:determining location information for the at least one bad column;compressing the location information;providing the compressed location information to a soft-input ECC decoder as a first soft data indicating low likelihood for hard data obtained from the at least one bad column; anddecoding hard data in combination with the soft data indicating low likelihood for the hard data obtained from the at least one bad column.2. The method of wherein the providing step comprises:providing the compressed location information to a soft-input ECC decoder as soft data indicating low likelihood for hard data obtained from any column which shares the compressed location information of the at least one bad column.3. The method of further comprising performing a high resolution read to obtain a second soft read data claim 1 , the second soft read data combined with the first soft data.4. The method of wherein compressing the location information includes dividing all columns into a plurality of sections and claim 1 , in each section claim 1 , treating a particular column as a bad column if the location information indicates that there is a bad column in any section of the plurality of sections at a location corresponding to the particular column.5. The method of wherein the memory array consists of a plurality of columns claim 1 , each of the plurality of columns containing a plurality of bit lines claim 1 , and wherein a column is considered as a bad column if it contains at least one defective bit line.6. The method of further comprising determining ...

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Номер записи: 143
12-06-2014 дата публикации

HEAD MOUNTABLE CAMERA SYSTEM

Номер: US20140160248A1
Автор: ALROD IDAN, LASSER MENAHEM, NAVON Ariel, Pomerantz Itzhak, PRESMAN Noam, SHARON ERAN, Yairi Rahav
Принадлежит: SANDISK TECHNOLOGIES INC.

Head mountable camera devices, systems, and methods are disclosed. 1. An apparatus comprising:at least two cameras; anda mounting structure attached to the at least two cameras that is configured to, while the mounting structure is on a user's head, remain substantially or entirely outside of a field of vision of the user and to position the at least two cameras to be substantially or entirely outside of the field of vision of the user and to be at approximately an eye level of the user.2. The apparatus of claim 1 , wherein the at least two cameras are positioned to enable stereo video recording via the at least two cameras.3. The apparatus of claim 1 , further comprising:a sensor; anda controller configured to adjust at least one of a focal distance of a camera of the at least two cameras and a field of view of the camera in response to receiving an output of the sensor, wherein the sensor includes at least one of an inclinometer or a satellite-based positioning sensor.4. The apparatus of claim 3 , wherein the controller is configured to toggle between multiple modes of operation of the at least two cameras claim 3 , the multiple modes including a stereo recording mode and an extended field of view mode.5. The apparatus of claim 1 , further comprising:a storage device attached to the mounting structure and configured to store first data received from the at least two cameras, the first data including one or both of image data and video data, wherein the stored first data has a first quality; anda controller coupled to the mounting structure and configured to provide second data to a transmitter, wherein the second data corresponds to the first data and wherein the second data has a second quality different from the first quality.6. The apparatus of claim 5 , wherein the first quality corresponds to a first resolution and wherein the second quality corresponds to a second resolution that is less than the first resolution.7. The apparatus of claim 5 , wherein the ...

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Номер записи: 144
12-06-2014 дата публикации

ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS

Номер: US20140164865A1
Автор: ALROD IDAN, FAINZILBER Omer, LITSYN SIMON, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES, INC.

An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations. 1. An apparatus comprising a processor configured to at least perform or cause the apparatus to at least perform:receiving a representation of a codeword that includes a plurality of bits;associating the bits with a respective plurality of one-bit hard-bit values and multiple-bit soft-bit values, the hard-bit values being initially set according to the representation of the codeword and representing the bits of the codeword, and the soft-bit values representing measures of reliability of respective hard-bit values; andupdating at least some of the hard-bit values or soft-bit values of the bits including for each of a plurality of iterations, computing an updated hard-bit value or soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the bits of the subset, and the current hard-bit value and soft-bit value of the respective bit,wherein for two iterations in which the current hard-bit value for each bit of a subset of the bits for both iterations is the same, and in which the current soft-bit value for each ...

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Номер записи: 145
31-03-2016 дата публикации

READING RESISTIVE RANDOM ACCESS MEMORY BASED ON LEAKAGE CURRENT

Номер: US20160093372A1
Автор: ALROD IDAN, FAINZILBER Omer, Liu Tz-Yi, NAVON Ariel, SHARON ERAN, Yan Tianhong
Принадлежит:

A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current. 1. A data storage device comprising:a resistive random access memory (ReRAM) including a plurality of storage elements, wherein a storage element of the ReRAM is configured to store a data value;read circuitry coupled to the storage element and configured to read the data value, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation; anda controller coupled to the read circuitry, wherein the controller is configured to provide an input value to an error correction coding (ECC) decoder, wherein the input value includes a hard bit value and a soft bit value, wherein the hard bit value corresponds to the data value and the soft bit value is at least partially based on the leakage current.2. The data storage device of claim 1 , wherein the soft bit value is determined by quantizing a sensed value of the leakage current.3. The data storage device of claim 1 , wherein the soft bit value corresponds to a reliability that is selected based on the leakage current.4. The data storage device of claim 1 , wherein in response to the leakage current exceeding a leakage ...

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Номер записи: 146
30-03-2017 дата публикации

ERROR CORRECTION BASED ON HISTORICAL BIT ERROR DATA

Номер: US20170091028A1
Автор: ALROD IDAN, Elmoalem Eli, Golan Ronen
Принадлежит:

A data storage device includes a memory including a plurality of storage elements. The data storage device further includes a controller coupled to the memory. The controller includes an error correction code (ECC) engine. The controller further includes a reliability engine configured to access historical bit error data. The historical bit error data includes a first count of bit errors associated with a first set of storage elements of the plurality of storage elements. The reliability engine is configured to generate reliability information based on the historical bit error data and to provide the reliability information to the ECC engine. 1. A data storage device comprising:a memory including a plurality of storage elements; and an error correction code (ECC) engine; and', 'a reliability engine configured to access historical bit error data, wherein the historical bit error data includes a first count of bit errors associated with a first set of storage elements of the plurality of storage elements, and wherein the reliability engine is configured to generate reliability information based on the historical bit error data and to provide the reliability information to the ECC engine., 'a controller coupled to the memory, wherein the controller comprises2. The data storage device of claim 1 , wherein the reliability engine is configured to access the historical bit error data from a controller memory.3. The data storage device of claim 1 , wherein the memory comprises a non-volatile memory claim 1 , and wherein the reliability engine is configured to access the historical bit error data from the non-volatile memory.4. The data storage device of claim 1 , wherein the reliability information indicates a reliability of one or more bits read from the first set of storage elements claim 1 , and wherein the ECC engine is configured to process the reliability information to decode the one or more bits read from the first set of storage elements.5. The data storage device ...

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Номер записи: 147
29-03-2018 дата публикации

ECC AND RAID-TYPE DECODING

Номер: US20180091172A1
Автор: ALROD IDAN, GHALY MAI, ILANI ISHAI, SHARON ERAN
Принадлежит:

A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword. The controller is configured to read a representation of the inverse bit string from the physical location of the memory. The controller is further configured to designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string. 1. A device comprising:a memory; and read a codeword from a physical location of the memory,', 'write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword,', 'read a representation of the inverse bit string from the physical location of the memory, and', 'designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string., 'a controller coupled to the memory, wherein the controller is configured to2. The device of claim 1 , wherein a value of each bit of the inverse bit string is inverted with respect to a value of a corresponding bit of the codeword.3. The device of claim 1 , wherein the inverse bit string is generated and written to the memory in response to a decoding failure associated with the codeword claim 1 , the inverse bit string overwriting the codeword at the memory.4. The device of claim 1 , wherein the controller is further configured to perform an exclusive-or (XOR) operation on the codeword and on the representation of the inverse bit string to determine the one or more erased bits.5. The device of claim 4 , wherein the one or more erased bits correspond to one or more bits that have the same value in the codeword and in the representation of the inverse bit string.6. The device of claim 1 , further comprising a decoder configured ...

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Номер записи: 148
06-04-2017 дата публикации

DATA STORAGE DEVICE WITH A MEMORY DIE THAT INCLUDES AN INTERLEAVER

Номер: US20170097869A1
Автор: ALROD IDAN, Chu Alexander Tsang-nam, NAVON Ariel, SHARON ERAN, Tsai Wanfang
Принадлежит:

A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die. 1. A data storage device comprising:a set of latches configured to receive data;read/write circuitry coupled to the set of latches;a memory coupled to the read/write circuitry; andan interleaver configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory,wherein the set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.2. The data storage device of claim 1 , wherein the set of latches includes a first latch configured to receive a first page of the data and a second latch configured to receive a second page of the data.3. The data storage device of claim 2 , wherein the read/write circuitry is configured to access the interleaved data from the set of latches and to program the interleaved data to a word line of the memory.4. The data storage device of claim 3 , further comprising a counter claim 3 , wherein the counter is configured to store a value indicating one or more values of the data during a read operation from the word line claim 3 , the read operation including an on-the-fly (OTF) ramp sensing and deinterleaving process.5. The data storage device of claim 1 , wherein the memory has a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area above a silicon substrate claim 1 , and further comprising circuitry associated with operation of the memory ...

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Номер записи: 149
13-04-2017 дата публикации

DATA ENCODING TECHNIQUES FOR A DEVICE

Номер: US20170102993A1
Автор: ALROD IDAN, HU Xinde, NAVON Ariel, PETTI CHRISTOPHER JOHN, SHARON ERAN
Принадлежит:

A data storage device includes a controller and a non-volatile memory coupled to the controller. The controller is configured to generate first parity information based on first data and to generate second parity information based on second data. The non-volatile memory is configured to store the first data and the second data. The data storage device also includes a buffer configured to store the first parity information. The controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold. 1. A data storage device comprising:a controller configured to generate first parity information based on first data and to generate second parity information based on second data;a non-volatile memory coupled to the controller, the non-volatile memory configured to store the first data and the second data; anda buffer configured to store the first parity information,wherein the controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold.2. The data storage device of claim 1 , wherein a parity size of the joint parity information is different than a combined parity size of the first parity information and the second parity information.3. The data storage device of claim 1 , wherein the joint parity information is generated based on an algebraic error correcting code.4. The data storage device of claim 1 , wherein a size of the buffer is based on a programming throughput associated with the non-volatile memory and is further based on a data retention effect associated with storage elements of the non-volatile memory.5. The data storage device of claim 1 , further comprising refresh circuitry configured to refresh the first data based on a refresh schedule.6. The data storage ...

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Номер записи: 150
21-04-2016 дата публикации

MODIFIED WRITE PROCESS BASED ON A POWER CHARACTERISTIC FOR A DATA STORAGE DEVICE

Номер: US20160109926A1
Автор: Achtenberg Stella, ALROD IDAN, Bazarsky Alexander, Liu Tz-Yi, NAVON Ariel, SHARON ERAN, Yan Tianhong
Принадлежит:

A data storage device includes a memory die. The memory die includes a resistive memory. A method includes determining a power characteristic associated with performing a write process to write data to the resistive memory. The method further includes initiating a modified write process in response to detecting that the power characteristic satisfies a threshold. 1. A method comprising: determining a power characteristic associated with performing a write process to write data to the resistive memory; and', 'initiating a modified write process in response to detecting that the power characteristic satisfies a threshold., 'at a data storage device that includes a memory die, wherein the memory die includes a resistive memory, performing2. The method of claim 1 , wherein performing the modified write process reduces a peak power consumption as compared to performing the write process.3. The method of claim 1 , further comprising:determining that the write process is to program at least a threshold number of storage elements of the resistive memory to a particular state during a particular programming cycle of the write process; andrescheduling one or more programming operations of the write process that are associated with the particular state.4. The method of claim 3 , wherein rescheduling the one or more programming operations of the write process interchanges one or more low-resistance programming operations with one or more high-resistance programming operations to reduce a number of low-resistance programming operations during the particular programming cycle.5. The method of claim 1 , wherein modifying the write process includes reducing a number of programming operations during one or more programming cycles of the write process.6. The method of claim 1 , wherein modifying the write process includes decreasing a programming voltage during one or more programming cycles of the write process.7. The method of claim 1 , wherein modifying the write process increases ...

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Номер записи: 151
21-04-2016 дата публикации

DUAL POLARITY READ OPERATION

Номер: US20160111150A1
Автор: Achtenberg Stella, ALROD IDAN, Bazarsky Alexander, Liu Tz-Yi, NAVON Ariel, SHARON ERAN, Yan Tianhong
Принадлежит:

A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory. 1. A method comprising: performing a first read operation with respect to a storage element of the resistive memory to determine a first read bit value of the storage element, wherein performing the first read operation comprises applying a first read voltage having a first polarity;', 'performing a second read operation with respect to the storage element to determine a second read bit value of the storage element, wherein performing the second read operation comprises applying a second read voltage having a second polarity opposite the first polarity; and', 'determining read confidence information associated with the storage element based on at least one of the first read operation or the second read operation., 'at a data storage device that includes a resistive memory2. The method of claim 1 , wherein the second read operation is performed in response to determining that a number of read errors associated with the resistive memory exceeds a threshold.3. The method of claim 1 , wherein the second read operation is performed in response to determining that a number of program/erase cycles associated with the resistive memory exceeds a threshold.4. The method of claim 1 , wherein the read confidence information is determined at a memory die that includes the memory and is provided to a controller of the data storage device.5. The method of claim 1 , wherein the first read bit value and the second read bit value are provided from a memory die that includes the memory to a ...

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Номер записи: 152
02-04-2020 дата публикации

SINGLE PAGE READ LEVEL TRACKING BY BIT ERROR RATE ANALYSIS

Номер: US20200105353A1
Автор: ALROD IDAN, Bazarsky Alex, SHARON ERAN
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

A method for calibrating read threshold voltages includes receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a page associated with the at least one memory die. The method further includes determining voltage bins for each bit of the number of page bits. The method further includes determining, for each voltage bin, a bit error rate. The method further includes adjusting read threshold voltages associated with the at least one memory die using the bite error rate for each voltage bin. 1. A method for calibrating read threshold voltages , the method comprising:receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a logical page associated with the at least one memory die;determining voltage bins for each logical bit of the number of page bits;determining, for each voltage bin, a bit error rate; andadjusting read threshold voltages associated with the at least one memory die using the bit error rate for each voltage bin.2. The method of claim 1 , further comprising flipping logical values of erroneous bits associated with each voltage bin.3. The method of claim 2 , wherein determining claim 2 , for each voltage bin claim 2 , the bit error rate further comprises determining a first number of logical values of bits associated with each voltage bin flipped from a first logical value to a second logical value and determining a second number of logical values of bits associated with each voltage bin flipped from the second logical value to the first logical value.4. The method of claim 3 , wherein adjusting read threshold voltages associated with the at least one memory die using the bit error rate for each voltage bin further comprises adjusting the read threshold voltages based on a determination of whether the first number is greater than the second number.5. The method of claim 1 , wherein determining claim 1 , for each voltage bin ...

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Номер записи: 153
26-04-2018 дата публикации

First Read Solution For Memory

Номер: US20180113759A1
Автор: ALROD IDAN, Eyal Alon, Mekhanik Evgeny, Pang Liang, SHARON ERAN
Принадлежит: SanDisk Technologies LLC

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines. 1. An apparatus , comprising:a set of memory cells, the memory cells arranged in strings and connected to a set of word lines;a set of sense circuits, each circuit sense is connected to a respective string of the strings and comprises a sense node;a first set of latches comprising a first latch in each of the sense circuits;a second set of latches comprising a second latch in each of the sense circuits; and apply a read voltage to a selected word line of the set of word lines;', 'during application of the read voltage, for each sense circuit, charge the sense node, connect the sense node to one end of the respective string, determine voltages of the sense node at first and second times relative to a trip voltage, and store data in the first and second latches of the sense circuit based on the determined voltages;', 'evaluate the data in the first set of latches and the second set of latches to determine whether the first set of latches or the second set of latches includes data with fewer errors; and', 'select the data with the fewer errors in one of the first set of latches and the second set of latches as read data., 'a control circuit, the control circuit is configured to, in response to a ...

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Номер записи: 154
26-04-2018 дата публикации

Command Sequence For First Read Solution For Memory

Номер: US20180114580A1
Автор: ALROD IDAN, Eyal Alon, Mekhanik Evgeny, Pang Liang, SHARON ERAN
Принадлежит: SanDisk Technologies LLC

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die. 1. An apparatus , comprising:a plurality of memory cells within an array, the array comprising word lines, each memory cell connected to a word line; anda maintenance circuit, to perform a conditioning operation on one or more word lines of the array, configured to increase voltages of the one or more word lines to an elevated level, followed by a decrease of the voltages of the one or more word lines to a final level, wherein the maintenance circuit performs the conditioning operation on the one or more word lines in response to a trigger.2. The apparatus of claim 1 , wherein:the maintenance circuit is configured to connect a voltage source to the one or more word lines to perform the increase and the decrease of the voltages of the one or more word lines, and to disconnect the voltage source from the one or more word lines after the decrease, to float the voltages of the one or more word lines.3. The apparatus of claim 1 , further comprising:a timer configured to track a duration since a last sensing operation in the array, wherein the trigger comprises a determination that the duration ...

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Номер записи: 155
27-04-2017 дата публикации

SYSTEMS AND METHODS OF DETECTING ERRORS DURING READ OPERATIONS AND SKIPPING WORD LINE PORTIONS

Номер: US20170116070A1
Автор: ALROD IDAN, Eli Yigal, Inbar Karin, Kirshenbaum Roi, PELTZ Uri, SHARON ERAN
Принадлежит:

A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The non-volatile memory includes a plurality of blocks and each block of the plurality of blocks includes a plurality of word lines. The controller is configured to receive data read from a word line of a block of the non-volatile memory and to determine an error indicator value based on the data. The controller is further configured to, responsive to the error indicator value satisfying a threshold, indicate that at least a portion of the word line is to be skipped during writing of second data to the block of the non-volatile memory. 1. A device comprising:a non-volatile memory including a plurality of blocks, each block of the plurality of blocks including a plurality of word lines; and receive data read from a word line of a block of the plurality of blocks;', 'determine an error indicator value based on the data; and', 'responsive to the error indicator value satisfying a threshold, indicate that at least a portion of the word line is to be skipped during writing of second data to the block of the non-volatile memory., 'a controller coupled to the non-volatile memory, the controller configured to2. The device of claim 1 , wherein the error indicator value comprises a failed bit count claim 1 , a syndrome weight claim 1 , or a bit error rate.3. The device of claim 1 , further comprising an error correction coding (ECC) engine configured to decode the data to determine the error indicator value claim 1 , wherein the threshold is less than an ECC correction capability of the ECC engine.4. The device of claim 1 , wherein the portion of the word line is associated with a first physical address claim 1 , and wherein the controller is further configured to:correct one or more bit errors in the data to generate corrected data; andsend the corrected data to the non-volatile memory for writing to a storage location associated with a second physical address that differs from the ...

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Номер записи: 156
09-06-2022 дата публикации

TWO-SIDED ADJACENT MEMORY CELL INTERFERENCE MITIGATION

Номер: US20220180940A1
Автор: ALROD IDAN, Bazarsky Alexander, SHARON ERAN
Принадлежит: SanDisk Technologies LLC

Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line. 1. An apparatus , comprising: apply two or more read reference voltages to the first word line along with two or more read pass voltages to the second word line for each of the two or more read reference voltages, wherein the two or more read reference voltages are associated with the same data state; and', 'determine a condition for each respective first memory cell based on sensing the respective first memory cell for a combination of a first voltage from the two or more read reference voltages that depends on a state of an adjacent cell on the third word line and a second voltage from the two or more read pass voltages that depends on a state of an adjacent cell on the second word line., 'a control circuit configured to connect to first non-volatile memory cells connected to a first word line, second non-volatile memory cells connected to a second word line adjacent to the first word line, and third non-volatile memory cells connected to a third word line adjacent to the first word line, the control circuit configured to2. The apparatus of ...

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Номер записи: 157
27-04-2017 дата публикации

BURN-IN MEMORY TESTING

Номер: US20170117061A1
Автор: ALROD IDAN, Bazarsky Alexander, Eyal Alon, NAVON Ariel, Shapira Ofer, SHARON ERAN
Принадлежит:

A method performed by a controller includes initiating a first data write operation and an erase operation on a portion of a non-volatile memory. The first data write operation corresponds to a first write resolution. The method includes initiating a second data write operation to write test data to the portion of the non-volatile memory. The second data write operation corresponds to a second write resolution that is greater than the first write resolution. The method also includes reading a representation of the test data from the portion of the non-volatile memory. 1. A data storage device comprising: first circuitry configured to perform a first data write operation corresponding to a first write resolution; and', 'second circuitry configured to perform a second data write operation corresponding to a second write resolution that is greater than the first write resolution; and, 'a non-volatile memory includinga controller comprising a burn-in tester, the burn-in tester configured to initiate a memory initialization test that includes performance of the first data write operation, an erase operation, and the second data write operation on a portion of the non-volatile memory.2. The data storage device of claim 1 , wherein the burn-in tester is configured to cause the second data write operation to write test data to the portion of the non-volatile memory claim 1 , and wherein the controller is configured to read a representation of the test data from the portion of the non-volatile memory.3. The data storage device of claim 1 , wherein a first cell voltage distribution of storage elements of the portion of the non-volatile memory after the first data write operation corresponding to the first write resolution has a first lobe that spans a first voltage range claim 1 , and wherein a second cell voltage distribution of the storage elements after the second data write operation corresponding to the second write resolution has a second lobe that spans a second ...

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Номер записи: 158
09-04-2020 дата публикации

OPTIMIZING DATA STORAGE DEVICE OPERATION BY GROUPING LOGICAL BLOCK ADDRESSES AND/OR PHYSICAL BLOCK ADDRESSES USING HINTS

Номер: US20200110536A1
Автор: ALROD IDAN, Bazarsky Alexander, HAHN JUDAH GAMLIEL, Inbar Karin, NAVON Ariel, Rom Rami, SHARON ERAN
Принадлежит:

Methods and apparatus for managing and optimizing data storage devices that include non-volatile memory (NVM) are described. One such method involves deriving a hint for one or more logical block addresses (LBAs) of a storage device based on information received from a host device and/or physical characteristics of the storage device, such as LBAs that are invalidated together; grouping the LBAs into one or more clusters of LBAs based on the derived hint and a statistical analysis of the physical characteristics of the storage devices; allocating available physical block addresses (PBAs) in the storage device to one of the LBAs based on the one or more clusters of LBAs to achieve optimization of a data storage device. 1. A data storage device comprising:a hint derivation circuit configured to derive a hint for one or more logical block addresses (LBAs) of the data storage device based on information received from a host device and/or a plurality of physical characteristics of the data storage device;a machine learning circuit configured to group the one or more LBAs into one or more clusters of LBAs based on the derived hint and a machine learning process based on the plurality of physical characteristics of the data storage device; anda flash translation layer (FTL) circuit configured to allocate available physical block addresses (PBAs) in the data storage device to the one or more LBAs based on the one or more clusters of LBAs.2. The data storage device of claim 1 , wherein the hint derivation circuit is further configured to derive a hint that the one or more LBAs refer to a common user file stored in the data storage device based on a plurality of physical characteristics of the data storage device.3. The data storage device of claim 1 , wherein the plurality of physical characteristics comprise one or more of LBA ranges claim 1 , invalidation times claim 1 , LBA types according to associated metadata claim 1 , read access frequency of the LBAs claim 1 , ...

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Номер записи: 159
24-07-2014 дата публикации

SYSTEMS AND METHODS OF UPDATING READ VOLTAGES

Номер: US20140204671A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method includes, in a data storage device that includes a non-volatile memory, reading data from the non-volatile memory using a first read voltage. The method includes determining a first count of errors in the data having a first error type and a second count of errors in the data having a second error type. A value of the first read voltage is selectively updated based on a comparison of the first count to the second count. 1. A method comprising: reading data from the non-volatile memory using a first read voltage;', 'determining a first count of errors in the data having a first error type and a second count of errors in the data having a second error type; and', 'selectively updating a value of the first read voltage based on a comparison of the first count to the second count., 'in a data storage device that includes a non-volatile memory, performing2. The method of claim 1 , wherein the first error type corresponds to a bit of the data having a first bit value that differs from a second bit value programmed to the non-volatile memory claim 1 , wherein errors having the first error type are correctable by lowering the value of the first read voltage claim 1 , wherein the second error type corresponds to another bit of the data having the second bit value that differs from the first bit value programmed to the non-volatile memory claim 1 , and wherein errors having the second error type are correctable by increasing the value of the first read voltage.3. The method of claim 1 , wherein selectively updating the value of the first read voltage includes selectively increasing or decreasing the value of the first read voltage by a first amount in response to a difference between the first count and the second count exceeding a first threshold.4. The method of claim 3 , wherein selectively updating the value of the first read voltage includes selectively increasing or decreasing the value of the first read voltage by a second amount in response to the difference ...

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Номер записи: 160
04-05-2017 дата публикации

SYSTEM AND METHOD OF DATA COMPRESSION

Номер: US20170123662A1
Автор: ALROD IDAN, ILANI ISHAI, NAVON Ariel, Rom Rami, SHARON ERAN
Принадлежит:

A data storage device includes a shaping engine and a compression engine. The shaping engine is configured to shape first data to generate second data. The compression engine is configured to compress the second data to generate third data. 1. A data storage device comprising:a shaping engine configured to shape first data to generate second data; anda compression engine configured to compress the second data to generate third data.2. The data storage device of claim 1 , further comprising a set of one or more counters configured to indicate a number of bits of the second data having a particular logic value.3. The data storage device of claim 2 , wherein the compression engine is further configured to access the set of one or more counters to determine the number of bits having the particular logic value and to generate a set of symbols that indicate the number of bits having the particular logic value.4. The data storage device of claim 3 , wherein the compression engine is further configured to determine a compression ratio on-the-fly during a write process associated with the first data.5. The data storage device of claim 4 , wherein the compression engine is further configured to generate an indication of the compression ratio claim 4 , and wherein the third data includes the indication of the compression ratio.6. The data storage device of claim 3 , further comprising a memory claim 3 , wherein the compression engine is configured to generate multiple symbols to compress the second data claim 3 , each symbol includes a number of bits based on a data storage scheme associated with the memory.7. The data storage device of claim 6 , wherein the data storage scheme indicates a number of bits-per-cell associated with the memory.8. The data storage device of claim 1 , further comprising:a controller that includes the shaping engine and the compression engine; anda memory device coupled to the controller.9. A method comprising: shaping first data by the shaping ...

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Номер записи: 161
04-05-2017 дата публикации

PARTIAL SOFT BIT READ

Номер: US20170123902A1
Автор: ALROD IDAN, Jayaraman Muralitharan, Manohar Abhijeet, Ravimohan Narendhiran Chinnaanangur
Принадлежит:

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder. 1. A data storage device comprising:a controller that includes an error correction coding (ECC) decoder; anda non-volatile memory coupled to the controller, the non-volatile memory configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory, the soft bit data including sub codes for each of the multiple ECC codewords;the non-volatile memory configured to send at least one sub code of the soft bit data for each ECC codeword in a subset of the multiple ECC codewords to the ECC decoder, the subset including at least one, but not all, of the multiple ECC codewords.2. The data storage device of claim 1 , further comprising latches coupled to the non-volatile memory and configured to store the soft bit data.3. The data storage device of claim 1 , further comprising a bus coupled to the non-volatile memory and to the controller.4. The data storage device of claim 1 , wherein the controller includes a random access memory (RAM) coupled to the ECC decoder and configured to store the at least one sub code of the soft bit data.5. The data storage device of claim 1 , wherein the subset of ECC codewords corresponds to one-quarter of the multiple ECC codewords claim 1 , half of the multiple ECC codewords claim 1 , or three-quarters of the multiple ECC codewords.6. The data storage device of claim 1 , wherein the non-volatile memory ...

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Номер записи: 162
12-05-2016 дата публикации

DISTURB CONDITION DETECTION FOR A RESISTIVE RANDOM ACCESS MEMORY

Номер: US20160133322A1
Автор: ALROD IDAN, Liu Tz-Yi, NAVON Ariel, SHARON ERAN, Yan Tianhong, Zamir Ran
Принадлежит:

A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information. 1. A method comprising: in response to initiating a first operation targeting a first portion of the ReRAM, determining whether to access a second portion of the ReRAM, wherein the second portion is adjacent to the first portion;', 'in response to determining to access the second portion, initiating a second operation that senses information stored at the second portion to generate sensed information; and', 'in response to detecting an indication of a disturb condition based on the sensed information, initiating a third operation to rewrite the information at the ReRAM., 'at a data storage device that includes a memory die, wherein the memory die includes a resistive random access memory (ReRAM), performing2. The method of claim 1 , wherein the first operation corresponds to a write operation to the first portion of the ReRAM or a sense operation to the first portion of the ReRAM.3. The method of claim 1 , wherein the first operation accesses a first storage element that is included in the first portion of the ReRAM claim 1 , and wherein the first storage element is associated with a word line of the ReRAM and is further associated with a bit line of the ReRAM.4. The method of claim 3 , wherein the second portion of the ReRAM ...

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Номер записи: 163
12-05-2016 дата публикации

SHAPED DATA ASSOCIATED WITH AN ERASE OPERATION

Номер: US20160133324A1
Автор: ALROD IDAN, Liu Tz-Yi, NAVON Ariel, PRESMAN Noam, Yan Tianhong
Принадлежит:

A method includes, in a data storage device including a resistive memory, receiving an erase command to erase a portion of the resistive memory. The method further includes sending shaped data to be stored at the portion of the resistive memory responsive to the erase command. 113-. (canceled)14. A device comprising:a resistive memory including multiple storage elements; anda controller coupled to the resistive memory, the controller configured to receive an erase command and to send shaped data to be stored at a portion of the resistive memory responsive to the erase command.15. The device of claim 14 , wherein the portion of the resistive memory includes multiple storage elements.16. The device of claim 14 , wherein the portion of the resistive memory corresponds to a word line of the resistive memory.17. The device of claim 14 , wherein a common shaping scheme is used to generate the shaped data based on the erase command and to generate the shaped user data based on a write command.18. The device of claim 14 , wherein the shaped data includes a first number of bits having a first bit value and a second number of bits having a second bit value claim 14 , and wherein each of the first number and the second number is greater than zero.19. The device of claim 14 , wherein the shaped data is associated with a pattern of first storage elements in a low-resistance state and second storage elements in a high-resistance state.20. The device of claim 14 , wherein the controller is further configured to generate a pseudo-random sequence of data values claim 14 , and wherein the pseudo-random sequence of data values is used as the shaped data.21. The device of claim 14 , wherein the controller is further configured to determine whether the erase command is associated with a soft erase or a hard erase claim 14 , and wherein the shaped data is sent to the portion of the resistive memory based on a determination that the erase command is associated with the hard erase.22. The ...

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Номер записи: 164
19-05-2016 дата публикации

HEALTH DATA ASSOCIATED WITH A RESISTANCE-BASED MEMORY

Номер: US20160141029A1
Автор: ALROD IDAN, Bazarsky Alexander, Goldenberg Idan, Liu Tz-Yi, NAVON Ariel, SHARON ERAN, Yan Tianhong
Принадлежит:

A method of fabricating a resistance-based memory includes initiating formation of a conductive path through a storage element of the resistance-based memory. The method further includes recording data of one or more parameters associated with the formation of the conductive path. 1. A method of fabricating a resistance-based memory , the method comprising:initiating formation of a conductive path through a storage element of the resistance-based memory; andrecording data of one or more parameters associated with the formation of the conductive path.2. The method of claim 1 , wherein the conductive path is formed by applying a set of one or more voltage pulses to the storage element claim 1 , and further comprising claim 1 , after applying the set of one or more voltage pulses claim 1 , applying a test voltage to the storage element after forming the conductive path and identifying a current flow through the storage element during application of the test voltage.3. The method of claim 1 , wherein the one or more parameters includes a first parameter associated with a resistance of the storage element that indicates successful formation of the conductive path claim 1 , a second parameter associated with a first amount of current through a region of the resistance-based memory that includes the storage element based on a first test voltage applied to the region after the formation of the conductive path claim 1 , a third parameter associated with a first amount of leakage current through a neighbor storage element of the storage element based on a second test voltage applied to the storage element after the formation of the conductive path claim 1 , a fourth parameter associated with a second amount of leakage current through the storage element based on a third test voltage applied to the neighbor storage element of the storage element after the formation of the conductive path claim 1 , a fifth parameter associated with a number of voltage pulses applied to the ...

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Номер записи: 165
17-06-2021 дата публикации

ZONED NAMESPACE MANAGEMENT OF NON-VOLATILE STORAGE DEVICES

Номер: US20210182166A1
Автор: ALROD IDAN, Benisty Shay, HAHN JUDAH GAMLIEL, Meza Joe, NAVON Ariel, SHARON ERAN
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

This disclosure relates to an apparatus including a zone manager to manage memory allocation and behavior under a Zoned Namespaces (ZNS) implementation. The zone manager may include a monitor circuit, an evaluation circuit, and a signaling circuit. The monitor circuit is configured to monitor a zone metric for each zone of a non-volatile storage device. The evaluation circuit is configured to determine health for each zone based on the zone metric. The signaling circuit is configured to notify a host of the zone health for one or more zones in response to the zone metric for the zone(s) satisfying an alert threshold. 1. An apparatus , comprising: a monitor circuit configured to monitor a zone metric for each zone of a non-volatile storage device;', 'an evaluation circuit configured to determine a zone health for each zone based on the zone metric; and', 'a signaling circuit configured to notify a host of the zone health for one or more zones, in response to the zone metric of the one or more zones satisfying an alert threshold., 'a zone manager comprising2. The apparatus of claim 1 , wherein the signaling circuit is further configured to notify the host of the zone health by sending metadata for the one or more zones.3. The apparatus of claim 1 , further comprising a remediation circuit configured to implement a countermeasure in response to the zone metric satisfying a critical threshold.4. The apparatus of claim 1 , further comprising a remediation circuit configured to implement a countermeasure in response to a countermeasure command from the host.5. The apparatus of claim 1 , wherein the zone metric comprises one or more of a block health metric for each zone and a cross temperature metric for each zone.6. The apparatus of claim 1 , wherein the evaluation circuit is configured to:receive a temperature from a temperature sensor configured to monitor a plurality of physical erase blocks of each zone,determine a wear level for each physical erase block of each ...

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Номер записи: 166
09-06-2016 дата публикации

Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization

Номер: US20160163382A1
Автор: ALROD IDAN, Cernea Raul-Adrian, Conley Kevin Michael, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements. 1. A method of reading non-volatile storage , comprising:selecting a word line associated with a read operation, the word line is in communication with a group of non-volatile storage elements that are programmable to a plurality of physical states;applying to the word line a continuous scanning voltage signal that spans a range of read reference levels for the plurality of physical states;determining a threshold voltage of each non-volatile storage element based on time-domain sensing while applying the continuous scanning voltage signal;determining state information for each non-volatile storage element based on the threshold voltage from the time-domain sensing, wherein the state information exceeds a number of encoded bits in each non-volatile storage element;transferring from the non-volatile memory the state information for each storage element; andperforming an initial decode to determine data for the plurality of storage elements based on the state information for each non-volatile storage element.2. The method of claim 1 , wherein:the initial decode is a hard bit decode that uses a number of bits in the state information for each storage element that is equal to the number of encoded bits.3. The method of claim 2 , further comprising:after ...

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Номер записи: 167
28-08-2014 дата публикации

Systems and Methods for Managing Data in a System for Hibernation States

Номер: US20140245040A1
Автор: Eran Sharon, Hanan Borukhov, Idan Alrod, Yair Baram
Принадлежит: SanDisk Technologies LLC

The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor. The processor is configured to manage data storage in conjunction with hibernation of the memory device. The processor is in communication with the controller memory, the main memory and the buffer, and is configured to read data from the controller memory; write at least a portion of the data read from the controller memory into the buffer prior to the memory device entering a hibernation state; and after writing the at least a portion of the data read from the controller memory into the buffer and prior to the memory device entering the hibernation state, reduce an amount of power provided to the buffer of the to a reduced power level.

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Номер записи: 168
28-08-2014 дата публикации

ERROR CORRECTION CODING IN NON-VOLATILE MEMORY

Номер: US20140245098A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A method includes encoding data bits into codewords according to a first error correction encoding scheme. The method includes storing the codewords into a memory and generating a combined codeword by encoding, at the memory, the codewords according to a second error correction encoding scheme to generate parity bits of the combined codeword. The method includes, after storing the codewords into the memory, storing the parity bits of the combined codeword into the memory. 1. A method comprising:encoding data bits into codewords according to a first error correction encoding scheme;storing each of the codewords into a memory;generating a combined codeword by encoding, at the memory, the codewords according to a second error correction encoding scheme to generate parity bits of the combined codeword; andafter storing the codewords into the memory, storing the parity bits of the combined codeword into the memory.2. The method of claim 1 , wherein the memory includes a non volatile memory3. The method of claim 2 , wherein the non volatile memory includes a flash memory.4. The method of claim 1 , further comprising claim 1 , after storing the codewords into the memory claim 1 , reading the codewords from the memory and generating the parity bits of the combined codeword claim 1 , wherein the parity bits are generated within a memory die that includes the memory.5. The method of claim 4 , wherein the memory is a flash memory claim 4 , wherein each of the codewords are stored into a single level cell (SLC) portion of a flash memory claim 4 , and wherein the combined codeword is stored into a multi-level cell (MLC) portion of the flash memory.6. The method of claim 1 , wherein the memory is a flash memory claim 1 , wherein the combined codeword is stored into multiple logical pages of a single word line of a multi-level cell (MLC) portion of the flash memory claim 1 , and wherein each of the codewords is stored in a respective one of the logical pages.7. The method of claim ...

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Номер записи: 169
07-06-2018 дата публикации

ECC DECODER WITH MULTIPLE DECODING MODES

Номер: US20180159553A1
Автор: ALROD IDAN, Dumchin Yan, Fiterman Mark, Goldenberg Idan, ILANI ISHAI, RYABININ YURI, SHARON ERAN, Zamir Ran
Принадлежит:

A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator. 1. A device comprising:a non-volatile memory; and a message memory configured to store decoding messages;', 'multiple data processing units (DPUs);', 'a control circuit responsive to a decoding mode indicator, the control circuit configured to enable a first number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode; and', 'a reordering circuit coupled to the control circuit and configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator., 'a low density parity check (LDPC) decoder configured to receive a representation of a codeword read from to the non-volatile memory, the LDPC decoder comprising2. The device of claim 1 , wherein the LDPC decoder is configured to process the representation of the codeword based on a quasi-cyclic LDPC (QC-LDPC) parity check matrix that has a first block matrix size claim 1 , and wherein the reordering circuit is configured to selectively reorder the decoding messages to transform the ...

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Номер записи: 170
24-06-2021 дата публикации

SOFT BIT READ MODE SELECTION FOR NON-VOLATILE MEMORY

Номер: US20210191651A1
Автор: ALROD IDAN, Bazarsky Alex, SHARON ERAN
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times. 1. An apparatus , comprising:an array of non-volatile memory cells; and select a read mode from a plurality of read modes for reading data from a region of the array, the plurality of read modes comprising at least a time-based soft bit read mode;', 'apply a set of bias conditions to cells of the region such that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region; and', 'in response to selecting the time-based soft bit read mode, read hard bits and soft bits for the region by sensing the capacitor voltages resulting from the applied set of bias conditions, at multiple integration times., 'a controller configured to2. The apparatus of claim 1 , wherein:the plurality of read modes further comprises a hard bit read mode and a bias-based soft bit read mode; and in response to selecting the hard bit read mode, read hard bits for the region by sensing the capacitor voltages resulting from the applied set of bias conditions, at a single integration time; and', 'in response to selecting the bias-based soft bit read mode, read hard bits and soft bits for the region by sensing the capacitor voltages resulting from the applied set of bias ...

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Номер записи: 171
11-09-2014 дата публикации

DIRECT MULTI-LEVEL CELL PROGRAMMING

Номер: US20140254266A1
Автор: ALROD IDAN, Li Yan, Marcu Alon, Oshinsky Hadas, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A data storage device includes a controller coupled to a non-volatile memory having a three-dimensional (3D) configuration. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

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Номер записи: 172
11-09-2014 дата публикации

Simultaneous sensing of multiple wordlines and detection of nand failures

Номер: US20140254272A1
Автор: Dana Lee, Eran Sharon, Idan Alrod, Yan Li
Принадлежит: SanDisk Technologies LLC

Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.

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Номер записи: 173
30-05-2019 дата публикации

OPTIMISTIC READ OPERATION

Номер: US20190163367A1
Автор: ALROD IDAN, Bazarsky Alexander, SHAH GRISHMA, SHARON ERAN
Принадлежит: SanDisk Technologies LLC

A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host. 1. A method of executing a read operation in a non-volatile memory system , the method comprising:receiving, with a front end module, a host read request to read a requested data set, the host read request identifying a logical address associated with the requested data set,performing, with a sensing control module of a non-volatile memory die, a first sensing operation on an entry stored in a non-volatile memory array of the non-volatile memory die, the entry mapping the logical address identified in the host read request to a physical address;performing with the sensing control module, a second sensing operation on a data set stored in the nonvolatile memory array at the physical address identified in the entry without first performing error correction on a copy of the entry; andverifying, with a verification module, that a copy of the data set generated in response to the second sensing operation matches the requested data set before the front end module transfers the data set copy to the host.2. The method of claim 1 , further comprising:determining, with a cache checking module, whether a copy of the entry is stored in an external memory that is external the non-volatile memory die before performing, with the sensing control module, the first sensing ...

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Номер записи: 174
21-05-2020 дата публикации

Temperature Variation Compensation

Номер: US20200159465A1
Автор: Achtenberg Stella, ALROD IDAN, Eyal Alon, Lee Dana, ROZMAN DAVID, SHARON ERAN
Принадлежит:

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is operable to measure a first threshold voltage (Vt) of a memory cell under a first parameter at a read temperature and measure a second Vt of the memory cell under a second parameter at the read temperature in which the first parameter is different from the second parameter. A Vt correction term for the memory cell is determined based upon the first Vt measurement and the second Vt measurement. A read Vt of the memory cell is adjusted by using the Vt correction term. 1. A non-transitory computer readable storage medium containing instructions that , when executed by a controller , perform a method of accessing data from a data storage device , comprising:measuring a first threshold voltage and a second threshold voltage of a memory cell at different read parameters;determining a temperature coefficient proxy for the memory cell;retrieving an estimated temperature coefficient value correlated to the temperature coefficient proxy of the memory cell; andadjusting a read threshold voltage of the memory cell by using the estimated temperature coefficient value.2. The non-transitory computer readable storage medium of claim 1 , wherein a first parameter of measuring the first threshold voltage is a default read parameter.3. The non-transitory computer readable storage medium of claim 1 , wherein a first parameter and a second parameter are different than a default read parameter claim 1 , the method further comprising measuring a third threshold voltage of the memory cell under the default read parameter.4. The non-transitory computer readable storage medium of claim 1 , wherein the read threshold voltage of the memory cell is measured under a default read parameter at a read temperature.5. The non-transitory computer readable storage medium of claim 1 , wherein estimated temperature coefficient value is based upon an estimation of actual temperature ...

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Номер записи: 175
25-06-2015 дата публикации

Mitigating disturb effects for non-volatile memory

Номер: US20150179254A1
Автор: Eran Sharon, Idan Alrod, Menahem Lasser, Tianhong Yan, Tz-yi Liu
Принадлежит: SanDisk Technologies LLC

A method includes adjusting a counter value to indicate an access operation to a first portion of a non-volatile memory. The access operation is an erase operation or a write operation. The adjusted counter value indicates that a number of access operations to the first portion have been performed since an access operation to a second portion of the non-volatile memory has been performed. The method also includes selectively initiating a remedial action to the second portion in response to a comparison of the number of access operations to a threshold.

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Номер записи: 176
25-06-2015 дата публикации

SYSTEMS AND METHODS OF SHAPING DATA

Номер: US20150179260A1
Автор: ALROD IDAN, Liu Tz-Yi, SHARON ERAN, Yan Tianhong
Принадлежит: SANDISK TECHNOLOGIES INC.

A method of shaping data includes receiving data represented as a first set of bits, where each bit of the first set of bits corresponds to a logical value. A first write current to write a first logical value to a storage element is less than a second write current to write a second logical value to the storage element. The method also includes applying a shaping operation to generate a second set of bits, where a proportion of bits having the first logical value is larger for the second set of bits than for the first set of bits. The method also includes writing the second set of bits to the memory.

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Номер записи: 177
25-06-2015 дата публикации

SYSTEM AND METHOD OF MANAGING TAGS ASSOCIATED WITH READ VOLTAGES

Номер: US20150179284A1
Автор: ALROD IDAN, Mekhanik Evgeny, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A data storage device includes a controller coupled to a non-volatile memory. The non-volatile memory is configured to store multiple tags that include a first tag and a second tag. The controller is configured to determine one or more candidate values associated with a candidate tag. The one or more candidate values may be determined based on an operation applied to the first tag and the second tag. The controller is further be configured to cause the non-volatile memory to remove the first tag or the second tag from the multiple tags. 1. A method of merging tags , the method comprising: identifying a first tag and a second tag from a plurality of tags;', 'determine one or more candidate values associated with a candidate tag, wherein the one or more candidate values are determined based on an operation applied to the first tag and the second tag; and', 'removing the first tag or the second tag from the plurality of tags., 'in a data storage device including a controller and a non-volatile memory, performing'}2. The method of claim 1 , wherein the first tag is associated with a first set of read voltages to be applied to one or more first blocks of the non-volatile memory claim 1 , wherein the second tag is associated with a second set of read voltages to be applied to one or more second blocks of the non-volatile memory claim 1 , and wherein the one or more candidate values are associated with a candidate set of read voltages.3. The method of claim 2 , wherein each read voltage of the first set of read voltages is associated with a range of read voltage values.4. The method of claim 2 , wherein the operation comprises an average function claim 2 , and wherein the candidate set of read voltages of the candidate tag is calculated as an average of the first set of read voltages and the second set of read voltages.5. The method of claim 2 , further comprising:updating the first set of read voltages based on the candidate set of read voltages, wherein the second tag is ...

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Номер записи: 178
18-09-2014 дата публикации

SYSTEM AND METHOD OF DETERMINING READING VOLTAGES OF A DATA STORAGE DEVICE

Номер: US20140269052A1
Автор: ALROD IDAN, Avila Chris, Dusija Gautam, Huang Jianmin, Mekhanik Evgeny, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A data storage device includes a memory and a controller. In a particular embodiment, a method is performed in the data storage device. The method is performed during a read threshold voltage update operation and includes determining a first read threshold voltage of a set of storage elements of a memory according to a first technique and determining a second read threshold voltage of the set of storage elements of the memory according to a second technique. The first read threshold voltage is different from the second read threshold voltage, and the first technique is different from the second technique. 1. A method comprising: determining a first read threshold voltage of a set of storage elements of a multi-level cell memory according to a first technique; and', 'determining a second read threshold voltage of the set of storage elements of the multi-level cell memory according to a second technique,', 'wherein the first read threshold voltage is different from the second read threshold voltage and wherein the first technique is different from the second technique., 'in a data storage device including a controller and a flash memory, performing, during a read threshold voltage update operation2. The method of claim 1 , wherein the first technique is a bit error rate technique.3. The method of claim 1 , wherein the first technique determines the first read threshold voltage according to a fixed ratio of activated storage elements to non-activated storage elements.4. The method of claim 1 , wherein the first technique includes a pre-processing extrapolation operation.5. The method of claim 1 , wherein the first technique is a first cell voltage distribution technique performed at a first resolution claim 1 , and wherein the second technique is a second cell voltage distribution technique performed at a second resolution.6. The method of claim 1 , wherein the second technique is a bit error rate technique claim 1 , a cell voltage distribution technique claim 1 , or a ...

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Номер записи: 179
29-06-2017 дата публикации

Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization

Номер: US20170185299A1
Автор: ALROD IDAN, Cernea Raul-Adrian, Conley Kevin Michael, SHARON ERAN
Принадлежит: SanDisk Technologies LLC

A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements. 1. A non-volatile storage device comprising:a non-volatile memory including a plurality of non-volatile storage elements configured to store a plurality of hard bits using a plurality of physical states;a plurality of word lines coupled to the plurality of non-volatile storage elements, each word line is associated with a plurality of bit sets including two or more hard bit sets and one or more soft bit sets;a controller in communication with the non-volatile memory array, the controller configured to encode user data from a host device by interleaved coding across all of the hard bit sets associated with a selected word line and shape the user data over all of the physical states; andone or more read/write circuits configured to apply time-domain sensing to determine a threshold voltage of each non-volatile storage element of the selected word line using a continuous scanning voltage in response to a read request;wherein the controller receives in response to each read request a plurality of hard bits and one or more soft bits for each non-volatile storage element of the selected word line in a single sequence.2. The non-volatile storage device of claim 1 , wherein the one or more read/write circuits are configured to determine the plurality of ...

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Номер записи: 180
29-06-2017 дата публикации

ERROR LOCATOR POLYNOMIAL DECODER AND METHOD

Номер: US20170187391A1
Автор: ALROD IDAN, ILANI ISHAI
Принадлежит:

A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter. 1. An apparatus comprising:an interface configured to receive a representation of a codeword; and an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter associated with a first iteration of the decode operation and based on a value of an error locator polynomial associated with a prior iteration of the decode operation,', 'wherein the error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial associated with a second iteration of the decode operation and based on the first value of the parameter., 'a decoder coupled to the interface and configured to perform a decode operation to decode the representation of the codeword, the decoder comprising2. The apparatus of claim 1 , wherein the error locator polynomial generator circuit is further configured to determine a second value of the parameter during the second cycle and to ...

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Номер записи: 181
15-07-2021 дата публикации

Memory Health Tracking for Differentiated Data Recovery Configurations

Номер: US20210216412A1
Автор: ALROD IDAN, Bazarsky Alex, NAVON Ariel, SHARON ERAN
Принадлежит:

Example systems and methods provide differentiated data recovery configurations based on memory health data. A distributed storage system, such as a cloud-based storage system, stores backup data from a remote storage device using a first data recovery configuration. Based on memory health data collected from the remote storage device, a change in a memory health state of the remote storage device may be determined. Responsive to the change in the memory health state, a different data recovery configuration may be used for storing backup data going forward and reallocating previously stored backup data in the distributed storage system. 1. A computer-implemented method , comprising:storing, using a first data recovery configuration, a redundant set of data from a remote storage device in a distributed storage system;receiving memory health data associated with the remote storage device, wherein the memory health data corresponds to a memory health state of a non-transitory medium of the remote storage device;determining, based on the memory health data, a change in the memory health state of the non-transitory medium of the remote storage device; andreallocating, using a second data recovery configuration, the redundant set of data in the distributed storage system responsive to the change in the memory health state.2. The computer-implemented method of claim 1 , wherein:the remote storage device is a non-volatile memory device at a site that is remote from the distributed storage system; andreallocating the redundant set of data in the distributed storage system comprises periodically backing up a difference between a current set of data stored on the remote storage device and a comprehensive copy of data stored on the remote storage device at an earlier time.3. The computer-implemented method of claim 1 , further comprising:determining a periodic backup configuration for the remote storage device;determining at least one initial memory health value for the remote ...

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Номер записи: 182
18-09-2014 дата публикации

SYSTEM AND METHOD OF PROCESSING OF DUPLICATE DATA AT A DATA STORAGE DEVICE

Номер: US20140281134A1
Автор: AGAMI UDI, ALROD IDAN, EITAN YARDEN, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A data storage device includes a memory and a controller. A method may be performed at the data storage device. The method includes receiving a request to write data, generating a signature of the data, and searching a signature table to determine if the generated signature is in the signature table. The signature table includes at least one signature table entry that includes a signature of stored data and a physical address of the stored data. 1. A method comprising: receiving a request to write data;', 'generating a signature of the data; and', 'searching a signature table in a memory of the controller to determine if the generated signature is in the signature table, wherein the signature table includes a signature table entry corresponding to stored data, the signature table entry comprising a signature of the stored data and a physical address of the stored data., 'in a data storage device including a controller and a flash memory, performing2. The method of claim 1 , further comprising claim 1 , in response to determining that the generated signature is in the signature table:reading the stored data from the flash memory based on the physical address retrieved from the signature table entry; andcomparing the read data to the data.3. The method of claim 2 , further comprising claim 2 , in response to the read data matching the data:writing mapping information to an entry in a logical mapping table to point to the signature table entry; andincrementing a count value in a count field in the signature table entry.4. The method of claim 3 , wherein the signature table includes a second signature table entry corresponding to second stored data claim 3 , the second signature table entry comprising a second signature of the second stored data and a second physical address of the second stored data claim 3 , and further comprising:receiving a second request to write the second data;determining that a generated second signature corresponding to the second data matches ...

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Номер записи: 183
18-09-2014 дата публикации

DETECTING EFFECT OF CORRUPTING EVENT ON PRELOADED DATA IN NON-VOLATILE MEMORY

Номер: US20140281750A1
Автор: ALROD IDAN, JEON SEUNGJUNE, Li Qing, Yang Xiaoyu
Принадлежит: SANDISK TECHNOLOGIES INC.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event. 1. A method comprising: determining a read threshold voltage corresponding to a group of storage elements in the non-volatile memory;', 'determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage; and', 'comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event., 'in a data storage device including a controller and a non-volatile memory, performing2. The method of claim 1 , wherein the corrupting event is an infrared reflow process.3. The method of claim 1 , wherein determining the read threshold and the error metric are performed in response to a power-up of the controller.4. The method of claim 3 , further comprising determining a value of a recovery process indicator claim 3 , and wherein the read threshold voltage and the error metric are determined in response to the recovery process indicator indicating that a recovery process is not complete.5. The method of claim 3 , further comprising comparing a count of write/erase cycles of the non-volatile memory to a threshold claim 3 , and wherein the read threshold voltage and the error metric are determined in response to the count being less than the threshold.6. The method of claim 1 , wherein the group of storage elements stores preloaded data.7. The method of claim 1 , wherein the read threshold voltage and the error metric are determined during a recovery process performed by the controller upon power-up claim 1 , and further comprising:in response to the ...

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Номер записи: 184
18-09-2014 дата публикации

DETECTING EFFECT OF CORRUPTING EVENT ON PRELOADED DATA IN NON-VOLATILE MEMORY

Номер: US20140281772A1
Автор: ALROD IDAN, JEON SEUNGJUNE, Li Qing, Yang Xiaoyu
Принадлежит: SANDISK TECHNOLOGIES INC.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event. 1. A method comprising: determining a read threshold voltage corresponding to a group of storage elements in the non-volatile memory;', 'determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage; and', 'comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event., 'in a data storage device including a non-volatile memory that includes a three-dimensional (3D) memory and circuitry associated with operation of memory cells of the 3D memory, performing2. The method of claim 1 , wherein the corrupting event is an infrared reflow process.3. The method of claim 1 , wherein determining the read threshold and the error metric are performed in response to a power-up of the controller.4. The method of claim 3 , further comprising determining a value of a recovery process indicator claim 3 , and wherein the read threshold voltage and the error metric are determined in response to the recovery process indicator indicating that a recovery process is not complete.5. The method of claim 3 , further comprising comparing a count of write/erase cycles of the non-volatile memory to a threshold claim 3 , and wherein the read threshold voltage and the error metric are determined in response to the count being less than the threshold.6. The method of claim 1 , wherein the group of storage elements stores preloaded data.7. The method of claim 1 , wherein the read threshold voltage and the ...

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Номер записи: 185
18-09-2014 дата публикации

ERROR-CORRECTION DECODING WITH CONDITIONAL LIMITING OF CHECK-NODE MESSAGES

Номер: US20140281785A1
Автор: ALROD IDAN, FAINZILBER Omer, SHARON ERAN
Принадлежит:

An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method may include determining whether participating bits for a particular parity-check equation from the plurality of parity check equations satisfy the particular parity-check equation. The method may further include determining, based on whether the particular parity-check equation is satisfied, a magnitude of a reliability modification to one or more reliability values associated with at least one of the participating bits. The method may also include modifying the one or more reliability values by the magnitude of the reliability modification. 1. A method comprising:receiving a representation of a codeword that includes a plurality of bits, each of the plurality of bits associated with at least one bit-value and at least one reliability value, wherein the codeword is subject to a plurality of parity-check equations each of which includes participating bit-values corresponding to a respective plurality of the bits of the codeword, each bit of the codeword participating in one or more parity-check equations;determining whether the bit-values of the participating bits for a particular parity-check equation from the plurality of parity check equations satisfy the particular parity-check equation;determining for at least one participating bit, based on whether the particular parity-check equation is satisfied, at least one magnitude of a reliability modification to the reliability value associated with at least one of the participating bits; andmodifying the reliability value of the at least one participating bit as a function of the magnitude of the reliability modification.2. The method of claim 1 , further comprising:modifying one or more of ...

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Номер записи: 186
18-09-2014 дата публикации

SYSTEM AND METHOD TO REDUCE READ LATENCY OF A DATA STORAGE DEVICE

Номер: US20140281806A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: SANDISK TECHNOLOGIES INC.

A data storage device includes a memory and a controller. The controller is configured to receive a read request that indicates a logical address. The controller is further configured to perform a first read operation to retrieve a representation of an entry of a logical mapping table from the memory, and perform a second read operation to retrieve a representation of a codeword from the memory. The controller is further configured to decode the representation of the codeword to determine whether an error exists at the entry, and, prior to completion of decoding, to initiate a third read operation to retrieve first read data from a first physical address corresponding to the logical address as determined based on the representation of the entry. 1. A method comprising: receiving a read request that indicates a logical address, the read request received from a host device while the data storage device is operatively coupled to, or embedded within, the host device;', 'performing a first read operation to retrieve a representation of an entry of a logical mapping table from the memory;', 'performing a second read operation to retrieve a representation of a codeword from the memory;', 'decoding the representation of the codeword to determine whether an error exists at the entry; and', 'prior to completion of decoding, initiating a third read operation to retrieve first read data from a first physical address corresponding to the logical address as determined based on the representation of the entry., 'in a data storage device that includes a memory and a controller performing2. The method of claim 1 , further comprising claim 1 , after retrieving the first read data claim 1 , decoding the first read data to produce error corrected data and transferring the error corrected data to the host device.3. The method of claim 1 , further comprising claim 1 , when decoding the representation of the codeword identifies an error at the entry claim 1 , initiating a fourth read ...

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Номер записи: 187
18-09-2014 дата публикации

METHOD AND SYSTEM FOR ADAPTIVE SETTING OF VERIFY LEVELS IN FLASH MEMORY

Номер: US20140281820A1
Автор: ALROD IDAN, Bekkerman Ilya, PRESMAN Noam, SHARON ERAN
Принадлежит:

A system and method for computing MLC flash memory cell programming parameters to dynamically adjust verify voltage levels is provided. The method may use an iterative guess and check process that will result in a distribution of states, specifically a cell voltage distribution (CVD) that minimizes the cell error rate in cells encoded in interleaved error correction code (ECC) mode, and that balances the bit error rate between pages in cells encoded in non-interleaved ECC mode. 1. A method for adaptively setting write verify levels in a flash memory device , the method comprising: determining if a verify level trigger event has occurred;', 'responsive to determining that the verify level trigger event has occurred, determining a cell voltage distribution (CVD) for each of a plurality of states of multi-level cell (MLC) memory cells in a group of the MLC memory cells; and', 'based on the determined cell voltage distribution, adjusting a write verify level for a portion of the plurality of states to achieve a desired error probability distribution between states in the group of the MLC memory cells of the flash memory device., 'in a controller of the flash memory device, the controller2. The method of claim 1 , wherein the verify level trigger event comprises completion of a predetermined number of program and erase cycles in the group of the memory cells in the flash memory device.3. The method of claim 1 , wherein the verify level trigger event comprises detecting a bit error rate or cell error rate greater than a respective predetermined threshold.4. The method of claim 1 , wherein:the group of the MLC memory cells comprise MLC memory cells programmed in an interleaved ECC mode;the desired error probability distribution between states in the group of the MLC memory cells of the flash memory device comprises a minimized cell error rate for the group of the MLC memory cells; andadjusting the write verify level comprises moving the portion of the plurality of write ...

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Номер записи: 188
18-06-2020 дата публикации

NON-VOLATILE STORAGE SYSTEM WITH DATA SHAPING MEMORY PARTITIONS

Номер: US20200192591A1
Автор: ALROD IDAN, Bazarsky Alex, NAVON Ariel, SHARON ERAN
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

A non-volatile storage apparatus comprises a non-volatile storage and a control circuit connected to the non-volatile storage. The non-volatile storage structure is organized into multiple partitions. Each partition is preassigned to a different data shaping level. Data to be stored in the non-volatile storage is shaped based on its entropy. The control circuit is configured to write shaped data to a partition of the multiple partitions that is preassigned to a same shaping level as the shaped data. 1. A non-volatile storage apparatus , comprising:a non-volatile storage structure comprising non-volatile memory cells organized into multiple partitions, each partition preassigned to a different shaping level; anda control circuit connected to the non-volatile storage structure, the control circuit is configured to write shaped data to a partition of the multiple partitions that is preassigned to a same shaping level as the shaped data.2. The non-volatile storage apparatus of claim 1 , wherein:the control circuit is configured to receive data, determine entropy of the data, choose a shaping level for the data based on the determined entropy, shape the data to achieve the chosen shaping level which results in the shaped data, transform the shaped data by rearranging bits into runs of same values, and choose the partition of the multiple partitions that is preassigned to the same shaping level as the shaped data.3. The non-volatile storage apparatus of claim 1 , wherein:the control circuit is configured to receive data, choose a shaping level for the data based on the determined entropy, shape the data to achieve the chosen shaping level which results in the shaped data, and choose the partition of the multiple partitions that is preassigned to the same shaping level as the shaped data.4. The non-volatile storage apparatus of claim 1 , wherein:the control circuit is configured to transform the shaped data by rearranging bits into runs of same values prior to writing the ...

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Номер записи: 189