СПОСОБ ВЗАИМОДЕЙСТВИЯ С ВЫЧИСЛИТЕЛЬНЫМ УСТРОЙСТВОМ НА БОРТОВОЙ ШИНЕ ТРАНСПОРТНОГО СРЕДСТВА

Изобретение относится к способу взаимодействия с вычислительным устройством на бортовой шине транспортного средства. Технический результат заключается в предотвращении бесполезной нагрузки шины. Способ диалога при помощи первой шины (1), установленной в транспортном средстве, с первым вычислительным устройством (12, 13, 14), соединенным со второй бортовой шиной (2) транспортного средства, при этом первая шина соединена со второй шиной через второе вычислительное устройство (11), а третье вычислительное устройство (10) соединено с первой бортовой шиной и выполнено с возможностью обработки главной команды, предназначенной для первого вычислительного устройства (12, 13, 14), содержит этапы, на которых: генерируют (102), с помощью третьего вычислительного устройства (10), команду записи описания (27) указанной главной команды в первой выделенной зоне (61) данных второго вычислительного устройства (11); передают (104), с помощью третьего вычислительного устройства (10), указанную команду записи ...

УСТРОЙСТВО И СПОСОБ ДЛЯ ПОСЛЕДОВАТЕЛЬНОЙ ПЕРЕДАЧИ ДАННЫХ С ВЫСОКОЙ СКОРОСТЬЮ

Изобретение относится к области передачи данных, в частности к передаче данных между двумя абонентами шинной системы передачи данных. Технический результат заключается в повышении гибкости управления передачей сообщений по шине в реальном времени. Технический результат достигается за счет устройства для подключения абонента шины к двухпроводной коммуникационной шине, позволяющего абоненту шины с использованием устройства посылать другим подключенным к шине абонентам и принимать от них сообщения, представляемые последовательностью доминантных и рецессивных уровней сигнала на линиях шины, содержащего первые средства, предназначенные для установления доминантного уровня сигнала в виде первой заданной разности напряжений между двумя линиями шины путем формирования первого электрического тока, выполненного с возможностью установления рецессивного уровня сигнала в виде второй заданной, не обязательно отличной от нуля разности напряжений между двумя линиями шины за счет протекания тока разряда ...

СПОСОБ И УСТРОЙСТВО ДЛЯ УПРАВЛЕНИЯ РЕЖИМОМ УСТРОЙСТВА

Изобретение относится к области вычислительной техники. Технический результат заключается в обеспечении управления режимом устройства за счет его конфигурирования. Способ содержит этапы, на которых происходит: определение напряжения Vbus на контакте Vbus в USB-разъеме на устройстве; сравнение напряжения Vbus с порогом; определение, прикладывает ли устройство напряжение к контакту Vbus; конфигурирование устройства на основании сравнения напряжения Vbus и порога и определения, прикладывает ли устройство напряжение к контакту Vbus. 2 н. и 13 з.п. ф-лы, 5 ил.

СПОСОБЫ И УСТРОЙСТВО ДЛЯ ОСУЩЕСТВЛЕНИЯ СВЯЗИ ЧЕРЕЗ УДАЛЕННОЕ ТЕРМИНАЛЬНОЕ УСТРОЙСТВО

Изобретение относится к области вычислительной техники для осуществления связи через удаленное терминальное устройство. Технический результат заключается в улучшении инструментов настройки сети и мониторинга сети. Приведенное в качестве примера устройство содержит первый модуль центрального процессора, который предназначен для связи с хостом системы управления технологическим процессом. Приведенное в качестве примера устройство также содержит первую стойку, содержащую объединительную панель и множество щелевых разъемов. Множество щелевых разъемов содержит основной щелевой разъем для приема первого модуля центрального процессора. Объединительная панель соединяет с возможностью связи первый модуль центрального процессора по меньшей мере с одним из первого модуля связи или первого модуля ввода-вывода, вставленного во второй из щелевых разъемов. Объединительная панель содержит первую коммуникационную шину для передачи данных ввода-вывода и вторую коммуникационную шину для передачи по меньшей ...

УСТРОЙСТВО И СПОСОБ ИНТЕРФЕЙСА С ВЫСОКОЙ СКОРОСТЬЮ ПЕРЕДАЧИ ДАННЫХ

Изобретение относится цифровым интерфейсам передачи данных для мобильных устройств. Техническим результатом является управление состоянием энергопотребления клиентского устройства от главного устройства. Результат достигается тем, что обеспечивают пакет возможностей клиентского устройства, содержащий поле возможностей состояния энергопотребления клиентского устройства, отправляют пакет возможностей клиентского устройства при помощи клиентского устройства на главное устройство после запроса главным устройством, выбирают конкретное поддерживаемое клиентским устройством состояние энергопотребления из по меньшей мере одного поддерживаемого клиентским устройством состояния энергопотребления при помощи главного устройства и отправляют пакет состояния энергопотребления от главного устройства на клиентское устройство, причем пакет состояния энергопотребления содержит выбранное конкретное поддерживаемое клиентским устройством состояние энергопотребления. 3 н. и 24 з.п. ф-лы, 22 табл., 116 ил.

Адаптер тестирования канала PCI Express

Полезная модель относится к области вычислительной техники. Технический результат заключается в расширении функциональных возможностей адаптера за счет обеспечения возможности тестирования PCI Express соединителей, не ухудшать тактирующий сигнал и сигнал выбора режима тестирования при переходе с одного адаптера в другой, при подключении их в цепочку. Технический результат достигается за счет адаптера тестирования канала PCI Express, содержащего семь штыревых соединителей, девять перемычек и программируемую логическую интегральную схему, содержащую внутренний JTAG интерфейс, причем адаптер дополнительно содержит четыре буфера и ножевой соединитель PCI Express. 1 ил.

СИГНАЛЬНЫЙ ИНТЕРФЕЙС ДЛЯ ВЫСОКИХ СКОРОСТЕЙ ПЕРЕДАЧИ ДАННЫХ

... 1. Интерфейс передачи цифровых данных для передачи цифровых данных представления на высокой скорости между ведущим узловым устройством и клиентским устройством по каналу связи, содержащий: множество структур пакетов, соединенных вместе, для формирования протокола связи, для обмена заранее выбранным набором цифровых управляющих данных и данных представления между ведущим узлом и клиентом по упомянутому каналу связи; и по меньшей мере, один контроллер линии связи, размещающийся в упомянутом ведущем узловом устройстве, подключенном к упомянутому клиенту посредством упомянутого канала связи, сконфигурированный с возможностью генерирования, передачи и приема пакетов, формирующих упомянутый протокол связи, и формирования цифровых данных представления в один или более типов пакетов данных.2. Интерфейс по п.1, дополнительно содержащий упомянутые пакеты, сгруппированные вместе в рамках мультимедийных кадров, которые передаются между упомянутым ведущим узлом и клиентом, имеющих заданную фиксированную ...

ВСПОМОГАТЕЛЬНЫЕ ЗАПИСИ ПО КАНАЛУ АДРЕСА

... 1. Система обработки данных, содержащая: ! принимающее устройство; ! шину, содержащую первый, второй и третий каналы; и ! отправляющее устройство, сконфигурированное для адресации к принимающему устройству по первому каналу, и чтения полезной нагрузки от принимающего устройства по второму каналу, причем отправляющее устройство дополнительно сконфигурировано для выбора между первым и третьим каналами для записи полезной нагрузки на принимающее устройство. ! 2. Система обработки данных по п.1, в которой отправляющее устройство дополнительно сконфигурировано для записи полезной нагрузки в первый адрес принимающего устройства по первому каналу и записи второй полезной нагрузки во второй адрес принимающего устройства по третьему каналу. ! 3. Система обработки данных по п.1, дополнительно содержащая второе принимающее устройство, и в которой отправляющее устройство дополнительно сконфигурировано для записи полезной нагрузки на принимающее устройство по первому каналу и записи полезной нагрузки ...

Модуль типовых авиационных интерфейсов

Изобретение относится к области вычислительной техники. Технический результат заключается в расширении функциональных возможностей за счет возможности подключения к оптическим или медным линиям связи для обмена данными по сети AFDX, Ethernet и возможности подключения мезонинов с набором интерфейсов, совместимым с компьютером типа Raspberry Pi. Технический результат достигается за счет модуля типовых авиационных интерфейсов, который содержит модуль-носитель, представляющий собой печатную плату, на которой расположены торцевой разъём приема-выдачи дискретных сигналов и сигналов физического уровня авиационных интерфейсов, разъёмы для подключения сигналов физического уровня мезонинов, разъемы серии PLD для подключения промежуточных шин мезонинов, разъемы серии PBD для подключения вычислительного устройства, встроенный блок преобразования физического уровня дискретных сигналов +27В/разрыв и Корпус/разрыв, разъём для приёма-передачи логических уровней дискретных сигналов, также модуль типовых ...

ЛОГИКА ИНТЕРФЕЙСА ДЛЯ МНОГОЯДЕРНОЙ "СИСТЕМЫ НА КРИСТАЛЛЕ" (SoC)

... 1. Устройство содержащее: !"систему на кристалле" (SoC), включающую в себя: ! первое ядро и второе ядро; ! логику интерфейса, соединенную с первым ядром и вторым ядром, причем логика интерфейса включает в себя логику брандмауэра, логику шины и тестовую логику; ! логику набора схем, соединенную с логикой интерфейса и включающую в себя контроллер памяти, который обеспечивает возможность обмена данными с памятью, соединенной с SoC; и ! логику виртуального брандмауэра, соединенную между логикой набора схем и вторым ядром, в котором второе ядро может быть отключено во время нормальной работы для обеспечения одноядерной SoC. ! 2. Устройство по п.1, в котором логика шины, предназначенная для наложения сигналов шины и тестовых сигналов непосредственного доступа из первого и второго ядер на первый набор взаимных соединений, соединенных между логикой интерфейса и логикой набора схем. ! 3. Устройство по п.2, в котором логика набора схем, предназначенная для наложения на сигналы шины и тестовые сигналы ...

VERFAHREN UND VORRICHTUNG ZUR NRZ-DATENSIGNALENÜBERTRAGUNG DURCH EINE ISOLIERUNGBARRIERE IN EINER SCHNITTSTELLE ZWISCHEN NACHBARVORRICHTUNGEN AUF EINEM BUS

Datenverarbeitungssystem mit einer Adressenbus-Steuereinrichtung

BUSBRÜCKE

ADRESSENBUS-STEUEREINRICHTUNG

Parallel data bus

A parallel data bus is used to connect several units of a data processing device. To increase the clock speed and transfer capacity, as well as to give the possibility of simultaneous transmission by several units and of pipeline operation, the data bus is divided into various sections by a plurality of intermediate registers, by means of which data can be transmitted on the data bus independently at any time, and can be transported in the form of a large shift register, like a conveyor belt. Also, the functions of the units and of the data bus at each point in the program are determined in advance, and are controlled globally by a control unit. Preferably, several intermediate registers are connected in parallel, and intermediate registers are also provided for access to the data bus and for taking data from it. The data bus can be constructed modularly, so that all sections of one or more buses, which are connected in parallel and belong to a particular unit, are combined with one part ...

SERIELLE SCHNITTSTELLE DIE, IN ZWEI UNTERSCHIEDLICHEN MODI, SERIELLE DATEN ZU ÜBERTRAGEN IMSTANDE IST

BUSBETRIEB VON INTEGRIERTEN SCHALTUNGEN MIT ABGESCHALTETER VERSORGUNGSSPANNUNG

Schaltbarer Bustreiberabschlusswiderstand

Serializer/De-serializer bus and controller for a ASIC with a method for testing the ASIC.

An application specific integrated circuit (ASIC) uses a dedicated interface between its core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core. The ASIC has a controller configured as the interface and a plurality of receivers connected to the SBus, distributed about the chip. The controller interfaces with the core asynchronously. The controller may have a test interface that operates asynchronously to the core interface. The controller may have a programmable divider to configure the SBus clock. The controller may have a state machine that issues consecutive SBus commands at set intervals. Each of the receivers may have a plurality of clocks, each clock having a distinct period from the other clocks. Also, disclosed is a method of providing the SBus capabilities to the core by coupling the core to the SBus controller via a multiple conductor interface. In addition, a method of testing the ASIC is disclosed. The method of testing comprises ...

ADDRESS BUS CONTROL APPARATUS

Retrieving status information from a remote device and corresponding host system

Methods and apparatus to implement communications via a remote terminal unit

Methods and apparatus to implement communications via a remote terminal unit are disclosed. An example apparatus includes a first central processing unit module to be in communication with a host of a process control system. The example apparatus also includes a first rack including a backplane and a plurality of slots. The plurality of slots includes a master slot to receive the first central processing unit module. The backplane communicatively couples the first central processing unit module to at least one of a first communication module or a first input/output (I/O) module inserted in a second one of the slots. The backplane includes a first communication bus for communication of I/O data and a second communication bus for communication of at least one of maintenance data, pass- through data, product information data, archival data, diagnostic data, or setup data. The first communication bus is independent of the second communication bus.

Address translation for input/output devices using hierarchical translation tables

Socket insert and socket for an aircraft seat

A socket insert comprises a lower housing section 3 and an upper housing section 2. The lower housing section incorporates a current infeed terminal 4, such as a LAN port. The upper housing section has a snap-fit connecting part 7 on one of the sidewalls. The socket insert further comprises a cover plate 1, which is integrally connected to the upper housing section and incorporates at least one device terminal 5a such as a USB socket which is electrically connected to the current infeed terminal. The cover plate has an overhang 1a which projects beyond the side walls of the upper housing section. The cover plate may also include LEDs 6a. The snap-fit arm may have step-shaped graduations to fit panels of different thicknesses, and two adjacent arms may have different sized steps. Holes 7a may allow the insertion of a release tool (W, Fig 4). The socket insert may be used to quickly change a socket inside an aircraft.

Multiple independant on-chip interconnect

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

DEVICE FOR THE PRESERVATION OF THE PRODUCER CONSUMER ARRANGEMENT ALONG AN UNORDERED INTERFACE

RECOGNITION OF THE CONNECTION TO A USB HOST OR STROKE WITHOUT USE OF AN EXTRA STATUS INPUT

FLOW CONTROL PROCEDURE FOR IMPROVED DATENTRANSFER VIA CROSSPOINT SWITCH

REPEATED BURST MINUTEs EINRICHTUNGSSTEUERUNG

SCALE-CASH BUS STRUCTURE

TO SWITCH OFF PROCEDURE AND DEVICE FOR REMOVING AND INSTALLING A COMPUTER SYSTEM BUS AGENT WITHOUT THE SUPPLY VOLTAGE OF THE COMPUTER SYSTEM

STATICALLY PULSING BUS CIRCUIT AND PROCEDURE WITH DYNAMIC CURRENT SUPPLY RAIL SELECTION

SCALE-CASH HOUSE TAX PLATFORM AND - ARCHITECTURE

DATA PROCESSING SYSTEM

DATA PROCESSING SYSTEM WITH RETARDED CACHE RECORDING PROCEDURE.

SEMICONDUCTOR CIRCUIT FOR ELECTRONIC EQUIPMENT

SCALE-CASH DATA ACQUISITION AND RECHENGERÄT

RADIAL TYPE OF PARALLEL SYSTEM BUS STRUCTURE

ARBITRATION MECHANISM FOR ASSIGNING CONTROL OF A COMMUNICATIONS PATH

PXI device for video generation and acquisition

Disclosed herein is a video generation and acquisition device (2) based on PXI technology and designed to: acquire 5 a plurality of input video signals having different video formats from one or more video display systems under test and/or from one or more video sources; receive one or more input sync signals; process one or more of the input video signals; carry out frame grabbing from one or more of the 10 input video signals; generate and output a plurality of video test patterns having different video formats; and generate and output one or more video signals which have different video formats and are, each, synchronized with a respective input sync signal. Figure 1 PXI Bus Data 2) 0 Y/ C Y/ P Master a- Clock U) 12 Power FRONTL INTA-BAR 2 x CVBS 4 xRGB B Burst Power FIG. 1 FRONT INTRA-BOARD CONNECTOR CONNECTOR MON01CONNECTOR FIG.

HIGH SPEED LOW PIN COUNT BUS INTERFACE

Docking system and method

DATA COMMUNICATION DEVICE AND SYSTEM

The present disclosure provides a data communication device and a data communication system. The data communication device includes a power supply interface coupled to a direct current power supply, a wired communication interface, a main control chip, and an energy storage component. The data communication system includes a master communication device and a slave communication device.

A METHOD AND APPARATUS TO CONTROL A MODE OF A DEVICE

A method of controlling a mode of a device is provided. The method includes determining a Vbus voltage on a Vbus pin in a USB connector on the device, comparing the Vbus voltage with a threshold, and configuring the device based on the comparison of the Vbus voltage and the threshold.

PARALLEL PROCESSING SYSTEM

Disclosed is an improved parallel processing system using a radial bus assembly comprising a stack of disks each having an integrated circuit crossbar switch fixed at its center, a plurality of communication lines of equal length radially extending from the communication terminals of the crossbar switch and terminating on the circumference of the disk, a plurality of control lines each being arranged between adjacent communication lines, and radially extending from the control terminals of the crossbar switch and terminating short of the circumference of the disk, and maleand-female joints to electrically connect the terminations of the control lines of all disks in terms of same angular positions longitudinally in common. This arrangement permits substantial reduction of disk size by shifting the control terminals from the circumference of the disk to the inside space thereof, thus accordingly reducing the whole size of the laminated cylindrical bus structure, and hence increasing the ...

MECHANISM FOR THE UNIFICATION OF PROCESS SIGNALS.

System and procedure for the control of bus-interlaced devices over an open field bus, bus participant for such an system and arrangement comprehensively such a system and at least such a bus participant.

Bei einem System und einem Verfahren zur Steuerung von busvernetzten Geräten mit einem Gateway über einen offenen Feldbus soll eine Vereinfachung derart vorgesehen werden, dass eine aufwändige Verdrahtung entfällt und der Anwender mit geringem Bedienaufwand das System überprüfen, konfigurieren und bei Fehlermeldungen neu starten kann. Hierzu ist bei einem solchen System eine einzige steckbare Verbindungsleitung (8) innerhalb des Systems zum Verbinden von Busteilnehmern (N1 bis Nx) und Gateway (20) und zur Übertragung von Steuer- und/oder Statusdaten und Energie vorgesehen. Bei einem Verfahren zur Steuerung von busvernetzten Geräten in Schaltkreisen mit einem Gateway über einen offenen Feldbus erwartet zur Lösung des Problems das Gateway in einer Ausgangs-Soll-Konfiguration keinen Busteilnehmer (N1 bis Nx) und wird zur Übernahme zumindest eines Busteilnehmers (N1 bis Nx) und Erzeugen einer neuen Soll-Konfiguration mit dem zumindest einen Busteilnehmer (N1 bis Nx) ein Konfigurationsmodus ...

Method for operating a ring spinning machine and ring spinning machine.

Offenbart ist ein Verfahren zum Betreiben einer Ringspinnmaschine mit einer Vielzahl von Spindeln (8), die auf einer Spindelbank (22) angeordnet sind, und jeweils einen elektrischen Antrieb (9) umfassen, wobei jeder elektrische Antrieb (9) ein dezentrales Kontrollmodul (10) aufweist, welches mit dem elektrischen Antrieb (9) zusammenwirkt, welches durch Mittel zur Kommunikation mittels eines Datenbuses (13, 14) mit einer übergeordneten Zentralkontrolleinrichtung (12) kommunizieren kann. Erfindungsgemäss ist ein vom Datenbus (13, 14) unabhängiges, digitales Kommunikationsnetzwerk (15) zwischen der Zentralkontrolleinrichtung (12) und den dezentralen Kontrollmodulen (10) vorhanden, über welchen zeitgleich alle dezentralen Kontrollmodule (10) der elektrischen Antriebe (9) von der Zentralkontrolleinrichtung (12) angesprochen werden. Die Erfindung bezieht sich auch auf eine entsprechende Ringspinnmaschine.

A DATA LOAD UNIT

Device for evaluating whether e.g. radio of car is compatible with e.g. apparatuses, has switching elements successively connecting root connector to secondary connectors by switching independent of power and data tracks

Pour évaluer si un système électronique (40) comportant un premier connecteur (47) équipé d'une ou plusieurs pistes de puissance (GND, 5V) et d'une ou plusieurs pistes de données (D-, D+), est compatible avec successivement au moins deux appareils (41, 42) connectables chacun sur le premier connecteur (47), un dispositif (1) comprend un deuxième connecteur (17) équipé d'une ou plusieurs pistes de puissance (GND, 5V) et d'une ou plusieurs pistes de données (D-, D+) prévu pour être raccordé au premier connecteur (47), au moins deux troisièmes connecteurs (11, 12) équipés d'une ou plusieurs pistes de puissance (GND, 5V) et d'une ou plusieurs pistes de données (D-, D+) prévus pour être raccordés chacun à l'un des appareils (41, 42), et un mécanisme pour relier le deuxième connecteur (17) successivement à chacun des troisièmes connecteurs (11, 12) au moyen d'une commutation indépendante de la ou des pistes de puissance (GND, 5V) et de la ou des pistes de données (D-, D+) du deuxième et du troisième ...

SYNCHRONOUS DATA LINK CONTROL COMMUNICATION DEVICE

The present invention relates to a synchronous data link control communication device. More specifically, the synchronous data link control communication device is installed on a power management controller (PMC) board in a central process device board and provides a four-channel synchronous data link control communication function. The present invention comprises: a central process block for performing data link control communication; and a connection board block for being connected to the central process board block formed on one board and being connected to an external communication device. COPYRIGHT KIPO 2017 (111) FPGA data link controller (112) CLK circuit (113) Power supply circuit (121) PCI chip (221-1) P11 PMC connector (222-2) P12 PMC connector (222-3) P14 PMC connector ...

가상 PCI 장치 및 가상 MMIO 장치를 형성하기 위한 일반적인 방법

... 가상 장치를 가상 PCI(Peripheral Controller Interconnect) 장치 또는 가상 입출력(I/O) 장치 중 적어도 하나로서 형성하기 위한 방법을 구현하기 위한 기술이 개시된다. 본 개시 내용의 방법은 PCI 호환 장치에 대한 요청을 수신하는 단계를 포함한다. 방법은 PCI 호환 장치에 대한 요청에 기초하여 가상 장치를 형성하는 단계를 더 포함하며, 가상 장치는 가상 PCI 장치 또는 가상 I/O 장치 중 적어도 하나로서 형성된다.

INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING SAME, AND STORAGE

An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a determination unit, an address translation unit, a controller unit, and a transmission unit. The receiving unit receives data and address information from the first chip. The determination unit determines whether the received address information corresponds to an address translation area based on address translation information set to the resister. The address translation unit outputs translated address information to an internal bus. The controller unit perform control to store data to which address information corresponding to an address area set for the second chip is attached. The transmission unit transmits to the third chip data to which address information is attached. The address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip ...

SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor device for training a control signal. The semiconductor device comprises: an effective command generation circuit for generating a latch chip selection signal and a latch control signal by latching an internal chip selection signal and an internal control signal by synchronizing with a division clock, and generating an effective command to perform a preset function from the latch control signal; and a training control circuit for generating a training result signal from the latch chip selection signal or the latch control signal in response to a flag. COPYRIGHT KIPO 2018 (1) Input buffer circuit (2) Divided clock generator (3) Effective command generation circuit (4) Flag generation circuit (5) Training control circuit (7) Operation control circuit ...

ELECTRONIC DEVICE

Embodiments of the present invention are to provide an electronic device including a semiconductor memory that may improve characteristics of a variable resistor element. The electronic device for solving the above aspects according to an embodiment of the present invention is the electronic device including the semiconductor memory. The semiconductor memory may include: a stack in which an insulation layer and a horizontal electrode are alternately stacked on a substrate; a square hole pattern that passes through the stack; a plurality of vertical electrodes that are formed on side walls of the square hole pattern; and variable resistor layers that are interposed between each of the plurality of vertical electrodes and the horizontal electrode. According to the electronic device including the semiconductor memory according to embodiments of the present invention, characteristics of the variable resistor element may be improved. COPYRIGHT KIPO 2017 ...

Memory interface for volatile and non-volatile memory devices

A switching I/O node for connection in a multiprocessor computer system

A switching I/O node for connection in a multiprocessor computer system. An input/output node switch includes a bridge unit and a packet bus switch unit implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link in response to determining the destination each of the upstream packet transactions.

CONTROL MODULE AND CABLES FOR NETWORKING ELECTRICAL DEVICES

Systems are described for controlling electrical (typically unautomated electrical) devices with a programmed control module including electronic memory and a computer processor together with a selection of purpose-specific cables selected from any of infrared IR (send and/or receive), serial cables, power cables, sensor cables or others. One such additional example is a relay / contact-closure cable includes circuitry for modifying its communication parameters and/or providing a power boost for expanded power-intensive uses. A serial cable includes circuitry for modifying its gender and/or other communication parameters. A system or kit includes the cable and a conversion connector to physically alter cable connection gender. Such a system or kit may also include the control module.

SERIAL PORT REDIRECTION PROCESSING METHOD, DEVICE, AND SYSTEM

Embodiments of the present invention provide a serial port redirection processing method, device, and system. A method comprises: A motherboard calls a redirection program, writes, according to the physical address and memory size of a shared memory, the input information received by the motherboard into the input buffer of the shared memory as the serial port input information, and reads the information in the output buffer of the shared memory as the serial port output information; the shared memory is used for serial port management between the motherboard and a peripheral component interconnect express (PCIE) device inserted on the mother board. The embodiments of the present invention conserve serial port connection wires, and require no manual on-site debugging, thereby enhancing debugging efficiency.

MULTISECTIONAL BUS IN RADIO BASE STATION AND METHOD OF USING SUCH A RADIO BASE STATION

A communication system has a monitor (31), memory (33,49) and one or more resources (35(i), 37(j), 39(k), 41(m), 43(n), 45(o), 47(p)). The memory (33,49) is connected to the monitor (31) and stores tasks and data. Each of the resources (35(i), 37(j), 39(k), 41(m), 43(n), 45(o), 47(p)) is connected to the monitor (31) and performs a function or executes a program. The bus (51) is implemented by a plurality of adjacent sections, each section being implemented as an ASIC connected to a resource.

Memory interface for volatile and non-volatile memory devices

Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Method and Apparatus for Conditional Broadcast of Barrier Operations

A weakly-ordered processing system implements an execution synchronization bus transaction, or "memory barrier" bus transaction, to enforce strongly-ordered data transfer bus transactions. A slave device that ensures global observability may "opt out" of the memory barrier protocol. In various embodiments, the opt-out decision may be made dynamically by each slave device asserting a signal, may be set system-wide during a Power-On Self Test (POST) by polling the slave devices and setting corresponding bits in a global observability register, or it may be hardwired by system designers so that only slave devices capable of performing out-of-order data transfer operations participate in the memory barrier protocol.

Network on-chip topology generation

The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. A color is assigned to each HCG node to minimize HoL conflicts. A traffic graph (TG) is constructed for each color based on the physical data, the bridge data, the traffic data and the HCG, and a candidate topology is generated for each color based on the respective TG. The candidate topology for each color is merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.

System and method for sending multiple data signals over a serial link

A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data streams and then merges the encoded data into a serial stream that is output across a serial line to the removing unit. The removing unit receives a serial stream of data, decodes the serial stream, and then separates the decoded serial stream into separate streams thereby reconstructing the streams input to the embedding unit. The encoding and transmission by the embedding unit and the receipt and decoding by the removing unit are completely transparent, the signals output by the removing unit are identical in timing and data content to the signals input to the embedding unit. The present invention also includes a method for transmitting a plurality of data streams over a signal line, and a method for generating a plurality of data streams from a serial sequence ...

Interface system for a television receiver

An interface system for a television receiver includes an interface connector having a plurality contacts connected to various component circuits in the television receiver. In order to provide various functions for the television receiver, the interface system includes various circuit boards each having a plug connectable with the interface connector. The plug includes a number of contacts equal to or less than the plurality of contacts in the interface connector. Depending on the desired function, the circuit board further includes circuits for providing the function, these circuits being interconnected and connected to the appropriate contacts in the plug for connecting with the appropriate component circuits in the television receiver. The interface system allows the television receiver functions to be modified and/or updated without the need for opening the television and modifying the circuits and/or the wiring to the circuits.

Scalable high performance 3D graphics

A high-speed ring topology. In one embodiment, two base chip types are required: a "drawing" chip, LoopDraw, and an "interface" chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Data transmission circuit for digital signal processor chip and method therefor

A data transmission circuit for a digital signal processor chip having a plurality of function blocks, a plurality of global buses which may be selectively connected to each other, and a plurality of local buses which may be selectively connected to an associated global bus and an associated function block. The circuit includes a plurality of first switches for selectively connecting the plurality of local buses to both the plurality of function blocks and the plurality of global buses, and a plurality of second switches means for selectively connecting the plurality of global buses. In a data transmission method for a digital signal processor chip, only those local buses and global buses necessary for data transmission are connected when data is transmitted between the plurality of function blocks. Therefore, movement of data through buses irrelevant to the desired operation is eliminated, and electrical consumption is reduced.

Network control model driver

A method and apparatus of operating a Universal Serial Bus device to determine if a host sending Network Control Model Transfer Blocks (NTBs) is compliant with end of transfer rules for NTBs and to then determine appropriate operations at the device to complete transactions with a non-compliant host.

Hot plug interface control method and apparatus

Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

Configurable multi-lane scrambler for flexible protocol support

Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (LSB) and most significant bit (MSB) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

AUXILIARY WRITES OVER ADDRESS CHANNEL

A method for communicating via a bus including a first channel, a second channel, and a third channel is disclosed. The method includes addressing a slave device via the first channel, receiving from the slave device via the second channel, and writing to the slave device via the third channel. The method further includes selecting between first and second bus transmission modes. In the first bus transmission mode, payload write data is to be sent to the slave device via the first channel or the third channel. In the second bus transmission mode, during a first clock cycle, second payload write data associated with a second write operation is to be sent to the slave device via the first channel and first payload write data associated with a first write operation is to be concurrently sent to the slave device via the third channel.

Device for processing a stream of data words

State of the art processor systems, esp. in embedded systems, are not able to process data under real-time conditions especially with throughput rates near 10 Gbps. So, when using interfaces like PCI Express (PCIe) or Infiniband or 10 G-Ethernet for 10 Gbps data throughput, special data-paths have to process the high throughput rate data. But tasks like connection management or time uncritical control messaging are better manageable by a processor. According to the invention it is proposed a kind of multiplexer architecture that is needed to split between control and data-path access for a PCI Express based architecture.

Integration of a programmable device and a processing system in an integrated circuit package

An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

High speed memory modules utilizing on-pin capacitors

Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a capacitor connected in parallel to the TS line or STS line and the DRAM device or SDRAM device. A computing system implementing the memory modules is also discussed.

Ноt plug intеrfасе соntrоl mеthоd аnd аppаrаtus

Ноt plug mоdulеs соmprising prосеssоrs, mеmоrу, аnd/оr I/О hubs mау bе аddеd tо аnd rеmоvеd frоm а running соmputing dеviсе withоut rеbооting thе running соmputing dеviсе. Тhе hоt plug mоdulеs аnd соmputing dеviсе соmprisе hоt plug intеrfасеs thаt suppоrt hоt plug аdditiоn аnd hоt plug rеmоvаl оf thе hоt plug mоdulеs.

Modular motherboard for a computer system and method thereof

One feature pertains to a modular design of a motherboard for a computer system. The mother board is disaggregated into a CPU board and an IO board. The CPU board contains at least one CPU, the associated memory subsystem and the voltage regulator module. The integrated IO ports escape to a high speed connector mating with its counterpart on an IO board which contains all peripheral devices including system logic not part of the CPU. In a multi-socket configuration the CPUs are on the CPU board and the processor interconnects are routed directly in a point to point manner.

High performance computer system

A high performance computer system with a plurality of processors and memory modules is arranged with the processor modules stacked one upon the other with first switch modules in a first stack and with the memory modules stacked one on the other with second switch modules in a second stack. The first and second stacks are arranged adjacent to each other with the first and second switch modules diagonally opposed. Interconnecting bus lines couple the processors to the memory modules through the first switch modules and couple the memory modules back to the processors through the second switch modules. The flow of data is in one direction through the memory modules and switches to reduce wire length, latency and skew while supporting fast cycle time and high bandwidth.

СПОСОБ И УСРОЙСТВО МАРШРУТИЗАЦИИ ВВОДА-ВЫВОДА И КАРТА

Изобретение относится к устройствам маршрутизации. Технический результат заключается в повышении скорости передачи данных. Способ содержит: сетевой узел, имеющий множество первых карт на интегральных схемах (IC), множество вторых карт IC и коммутирующую матрицу, причем каждая вторая карта IC соединена с соответствующей первой картой IC в соответствующем слоте сетевого узла. Способ включает получение данных ввода-вывода через внешний порт любого из множества первых или вторых карт IC. Когда пакеты данных ввода-вывода принимаются через внешний порт указанной второй карты IC, указанная вторая карта IC выполняет пакетную классификацию пакетов и, по меньшей мере, частично определяет место назначения для пакетов. Способа включает доставку пакетов в первое или второе место назначения карты IC согласно классификации пакетов, выполняемой указанной второй картой IC через логический сетевой уровень, существующий на первой и второй картах IC и в коммутирующей матрице. 3 н. и 17 з.п. ф-лы, 6 ил.

ЛОГИКА ИНТЕРФЕЙСА ДЛЯ МНОГОЯДЕРНОЙ "СИСТЕМЫ НА КРИСТАЛЛЕ" (SoC)

Изобретение относится к многоядерным «системам на кристалле» (SoC). Техническим результатом является снижение потребления энергии SoC за счет отключения второго ядра во время нормальной работы для обеспечения одноядерной SoC. Устройство для управления потреблением энергией содержит "систему на кристалле", включающую в себя первое ядро и второе ядро; логику интерфейса, соединенную с первым ядром и вторым ядром, причем логика интерфейса включает в себя логику брандмауэра, логику шины и тестовую логику; логику набора схем, соединенную с логикой интерфейса и включающую в себя контроллер памяти, который обеспечивает возможность обмена данными с памятью, соединенной с SoC; и логику виртуального брандмауэра, соединенную между логикой набора схем и вторым ядром, в котором второе ядро может быть отключено во время нормальной работы для обеспечения одноядерной SoC. 3 н. и 17 з.п. ф-лы. 5 ил.

Способ идентификации интерфейса и терминал

Изобретение относится к области вычислительной техники. Технический результат заключается в исключении повреждений интерфейсов из-за больших перепадов в уровне сигнала при их ручном переключении. Способ содержит: контроль значения уровня сигнала на первом контакте разъема внешнего интерфейса универсальной последовательной шины; определение, принят ли на первом контакте разъема сигнал электропитания первого заранее заданного напряжения в соответствии с упомянутым значением уровня сигнала; если на первом контакте разъема принят сигнал электропитания, определение того, что устройство, внешне подключенное к терминалу, является первым устройством; и если на первом контакте разъема сигнал электропитания не принят, получение значения уровня сигнала на втором контакте разъема; при этом если на первом контакте разъема сигнал электропитания не принят, получение значения уровня сигнала на втором контакте разъема внешнего USB-интерфейса; определение, является ли полученное значение уровня сигнала на ...

СИСТЕМА СВЯЗИ С ГЛАВНОЙ СТАНЦИЕЙ И ПО МЕНЬШЕЙ МЕРЕ ОДНОЙ ПОДЧИНЕННОЙ СТАНЦИЕЙ

Изобретение относится к системам связи между главной и подчиненными станциями. Технический результат заключается в повышении скорости передачи данных, а также в увеличении числа подчиненных станций. В каждой из подчиненных станций первая выходная схема и вторая выходная схема связаны друг с другом на стороне выхода. В первом режиме эксплуатации подчиненные станции идентифицируются главной станцией, все первые выходные схемы являются активируемыми и система работает с низкой частотой такта. Во втором режиме эксплуатации имеет место передача данных, одна из вторых выходных схем является активируемой и система работает с более высокой частотой такта. 2 с. и 4 з. п. ф-лы, 7 ил.

Устройство цифровой обработки сигналов

Полезная модель относится к области устройств цифровой обработки сигналов. Техническим результатом является улучшении технических характеристик устройства. Раскрыто устройство цифровой обработки сигналов, включающее связанные каналами обмена данными программируемую логическую интегральную схему (ПЛИС) и цифровой сигнальный процессор (ЦСП), аналого-цифровой преобразователь (АЦП), подключенный к ПЛИС посредством буферизированных каналов и к тактовым генераторам, модули внешней памяти типа DDR3, подключенные к ПЛИС и ЦСП, приемопередатчик Ethernet, связанный с ЦСП, мост PCIe-PCI для обмена данными с персональным компьютером, подключенный к ПЛИС, отличающееся тем, что включает разъемы JTAG для подключения к аппаратуре тестирования и отладки, связанные с ПЛИС и ЦСП, включает буферизированные настраиваемые цифровые линии ввода/вывода стандарта LVTTL, подключенные к ПЛИС. 2 з.п. ф-лы, 1 ил.

УСТРОЙСТВО PXI (РАСШИРЕНИЯ ШИНЫ PCI (МЕЖСОЕДИНЕНИЕ ПЕРИФЕРИЙНЫХ КОМПОНЕНТОВ) ДЛЯ КОНТРОЛЬНО-ИЗМЕРИТЕЛЬНОГО ОБОРУДОВАНИЯ) ДЛЯ ГЕНЕРИРОВАНИЯ И ПОЛУЧЕНИЯ ВИДЕО

... 1. Устройство (2) генерирования и получения видео, основанное на технологии PXI (расширения шины PCI (межсоединение периферийных компонентов) для контрольно-измерительного оборудования), содержащее:ведущую плату (21) PXI, которая имеет несколько интерфейсов ввода и выполнена с возможностью подключения к шине (11) PXI; иведомую плату (22) PXI, которая имеет несколько интерфейсов вывода видео и механически соединена многослойным образом с ведущей платой (21) PXI с возможностью обмена сигналами с ней, при этом ведущая плата (21) PXI выполнена с возможностью:получать через интерфейсы ввода множество входных видеосигналов, имеющих разные форматы видео, от одной или более испытываемых систем отображения видео и/или от одного или более источников видео,принимать через интерфейсы ввода один или более входных сигналов синхронизации,обрабатывать один или более из входных видеосигналов и выполнять захват кадра из одного или более из входных видеосигналов;при этом ведомая плата (22) PXI выполнена с ...

СОХРАНЕНИЕ/ВОССТАНОВЛЕНИЕ ВЫБРАННЫХ РЕГИСТРОВ ПРИ ТРАНЗАКЦИОННОЙ ОБРАБОТКЕ

... 1. Компьютерный программный продукт для облегчения обработки транзакций внутри вычислительной среды, причем компьютерный программный продукт содержит:считываемую компьютером запоминающую среду, считываемую обрабатывающим устройством и хранящую команды для выполнения обрабатывающим устройством для выполнения метода, содержащего:определение процессором из информации, предоставленной командой, одного или более выбранных регистров, которые необходимо сохранить при транзакционной обработке, команды начать обработку транзакции, причем транзакция эффективно задерживает фиксацию транзакционных сохранений в главной памяти до тех пор, пока не завершится выбранная транзакция, и один или более выбранных регистров составляют меньше, чем все регистры, используемые транзакцией при выполнении транзакции; исохранение содержимого одного или более выбранных регистров, основанное на выполнении команды.2. Компьютерный программный продукт по п.1, в котором метод дополнительно включает:определение того, что транзакция ...

СПОСОБЫ И УСТРОЙСТВО ДЛЯ ОСУЩЕСТВЛЕНИЯ СВЯЗИ ЧЕРЕЗ УДАЛЕННОЕ ТЕРМИНАЛЬНОЕ УСТРОЙСТВО

СПОСОБ И УСТРОЙСТВО ДЛЯ УПРАВЛЕНИЯ РЕЖИМОМ УСТРОЙСТВА

Richtungsabhängiger und asymmetrischer Signalhub in Bussystem für Schaltungsmodularchitektur

SKALIERBARES DATENERFASSUNGS-/ UND RECHENGERÄT

Sending data off-chip

PCI express interface

Data processing systems with delayed cache write

In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

Controlling bus-networked devices by way of a gateway connected to an open fieldbus

A system for and a method of controlling bus-networked devices (N1 to Nx) with a gateway (20) by way of an open fieldbus (fig.3A, not shown) provides a simplification in that expensive wiring is dispensed with and the user, with a low level of operating complication and expenditure, can check the system, configure it and re-start it in the event of error messages. For that purpose in such a system there is provided a single pluggable connecting line (8) within the system for connecting bus subscribers and the gateway and for the transfer of control and/or status data and energy. In an initial reference configuration the gateway does not expect any subscriber and a configuration mode is started in the gateway for adopting at least one bus subscriber and producing a fresh reference configuration with the at least one bus subscriber. Applications include motor switches and the like.

Processor surrogate for use in multiprocessor systems and multiprocessor system using same

A processor surrogate (320/520) is adapted for use in a processing node (S 1) of a multiprocessor data processing system (300/500) having a plurality of processing nodes (P0, S1) coupled together and to a plurality of input/output devices (330, 340, 350/530, 540, 550, 560) using corresponding communication links. The processor surrogate (320/520) includes a first port (372, 374/620, 622) comprising a first set of integrated circuit terminals adapted to be coupled to a first external communication link (370/590) for coupling (P0) of the plurality of processing nodes (310, 320/510, 520), a second port (382, 384/630, 632) comprising a second set of integrated circuit terminals adapted to be coupled to a second external communication link (380/592) for coupling to one (350/550) of the plurality of input/output devices (330, 340, 350/530, 540, 550, 560), and an interconnection circuit (390, 392/608, 612, 614) coupled between the first port (372, 374/620, 622) and the second port (382, 384/630 ...

COMPUTER TERMINALS

Controller data sharing using a modular DMA architecture

Retrieving status information from a remote device and corresponding host system

Modular computer system, server module and rack arrangement

MULTIPLEXER AND INTEGRATED PROCESSOR WITH SUCH A MULTIPLEXER

Communication circuit of inter-integrated circuit device

A communication circuit of an Inter-Integrated Circuit (I2C) includes a master device, a switch circuit, first and second groups of slave devices. Each slave device includes a data signal pin and a clock signal pin, which are connected to the switch circuit. The master device includes a data signal pin, a clock signal pin, and a general purpose input output (GPIO) pin, which are connected to the switch circuit. The GPIO pin of the master device outputs a control signal to the switch circuit, to allow communication between the first group of slave devices and the master device or communication between the second group of slave devices and the master device.

Устройство коммуникационное для кластерной цифровой подстанции

Полезная модель относится к области кластерных цифровых электрических подстанций (ЦПС).Техническим результатом является обеспечение подключения устройства кластерной ЦПС к независимым сегментам станционной и технологической шин коммуникационной сети (Ethernet) ЦПС, в каждом из которых дополнительно обеспечивается коммуникационное резервирование с применением «бесшовного» резервирования в соответствии с IEC 62432-3, в частности резервирования по протоколу PRP ("Parallel Redundancy Protocol"). Устройство коммуникационное (1) включает в себя четыре интерфейса (2-5) подключения к внешней коммуникационной сети Ethernet ЦПС, процессор (8); коммутатор (9), связанный с процессором (8), включающий в себя также, по меньшей мере, один внешний коммуникационный порт (12) для связи с соответствующим интеллектуальным электронным устройством (IED) (13) кластерной ЦПС. Устройство (1) дополнительно содержит два коммуникационных шлюза (10 и 11), связанных с процессором (8). При этом первый коммуникационный шлюз (10) также связан с первым (2) и вторым (3) интерфейсами подключения к внешней коммуникационной сети Ethernet ЦПС (6, 7), а второй коммуникационный шлюз (11) также связан с третьим (4) и четвертым (5) интерфейсами подключения к внешней коммуникационной сети Ethernet ЦПС (6, 7). При этом интерфейсы (2) и (3) устройства (1) предназначены для подключения к резервированному по протоколу PRP (IEC 62439-3) сегменту (6.1 - подсеть "A" (PRP), 7.1 - подсеть "В" (PRP)) станционной шины коммуникационной сети ЦПС, а интерфейсы (4) и (5) - к резервированному по протоколу PRP (IEC 62439-3) сегменту (6.2 - подсеть "A" (PRP), 7.2 - подсеть "В" (PRP)) технологической шины коммуникационной сети ЦПС. При этом первый коммуникационный шлюз (10) выполнен с возможностью обеспечения коммуникационного сопряжения с резервированным сегментом станционной шины (6.1, 7.1) внешней коммуникационной сети ЦПС с обеспечением двусторонней передачи данных в прямом и обратном ...

Low power, low pin count interface for an rfid transponder

A serial interface includes a select node, a clock node, a first bidirectional data port, a second bidirectional data port, and shift register circuitry coupled to both data ports such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift or transfer data.

Portable Storage Device With Retractable Connector

A thumb drive includes a retractable USB connector sized to translate between an extended position beyond a housing and a retracted position into the housing. An actuator, such as a dial or a lever, is sized to actuate the USB connector to move the USB connector between the extended position and the retracted position. The USB connector is sized to translate to the extended position when the actuator is moved in one direction. The USB connector is sized to translate to the retracted position when the actuator is moved in an opposite direction.

Data transfer circuit and data transfer method

A port A request queue is configured with a port AQ 0 to a port AQn for each of request types Q 0 to Qn connected with a requester resource busy flag controller Q 0 to a requester resource busy flag controller Qn, respectively. A port A resource checking unit of a port X arbiter unit gives instructions to the requester resource busy flag controller of the port AQ 0 to turn a busy flag on when it is determined that a data request from the port AQ 0 has difficulty in being output to a port X inter-port arbiter unit due to resources being busy as a result of referring to a resource information unit of a port X resource managing unit. The port AQ 0 inhibits output of a data request as long as the busy flag is on.

Isolation-free in-circuit programming system

Disclosed is an isolation-free in-circuit programming system including an in-circuit programmer and an application board connected to the in-circuit programmer through a peripheral interface bus and having a bus controller and a memory, wherein the bus controller is connected to the memory through a system bus, in which the in-circuit programmer includes a leakage current discharging circuit connected to the bus controller for detouring a leakage current flowing from the memory or the in-circuit programmer to the bus controller to flow therethrough. The in-circuit programmer also includes an input level shifter for receiving data signals from the memory and adjusting the high-level input voltage of the in-circuit programmer to decode any weak high-level output voltage from the memory, thereby allowing the high-level output voltage of the memory to be higher than the high-level input voltage of the in-circuit programmer.

Information handling system remote input/output connection system

An information handling system (IHS) remote input/output (I/O) connection system includes an enclosure having a power button, a communication bus connection point, and an audio connection point. A cable dongle extends from the enclosure. The cable dongle has a first end and a second end. The cable dongle also includes a connection from the power button on the enclosure on the first end to a communication connection point plug on the second end, which mates with a connection point plug on a remote I/O device card that enables a parallel (ACPI) S5-capable power button from the IHS to exist on the enclosure. The cable dongle further includes a communication cable coupled to the communication bus connection point on the first end and having a communication connection point plug on the second end. In addition, the cable dongle includes an audio cable coupled to the audio connection point on the first end and having an audio connection point plug on the second end.

Optical memory expansion

Various embodiments of the present invention are directed to optical-based methods and expansion memory systems for disaggregating memory of computer systems. In one aspect, an expansion memory system comprises a first optical/electronic interface in electrical communication with a processor, a memory expansion board configured with memory, and a second optical/electronic interface attached to the memory expansion board. The first interface converts optical signals into electronic signals that are sent to the processor and converts electronic signals produced by the processor into optical signals. The second interface converts optical signals into electronic signals that are sent to the memory and converts electronic signals produced by the memory into optical signals. The optical signals are exchanged between the first and second interfaces. Embodiments also include methods for sending and receiving data in an expansion memory system.

Method for finding starting bit of reference frames for an alternating-parity reference channel

The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.

Method for Assigning Addresses to Nodes of a Bus System, and Installation

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

Precision synchronisation architecture for superspeed universal serial bus devices

A method of providing a synchronisation channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D− data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D− signalling lines at a downstream connection point of the cable; whereby the synchronisation channel is maintained across the D+/D− data signalling lines.

Non-invasive direct-mapping usb switching device

A non-invasive direct-mapping USB switching device includes a main-controlled microprocessing module connected to a high-impedance module, and the high-impedance module is provided for detecting and monitoring a functional instruction code of a USB device transmitted from a data transmission module, such that a USB connecting module can be used for transmitting the USB data and functional instruction code to detect and monitor the data transmission module when the USB device is connected to the USB switching device. If the data transmitted from the data transmission module is not the required functional code, the non-required functional code (such as the USB data) will be passed, so that the USB device can be connected and communicated with a plurality of computer devices through another USB connecting module and a switching module to achieve a plug-and-play function.

Synchronous network of superspeed and non-superspeed usb devices

A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.

Method and system for transferring high-speed data within a portable device

A system for high-speed data transfer within a portable device, such as, cell phone or a set-top box, which includes a memory medium and a processor. The system includes a first port for coupling to the processor, and a second port for coupling to the memory medium. Further, the system includes an embedded Universal Serial Bus (USB) host configured for receiving data transfer commands from the processor, and transferring data at high speed between a USB device on the processor and the memory medium. Moreover, a data path is provided between the embedded USB host and the first port.

Multi-device docking with a displayport compatible cable

A docking system utilizing a single DisplayPort cable connection to a computer system is provided. In one embodiment, the docking system includes a single DisplayPort (“DP”) input, a management layer module coupled to receive video inputs from the single DP input and to provide video data to at least one video monitor output, and a USB layer module coupled to receive an AUX channel from the single DP input and to couple the AUX channel with a USB hub.

Use of pci express for cpu-to-cpu communication

CPUs that generate PCIe auxiliary signals and changing clock signals nevertheless communicate with each other using PCIe owing to PCIe switch assemblies that are disposed in the communication paths to isolate and terminate the auxiliary signals from reaching other CPUs and to isolate changing clock signals, communicating with each other using a fixed clock derived from one of the changing clock signals. Also, the CPUs directly access the memories of CPUs to which they wish to write data so that data is directly written from one CPU memory to another without store-and-forward operations being needed in the network.

Compound universal serial bus architecture providing precision synchronisation to an external timebase

A method of synchronising a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronisation channel to a non-Super Speed USB function of the compound USB device; and synchronising a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronisation channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.

Semiconductor integrated circuit

A constantly power-ON domain and a standby-time power OFF domain are included on the same chip, and the constantly power-ON domain includes: a shutoff control circuit shutting off a signal inputted and outputted between the constantly power-ON domain and the standby-time power OFF domain when the first power source is ON and the second power source is OFF; and a shutoff control circuit outputting a first control signal indicating that shutoff of an emergent shutoff control circuit unit is to be enabled or disabled, the standby-time power OFF domain includes the emergent shutoff control circuit unit shutting off, based on the first control signal from the shutoff control circuit, the signal inputted between the emergent shutoff control circuit unit and the constantly power-ON domain.

Implementing lane shuffle for fault-tolerant communication links

A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.

Transaction reordering arrangement

An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued.

Cooperative Writes over the Address Channel of a Bus

A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.

Solid State Drive Architecture

Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.

Virtual function boot in single-root and multi-root i/o virtualization environments

A method for virtual function boot in a system including a single-root I/O virtualization (SR-IOV) enabled server includes loading a PF driver of the PF of a storage adapter onto the server utilizing the virtual machine manager of the server; creating a plurality of virtual functions utilizing the PF driver, detecting each of the virtual functions on an interconnection bus, maintaining a boot list associated with the plurality of virtual functions, querying the storage adapter for the boot list utilizing a VMBIOS associated with the plurality of VMs, presenting the detected boot list to a VM boot manager of the VMM, and booting each of the plurality of virtual machines utilizing each of the virtual functions, wherein each VF of the plurality of VFs is assigned to a VM of the plurality of VMs via an interconnect passthrough between the VMM and the plurality of VMs.

Medical Data Collection Apparatus

A physiological data collection device obtains physiological data from a subject interface on a subject. The physiological data collection device includes a data connector such as a USB connector for connecting directly to a computer. When the physiological data collection device is connected to the computer, the physiological data is uploaded to a remote data processing center for computer-based analysis and review by a medical professional. A report can be provided to the subject based on the analysis and review. When the subject interface is physically connected to the physiological data collection device, the data connector is prevented from being connected to an external device such as the computer.

Usb connector device for an antenna

A USB connector device for an antenna has a first cable, a receiver, a second cable and a USB connector. The first cable has an end connected to the receiver. The second cable has two ends respectively connected to the receiver and the USB connector. Because the receiver and the USB connector are combined in a series-connection way, the series-connection design can compact the structure of the USB connector device for an antenna in accordance with the present invention and reduce redundant cables, and it occupies a single one USB slot of the computer only. The USB connector device is very useful and convenient in use.

Segmented transmission signal circuit

A segmented transmission signal circuit is provided with a parallel bus of data transmission. The bus includes a plurality of sections, each section transmits a corresponding parallel data of multiple bits, and the parallel data corresponding to different sections are in different bit orders.

Active business client

Methods and apparatuses enable generation of and consumption of business context data. A server generates business context data that describes a resource, a view, and actionable context data related to a business scenario. The business context data is not specific to any particular UI capability of the client device, and may include tittle or no UI information. The server transmits the business context data to a client device that has an active client. The active client identifies one or more UI capabilities of the client device and generates a UI component based on the business scenario and the UI capabilities. The UI component enables functionality in the client device related to execution of the actionable context data. In one embodiment, the active client enables predictive deployment of services on the client device based on an understanding of the business scenario.

Hybrid storage device and electronic system using the same

A hybrid storage device is provided. The hybrid storage device includes a first storage part that comprises an interface device based on a first standard, a second storage part that comprises an interface device based on a second standard, and a connector for interface devices that is shared by the first storage part and the second storage part and comprises a plurality of pins.

Determining addresses of electrical components arranged in a daisy chain

In one aspect, a system includes electrical components arranged in a daisy chain that include a first electrical component disposed at a first end of the daisy chain and a second electrical component disposed at an opposite end of the daisy chain than the first end. Each of the first and second electrical components includes an input port, an output port and a common port. The input port of the first electrical component is coupled to one of a supply voltage port or ground and the common ports of the first and second electrical components are coupled to the other one of the supply voltage or the ground. An address of the second electrical component is determined before addresses of the other of the electrical components are determined, and the addresses determine a position of an electrical component with respect to the other of the electrical components.

Computer chassis system and hard disk status display method thereof

A computer system displays and controls the hard disk condition. The computer system includes a host bus adapter which detects the status of the hard disk, and the status light gives light to display the hard disk status. The baseboard management controller and the host bus adapters are set on the motherboards, in which the baseboard management controller monitors and records the status of the hard disk. The microcontroller is set on the hard disk backplane for decoding the message from the host bus adapter in order to control the displaying of the status light.

Memory Modules and Devices Supporting Configurable Core Organizations

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

Apparatuses, systems, and methods for facilitating optical communication between electronic devices

Active optical cable assemblies, and systems, methods, and adapter modules and integrated circuits for facilitating communication between a host and a client device over a fiber optic cable are disclosed. In one embodiment, an active optical cable assembly includes a fiber optic cable having at least one optical fiber, a host active circuit, a client active circuit, a host connector, and a client connector. Upon a connection between the host active circuit and a host device, the client termination switch closes to couple the client termination impedance to the ground reference potential. Upon a connection between the client active circuit and a client device, the host termination switch closes to the couple the host termination impedance to the ground reference potential. In another embodiment, a method includes enabling a host termination impedance upon a connection of an active optical cable to a client device.

Multi-root sharing of single-root input/output virtualization

In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

Memory controller for strobe-based memory systems

A memory controller for strobe-based memory systems is disclosed. The memory controller comprises a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit comprises an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.

Protocol translation method and bridge device for switched telecommunication and computing platforms

A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Electrical Circuit For Transmitting Signals Between Two Masters And One Or More Slaves

An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch.

Apparatus and methods for serial interfaces

Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers.

Operation method for a computer system

A device receives a standard command. The device judges whether an address field and/or a data length field and/or a data field of the standard command includes at least one of a vendor command, a vendor data and a checkword. The device judges whether the address field and/or a data length field and/or the data field of the standard command matches a vendor predetermined pattern. If matched, the device performs a vendor operation based on the vendor command and/or the vendor data of the standard command.

Expandable asymmetric-channel memory system

An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Embedded system development platform

A modular development platform is described which enables creation of reliable, compact, physically robust and power efficient embedded device prototypes. The platform consists of a base module which holds a processor and one or more peripheral modules each having an interface element. The base module and the peripheral modules may be electrically and/or physically connected together. The base module communicates with peripheral modules using packets of data with an addressing portion which identifies the peripheral module that is the intended recipient of the data packet.

System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Transfer of Uncompressed Multimedia Contents or Data Communications

A system and corresponding method for transferring data via an interface assembly. The data may be transferred between a USB port of a first device and a media port of a second device. Uncompressed high definition media data may be received from the USB port. The received uncompressed high definition media data may be supplied to a media connector in accordance with a first media standard, such that the supplied data can be transmitted in accordance with the first media standard via the media connector to the media port of the second device. The uncompressed high definition media data may include multimedia data and side-band communication data. A single signal may be encoded and decoded in accordance with a protocol that enables the single signal to communicate all side-band communication to and from the source device via a single pin of a USB connector.

Memory System with Calibrated Data Communication

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Method and apparatus for plug and play, networkable iso 18000-7 connectivity

A device may comprise a Universal Serial Bus (USB) interface and a wireless interface operable to communicate in accordance with the ISO 18000-7 standard. The device may be operable to receive a command via the USB interface and transmit the command via the wireless interface. The device may be operable to receive data via the wireless interface and transmit the data via the USB interface. A form factor of the USB device may be such that it can be plugged directly into a USB port without any external cabling between the USB device and said USB port.

Usb interface device and circuit board thereof

An exemplary USB interface device includes a circuit board and a USB socket mounted on the circuit board. The USB socket includes a connecting port, a plurality of electrical pins and fixing pins extending from a side of the USB socket. The circuit board defines first and second inserting hole groups. The USB socket can be selectively inserted into the first or second inserting hole group according to the type of USB socket. When the electrical pins and the fixing pins of the USB socket are inserted into and fixed on the first inserting hole group of the circuit board, the second inserting hole group is standing idle. When the electrical pins and the fixing pins of the USB socket are inserted into and fixed on the second inserting hole group of the circuit board, the first inserting hole group is standing idle.

Supporting global input/output interconnect features on ports of a midpoint device

In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.

Method for the operation of a data bus, and data bus system

For operation of a data bus to which multiple bus participants each with a respective serial number are connected, a new bus participant is connected. A request bus message is generated by the new bus participant containing a preliminary participant identification number. The request bus message is arbitrated in the data bus by means of the identification number. A final participant identification number is assigned for the new bus participant having fewer digits than the serial number of the new participant. The final participant identification number is used for further bus messages by the new bus participant. During an initialization bus messages are used with an identifier in which a complete serial number is entered as the identifier. After the initialization a different type of bus message is used that has a shorter identifier.

Semiconductor memory device and method of controlling the same

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Configurable health-care equipment apparatus

An apparatus, system and method for providing health-care equipment in a plurality of customizable configurations. A configuration includes a selection and arrangement of health-care equipment modules that each provide specialized support for the provision of health care, including the measurement of physiological parameters. Various types of configurations include those adapted to be mounted upon a desk top or a wall surface, or adapted for wheel mounting or hand-carriable mobile configurations.

HID over Simple Peripheral Buses

In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system.

Circuit providing load isolation and noise reduction

Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Electronic device with card interface

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Kvm switcher with ability to extend universal serial bus (usb) host interface via serial peripherial interface (spi)

A multi-computer (KVM) switcher with ability to extend universal serial bus (USB) host interface via serial peripheral interface (SPI), characterized in that SPI master device interface of master control unit can switch the capability of controlling plural SPI slave devices via serial peripheral interface (SPI), and through installing SPI slave device interfaces on plural universal serial bus (USB) host interface control units to be extended, the object of extending peripheral device with USB interface via SPI interface is achieved.

Crosspoint switch with separate voltage sources for input and output ports

A crosspoint switch device has a plurality of input ports each connected to a respective voltage source and a plurality of output ports each connected to a respective voltage source. A switch array selectively provides signal paths between the input ports and the output ports. The voltage sources are separate from one another.

Microcomputer, system including the same, and data transfer device

A microcomputer is provided, which can load data of different areas in parallel and transfer the loaded data to a storage circuit. The microcomputer includes a CPU to control a DRIs each of which loads image data of a prescribed area out of image data inputted from a camera and transfers the image data to a memory blocks, and the DRIs each of which transfers image data of respectively different area out of the image data inputted from the camera to the memory blocks. Therefore, it becomes possible to load image data of different areas in parallel and to transfer the loaded image data to the memory blocks.

Server Input/Output Failover Device Serving Highly Available Virtual Devices

A failover input/output device and corresponding method are provided to manage failover events of input/output controller devices that operate in accordance with a computer expansion card standard, such as the Peripheral Component Interconnect Express (PCIe) standard. The failover input/output device connects to redundant first and second virtualized input/output controller devices each comprising multiple virtual network interfaces that are in an active or standby state at any given time, and to a computing device that hosts one or more processes. The failover input/output device broadcasts transactions in accordance with the computer expansion card standard initiated from the computing device to the first and second virtualized input/output controller devices. The failover input/output device receives signals associated with upstream transaction completions in accordance with the computer expansion card standard for both active and standby virtual network interfaces on the first and second virtualized input/output controller devices. The failover input/output device forwards signals associated with upstream transaction completions for active virtual network interfaces on the first and second virtualized input/output controller devices to the computing device.

Semiconductor module includes semiconductor chip initialized by reset signal

Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.

Disk subsystem

A protocol controller disposed between switches in a fiber channel fabric switch circuit and disk drive units for converting a protocol to enable one-to-one connectivity established between controllers and disk drive units.

Disc drive system

A disc drive may provide data communications to a host using a universal serial bus (“USB”) interface. Activation of the USB interface may be triggered upon insertion of a disc into the disc drive. A connection unit may activate the USB interface by providing power to the USB interface when a disc switch detects that the disc has been inserted into the disc drive. The connection unit may deactivate the USB interface by no longer providing power to the USB interface when the disc switch detects that the disc has been ejected or no longer is in the disc drive.

Zone group manager virtual phy

A switch is provided. The switch includes an expander configured to couple a server to a set of storage drive bays. The switch also includes a zone manager coupled to the expander and configured to maintain a zoning configuration corresponding to the set of storage drive bays. The zone manager is coupled to the expander through a virtual PHY.

Constituting a control system with virtual and physical backplanes and modules as building blocks

A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation.

Data transfer apparatus and data transfer method

A packet accompanying data valid information is transferred at high efficiency within an integrated circuit or between integrated circuits. A character indicating data enable information is provided and an identifier indicating a data enable character is assigned onto the packet. When the data enable information is valid in series, the data enable characters are eliminated from the packet to be transferred.

Motherboard of computing device

A motherboard of a computing device includes a dual inline memory module (DIMM), a processor socket, a platform controller hub (PCH), a switch, and a switch controller. The DIMM is connected to the processor socket or the PCH through the switch controller. The switch is connected to the switch controller, and generates a signal when the switch is operated. The switch controller controls the DIMM to connect either to the processor socket or to the PCH according to the signal, so that a solid state disk (SSD) or a memory that is connected to the DIMM can be supported appropriately by the motherboard.

Heat management in an above motherboard interposer with peripheral circuits

A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, at least one peripheral circuit on the interposer substrate, and a heat sink thermally coupled to the peripheral circuit.

Driving strength control apparatus, driving strength control method and terminal equipment

The embodiments of the present invention provide a driving strength control apparatus and method and terminal equipment. The control apparatus comprises: a signal receiving unit to receive a test signal transmitted by a peripheral device; a signal sampling unit to sample the test signal received by the signal receiving unit to obtain a plurality of rising edges and falling edges of the test signal; an interval measuring unit to measure the time interval between a rising edge and a falling edge, or between a rising edge and another rising edge, or between a falling edge and another falling edge; and a controlling unit to adjust the driving strength imposed on the peripheral device according to the time interval. With the embodiments of the present invention, the driving strengths imposed on the peripheral device may be made identical, preventing signal deviation and improving the quality of compatibility.

Implementing device physical location identification in serial attached scsi (sas) fabric using resource path groups

A method and controller for implementing device physical location identification in a Serial Attached SCSI (SAS) fabric using resource path groups, and a design structure on which the subject controller circuit resides are provided. The device physical location identification includes a Resource Path Group (RPG). Each RPG provides a unique persistent physical locator of a storage device in the system. Each RPG including at least two Resource Paths (RPs) and each RP has a fixed size identifying a type and a series of egress ports. A persistent RPG is stored within the device metadata on the storage device.

Parallel communication device and communication method thereof

Provided are a parallel communication device and a communication method thereof. The parallel communication device includes: a first receiving terminal receiving communication data transmitted through a master device; a first transmitting terminal transmitting the communication data received through the first receiving terminal to a slave device; a switch managing a communication line disposed between the first transmitting terminal and a plurality of slave devise; and a control unit confirming a first slave device to which the communication data are to be transmitted by using destination information in the communication data, and transmitting the received communication data to the confirmed first slave device.

Processor bridging in heterogeneous computer system

A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.

Apparatus and method for sharing i/o device

In a server apparatus in which a plurality of physical servers and an I/O device are connected via an I/O switch, when the plurality of physical servers share one I/O device, a tag included in a request packet transmitted from a first physical server to the I/O device is translated into a value that is not used in the I/O device in the I/O switch and thereafter the request packet is transferred to the I/O device, and then a tag included in a response packet which responds to the request packet and which is transmitted from the I/O device to the first physical server is restored to the original tag, so that conflict of tags when a plurality of physical servers share one I/O device is avoided.

High Availability Device Level Ring Backplane

A modular, high-availability network for an industrial control system employs a plurality of base modules having backplane and using network ring topology. Base modules may include I/O base modules for communicating with industrial processes or machines, an adapter base module for communicating with a programmable logic controller (PLC) and/or a bus expansion base module for providing additional I/O base modules. Base modules may be arranged side-by-side, having a backplane in a bank. Another embodiment may include having plurality of banks. The network ring topology used by the base modules is normally opened by a ring supervisor at the ring supervisor location. Upon failure of the network, the ring supervisor reconnects the ring to provide an alternative transmission path around the failure point.

Underlaying device for a computer device

An underlaying device includes a main signal port, an expanding signal port, a signal process component, and a power connector. The main signal port is receiving and sending a communication signal from/to the computer device by means of a main signal wire. The expanding signal port is receiving and sending the communication signal from/to an external expanding device. The signal process component is coupled between the main signal port and the expanding signal port for transforming the communication signal into a signal which is able to be received and sent between the main signal port and the expanding signal port. The power connector is supplying power by means of a power wire. The underlaying device is suitable for various computer devices and is able to integrate the functionality of connection ports.

Data transfer apparatus and image forming system

A data transfer apparatus includes a virtual channel unit configured to time share a serial bus for a first virtual channel and a second virtual channel and include a buffering control unit configured to receive data via the first virtual channel and the second virtual channel, first and second receive buffers being configured to store the data received via the first virtual channel and the second virtual channel, respectively; and a switching unit configured to control storing the data received via the first virtual channel in the second receive buffer when the buffering control unit receives the data from another data transfer apparatus which is configured to use only the first virtual channel and the capacity of the first receive buffer is smaller than that of the second receive buffer.

System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

Integrating Intellectual Property (IP) Blocks Into A Processor

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

Storage device having communication function and expandable memory capacity

The present invention relates to a storage device having communication function and expandable memory capacity, which comprises: a top housing having a first open slot at one side; a bottom housing engaged with the top housing for forming an accommodating space; a printed circuit board; a terminal seat; a memory array; a memory controller; a processer; and a wireless communication module. When the storage device is inserted in a portable electronic device, data in the memory array can be transmitted to a remote mainframe through the wireless communication module. Moreover, the storage device has a slot allowing a removable memory card to be inserted for expanding the memory capacity of the storage device.

Methods and devices for universal serial bus port event extension

Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.

Virtual Switch Extensibility

An extensible virtual switch allows virtual machines to communicate with one another and optionally with other physical devices via a network. The extensible virtual switch includes an extensibility protocol binding, allowing different extensions to be added to the extensible virtual switch. The extensible virtual switch also includes a miniport driver on which the extensions are loaded, tying the lifetimes of the extensions to the lifetime of the extensible virtual switch.

Diagnostic and managing distributed processor system

A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

ASYNCHRONOUS PROTOCOL CONVERTER

An asynchronous protocol converter, which is capable of flexibly carrying out communications between tens of IP cores in an asynchronous protocol Network-on-Chip system, and which is multiple input multiple output is provided. In an LSI (), which comprises a plurality of IP cores (), and routers () positioned adjacent to the plurality of IP cores (), an asynchronous protocol converter () is positioned between adjacent routers (). The asynchronous protocol converter () is configured to comprise: a two-to-four-phase converter () that is connected to an adjacent router () within the LSI (); a four-phase pipelined router () that is connected on the output side of the two-to-four-phase converter (); a four-to-two-phase converter () that is connected to the outputs of the four-phase pipelined router (); an input controller () that controls the two-to-four-phase converter (); and an output controller () that controls the four-to-two-phase converter (). 1. An asynchronous protocol converter provided between neighboring routers in an LSI including a plurality of IP cores and a router provided adjacent to the plurality of IP cores , comprising:a two-to-four-phase converter connected to the neighboring router in the LSI;a four-phase pipelined router connected to the output side of the two-to-four-phase converter;a four-to-two-phase converter connected to an output of the four-phase pipelined router;an input controller for controlling the two-to-four-phase converter; andan output controller for controlling the four-to-two-phase converter.2. An asynchronous protocol converter provided between neighboring routers in an LSI including a plurality of IP cores and a router provided adjacent to the plurality of IP cores , comprising:a two-to-four-phase converter connected to the neighboring router in the LSI;a four-phase pipelined router connected to the output side of the two-to-four-phase converter;a four-to-two-phase converter connected to an output of the four-phase pipelined ...

SYSTEMS AND METHODS FOR IMAGE STREAM PROCESSING

Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may provide vision systems and methods suitable for use in vehicles, particularly windowless vehicles, such as armored ground vehicles, submerged watercraft, and spacecraft. Some embodiments may enable sharing of image streams (e.g., with one or more other vehicles), generation of panoramic views (e.g., from various camera feeds), intelligent encoding of image streams, and implementation of security features based on image streams. 1. A system for image stream processing , comprising:an image stream input interface;an image stream output interface;a first image processing module configured to accept a plurality of image streams, stitch at least two image streams from the plurality of image streams into a contiguous image stream, and output the contiguous image stream, wherein the plurality of image streams comprises an image stream from the image stream input interface or from another image processing module;a second image processing module; and selectively map the image stream from the image stream input interface or from the second image processing module, to the first image processing module, and', 'selectively map the contiguous image stream from the first image processing module to the image stream output interface or to the second image processing module., 'a switching matrix in communication with the image stream input interface, the image stream output interface, the first image processing module, and the second image processing module, wherein the switching matrix is configured to2. The system of claim 1 , further comprising a plurality of image stream input interfaces claim 1 , the plurality of image stream input interfaces being in communication with the switching matrix and including the image stream input interface claim 1 , wherein at least two ...

System and method for reducing cross coupling effects

A device includes a plurality of driver circuits coupled to a plurality of bus lines. A first driver circuit of the plurality of driver circuits is coupled to a first bus line of the plurality of bus lines. The first driver circuit includes one of a skewed inverter, a level shifter, a latch, and a sense amplifier configured to produce an output signal that transitions after a first delay in response to a first digital value transition of an input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high. The first delay is different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line.

Virtual General Purpose Input/Output for a Microcontroller

A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.

CABLE REDUNDANCY AND FAILOVER FOR MULTI-LANE PCI EXPRESS IO INTERCONNECTIONS

Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device. 1. A method for providing a failover operation for a connection between a first PCIE bridge and a first input/output (IO) device , the method comprising:exchanging a first set of bussed bits between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge;in response to detecting a failure in the first link, exchanging a second set of bussed bits between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.2. The method of claim 1 , wherein exchanging the second set of bussed bits in response to detecting the failure comprises:at a PCIE bridge end, performing a first switch between the first set of lanes and a second set of lanes of the second PCIE bridge for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device using the unused portion of the second link, wherein the unused portion comprises the second set of lanes.3. The method of claim 2 , wherein exchanging the second set of bussed bits in response to detecting the failure further comprises:at an IO device end, performing a second switch between the first and the second sets of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device using the unused portion of the second link.4. The method of claim 3 , further comprising:in ...

Systems and methods for performing a hot input function

A computer software system is disclosed for facilitating a user's replacement or insertion of devices in a computer server network system. The system allows a user to swap or add peripheral devices while the system is running, or in a “hot” condition, with little or no user knowledge of how the system carries out the “hot swap” or “hot add” functions. The system, which consists of a graphical user interface (GUI) and associated computer software modules, allows the user to select a desired peripheral device location within a server, and then provides the modular software structure to automatically execute a series of steps in the hot swap or hot add process. Each step is prompted by the user from the GUI, to invoke commands to instruct a network server through its operating system and hardware to suspend the appropriate device adapters, if necessary, power down the desired device slot or canister, allow the user to replace or insert a new device, and finally restart the adapters and the slot power. The system requires very little detailed input from the user other than identifying the particular peripheral device slot within the server to be maintained.

SWITCHING LOGIC MODULE

The innovation applies to a switch logic module (), which can be electrically and mechanically connected to and disconnected from I/O modules () that are arranged next to each other, whereby the I/O modules have an electrical contact and the mechanical connection can be established using the electrical contacts. According to the innovation, a multiplex logic is provided that can be used to connect the electrical contacts of the I/O modules cyclically for a predefined switch time to an output () of the switch module. This provides a space-saving and cost-effective solution that can be used to cyclically switch multiple electrical signals to one output with little installation effort and great flexibility. 1. Switch logic module , which can be mechanically and electrically connected to and disconnected from eight I/O modules , which are arranged next to each other , whereby the I/O modules have at least one electrical contact each and the mechanical connection can be established using the electrical contacts , which is characterized in that a multiplex logic is provided that can be used to cyclically connect the electrical contacts of the I/O modules for a predefined switch time to an output of the switch module.2. Switch logic module according to claim 1 , characterized in that the output of the switch logic modules has an electrical contact claim 1 , preferably a terminal or a plug connector.3. Switch logic module according to marked in that the output of the switch logic module has a wireless device.4. Switch logic module according to characterized in that the multiplex logic is designed so that the switch time can be configured.5. Switch logic module according to claim 4 , characterized in that the switch time can be configured using a DIP switch.6. Switch logic module according to and characterized in that the number of I/O modules that can be connected to the switch logic module can be configured.7. Switch logic module according to claim 6 , characterized in ...

Serial Peripheral Interface and Method for Data Transmission

A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses. 1. A serial peripheral interface of an integrated circuit , the serial peripheral interface comprising:a plurality of pins coupled to the integrate circuit for transmitting an instruction, an address or a read out data: anda clock pin coupled to the integrated circuit for inputting a plurality of timing pulses;wherein at least one of the plurality of pins transmit the instruction, the address or the read out data at both rising edges and falling edges of the timing pulses.2. The serial peripheral interface according to claim 1 , wherein the integrated circuit receives the instruction under a control of selectively using only a first pin or a combination of the first pin claim 1 , a second pin claim 1 , a third pin claim 1 , and a fourth pin of the serial peripheral interface claim 1 , the integrated circuit receives the address using the first pin claim 1 , the second pin claim 1 , the third pin claim 1 , and the fourth pin of the serial peripheral interface claim 1 , and the integrated circuit sends a read out data using the first pin claim 1 , the second pin claim 1 , the third pin claim 1 , and the fourth pin of the serial peripheral interface.3. The serial peripheral interface according to claim 2 , wherein the second pin is for preventing the read out data from being read from the integrated circuit claim 2 , and transmitting the instruction claim 2 , the address or the read out data when the second pin is not for preventing the read out data from being read from the integrated circuit.4. The serial peripheral ...

COMMUNICATION CONTROL SYSTEM, SWITCHING NODE, COMMUNICATION CONTROL METHOD AND COMMUNICATION CONTROL PROGRAM

In a switching node, high-speed and advanced service protocol processing function is achieved by utilizing an external control server without affecting performance of conventional service protocol processing. Specifically, a forwarding engine has PCI express and an LAN interface. Depending on a type of an input packet, destination of the packet is switched to the PCI express side for conventional network service and to the LAN interface side for extended network service that cooperates with the external control server. A CPU having the PCI express and the LAN interface is provided ahead of the LAN interface. The CPU performs communication of service inquiry with the external control server at high speed via the LAN interface. After response from the control server is obtained, setting of the forwarding engine is performed through the PCI express. 1. A communication control system comprising:a switching node configured to execute conventional network service; anda control server configured to execute extended network service,wherein said switching node comprises:a first internal bus used for forwarding a frame for internal processing;a second internal bus for forwarding a frame for external transmission; anda forwarding engine configured to operate depending on a type of an input frame, to forward a frame regarding said conventional network service to said first internal bus for internal processing in said switching node, and to forward a frame regarding said extended network service to said second internal bus for utilizing said control server.2. The communication control system according to claim 1 ,wherein said switching node further comprises:a first processor configured to receive a frame from said forwarding engine through said first internal bus and to execute said conventional network service; anda second processor configured to receive a frame from said forwarding engine through said second internal bus, to perform processing related to said extended network ...

UNIVERSAL SERIAL BUS (USB) TO DIGITAL VIDEO

This document discusses, among other things, a system and method for serializing a video signal and providing non-packet-based serialized video information to a physical Universal Serial Bus (USB) interface and, in certain examples, receiving the non-packet-based serialized video information from the physical USB interface, deserializing the received non-packet-based serialized video information, and providing a high definition output signal to a video port (e.g., an HD video port, such as HDMI, DisplayPort, etc.) using the deserialized video information. 1. A system comprising:a video serializer configured to receive a video signal from a video controller, to serialize the video signal, and to provide non-packet-based serialized video information to a physical Universal Serial Bus (USB) interface using the serialized video signal.2. The system of claim 1 , including:a physical USB interface; anda deserializer configured to receive the non-packet-based serialized video information from the physical USB interface, to deserialize the received non-packet-based serialized video information, and to provide a high definition output signal to a video port using the deserialized video information.3. The system of claim 2 , including: a first input configured to receive USB information from a USB controller; a second input configured to receive the non-packet-based serialized video information from the video serializer; and', 'an output configured to provide at least one of the USB information or the non-packet-based serialized video information to the physical USB interface; and, 'a switch includingwherein the switch is configured to couple the first input with the output in a first state and to couple the second input with the output in a second state.4. The system of claim 3 , wherein the first input includes a USB port configured to receive packet-based information according to a USB protocol; andwherein the output is configured to provide the packet-based information to ...

Method and apparatus for device dynamic addition processing, and method and apparatus for device dynamic removal processing

A method and an apparatus for device dynamic addition processing, and a method and an apparatus for device dynamic removal processing. A dynamic addition dependency relationship list may be obtained from a BIOS, and dynamic addition processing is performed on a certain device to be dynamically added, according to the dynamic addition dependency relationship list; a user is prompted to dynamically add the target device, and when there is a certain device to be dynamically removed, a dynamic removal dependency relationship list and a dynamic addition dependency relationship list of a corresponding device may be obtained from the BIOS as needed, and dynamic removal analysis and processing are performed according to the combination of the dynamic removal dependency relationship list and dynamic addition dependency relationship list of the corresponding device, so as to prompt the user to dynamically remove the target device.

Field Bus Network Adapter and Field Bus Network Subscriber with Field Bus Connections

A field bus network adapter includes a first field bus connection configured to connect a first field bus cable, a second field bus connection configured to connect a second field bus cable, and N number of third field bus connections configured to connect a third cable each. The first field bus connection and the second field bus connection are connected to the N number of third field bus connections such that (i) data received at the first field bus connection are output at a first of the N number of third field bus connections, (ii) data received at an nth of the N number of third field bus connections are output at an (n+1)th of the N number of third field bus connections, and (iii) data received at an Nth of the N number of third field bus connections are output at the second field bus connection.

MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE

A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format. 1. A modular integrated circuit comprising:a plurality of spoke modules; and a power management unit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of power supply signals to the plurality of spoke modules via the plurality of hub interfaces; and', 'a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules via the plurality of hub interfaces;', 'wherein the plurality of hub interfaces provides a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format., 'a hub module that is coupled to the plurality of spoke modules to facilitate inter-spoke communications via a corresponding plurality of hub interfaces, the hub module including2. The modular integrated circuit of wherein the common signaling format for each of the plurality of hub interfaces includes:a clock request signal received from a corresponding one of the plurality of spoke modules; andat least one of the plurality of clock signals.3. The modular integrated circuit of wherein the common signaling format for each of the plurality of hub interfaces includes:a power ...

PCI EXPRESS ENHANCEMENTS AND EXTENSIONS

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. 1. An apparatus comprising: 'receive a packet of a transaction over an interconnect from a device, and identify a hint from the packet;', 'an I/O module towherein the hint indicates an intended use of data in a memory associated with the transaction.2. The apparatus of claim 1 , wherein the interconnect comprises at least one of a Peripheral Component Interconnect Express (PCIe)-compliant interconnect claim 1 , a physical layer to support PCIe protocols claim 1 , a Common Systems Interconnect (CSI)-compliant interconnect claim 1 , and a physical layer to support a layered communication protocol.3. The apparatus of claim 1 , wherein the apparatus comprises a root controller and the I/O module is included in the root controller.4. The apparatus of claim 3 , wherein the root controller is configured to perform an action on the memory based at least in part on the hint.5. The apparatus of claim 4 , wherein the action is included in completion of the transaction.6. The apparatus of claim 1 , wherein the transaction includes a read request of the memory.7. The ...

System and Method for High-Performance, Low-Power Data Center Interconnect Fabric

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

PCI EXPRESS ENHANCEMENTS AND EXTENSIONS

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. 1. An apparatus comprising: receive a plurality of transactions over a PCIe-compliant interconnect, wherein the plurality of transactions are to be received in a first order;', 'identify a relaxed ordering value included in at least one of the plurality of transactions; and', 'reorder the plurality of transactions into a second, different order based at least in part on the relaxed ordering value, wherein a particular one of the plurality of transactions is to precede another of the plurality of transactions in the first order and is to follow the other transaction in the second order., 'an I/O element to2. The apparatus of claim 1 , wherein at least one of the particular transaction and other transaction includes an atomic operation.3. The apparatus of claim 1 , wherein the plurality of transactions is to be completed according to the second order.4. The apparatus of claim 1 , wherein the I/O element is included in a root controller of the apparatus.5. The apparatus of claim 1 , wherein the plurality of transactions is to be reordered on the interconnect.6 ...

System and Method for High-Performance, Low-Power Data Center Interconnect Fabric

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch. 1. A system on a chip , comprising:one or more processing cores;a switching fabric; andone or more management processors coupled to the fabric switch and to each one of the one or more processing cores, wherein the management processor causes a communication request directed to a first one of the one or more processing cores to be held in the switching fabric while the first one of the one or more processing cores is in an inactive state and causes the communication request to be received by the first one of the one or more processing cores in response to the first one of the one or more processing cores being transitioned from the inactive state to an active state.2. The system on a chip of wherein:the inactive state is a state in which electrical power allocated to the first one of the one or more processing cores is inadequate for performing a task requested in the communication request; andthe active state is a state in which electrical power allocated to the first one of the one or more processing cores is adequate for performing a task requested in the communication request3. The system on a chip of wherein the first processor is asleep when in the inactive state.4. A system on a chip claim 2 , comprising:one or more processing cores;a switching fabric; andone or more management processors coupled to the fabric switch and to each one of the one or more processing cores, wherein the management processor causes a communication request directed to a first one of the one or more processing cores to be held in ...

CPU INTERCONNECT DEVICE

The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved. 1. A CPU interconnect device that is configured to connect to a CPU , the CPU interconnect device comprising:a quick path interconnect (QPI) interface; anda serial deserial (SerDes) interface,wherein:the QPI interface is configured to receive first serial QPI data from the CPU, convert the received first serial QPI data into first parallel QPI data, and output the first parallel QPI data to the SerDes interface; andthe SerDes interface is configured to convert the first parallel QPI data output by the QPI interface into a first high-speed serial SerDes data and then communicate the first high-speed serial SerDes data to another CPU interconnect device connected with a second CPU;the SerDes interface is further configured to receive a second high-speed serial SerDes data from the other CPU interconnect device, convert the received second high-speed serial SerDes data into second parallel QPI data, and output the second parallel QPI data to the QPI interface; andthe QPI interface is further configured to convert the second parallel QPI data output by the SerDes interface into a second serial QPI data and then send the second serial QPI data to the first CPU.2. The CPU ...

System and Method for Providing PCIE over Displayport

An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed 120-. (canceled)21. An information handling system comprising:a processor configured to generate information;a video display subsystem interfaced with the processor and configured to process the information into video information for communication to a display;a host main link interfaced with video display subsystem and configured to couple to a display cable;a display configured to present the video information as visual images;a display main link interfaced with the display and configured to couple to the display cable;a display cable coupled at a first end to the host main link and at a second end to the display main link, the display cable configured to communicate the video information from the video display subsystem to the display across four serial links; anda peripheral coupled to the display and having associated peripheral information;wherein the display main link is further configured to communicate the peripheral information through the display cable to the host main link, the display main link and host main link cooperating to selectively assign some of the four serial links to communicate the peripheral information while the remaining of the four serial links communicate the video information.22. The information handling system of further comprising:a display receiver interfaced with the display main link and configured to receive the video information from the display cable;a peripheral transceiver interfaced with the display main link and configured to communicate peripheral information with the display cable; anda multiplexor disposed between the main link and the display receiver and the peripheral transceiver, the ...

Universal usb charger

A universal USB charger connected to an electronic device stored with a set of preset voltage values has a power supply circuit, a USB interface having a V BUS terminal and a ground terminal respectively connected to a positive DC power terminal and a ground terminal of the power supply circuit, and an output voltage switching module having multiple preset voltage units corresponding to electronic devices of multiple brands and a switching interface connected between the preset voltage units and a D + terminal and a D − terminal of the USB interface. Each preset voltage unit outputs a D + voltage and a D − voltage. The switching interface is operated to output the D + and D − voltages associated with the electronic device through the D + and D − terminals. After determining that the D + and D − voltages match the set of preset voltage values, the electronic device allows itself to be charged by the charger.

Multi-Processor Architecture Implementing A Serial Switch And Method Of Operating Same

A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards. 1. A multi-processor architecture comprising:a plurality of blades, each including: a plurality of processors, a switch fabric that implements connections using point-to-point serial links, wherein the switch fabric is coupled to each of the plurality of processors, and packet processing logic coupled to the switch fabric; anda first external switch fabric that implements connections using point-to-point serial links, wherein the first external switch fabric is coupled to each switch fabric of the plurality of blades.2. The multi-processor architecture of claim 1 , further comprising a management processor coupled to the first external switch fabric.3. The multi-processor architecture of claim 2 , further comprising a processor accelerator coupled to the first external switch fabric.4. The multi-processor architecture of claim 1 , further comprising:one or more line cards that receive and transmit data packets; anda second external switch fabric coupling each of the one or more line cards to the packet processing logic of each of the plurality of blades.5. The multi-processor architecture of claim 4 , further comprising a third external switch fabric coupled to the first external switch fabric claim 4 , the one or more line cards and the second external switch fabric ...

I/O VIRTUALIZATION VIA A CONVERGED TRANSPORT AND RELATED TECHNOLOGY

The invention is directed to I/O Virtualization via a converged transport, as well as technology including low latency virtualization for blade servers and multi-host hierarchies for virtualization networks. A virtualization pipe bridge is also disclosed, as well as a virtual desktop accelerator, and a memory mapped thin client. 1. An I/O virtualization mechanism configured to enable use of a converged transport, configured to provide means for extension of PCI Express differentiated services via the Internet, LANs, WANs, and WPANs. This application claims priority of U.S. Provisional Patent Application Ser. No. 61/556,078 entitled I/O Virtualization via a Converged Transport and Related Technology filed Nov. 4, 2011 and U.S. Provisional Patent Application Ser. No. 61/560,401 entitled Virtual Desktop Accelerator, Remote Virtualized Desktop Accelerator Pool, and Memory Mapped Thin Client filed Nov. 16, 2011.i-PCI—A hardware/software system and method that collectively enables virtualization of the host bus computer's native I/O system architecture via the Internet, LANs, WANs, and WPANs is described in U.S. Pat. No. 7,734,859, the teaching of which are included herein in its entirety. The system described therein, designated “i-PCI”, achieves technical advantages as a hardware/software system and method that collectively enables virtualization of the host computer's native I/O system architecture via the Internet, LANs, WANs, and WPANs.This system allows devices native to the host computer native I/O system architecture—including bridges, I/O controllers, and a large variety of general purpose and specialty I/O cards—to be located remotely from the host computer, yet appear to the host system and host system software as native system memory or I/O address mapped resources. The end result is a host computer system with unprecedented reach and flexibility through utilization of LANs, WANs, WPANs and the Internet, as shown in .A solution for handling Quality of Service ...