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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 15. Отображено 15.
02-08-2012 дата публикации

System and Method for Improving Throughput of Data Transfers Using a Shared Non-Deterministic Bus

Номер: US20120198117A1
Автор: Srinjoy Das, Philip Crary, Alexander Raykhman, DAS SRINJOY, CRARY PHILIP, RAYKHMAN ALEXANDER
Принадлежит:

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination. 1. A data transfer subsystem for facilitating data transfer to a memory , wherein the memory is accessible via a non-deterministic bus , wherein the data transfer subsystem comprises control logic configured to:receive a first request that first data be transferred between a first logic subsystem and the memory;receive a second request that second data be transferred between the first logic subsystem and the memory;initiate a first data transfer in response to the first request;initiate a second data transfer in response to the second request, wherein the second data transfer is initiated before the first data transfer is completed;wherein the non-deterministic bus utilizes quality of service (QOS) timers for data transfer requests, wherein the non-deterministic bus is configured to service data transfer requests based on the QOS timers;wherein said initiating the second data transfer before the first data transfer is completed initiates a QOS timer for the second data transfer, wherein said initiating the second data transfer before the first data transfer is completed causes the second data transfer to be performed in immediate succession to the first data transfer.2. The data transfer subsystem of claim 1 ,wherein said initiating the second data transfer before the first data transfer is completed comprises initiating the second data transfer at a determined time interval after initiation of the first data transfer, wherein determined time interval is configured based on the QOS ...

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Номер записи: 1
02-08-2012 дата публикации

System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain

Номер: US20120198267A1
Автор: Srinjoy Das, Philip Crary, Alexander Raykhman, DAS SRINJOY, CRARY PHILIP, RAYKHMAN ALEXANDER
Принадлежит: Qualcomm Atheros Inc

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 2
30-04-2013 дата публикации

Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle

Номер: US0008433944B2
Автор: Srinjoy Das, Haikun Zhu, Kevin R. Bowles, Matthew L. Severson, DAS SRINJOY, ZHU HAIKUN, BOWLES KEVIN R, SEVERSON MATTHEW L, BOWLES KEVIN R., SEVERSON MATTHEW L.
Принадлежит: QUALCOMM Incorporated, DAS SRINJOY, ZHU HAIKUN, BOWLES KEVIN R, SEVERSON MATTHEW L, QUALCOMM INC, BOWLES KEVIN R., SEVERSON MATTHEW L., QUALCOMM INCORPORATED

In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.

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Номер записи: 3
02-08-2012 дата публикации

System and Method for Facilitating Data Transfer Using a Shared Non-Deterministic Bus

Номер: US20120195350A1
Автор: Srinjoy Das, Philip Crary, Alexander Raykhman, DAS SRINJOY, CRARY PHILIP, RAYKHMAN ALEXANDER
Принадлежит:

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination. 1. A functional block implementing a wireless technology , comprising:a radio frequency (RF) subsystem, wherein the RF subsystem comprises an antenna for receiving RF data;one or more RF signal processing subsystems configured to process the RF data; receive a first RF data transfer request from the RF subsystem, wherein the first RF data transfer request is a request that first RF data be transferred from the RF subsystem to the non-local memory, wherein the first RF data transfer request has a first priority level;', 'receive a second RF data transfer request from a first RF signal processing subsystem, wherein the second RF data transfer request is a request that second RF data be transferred between the first RF signal processing subsystem and the non-local memory, wherein the second RF data transfer request has a second priority level, wherein the first priority level is higher than the second priority level; and', 'initiate the first RF data transfer, wherein said initiating is based on the first priority level being higher than the second priority level., 'a data transfer subsystem for facilitating transfer of the RF data between the functional block and a non-local memory, wherein the data transfer subsystem is configured to2. The functional block of claim 1 ,wherein the non-local memory is accessible via a non-deterministic bus, wherein the data transfer subsystem shares access to the non-deterministic bus with at least a second bus master.3. The functional block of claim 1 ...

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Номер записи: 4
16-07-2002 дата публикации

Method and apparatus for controlling the programming and erasing of flash memory

Номер: US0006421757B1
Автор: Peiqing Wang, Srinjoy Das, WANG PEIQING, DAS SRINJOY
Принадлежит: Conexant Systems, Inc, CONEXANT SYSTEMS INC, CONEXANT SYSTEMS, INC

A method and apparatus for automating and controlling the programming operations in a flash memory is provided to enable a microcontroller to accomplish various other controlling tasks while the programming operations are being conducted. A state machine is provided for controlling a plurality of sequences utilized in programming the flash memory, with various functional circuits provided to facilitate the programming and verification of flash memory cells. In a preferred embodiment, the reprogramming of the flash cells is limited to those flash cells verified as a programming failure, thus reducing the necessary programming of the flash memory cells which may impede the ability to program those flash cells. The control system may also be configured to provide for automating and controlling the erasing operations in a flash memory. The common interface circuitry may be employed to facilitates automation and control of both programming and erasing functions.

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Номер записи: 5
15-05-2001 дата публикации

Method and apparatus for pre-conditioning flash memory devices

Номер: US0006233178B1
Автор: Shyam Krishnamurthy, Srinjoy Das, Michael Le, Frank Van Gieson, Surya Bhattacharya, Umesh Sharma, KRISHNAMURTHY SHYAM, DAS SRINJOY, LE MICHAEL, GIESON FRANK VAN, BHATTACHARYA SURYA, SHARMA UMESH
Принадлежит: Conexant Systems, Inc., CONEXANT SYSTEMS INC, CONEXANT SYSTEMS, INC.

Pre-conditioning method and apparatus for mitigating erase-induced stress within flash memory devices are disclosed. The pre-condition method includes subjecting flash memory cell to a short write process to at least partially discharge the cells. The pre-condition process is applied to an entire sector at one time, and is performed immediately prior to erasing (charging) the cells within the sector.

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Номер записи: 6
13-10-2011 дата публикации

Clock Divider System and Method

Номер: US20110248764A1
Автор: Srinjoy Das, Haikun Zhu, Kevin R. Bowles, Matthew L. Severson, DAS SRINJOY, ZHU HAIKUN, BOWLES KEVIN R, SEVERSON MATTHEW L, BOWLES KEVIN R., SEVERSON MATTHEW L.
Принадлежит: QUALCOMM INCORPORATED

In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.

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Номер записи: 7
22-10-2013 дата публикации

System and method for improving throughput of data transfers using a shared non-deterministic bus

Номер: US0008566491B2
Автор: Srinjoy Das, Philip Crary, Alexander Raykhman, DAS SRINJOY, CRARY PHILIP, RAYKHMAN ALEXANDER
Принадлежит: QUALCOMM Incorporated, DAS SRINJOY, CRARY PHILIP, RAYKHMAN ALEXANDER, QUALCOMM INC, QUALCOMM INCORPORATED

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 8
02-08-2012 дата публикации

System and Method for Managing a Memory as a Circular Buffer

Номер: US20120198181A1
Автор: Srinjoy Das, Philip Crary, Alexander Raykhman, DAS SRINJOY, CRARY PHILIP, RAYKHMAN ALEXANDER
Принадлежит:

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination. 1. A method for facilitating data transfer between one or more logic subsystems and a memory , wherein the method manages at least a first portion of the memory as a circular buffer , the method comprising:maintaining a write location pointer, wherein the write location pointer indicates a location in the circular buffer which is currently being written to;maintaining a page pointer, wherein the page pointer indicates a page of the circular buffer which is currently being written to;receiving a notification of a desired search range, wherein the desired search range comprises a portion of the circular buffer to be searched;determining a validity of the desired search range, wherein said determining is based on the search range, the write location pointer, and the page pointer;sending a notification of the validity of the desired search range.2. The method of claim 1 ,wherein the notification of the desired search range is received from a first logic subsystem;wherein the notification of the validity of the desired search range is sent to the first logic subsystem;wherein the notification of the validity of the desired search range is used by the first logic subsystem to determine whether to perform the desired search.3. The method of claim 1 ,wherein the desired search range comprises locations on a plurality of pages of the circular buffer.4. The method of claim 1 , wherein the desired search range comprises the location indicated by the write location pointer on the page indicated ...

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Номер записи: 9
30-09-2014 дата публикации

System and method for facilitating data transfer using a shared non-deterministic bus

Номер: US0008848731B2
Автор: Srinjoy Das, Philip Crary, Alexander Raykhman, DAS SRINJOY, CRARY PHILIP, RAYKHMAN ALEXANDER
Принадлежит: QUALCOMM Incorporated, DAS SRINJOY, CRARY PHILIP, RAYKHMAN ALEXANDER, QUALCOMM INC, QUALCOMM INCORPORATED

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 10
09-08-2012 дата публикации

System and method for improving throughput of data transfers using a shared non-deterministic bus

Номер: WO2012106106A1
Автор: Alexander Raykhman, Philip Crary, Srinjoy Das
Принадлежит: Qualcomm Atheros, Inc.

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 11
09-08-2012 дата публикации

System and method for facilitating data transfer using a shared non-deterministic bus

Номер: WO2012106104A1
Автор: Alexander Raykhman, Philip Crary, Srinjoy Das
Принадлежит: Qualcomm Atheros, Inc.

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 12
09-08-2012 дата публикации

System and method for managing a memory as a circular buffer

Номер: WO2012106108A1
Автор: Alexander Raykhman, Philip Crary, Srinjoy Das
Принадлежит: Qualcomm Atheros, Inc.

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 13
09-08-2012 дата публикации

System and method for facilitating data transfer between a first clock domain and a second clock domain

Номер: WO2012106115A1
Автор: Alexander Raykhman, Philip Crary, Srinjoy Das
Принадлежит: Qualcomm Atheros, Inc.

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 14
20-10-2011 дата публикации

Clock divider system and method

Номер: WO2011130052A1
Автор: Haikun Zhu, Kevin R. Bowles, Matthew L. Severson, Srinjoy Das
Принадлежит: QUALCOMM INCORPORATED

In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.

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Номер записи: 15