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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 14648. Отображено 100.
21-03-2022 дата публикации

Устройство коммуникационное для кластерной цифровой подстанции

Номер: RU0000209720U1
Автор: Андрей Александрович Кузьмин, Андрей Владиславович Климов, Илья Викторович Лукьянов, Сергей Александрович Перегудов
Принадлежит: Акционерное общество "Русатом Автоматизированные Системы Управления" (АО "РАСУ")

Полезная модель относится к области кластерных цифровых электрических подстанций (ЦПС).Техническим результатом является обеспечение подключения устройства кластерной ЦПС к независимым сегментам станционной и технологической шин коммуникационной сети (Ethernet) ЦПС, в каждом из которых дополнительно обеспечивается коммуникационное резервирование с применением «бесшовного» резервирования в соответствии с IEC 62432-3, в частности резервирования по протоколу PRP ("Parallel Redundancy Protocol"). Устройство коммуникационное (1) включает в себя четыре интерфейса (2-5) подключения к внешней коммуникационной сети Ethernet ЦПС, процессор (8); коммутатор (9), связанный с процессором (8), включающий в себя также, по меньшей мере, один внешний коммуникационный порт (12) для связи с соответствующим интеллектуальным электронным устройством (IED) (13) кластерной ЦПС. Устройство (1) дополнительно содержит два коммуникационных шлюза (10 и 11), связанных с процессором (8). При этом первый коммуникационный шлюз (10) также связан с первым (2) и вторым (3) интерфейсами подключения к внешней коммуникационной сети Ethernet ЦПС (6, 7), а второй коммуникационный шлюз (11) также связан с третьим (4) и четвертым (5) интерфейсами подключения к внешней коммуникационной сети Ethernet ЦПС (6, 7). При этом интерфейсы (2) и (3) устройства (1) предназначены для подключения к резервированному по протоколу PRP (IEC 62439-3) сегменту (6.1 - подсеть "A" (PRP), 7.1 - подсеть "В" (PRP)) станционной шины коммуникационной сети ЦПС, а интерфейсы (4) и (5) - к резервированному по протоколу PRP (IEC 62439-3) сегменту (6.2 - подсеть "A" (PRP), 7.2 - подсеть "В" (PRP)) технологической шины коммуникационной сети ЦПС. При этом первый коммуникационный шлюз (10) выполнен с возможностью обеспечения коммуникационного сопряжения с резервированным сегментом станционной шины (6.1, 7.1) внешней коммуникационной сети ЦПС с обеспечением двусторонней передачи данных в прямом и обратном ...

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Номер записи: 1
12-01-2012 дата публикации

Low power, low pin count interface for an rfid transponder

Номер: US20120007720A1
Автор: Mark R. Whitaker
Принадлежит: Ramtron International Corp

A serial interface includes a select node, a clock node, a first bidirectional data port, a second bidirectional data port, and shift register circuitry coupled to both data ports such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift or transfer data.

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Номер записи: 2
22-03-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120068539A1
Автор: Masayoshi SHIOTANI
Принадлежит: Panasonic Corp

A constantly power-ON domain and a standby-time power OFF domain are included on the same chip, and the constantly power-ON domain includes: a shutoff control circuit shutting off a signal inputted and outputted between the constantly power-ON domain and the standby-time power OFF domain when the first power source is ON and the second power source is OFF; and a shutoff control circuit outputting a first control signal indicating that shutoff of an emergent shutoff control circuit unit is to be enabled or disabled, the standby-time power OFF domain includes the emergent shutoff control circuit unit shutting off, based on the first control signal from the shutoff control circuit, the signal inputted between the emergent shutoff control circuit unit and the constantly power-ON domain.

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Номер записи: 3
03-05-2012 дата публикации

Medical Data Collection Apparatus

Номер: US20120110228A1
Автор: Anna McNamara, Charles Gropper, Erich Vlach
Принадлежит: Cardionet LLC

A physiological data collection device obtains physiological data from a subject interface on a subject. The physiological data collection device includes a data connector such as a USB connector for connecting directly to a computer. When the physiological data collection device is connected to the computer, the physiological data is uploaded to a remote data processing center for computer-based analysis and review by a medical professional. A report can be provided to the subject based on the analysis and review. When the subject interface is physically connected to the physiological data collection device, the data connector is prevented from being connected to an external device such as the computer.

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Номер записи: 4
10-05-2012 дата публикации

Usb connector device for an antenna

Номер: US20120112984A1
Автор: Cheng-Si Wang
Принадлежит: Trans Electric Co Ltd

A USB connector device for an antenna has a first cable, a receiver, a second cable and a USB connector. The first cable has an end connected to the receiver. The second cable has two ends respectively connected to the receiver and the USB connector. Because the receiver and the USB connector are combined in a series-connection way, the series-connection design can compact the structure of the USB connector device for an antenna in accordance with the present invention and reduce redundant cables, and it occupies a single one USB slot of the computer only. The USB connector device is very useful and convenient in use.

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Номер записи: 5
17-05-2012 дата публикации

Segmented transmission signal circuit

Номер: US20120119854A1
Автор: Chih-Chuan Huang
Принадлежит: Raydium Semiconductor Corp

A segmented transmission signal circuit is provided with a parallel bus of data transmission. The bus includes a plurality of sections, each section transmits a corresponding parallel data of multiple bits, and the parallel data corresponding to different sections are in different bit orders.

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Номер записи: 6
17-05-2012 дата публикации

Hybrid storage device and electronic system using the same

Номер: US20120124266A1
Автор: Byung-Hoon Chung, Jae-won You, Kyu-yeol Park, Tae-yung Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A hybrid storage device is provided. The hybrid storage device includes a first storage part that comprises an interface device based on a first standard, a second storage part that comprises an interface device based on a second standard, and a connector for interface devices that is shared by the first storage part and the second storage part and comprises a plurality of pins.

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Номер записи: 7
24-05-2012 дата публикации

Determining addresses of electrical components arranged in a daisy chain

Номер: US20120131231A1
Автор: Gerardo Monreal
Принадлежит: Allegro Microsystems LLC

In one aspect, a system includes electrical components arranged in a daisy chain that include a first electrical component disposed at a first end of the daisy chain and a second electrical component disposed at an opposite end of the daisy chain than the first end. Each of the first and second electrical components includes an input port, an output port and a common port. The input port of the first electrical component is coupled to one of a supply voltage port or ground and the common ports of the first and second electrical components are coupled to the other one of the supply voltage or the ground. An address of the second electrical component is determined before addresses of the other of the electrical components are determined, and the addresses determine a position of an electrical component with respect to the other of the electrical components.

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Номер записи: 8
12-07-2012 дата публикации

Protocol translation method and bridge device for switched telecommunication and computing platforms

Номер: US20120177035A1
Автор: Barton W. Stuck, Ching-Tai Hu, Viswa Nath Sharma, William Chu, Yi-chang Chou
Принадлежит: Psimast Inc

A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

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Номер записи: 9
19-07-2012 дата публикации

Apparatus and methods for serial interfaces

Номер: US20120185623A1
Автор: Florinel G. Balteanu, James Henry Ross
Принадлежит: Skyworks Solutions Inc

Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers.

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Номер записи: 10
26-07-2012 дата публикации

Expandable asymmetric-channel memory system

Номер: US20120191921A1
Автор: Arun Vaidyanath, Ian Shaeffer, Sanku Mukherjee
Принадлежит: RAMBUS INC

An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

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Номер записи: 11
16-08-2012 дата публикации

Method and apparatus for plug and play, networkable iso 18000-7 connectivity

Номер: US20120207141A1
Автор: John Peter Norair
Принадлежит: Blackbird Technology Holdings Inc

A device may comprise a Universal Serial Bus (USB) interface and a wireless interface operable to communicate in accordance with the ISO 18000-7 standard. The device may be operable to receive a command via the USB interface and transmit the command via the wireless interface. The device may be operable to receive data via the wireless interface and transmit the data via the USB interface. A form factor of the USB device may be such that it can be plugged directly into a USB port without any external cabling between the USB device and said USB port.

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Номер записи: 12
30-08-2012 дата публикации

Semiconductor memory device and method of controlling the same

Номер: US20120221918A1
Автор: Hironori Uchikawa, Shinichi Kanno
Принадлежит: Hironori Uchikawa, Shinichi Kanno

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

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Номер записи: 13
27-09-2012 дата публикации

HID over Simple Peripheral Buses

Номер: US20120246377A1
Автор: Arvind R. AIYAR, David Abzarian, Firdosh K. Bhesania, Randall E. Aull
Принадлежит: Individual

In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system.

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Номер записи: 14
29-11-2012 дата публикации

Heat management in an above motherboard interposer with peripheral circuits

Номер: US20120300392A1
Автор: Frederick G. Weiss, Morgan Johnson
Принадлежит: Morgan Johnson, Weiss Frederick G

A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, at least one peripheral circuit on the interposer substrate, and a heat sink thermally coupled to the peripheral circuit.

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Номер записи: 15
28-03-2013 дата публикации

Virtual General Purpose Input/Output for a Microcontroller

Номер: US20130080677A1
Автор: Michael Simmons
Принадлежит: Microchip Technology Inc

A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.

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Номер записи: 16
28-03-2013 дата публикации

CABLE REDUNDANCY AND FAILOVER FOR MULTI-LANE PCI EXPRESS IO INTERCONNECTIONS

Номер: US20130080678A1
Автор: BUCKLAND Patrick A., HERRING Jay R., Nordstrom Gregory M., THOMPSON William A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device. 1. A method for providing a failover operation for a connection between a first PCIE bridge and a first input/output (IO) device , the method comprising:exchanging a first set of bussed bits between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge;in response to detecting a failure in the first link, exchanging a second set of bussed bits between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.2. The method of claim 1 , wherein exchanging the second set of bussed bits in response to detecting the failure comprises:at a PCIE bridge end, performing a first switch between the first set of lanes and a second set of lanes of the second PCIE bridge for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device using the unused portion of the second link, wherein the unused portion comprises the second set of lanes.3. The method of claim 2 , wherein exchanging the second set of bussed bits in response to detecting the failure further comprises:at an IO device end, performing a second switch between the first and the second sets of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device using the unused portion of the second link.4. The method of claim 3 , further comprising:in ...

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Номер записи: 17
04-04-2013 дата публикации

SWITCHING LOGIC MODULE

Номер: US20130086291A1
Автор: Hagemann Jörg, Stövesand Peter
Принадлежит: PHOENIX CONTACT GMBH & CO. KG

The innovation applies to a switch logic module (), which can be electrically and mechanically connected to and disconnected from I/O modules () that are arranged next to each other, whereby the I/O modules have an electrical contact and the mechanical connection can be established using the electrical contacts. According to the innovation, a multiplex logic is provided that can be used to connect the electrical contacts of the I/O modules cyclically for a predefined switch time to an output () of the switch module. This provides a space-saving and cost-effective solution that can be used to cyclically switch multiple electrical signals to one output with little installation effort and great flexibility. 1. Switch logic module , which can be mechanically and electrically connected to and disconnected from eight I/O modules , which are arranged next to each other , whereby the I/O modules have at least one electrical contact each and the mechanical connection can be established using the electrical contacts , which is characterized in that a multiplex logic is provided that can be used to cyclically connect the electrical contacts of the I/O modules for a predefined switch time to an output of the switch module.2. Switch logic module according to claim 1 , characterized in that the output of the switch logic modules has an electrical contact claim 1 , preferably a terminal or a plug connector.3. Switch logic module according to marked in that the output of the switch logic module has a wireless device.4. Switch logic module according to characterized in that the multiplex logic is designed so that the switch time can be configured.5. Switch logic module according to claim 4 , characterized in that the switch time can be configured using a DIP switch.6. Switch logic module according to and characterized in that the number of I/O modules that can be connected to the switch logic module can be configured.7. Switch logic module according to claim 6 , characterized in ...

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Номер записи: 18
11-04-2013 дата публикации

PCI EXPRESS ENHANCEMENTS AND EXTENSIONS

Номер: US20130091317A1
Автор: Ajanovic Jasmin, Akiyama James, Barry Peter, Bhatt Ajay V., Blankenship Robert G., Das Sharma Debendra, Falik Ohad, Harriman David J., Mendelson Avi, Muthrasanallur Sridhar, Pardo Ilan, Rodgers Scott Dion, Rosenbluth Mark B., Sethi Prashant, Shamia Doron, Tamari Eran, Vasudevan Anil, Wagh Mahesh, Weissmann Eliezer
Принадлежит:

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. 1. An apparatus comprising: 'receive a packet of a transaction over an interconnect from a device, and identify a hint from the packet;', 'an I/O module towherein the hint indicates an intended use of data in a memory associated with the transaction.2. The apparatus of claim 1 , wherein the interconnect comprises at least one of a Peripheral Component Interconnect Express (PCIe)-compliant interconnect claim 1 , a physical layer to support PCIe protocols claim 1 , a Common Systems Interconnect (CSI)-compliant interconnect claim 1 , and a physical layer to support a layered communication protocol.3. The apparatus of claim 1 , wherein the apparatus comprises a root controller and the I/O module is included in the root controller.4. The apparatus of claim 3 , wherein the root controller is configured to perform an action on the memory based at least in part on the hint.5. The apparatus of claim 4 , wherein the action is included in completion of the transaction.6. The apparatus of claim 1 , wherein the transaction includes a read request of the memory.7. The ...

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Номер записи: 19
25-04-2013 дата публикации

Universal usb charger

Номер: US20130103878A1
Автор: Chun-Shih Yi, Lien-Hsun Ho, Yi-chang Chou
Принадлежит: Cyber Power Systems Inc

A universal USB charger connected to an electronic device stored with a set of preset voltage values has a power supply circuit, a USB interface having a V BUS terminal and a ground terminal respectively connected to a positive DC power terminal and a ground terminal of the power supply circuit, and an output voltage switching module having multiple preset voltage units corresponding to electronic devices of multiple brands and a switching interface connected between the preset voltage units and a D + terminal and a D − terminal of the USB interface. Each preset voltage unit outputs a D + voltage and a D − voltage. The switching interface is operated to output the D + and D − voltages associated with the electronic device through the D + and D − terminals. After determining that the D + and D − voltages match the set of preset voltage values, the electronic device allows itself to be charged by the charger.

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Номер записи: 20
23-05-2013 дата публикации

Pci express enhancements and extensions

Номер: US20130132622A1
Автор: Ajay V. Bhatt, Anil Vasudevan, Avi Mendelson, David J. Harriman, Debendra Das Sharma, Doron Shamia, Eliezer Weissmann, Eran Tamari, Ilan Pardo, James Akiyama, Jasmin Ajanovic, Mahesh Wagh, Mark B. Rosenbluth, Ohad Falik, Peter Barry, Prashant Sethi, Robert G. Blankenship, Scott Dion Rodgers, Sridhar Muthrasanallur
Принадлежит: Individual

A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

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Номер записи: 21
06-06-2013 дата публикации

Electronic device and method for switching modes of thunderbolt connector thereof

Номер: US20130145071A1
Автор: Chen-Yi Chu, Chih-Pang Hsu, Ching-Hang Chen
Принадлежит: ASUSTeK Computer Inc

An electronic device and a method for switching mode of a thunderbolt connector thereof are provided. The electronic device includes a core unit, a PCIE device, a thunderbolt control unit, a first switch circuit and a second switch circuit. The thunderbolt control unit has a host mode and an end-point device mode. A common terminal of the first switch circuit is coupled to a PCIE port of the PCIE device. A first selection terminal of the first switch circuit is coupled to a first PCIE port of the core unit. A common terminal of the second switch circuit is coupled to a PCIE port of the thunderbolt control unit. A first selection terminal of the second switch circuit is coupled to a second PCIE port of the core unit. A second selection terminal of the first switch circuit is coupled to a second selection terminal of the second switch circuit.

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Номер записи: 22
13-06-2013 дата публикации

USB CHARGING MODULE

Номер: US20130151731A1
Автор: Chiu Hao-Hsuan, LAI YI-LIN, Shih Terrance
Принадлежит: VIA TECHNOLOGIES, INC.

An apparatus is provided for charging a Universal Serial Bus (USB) device according to an optimal charging mode. The apparatus includes a charging module that is configured to obtain a descriptor from the USB device upon detection of the USB device on a USB bus. The charging module includes one or more descriptor entries disposed in a memory and a controller. The one or more descriptor entries include descriptor data, for matching the descriptor to a specific descriptor entry, and charging data, that specifies the optimal charging mode for the USB device. The controller is coupled to the memory, and is configured to match the descriptor to the specific descriptor entry, and is configured to initiate the optimal charging mode on the USB bus according to the charging data. 1. An apparatus for charging a Universal Serial Bus (USB) device according to an optimal charging mode , the apparatus comprising: [ descriptor data, being arranged for matching the descriptor to a specific descriptor entry; and', 'charging data, being arranged specifying the optimal charging mode for the USB device; and, 'a memory, storing one or more descriptor entries, the one or more descriptor entries comprising, 'a controller, coupled to said memory, configured to compare the descriptor to the specific descriptor entry, and configured to initiate the optimal charging mode on the USB bus according to the charging data., 'a charging module, configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, the charging module comprising2. The apparatus as recited in claim 1 , wherein the charging module obtains the descriptor by causing a descriptor read command to be transmitted to the USB device over the USB bus.3. The apparatus as recited in claim 1 , wherein the charging module is disposed within a USB hub.4. The apparatus as recited in claim 3 , wherein the charging module obtains the descriptor when the USB hub is not coupled to a USB host.5. The apparatus ...

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Номер записи: 23
20-06-2013 дата публикации

APPARATUS, SYSTEMS AND METHODS FOR MODIFYING OPERATING STATES BASED ON MONITORED HDMI CEC COMMUNICATIONS

Номер: US20130159753A1
Автор: Richardson Jon
Принадлежит: EchoStar Technologies L.L.C.

Systems and methods provide control of operating states of an electronic device. A first exemplary electronic device detects a consumer electronic control (CEC) communication sent from a second electronic device to a third electronic device, the CEC communication communicated over high-definition multimedia (HDMI) connectors communicatively coupling the first electronic device, the second electronic device and the third electronic device; determines, based on information in the CEC communication, whether the CEC communication is one of a first kind of CEC communication or a second kind of CEC communication; in response to determining that the CEC communication is one of the first kind of CEC communication, transitions the first electronic device to a predefined operating state; and in response to determining that the CEC communication is one of the second kind of CEC communication, maintains the first electronic device in a current operating state. 1. A method , comprising:detecting, at a first electronic device, a consumer electronic control (CEC) communication sent from a second electronic device to a third electronic device, the CEC communication communicated over high-definition multimedia (HDMI) connectors communicatively coupling the first electronic device, the second electronic device and the third electronic device;determining, based on information in the CEC communication, whether the CEC communication is one of a first kind of CEC communication or a second kind of CEC communication;in response to determining that the CEC communication is one of the first kind of CEC communication, transitioning the first electronic device to a predefined operating state; andin response to determining that the CEC communication is one of the second kind of CEC communication, maintaining the first electronic device in a current operating state.2. The method of claim 1 , where in response to determining that the CEC communication is the first kind of CEC communication claim ...

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Номер записи: 24
18-07-2013 дата публикации

USB 3.0 DEVICE AND CONTROL METHOD THEREOF

Номер: US20130185462A1
Автор: MANABE Masao
Принадлежит: RENESAS ELECTRONICS CORPORATION

A control unit of a USB 3.0 device controls the USB 3.0 device that has entered an SS.Disabled state to transition to an Rx.Detect state when a USB 2.0 connection is not established after a predetermined time, in which the USB 2.0 connection is one of an HS (High Speed) connection, an FS (Full Speed) connection, and an LS (Low Speed) connection. This enables quick return to the Rx.Detect state for the USB 3.0 device that entered the SS.Disabled state due to an error in the host. 1. A control method for a USB 3.0 (USB: Universal Serial Bus) device comprising controlling the USB 3.0 device that has entered an SS.Disabled state to transition to an Rx.Detect state when a USB 2.0 connection is not established with a host even after a predetermined time , the USB 2.0 connection being any one of an HS (High Speed) connection , an FS (Full Speed) connection , and an LS (Low Speed) connection.2. A USB 3.0 (USB: Universal Serial Bus) device comprising a control unit that controls the USB 3.0 device that has entered an SS.Disabled state to transition to an Rx.Detect state when a USB 2.0 connection is not established after a predetermined time , the USB 2.0 connection being one of an HS (High Speed) connection , an FS (Full Speed) connection , and an LS (Low Speed) connection.3. The USB 3.0 device according to claim 2 , further comprising:a USB 2.0 connection unit that performs a connection procedure for the USB 2.0 connection; andan SS connection unit that performs a connection procedure for an SS (Super Speed) connection, wherein comprises a timer that counts time from when the USB 3.0 device enters the SS.Disabled state,', 'controls the SS connection unit to stop operating and also controls the USB 2.0 connection unit to start the connection procedure when Receiver Detection performed by the SS connection unit fails in the Rx.Detect state, so that the USB 3.0 device transitions to the SS.Disabled state, and', 'controls the SS connection unit to start the Receiver Detection ...

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Номер записи: 25
01-08-2013 дата публикации

Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits

Номер: US20130198430A1
Автор: Chu William W. Y.
Принадлежит: ACQIS LLC

A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. 1. A printed circuit board , comprising:an integrated central processing unit and graphics subsystem in a single chip;a Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and graphics subsystem to convey address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form, wherein the LVDS channel comprises a first unidirectional, differential signal line pair to convey data in a first direction and a second unidirectional, differential signal line pair to convey data in a second, opposite direction; anda socket for a system memory module, directly coupled to the integrated central processing unit and graphics subsystem.2. The printed circuit board of claim 1 , further comprising an Ethernet controller that couples to the integrated central processing unit and graphics subsystem through the LVDS channel.3. A printed circuit board claim 1 , comprising:a central processing unit connected directly to a Low Voltage Differential Signal (LVDS) channel to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form, wherein the LVDS channel comprises a first plurality of unidirectional, ...

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Номер записи: 26
01-08-2013 дата публикации

DATA PROCESSING APPARATUS, INPUT CONTROL APPARATUS, AND CONTROL METHOD

Номер: US20130198431A1
Автор: HARA Yuji, ISHIKAWA Hisashi
Принадлежит: CANON KABUSHIKI KAISHA

An input control apparatus, which accepts input of data from the outside and inputs the data to a bus in a data processing system in which a plurality of communication units are connected by the bus in a ring shape and data processed by processing units are delivered via the bus, controls acceptance of data based on the number of data items which should be output outside, are suspended from output, and remain on the bus. 1. A data processing apparatus comprising:a plurality of communication units configured to be connected by a ring-shaped bus; anda plurality of processing units corresponding to said respective communication units configured to process data supplied from said plurality of communication units,wherein when a processing unit corresponding to a first communication unit out of said plurality of communication units is in a data unacceptable state, said first communication unit adds, to data which could not be accepted by said processing unit, stall information representing that said processing unit could not accept data, and makes the data go around the ring-shaped bus, anda second communication unit out of said plurality of communication units suppresses input of data to the ring-shaped bus based on the data to which the stall information is added.2. An input control apparatus which accepts input of data from outside and inputs the data to a bus in a data processing system in which a plurality of communication units are connected by the bus in a ring shape and data processed by processing units are delivered via the bus , comprising:an acquisition unit configured to acquire the number of data items which are to be output outside, are suspended from output, and remain on the bus; anda control unit configured to control acceptance of data based on the number of data items.3. The apparatus according to claim 2 , wherein when the number of data items is larger than or equal to a first predetermined value claim 2 , said control unit suspends acceptance of ...

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Номер записи: 27
15-08-2013 дата публикации

Inter-component communication including slave component initiated transaction

Номер: US20130212311A1
Автор: Mikal C. Hunsaker, Ricardo E. James, Su Wei Lim
Принадлежит: Intel Corp

Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed. A component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. Other embodiments may be disclosed or claimed.

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Номер записи: 28
22-08-2013 дата публикации

DIGITAL RACK INTERFACE POD SYSTEM AND METHOD

Номер: US20130215884A1
Автор: Lew Adam W., Lo Lawrence, Mills Karl, Nurmohamed Mehmood
Принадлежит: AVOCENT HUNTSVILLE CORP.

A digital rack interface pod (DRIP) that is able to establish a communications link between a remote access appliance and a server having a USB port and a video port, to facilitate a keyboard/video/mouse (KVM) session between the server and the appliance. The DRIP is also able to establish a communications link between the appliance and an Ethernet port of the server that is associated with a service processor (SP) of the server. In this manner the DRIP is able to route data from the SP of the server to the appliance as well as communications from the appliance to the SP Ethernet port of the server. The DRIP is able to intelligently determine which packets of information received from the appliance are intended for the SP Ethernet port of the server and routes those packets to the SP Ethernet port of the server. The DRIP also automatically monitors and dynamically reassigns its two Ethernet ports as needed so that whichever one of its two Ethernet ports it discovers a connection with the appliance on will be the port that it continues using to communicate with the appliance. 1. A digital rack interface pod apparatus adapted to facilitate communications with a service processor of a server , the apparatus comprising:a first bidirectional communications port and a second bidirectional communications port, at least one of the first and second bidirectional communications ports enabling a first communications cable to be coupled thereto to enable a connection to be made to an appliance, and the other one of the bidirectional communications ports enabling a second communications cable to be coupled thereto to enable a connection to be made with a service processor port of the server;a cable assembly for enabling the apparatus to be coupled to a video port and to a universal serial bus (USB) port of the server;a circuit in communication with at least the first and second bidirectional communication ports, the circuit configured to monitor communications from the appliance ...

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Номер записи: 29
22-08-2013 дата публикации

High-definition multimedia interface (hdmi) receiver apparatuses, hdmi systems using the same, and control methods therefor

Номер: US20130219087A1
Автор: Liyan Du
Принадлежит: Mediatek Singapore Pte Ltd

A high-definition multimedia interface (HDMI) receiver apparatus is provided. The HDMI receiver apparatus includes a pin, a control module, and an extended display identification data (EDID) module. The pin is used to receive an HDMI cable connection voltage in a first operation state and output a hot plug detection signal in a second operation state. The control module is connected with the pin. When the pin receives the HDMI cable connection voltage in the first operation state, the control module switches the pin to the second operation state from the first operation state and outputs the hot plug detection signal to an HDMI transmitter apparatus through the pin, such that the HDMI transmitter apparatus reads EDID information according to the hot plug detection signal. The EDID module is used to store the EDID information.

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Номер записи: 30
22-08-2013 дата публикации

Device Interface Module

Номер: US20130219099A1
Автор: PYK MAGNUS
Принадлежит: AMERICAN RELIANCE, INC.

A computer, such as a portable computer, can include a removable interface module. The module can contain a device having a computer interface. The device can be a radio or a fiber optic communications device, for example. The use of such a module can facilitate repair and reconfiguration of the portable computer in the field. Such computers can be used by military personnel, police, emergency medical personnel, fire fighters, and the like. 1. A system comprising:a host computer having a device bay;a first circuit contained within the host computer and configured to route LAN signals inside of the host computer;a second circuit configured to route the LAN signals out of the host computer to a complimentary docking connector of the device bay;a device bay module within the device bay;a router board within the device bay module to which the LAN signals are routed from the complimentary docking connector;a third circuit within the device bay module to which the LAN signals are routed from the router board; andwherein the LAN signals facilitate communication between the host computer and the module.2. The system as recited in claim 1 , wherein:the module comprises a computer interface that is configured to facilitate communication of at least one device with the computer; and a PCI interface;', 'a USB interface;', 'an RS232 serial interface;', 'an RS422 serial interface;', 'a SATA interface;', 'an RS485 serial interface; and', 'an IEEE 1394 interface., 'wherein the computer interface is selected from the list comprising3. The system as recited in claim 1 , wherein:the module comprises a plurality of computer interfaces that are configured to facilitate communication of at least one device with the computer; and a PCI interface;', 'a USB interface;', 'an RS232 serial interface;', 'an RS422 serial interface;', 'a SATA interface;', 'an RS485 serial interface; and', 'an IEEE 1394 interface., 'wherein the computer interfaces comprise4. The system as recited in claim 1 , ...

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Номер записи: 31
12-09-2013 дата публикации

Semiconductor device and mobile terminal device

Номер: US20130238824A1
Автор: Satoshi Sasaki
Принадлежит: Renesas Mobile Corp

To provide a semiconductor device and a mobile terminal device capable of operating with stability. A semiconductor device includes an HSIC physical layer circuit fixedly connected to another semiconductor device through a bus line, a USB link control unit that operates with either a USB host function or a USB device function, and link-connects to the another semiconductor device, a nonvolatile storage unit that stores selection data, the selection data being used to select the USB function with which the USB link control unit operates, and a semiconductor substrate on which the HSCI physical control unit, the USB link control unit, and the nonvolatile storage unit are formed.

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Номер записи: 32
17-10-2013 дата публикации

MOBILE DEVICE, TRANSACTION SYSTEM INCLUDING THE MOBILE DEVICE, AND METHOD OF SIGNAL TRANSMISSION IN A MOBILE DEVICE

Номер: US20130275641A1
Автор: CHOU Yi-Fen, TSAI Irene
Принадлежит:

A mobile device includes a baseband module, an electronic card slot and a control module. A control unit of the control module is configured to control a switching unit to operate in a first transmission mode, such that the baseband module is able to communicate with an electronic card that is connected to the electronic card slot, based on a baseband signal received from the baseband module. The control unit is further configured to control the switching unit to operate in a second transmission mode, such that the control unit that executes an executable program is able to communicate with the electronic card that is connected to the electronic card slot. 1. A mobile device , comprising:a first baseband module;an electronic card slot to be connected to an electronic card; and a first input/output (I/O) port coupled to said first baseband module,', 'a second I/O port coupled to said electronic card slot,', 'a switching unit connected electrically to said first and second I/O ports,', 'a control unit coupled to said switching unit, and', 'a storage unit coupled to said control unit and having at least one executable program stored therein,, 'a control module including'}wherein said control unit is configured to control said switching unit to operate in a first transmission mode, in which said first I/O port and said second I/O port are electrically interconnected such that said first baseband module is able to communicate with the electronic card that is connected to said electronic card slot, based on a baseband signal received from said first baseband module via said first I/O port and said switching unit,wherein said control unit is further configured to control said switching unit to operate in a second transmission mode, in which said second I/O port and said control unit are electrically interconnected such that said control unit that executes said at least one executable program stored in said storage unit is able to communicate with the electronic card that ...

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Номер записи: 33
17-10-2013 дата публикации

Remote memory management when switching optically-connected memory

Номер: US20130275705A1
Автор: Abhirup CHAKRABORTY, Eugen Schenfeld
Принадлежит: International Business Machines Corp

A remote memory superpage is retained in a remote memory of the memory blade when reading the remote memory super page of the remote memory into a local memory.

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Номер записи: 34
31-10-2013 дата публикации

DATA TRANSMITTING DEVICE AND SERIAL ADVANCED TECHNOLOGY ATTACHMENT MODULE THEREOF

Номер: US20130290588A1
Автор: YANG MENG-LIANG
Принадлежит:

A serial advanced technology attachment (SATA) module includes a number of circuit boards and a number of SATA devices. Each of the circuit boards includes an expansion microchip. The expansion microchip includes an input terminal, an output terminal and an expansion terminal. The expansion microchips are electrically connected in series with the input terminal of one expansion microchip connecting to the expansion terminal of another expansion microchip. The input terminal of a front expansion terminal positioned at a first end of the expansion microchips is configured to connect to a SATA controller. Each of the SATA devices is electrically connected to the output terminal of one expansion microchip and configured to transmit data with the SATA controller by the corresponding expansion microchip. 1. A serial advanced technology attachment (SATA) module , comprising:a plurality of circuit boards, each of the circuit boards comprising an expansion microchip, each of the expansion microchips comprising an input terminal, an output terminal and an expansion terminal; the expansion microchips electrically connected in series with the input terminal of one expansion microchip connected to the expansion terminal of another expansion microchip, the input terminal of a front expansion microchip positioned at a first end of the expansion microchips configured to connect to a SATA controller; anda plurality of SATA devices, each of the SATA devices electrically connected to the output terminal of one expansion microchip and configured to transmit data with the SATA controller by the corresponding expansion microchip.2. The SATA module of claim 1 , further comprising a connector connected between the front expansion microchip and the SATA controller.3. The SATA module of claim 1 , wherein the SATA device is selected from one of the group consisting of a hard disk and a DVD drive.4. A data transmitting device claim 1 , comprising:a main board comprising a serial advanced ...

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Номер записи: 35
07-11-2013 дата публикации

SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

Номер: US20130297956A1
Автор: Tanada Yoshifumi
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A semiconductor device which can consume less power and a method for driving the semiconductor device can be provided. The semiconductor device includes a processor including a control device and an arithmetic unit, a memory device, an input/output device, and a plurality of bus lines which is a path for transmitting and receiving instructions, addresses, or data between the processor and the memory device, or the processor and the input/output device. A first memory storing each piece of information over the bus line is connected to each of the bus lines, and a second memory storing a status flag relating to information over the bus line is connected to the control device. 1. A semiconductor device comprising:a processor comprising a control device and an arithmetic unit;a plurality of bus lines electrically connected to the processor, each of the plurality of bus lines provided with a first memory comprising a first transistor comprising a first oxide semiconductor layer in a channel region; anda second memory electrically connected to the control device, the second memory comprising a second transistor comprising a second oxide semiconductor layer in a channel region.2. The semiconductor device according to claim 1 , wherein the plurality of bus lines include an address bus claim 1 , a data bus claim 1 , or an input/output bus.3. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer comprises In claim 1 , Ga claim 1 , and Zn.4. The semiconductor device according to claim 1 , further comprising a capacitor and a bit line claim 1 ,wherein a source of the first transistor is electrically connected to the bit line,wherein the bit line is electrically connected to one of the plurality of bus lines, andwherein a drain of the first transistor is electrically connected to the capacitor.5. An electronic device comprising the semiconductor device according to .6. A semiconductor device comprising:a processor comprising a control device ...

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Номер записи: 36
21-11-2013 дата публикации

SYSTEM AND METHOD FOR WIRELESS DOCKING UTILIZING A WIRELESS DOCKING PROFILE

Номер: US20130311693A1
Автор: de VEGT Rolf, Froelicher Jeffree S., Huang Xiaolong, Raveendran Vijayalakshmi R.
Принадлежит: QUALCOMM INCORPORATED

Various aspects of the present disclosure provide the concept of a wireless docking profile, which may be standardized across a number of vendors, such that a common standard defining minimum sets of peripherals can be shared by dockees and docking hosts to simplify connection setup and negotiation. Further aspects of the disclosure provide a docking procedure that may be utilized to establish a docking connection between the dockee and the docking host to utilize such a docking profile. Other aspects, embodiments, and features are also claimed and described. 1. A method operable at a docking host for docking with a dockee , comprising:generating a list of peripherals available for communication with the docking host;determining one or more supported docking profiles capable of being supported by the list of peripherals;transmitting an indication of the one or more supported docking profiles to the dockee; anddocking with the dockee to utilize a set of one or more peripherals communicatively coupled to the docking host corresponding to one of the supported docking profiles.2. The method of claim 1 , wherein the determining one or more docking profiles comprises:comparing the generated list of peripherals to a stored list of docking profiles, andpopulating a list of supported docking profiles, wherein each of the one or more supported docking profile comprises a minimum set of peripherals corresponding to a pre-configured use case.3. The method of claim 2 , wherein the docking with the dockee comprises selecting for the docking one of a public mode claim 2 , a private mode claim 2 , or a managed mode claim 2 ,wherein the public mode is a docking mode adapted for limiting access to docking host functionality,wherein the private mode is a docking mode adapted for providing full access to the docking host functionality, andwherein the managed mode is a docking mode adapted for providing managed access to the docking host functionality.4. A method operable at a docking ...

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Номер записи: 37
28-11-2013 дата публикации

APPARATUS AND METHOD FOR POLLING ADDRESSES OF ONE OR MORE SLAVE DEVICES IN A COMMUNICATIONS SYSTEM

Номер: US20130318267A1
Автор: Chapelle Donald William
Принадлежит: Lexmark International, Inc.

An address polling method and system for communicating unique slave address values to a master device over a shared bus. The method includes receiving a request signal from the master device requesting that a slave address from each slave device coupled to the data line be sent to the master; causing, in a serial manner, the data line to be placed in logic states corresponding to bit values in a first slave address; and upon the data line being placed in a logic state that is different from a corresponding bit value of the first slave address, determining that another slave device is placing its slave address on the data line and temporarily entering an idle state until such other slave device has finished communicating its slave address to the master device. 1. A method of communicating with a master over a shared bus having a data line , comprising:receiving, by a slave device, a request signal from a master requesting a slave address from each slave device coupled to the data line be sent to the master;controlling, by the slave device, the data line for the data line to be sequentially placed in logic states corresponding to bit values in a first slave address of the slave device; andupon the data line being placed in a logic state that is different from the corresponding bit value of the first slave address, temporarily entering an idle state until another slave device has completed sending a slave address thereof to the master.2. The method of claim 1 , further comprising entering the idle state when all bits of the first slave address have been placed on the data line.3. The method of claim 1 , wherein the controlling comprises driving the data line to a first logic state when the corresponding bit value of the first slave address is the first logic state claim 1 , and releasing the data line when the corresponding bit value of the first slave address is a second logic state.4. The method of claim 3 , wherein the first logic state is a logic zero state and the ...

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Номер записи: 38
28-11-2013 дата публикации

Wireless Communication Device and Method for Manufacturing Wireless Communication Device

Номер: US20130318273A1
Автор: Ma Liang, Qi Jie
Принадлежит:

The present invention provides a wireless communication device and a method for manufacturing a wireless communication device. The wireless communication device includes: an antenna; a main board, including a ground part, where the ground part is connected to the antenna; at least one matching network, connected to the ground part; a USB connector, including a shell and at least one first pin extending from the shell, where the at least one first pin is connected to the at least one matching network, and at least one first pin is one-to-one corresponding to at least one matching network. According to the present invention, a matching network may be connected between a pin of the USB connector of the wireless communication device and the ground part of the main board, and is configured to control wireless performance of an antenna radiation system of the wireless communication device. 121-. (canceled)22. A wireless communication device , comprising:an antenna;a main board, comprising a ground part, wherein the ground part is connected to the antenna;a matching network connected to the ground part; anda USB connector comprising a shell and a first pin extending from the shell, wherein the first pin is connected to the matching network and the first pin is one-to-one corresponding to the matching network.23. The wireless communication device according to claim 22 , wherein the main board further comprises a conductive part claim 22 , wherein the conductive part is independent of the ground part and is configured to connect the first pin to the matching network and wherein the conductive part is one-to-one corresponding to the matching network.24. The wireless communication device according to claim 22 , wherein the main board further comprises:a conductive part, wherein the conductive part is independent of the ground part, and is configured to connect a plurality of pins extending from the shell to a plurality of matching networks, wherein the conductive part is ...

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Номер записи: 39
05-12-2013 дата публикации

On-package input/output clustered interface having full and half-duplex modes

Номер: US20130322556A1
Автор: Randy B. Osborne, Stanley S. Kulick, Thomas P. Thomas
Принадлежит: Intel Corp

An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.

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Номер записи: 40
05-12-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130326097A1
Автор: Ami Yasuhiro, MORITA Toshihiro, Shimizu Kenichi
Принадлежит: RENESAS ELECTRONICS CORPORATION

A semiconductor device capable of implementing system configurations corresponding to various PCIe topologies is provided. A RAM stores one or more configuration registers that define function information of a PCIe device. A Link control unit decodes a request received from a PCIe host and outputs a decoded result to a CPU. The CPU reads a corresponding configuration register from the RAM based on the decoded result received from the Link control unit, and generates a response to the request and causes the Link control unit to transmit the response. Thus, system configurations corresponding to various PCIe topologies can be implemented. 1. A semiconductor device that implements a device configuring a topology of a serial interface bus comprising:a processor;a storage unit configured to store data to which reference is made by said processor; anda serial interface bus control unit configured to control a physical layer and a data link layer of said serial interface bus,said storage unit storing one or more configuration registers that define function information of said device,said serial interface bus control unit decoding a request received from a host and outputting a decoded result to said processor, andsaid processor reading a corresponding configuration register from said storage unit based on the decoded result received from said serial interface bus control unit, generating a response to said request and causing said serial interface bus control unit to transmit the response, setting a content of said configuration register in said serial interface bus control unit, and changing control of devices connected to said serial interface bus control unit based on said content of said configuration register set in said serial interface bus control unit.2. The semiconductor device according to claim 1 , whereinsaid serial interface bus is a PCIe bus.3. The semiconductor device according to claim 1 , whereinsaid processor changes a device that is to be implemented by ...

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Номер записи: 41
05-12-2013 дата публикации

METHOD FOR AUTOMATICALLY ALLOCATING ADDRESSES TO SIMILAR BUS USERS

Номер: US20130326099A1
Автор: Astor Christian, Schlottmann Eckart, Schmidt Ralph, Suprijadi Eko-Bono
Принадлежит:

In a method for allocating addresses in a CAN network having at least one master bus user and at least one slave bus user, the master bus user initiates the address allocation via a query message that is arranged for all bus users. Slave bus users which have already been assigned an address respond to this query message by transmitting a message at their assigned address. Slave bus users which have not yet been assigned an address take measures in response to this query message to be able to transmit on the bus without collisions, and transmit their serial number to the master bus user using these measures. At least the slave bus users which have not yet been assigned an address are assigned a suitable address by the master after receipt of the serial number, and use this address for further communication on the bus. 115-. (canceled)16. A method for allocating addresses in a communication bus system having at least one master bus user and slave bus users , comprising:initiating, by the master bus user, an address allocation via a query message sent to all bus users;responding, by each slave bus user which has already been assigned an address, to the query message by transmitting a message at the assigned address;responding, by each slave bus user which has not yet been assigned an address, to the query message by (i) taking measures to enable transmission on the bus without collisions, and (ii) transmitting a serial number of the slave bus user to the master bus user;assigning, by the master bus user, an address to each slave bus user which has not yet been assigned an address after receipt of the serial number, wherein the assigned address is used for further communication on the bus; andrecognizing, by the master bus user, when all slave bus users have successfully been assigned an address.17. The method as recited in claim 16 , wherein the measures taken by the slave bus user to enable transmission on the bus without collisions include one of (i) the use of the ...

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Номер записи: 42
12-12-2013 дата публикации

METHOD FOR CONFIGURATING CANOPEN NETWORK, METHOD FOR OPERATING SLAVE DEVICE OF CANOPEN NETWORK AND SYSTEM FOR CONTROLLING PLC DEVICE USING CANOPEN NETWORK

Номер: US20130332636A1
Автор: HAN SEUNG SHIN
Принадлежит: LSIS CO., LTD.

Disclosed are a method of configurating a CANopen network, a method of operating a slave device of the CANopen network, and a system for controlling a PC device using the CANopen network. The method of operating the slave device connected to the CANopen network includes creating a process data object for transmission, designating identifier information for the process data object, and transmitting the created process data object to a device corresponding to the designated identifier information. The identifier information includes a communication object identifier allowing another slave device or a master device connected to the CANopen network to receive the process data object. 1. A method of operating a slave device connected to a CANopen network , the method comprising:creating a process data object for transmission;designating identifier information for the process data object; andtransmitting the created process data object to a device corresponding to the designated identifier information,wherein the identifier information includes a communication object identifier allowing another slave device or a master device connected to the CANopen network to receive the process data object.2. The method of claim 1 , further comprising:setting a communication object identifier to receive a process data object by using the slave device; andreceiving a process data object from the another slave device by using the set communication object identifier by using the slave device.3. The method of claim 2 , wherein the another slave device includes a first slave device and a second slave device claim 2 , and a communication object identifier corresponding to the first slave device is identical to a communication object identifier corresponding to the second slave device.4. The method of claim 2 , wherein a communication object identifier for the master device is identical to a communication object identifier for the another slave device.5. A method of configurating a CANopen ...

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Номер записи: 43
12-12-2013 дата публикации

MOTOR VEHICLE HAVING A FLEXRAY BUS

Номер: US20130332637A1
Автор: Brunner Christian, Milbredt Paul
Принадлежит:

A motor vehicle has a FlexRay bus. Values for operating parameters are stipulated for the FlexRay bus. The value for at least one selected operating parameter is obtained from an optimization method in which, on the basis of prescribed messages to be transmitted via the FlexRay, a plurality of values for the at least one selected operating parameter have an Allocation—associated with these values—of slots to the prescribed messages provided for them according to a predetermined rule, and a predetermined sequence of the allocation is rated according to a predetermined criterion. 16-. (canceled)7. A motor vehicle comprising:a FlexRay bus operating according to operating parameters including a macrotick length, each operating parameter having a value stipulated for the FlexRay bus, whereinthe value for the macrotick length is obtained from an optimization in which, based on prescribed messages to be transmitted via the FlexRay bus, a plurality of possible macrotick length values are evaluated,for each possible macrotick length value, slots are allocated to the prescribed messages according to a predetermined rule to produce a potential sequence of allocated slots, andeach potential sequence of allocated slots is rated according to a predetermined criterion to optimize the macrotick length.8. The motor vehicle as claimed in claim 7 , whereinthe operating parameter also include a payload magnitude,the value for the payload magnitude is also obtained from the optimization, such that a plurality of possible macrotick length-payload magnitude value combinations are evaluated,for each possible value combination, slots are allocated to the prescribed messages according to the predetermined rule to produce a potential sequence of allocated slots, andeach potential sequence of allocated slots is rated according to the predetermined criterion to optimize the macrotick length and the payload magnitude.9. The motor vehicle as claimed in claim 8 , whereinthe payload magnitude is a ...

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Номер записи: 44
12-12-2013 дата публикации

HID OVER SIMPLE PERIPHERAL BUSES

Номер: US20130332643A1
Автор: Abzarian David, Aiyar Arvind R., Aull Randall E., Bhesania Firdosh K.
Принадлежит: MICROSOFT CORPORATION

In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system. 1. A system , comprising:a simple peripheral bus (SPB) configured for data communication between components in a computing system, the simple peripheral bus configured as an inter-integrated circuit (I2C); andperipheral sensors implemented with a human interface device (HID) SPB interface configured to interface an interrupt and I2C input/outputs, each of the peripheral sensors configured to interface a peripheral device with the computing system via the simple peripheral bus in an HID data format, and receive, from the peripheral device, an HID descriptor that defines device data elements exchanged between the peripheral device and the computing system.2. A system as recited in claim 1 , wherein a peripheral sensor is configured to interface at least the interrupt and I2C data and clock input/outputs between the peripheral device and the computing system.3. A system as recited in claim 1 , wherein a peripheral sensor is further configured to communicate extensibility data for a proprietary function of the peripheral device in the ...

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Номер записи: 45
12-12-2013 дата публикации

Computer system

Номер: US20130332925A1
Автор: Hirotaka Motai, Hitoshi Suzuki, Koji Adachi, Yasuhiro Tawara
Принадлежит: Renesas Electronics Corp

There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU# 0 through VCPU# 2 each operate different OS's. VCPU# 0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU# 0 regardless of an execution sequence stored in schedule register A. VCPU# 0 reinitializes a bus where an error occurred.

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Номер записи: 46
19-12-2013 дата публикации

Randomized testing within transactional execution

Номер: US20130339675A1
Автор: Christian Jacobi, Dan F. Greiner, Timothy J. Slegel
Принадлежит: International Business Machines Corp

Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.

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Номер записи: 47
26-12-2013 дата публикации

MASTER DEVICE THAT CHANGES DATA COMMUNICATION SPEED WHEN PREPARATION TO DRIVE MOTOR IS COMPLETED

Номер: US20130346659A1
Автор: Sasaki Taku
Принадлежит:

A first communication speed setting unit sets a data communication speed of data transmitted and received between the master device and the slave device during the period from the time when the master device is activated to the time when the preparation to drive the motors is completed, to a first communication speed. A second communication speed setting unit sets a data communication speed of data transmitted and received between the master device and the slave device when the preparation to drive the motor is completed, to a second communication speed lower than the first communication speed. A change notification unit notifies the change of the data communication speed from the first communication speed to the second communication speed to the slave device. 1. A master device that is connected to a slave device via a serial communication bus for carrying out data transmission and reception in order to control a motor connected via an inverter to a DC link part , which is connected to an alternating-current power source via a converter , comprising:a first communication speed setting unit configured to set a data communication speed of data transmitted and received between the master device and the slave device during the period from the time when the master device is activated to the time when the preparation to drive the motors is completed, to a first communication speed;a second communication speed setting unit configured to set a data communication speed of data transmitted and received between the master device and the slave device when the preparation to drive the motors is completed, to a second communication speed lower than the first communication speed; anda change notification unit configured to notify the change of the data communication speed from the first communication speed to the second communication speed to the slave device.2. The master device according to claim 1 , whereinthe second communication speed setting unit sets a data communication ...

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Номер записи: 48
16-01-2014 дата публикации

HUB DEVICES AND METHODS FOR INITIALIZING HUB DEVICE

Номер: US20140019658A1
Автор: CHEN Yi-Te, CHENG Wen-Hao, HO Chih-Long, HUANG Po-Ming, LIN Chun-Heng, Wu Kuo-Yu
Принадлежит:

A hub device includes a first chip, a second chip and an external memory device. The first chip includes at least a first upstream port and multiple first downstream ports. The second chip includes at least a second upstream port and multiple second downstream ports. The external memory device stores firmware data corresponding to the first chip and the second chip. One of the first downstream ports of the first chip is coupled to the second upstream port of the second chip to form a tiered hub. The first chip and the second chip are sequentially enabled and the first chip and the second chip sequentially load the corresponding firmware data. 1. A hub device , comprising:a first chip, comprising at least a first upstream port and a plurality of first downstream ports;a second chip, comprising at least a second upstream port and a plurality of second downstream ports; andan external memory device, storing firmware data corresponding to the first chip and the second chip,wherein one of the first downstream ports of the first chip is coupled to the second upstream port of the second chip to form a tiered hub, and the first chip and the second chip are sequentially enabled and the first chip and the second chip sequentially load the corresponding firmware data.2. The hub device as claimed in claim 1 , further comprising:a start-up circuit, for generating a first start-up signal to the first chip,wherein the first chip is enabled in response to the first start-up signal to read the firmware data corresponding to the first chip from the external memory device, and then to generate a second start-up signal to the second chip, andwherein the second chip is enabled in response to the second start-up signal to read the firmware data corresponding to the second chip from the external memory device.3. The hub device as claimed in claim 1 , further comprising:a start-up circuit, for generating a first start-up signal to the first chip; anda delay circuit, for delaying the first ...

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Номер записи: 49
16-01-2014 дата публикации

DETACHABLE FABRIC CARD

Номер: US20140019659A1
Автор: Avimor Uri, Gvili Yoav
Принадлежит: Tejas Networks Limited

The invention relates to a detachable switch fabric card. In one embodiment this is accomplished by a fabric element including at least one chip to to perform the switching between a plurality of fabric access card and two or more backplane connectors to match the backplane connectors. 1. A daughter fabric card , comprisinga fabric element including at least one chip to perform the switching between a plurality of fabric access card; andat least one backplane connectors to match the backplane connectors.2. The daughter fabric card of claim 1 , wherein the distance between every two connectors on the backplane is equal to the distance between every two connectors on the daughter fabric card.3. The daughter fabric card of claim 1 , wherein the distance between every two connectors on the card is constant.4. A network element claim 1 , comprising:a chassis having a housing and plurality of slots;a plurality of switch fabric cards, inserted within the plurality of slots to receive and transmit network traffic, wherein the plurality of switch fabric cards include at least one daughter fabric card; anda backplane, within the chassis and communicatively coupled to the plurality of switch fabric cards to transport the network traffic between the plurality of switch fabric cards.5. The network element of claim 4 , wherein the backplane includes a fabric end points which provides multiple paths between the pluralities of switch fabric cards.6. The network element of claim 4 , wherein the daughter card is detachable from the switch fabric card and also capable of functioning independently.7. The network element of claim 4 , wherein the combination of daughter cards on the switch fabric card allow using different configuration of fabric links arriving from the backplane enable to create a scalable configuration of switch fabric card.8. The network element of claim 4 , wherein the daughter card is capable of using a single fabric end point with only the basic link connectivity ...

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Номер записи: 50
13-02-2014 дата публикации

Data communication interface for an agricultural utility vehicle

Номер: US20140047152A1
Автор: FLOERCHINGER THOMAS, Peters Ole, Pickel Peter, Von Hoyningen-Huene Martin
Принадлежит: Deere & Company

A data communication interface for an agricultural utility vehicle, particularly an agricultural tractor, having an interface connector that can be connected either to a first data communication network or to a second data communication network by means of an electrically operatable changeover device, wherein the first data communication network is terminated at a line end associated with the interface connector by means of a disconnectable terminating resistor, and having a control unit that connects the interface connector to the first data communication network by means of appropriate operating of the changeover device exclusively when it infers the presence of a control signal that is provided for disconnecting the terminating resistor. 112161814162012222812161422. A data communication interface for an agricultural utility vehicle , particularly an agricultural tractor , having an interface connector () that can be connected either to a first data communication network () or to a second data communication network () by means of an electrically operatable changeover device () , wherein the first data communication network () is terminated at a line end () associated with the interface connector () by means of a disconnectable terminating resistor () , and having a control unit () that connects the interface connector () to the first data communication network () by means of appropriate operating of the changeover device () exclusively when it infers the presence of a control signal that is provided for disconnecting the terminating resistor ().216341836. The data communication interface as claimed in claim 1 , characterized in that the first data communication network () is a CAN data bus () and the second data communication network () is an Ethernet data network ().334. The data communication interface as claimed in claim 2 , characterized in that the CAN data bus () is in the form of an ISOBUS according to the ISO 11783 standard.436. The data communication ...

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Номер записи: 51
20-02-2014 дата публикации

EXPANSION MODULE AND CONTROL METHOD THEREOF

Номер: US20140052883A1
Автор: Sip Kim Yeung
Принадлежит: ACER INCORPORATED

An expansion module suitable for providing expansion functions to a mobile electronic device is provided. The expansion module includes a cloud device and a first expansion device. The cloud device includes a first expansion bus interface and a first network interface, wherein the cloud device provides the network function through the first network interface, and provides at least one first peripheral device through the first expansion bus interface. The first expansion device includes at least one second peripheral device, a second expansion bus interface, a third expansion bus interface and a second network interface, wherein the first expansion device provides the network function through the second network interface. The mobile electronic device detects the first network interface and the second network interface, such that the expansion module provides the network function to the mobile electronic device for use through the first network interface or the second network interface. 1. An expansion module for providing expansion functions for a mobile electronic device , comprising:a cloud device comprising a first expansion bus interface and a first network interface, wherein the cloud device provides network function through the first network interface, and provides at least one first peripheral device to the mobile electronic device for use through the first expansion bus interface or the first network interface; anda first expansion device, comprising at least one second peripheral device, a second expansion bus interface, a third expansion bus interface and a second network interface, the second expansion bus interface being coupled to the second peripheral device, the third expansion bus interface and the second network interface, and being used for coupling to the mobile electronic device, the third expansion bus interface being used for coupling to the first expansion bus interface and the first network interface of the cloud device, wherein the first ...

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Номер записи: 52
20-02-2014 дата публикации

Memory with Alternative Command Interfaces

Номер: US20140052934A1
Автор: Ian Shaeffer, Liji GOPALAKRISHNAN, Yi Lu
Принадлежит: RAMBUS INC

A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

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Номер записи: 53
20-02-2014 дата публикации

Data processing system and data processor

Номер: US20140053010A1
Автор: Junichi Nishimoto, Koji Yamada, Takuichiro Nakazawa, Toshihiro Hattori
Принадлежит: Renesas Electronics Corp

One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

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Номер записи: 54
27-02-2014 дата публикации

Method, apparatus, and system for speculative abort control mechanisms

Номер: US20140059333A1
Автор: Alexandre J. Farcy, Ilhyun Kim, Konrad K. Lai, Martin G. Dixon, Matthew Merten, Prakash Math, Rajesh S. Parthasarathy, Ravi Rajwar, Robert S. Chappell, Vijaykumar Kadgi
Принадлежит: Intel Corp

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

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Номер записи: 55
06-03-2014 дата публикации

DATA TRANSMISSION BETWEEN A PORTABLE ELECTRONIC DEVICE AND VARIOUS ACCESSORY DEVICES VIA RESPECTIVE DEDICATED CONNECTION INTERFACES

Номер: US20140068113A1
Автор: YANG Sheng-Long
Принадлежит:

A portable electronic device comprises: a detecting unit for generating a detecting signal based on detection of a signal level at a detection terminal of a multi-interface extension connector, which includes plural connection interfaces dedicated for data transmission and is matable with an accessory connector of an accessory device; and a processing unit operable to control the extension connector to allow data transmission with the accessory device via at least one connection interface that is determined to be compatible with the accessory device based on accessory information from the accessory device upon detecting, based on the detecting signal, that the extension connector is coupled with the accessory connector. 1. A portable electronic device capable of use with a plurality of different accessory devices , each of the accessory devices including an accessory connector , said portable electronic device comprising:a multi-interface extension connector matable with the accessory connector of each of the accessory devices, said multi-interface extension connector including a detection terminal, and a plurality of connection interfaces that are dedicated for data transmission, each of said connection interfaces being compatible with at least a corresponding one of the accessory devices;a detecting unit connected electrically to said multi-interface extension connector for detecting a signal level present at said detection terminal of said multi-interface extension connector to output a detecting signal corresponding to the signal level detected thereby; anda processing unit connected electrically to said detecting unit and said multi-interface extension connector, and receiving the detecting signal from said detecting unit, said processing unit being operable to determine, based on the detecting signal, whether said multi-interface extension connector is coupled with the accessory connector of one of the accessory devices; communicate with said one of the ...

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Номер записи: 56
06-03-2014 дата публикации

INFORMATION PROCESSING APPARATUS AND CONTROLLING METHOD

Номер: US20140068130A1
Автор: Fujii Yuichi, HORIUCHI Toshihiro, MATSUURA Tsutomu, Ukai Masaki
Принадлежит: FUJITSU LIMITED

A control circuit performs control to initialize a plurality of interface circuits connected to a communication circuit and each connected to each of a plurality of communication lines, and detects whether or not initialization of each of the interface circuits has been completed. When the control circuit detects that initialization of all of the interface circuits has been completed, the control circuit controls the communication circuit so as to start data communication via the interface circuits. 1. An information processing apparatus comprising:a communication circuit configured to perform data communication that is at least one of data transmission and data reception;a plurality of interface circuits connected to the communication circuit and each connected to each of a plurality of communication lines; anda control circuit configured to perform control to initialize the plurality of interface circuits, to detect whether or not initialization of each of the plurality of interface circuits has been completed, and to control the communication circuit so as to start data communication via the plurality of interface circuits when the control circuit detects that initialization of all of the plurality of interface circuits has been completed.2. The information processing apparatus according to claim 1 , whereinwhen initialization of one interface circuit of the plurality of interface circuits is not completed within a certain time period, the control circuit controls the communication circuit so as to start data communication via the plurality of interface circuits other than the one interface circuit.3. The information processing apparatus according to claim 1 , whereinthe control circuit stops the communication circuit in a state in which the communication circuit confirms an electrical connection to a communication partner, andwhen the control circuit detects that initialization of all of the plurality of interface circuits has been completed, the control circuit ...

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Номер записи: 57
20-03-2014 дата публикации

Method and server for managing redundant arrays of independent disks cards

Номер: US20140082245A1
Автор: Chih-Huang WU
Принадлежит: Hon Hai Precision Industry Co Ltd

In a method for managing redundant arrays of independent disks (RAID) cards and a server for executing the method, the server calculates a theoretical percentage of a load of each RAID card according to a number of the RAID cards, and loads an actual percentage of the load of each RAID card through a multi input output (MIO) interface, and detects peripheral component interconnect-express (PCI-E) bandwidth of each RAID card. When the load of each RAID card is unbalanced or the PCI-E bandwidth of the RAID card is saturated, the server transfers the load from a RAID card having a greater actual percentage of the load into a RAID card having a less actual percentage of the load, and transfers the load from a RAID card whose PCI-E bandwidth is saturated into a RAID card whose PCI-E bandwidth is unsaturated according to differential signals through the MIO interface.

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Номер записи: 58
27-03-2014 дата публикации

System architecture and method for communication between devices over backplane to reduce interface count

Номер: US20140086261A1
Автор: Gajendra Singh RANKA, Srinivas Rao
Принадлежит: Tejas Networks India Ltd

The present disclosure discloses a system architecture and method for reducing pin count on a backplane connecting plurality of devices. In an embodiment, the signals from the plurality of devices are multiplexed or mapped into time slots using a MapMux device. The MapMux device then sends the multiplexed or mapped signals over backplane on TDM bus. The MapMux device at the receiving end de-multiplexes or de-maps and sends the received signals to plurality of devices for further processing. The present disclosure allows a large number of signals to be passed between the devices through a single stream.

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Номер записи: 59
03-04-2014 дата публикации

CIRCUIT STRUCTURE

Номер: US20140094222A1
Автор: Lee Tien Chi, LI JENG LUNG
Принадлежит: GOTrust Technology Inc.

A circuit structure is utilized in circuit connection in a hand-held mobile communication device. The circuit structure is enabled to interconnect electrically a SIM (Subscriber Identity Module) card with a microSD (Secure Digital) memory card installed in the hand-held mobile communication device to enhance transmission of signal and data therebetween. 1. A circuit structure adapted to be implemented in circuit connection of hand-held mobile communication device , the circuit structure comprising:a first connection circuit fabricated on one side surface of a flexible printed circuit substrate and formed with a plurality of SIM-host contacts for electrically contacting insert slots of a SIM (Subscriber Identity Module) card respectively;a second connection circuit fabricated on the other side surface of the flexible printed circuit substrate and formed with a plurality of SIM-host contacts for electrically contacting the SIM card;a plurality of card-contact points for electrically connecting a microSD memory card; anda conduction circuit electrically interconnecting said first and second connection circuits.2. A circuit structure adapted to be implemented in circuit connection of hand-held mobile communication device , the circuit structure comprising:a first connection circuit fabricated on one side surface of a flexible printed circuit substrate and formed with a plurality of SIM-host-contacts for electrically contacting insert slots of a SIM (Subscriber Identity Module) card respectively, said first connection circuit further being formed with a plurality of card-contact points for electrically connecting a microSD memory card;a second connection circuit fabricated on the other side surface of the flexible printed circuit substrate and formed with said plurality of SIM-host contacts for electrically contacting the SIM card respectively, said second connection circuit further being formed with said plurality of card-contact points for electrically connecting said ...

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Номер записи: 60
03-04-2014 дата публикации

METHOD FOR ADDRESSING THE PARTICIPANTS OF A BUS SYSTEM

Номер: US20140095749A1
Автор: LAMBRECHTS Marc
Принадлежит: MELEXIS TECHNOLOGIES N.V.

A robust method for addressing each of the participants of a bus system comprising a control unit, and a bus and a plurality of addressable participants connected to the bus, comprising the steps of a) pre-selecting a first number of participants, b) selecting from the pre-selected participants a second number of participants, and c) assigning one or more addresses to them, and repeating the steps a) to c). The selection and pre-selection is based on current sources, specific threshold values, and measurement error. The bus system and addressable device (are also claimed. 1. A method for addressing each of the addressable participants of a bus system , the bus system comprising a control unit , a bus coupled to the control unit , and a plurality of addressable participants connected to the bus , the method comprising:a) pre-selecting at least a first number of addressable participants, the pre-selection comprising:feeding by each of the addressable participants not addressed so far of a pre-selection current, wherein all pre-selection currents flow through the bus towards the control unit,measuring of the pre-selection current flowing through the bus by each of these participants, andpre-selecting those participants that measure a pre-selection current lower than a first threshold;b) selecting from the pre-selected participants a second number of addressable participants, the second number being at least one, the selection comprising:feeding by each of the pre-selected participants of a selection current, wherein all selection currents flow through the bus towards the control unit;measuring by each of the pre-selected participants of the selection current flowing through the bus;selecting the second number of participants based on at least a second threshold, different from the first threshold;c) assigning a second number of addresses to each of the participants selected in step b);d) repeating steps a) to c) without the participants already being addressed, until ...

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Номер записи: 61
03-04-2014 дата публикации

Network interface controller with direct connection to host memory

Номер: US20140095753A1
Автор: Crupnicoff Diego, Graham Richard, Kagan Michael, Wilde Todd
Принадлежит: MELLANOX TECHNOLOGIES LTD.

A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration. 1. A network interface device for a host computer , the device comprising:a network interface, configured to transmit and receive data packets to and from a network;packet processing logic, configured to transfer data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer; and a first memory interface configured to be connected to the system memory;', 'a second memory interface, configured to be connected to a host complex of the host computer; and', 'switching logic, which alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration., 'a memory controller, comprising2. The device according to claim 1 , wherein the system memory includes dynamic random access memory (DRAM) claim 1 , and wherein the first and second memory interface are Double Data Rate (DDR) interfaces.3. The device according to claim 1 , wherein the switching logic is configured claim 1 , in the pass-through configuration claim 1 , as a transparent channel claim 1 , whereby the host complex accesses addresses in the system memory as though the system memory was connected ...

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Номер записи: 62
03-04-2014 дата публикации

HIGH-SPEED DATA TRANSMISSION INTERFACE CIRCUIT AND DESIGN METHOD OF THE SAME

Номер: US20140095756A1
Автор: Tsai Chih-Wei, WU Shu-Jung
Принадлежит: ACCTON TECHNOLOGY CORPORATION

A high-speed data transmission interface circuit used in a network switch device is provided. The high-speed data transmission interface circuit comprises a main circuit hoard, a connector and a daughter circuit board. The main circuit board comprises a transmission port interface module and a first wire. The transmission port interface module comprises a reduced pin extended attachment unit interface (RXAUI). The first wire connects the connector and the main circuit board. The daughter circuit board comprises a high definition multimedia interface (HDMI) module and a second wire. The HDMI module is connected to an external network device through a HDMI signal wire. The second wire connects the connector and the HDMI module. The transmission port interface module communicates with the external network device through the connector and the daughter board. 1. A high-speed data transmission interlace circuit , used in a network switch device , comprising: a transmission port interlace module, further comprising a reduced pin extended attachment unit interface (RXAUI); and', 'a first wire, wherein a first impedance of the first wire is ±10% of 100 ohms;, 'a main circuit board, comprisinga connector, connected to the main circuit board through the first wire, wherein an insertion loss range of the connector at a working frequency of at least 3.125 GHz is smaller than or equal to 0.2 dB and more than 0 dB; and a high definition multimedia interface (HDMI) module, connected to an external network device by a HDMI signal wire; and', 'a second wire, used to connect the connector and the HDMI module, wherein a second impedance of the second wire is ±10% of 100 ohms;, 'a daughter circuit board, comprisingwherein by the first wire, the transmission port interface module outputs an output data to the external network device and receives an input data from the external network device through the connector, the second wire of the daughter circuit board and the HDMI module.2. The ...

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Номер записи: 63
03-04-2014 дата публикации

Memory sharing across distributed nodes

Номер: US20140095810A1
Автор: John G. Johnson, Kathirgamar Aingaran, Paul N. Loewenstein, Zoran Radovic
Принадлежит: Oracle International Corp

A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, load and store instructions that target the mirrored memory portion of a sharer node are trapped, and store instructions that target the shared memory portion of a home node are trapped. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no “dirty” data is transferred between sharer nodes. As a result, the failure of one node will not cause the failure of another node or the failure of the entire system.

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Номер записи: 64
05-01-2017 дата публикации

Connecting circuitry and computing system having the same

Номер: US20170003709A1
Автор: Ming-Chun Lee, Syu-Siang Lee, Zh-Wei Zhang
Принадлежит: Wistron Corp

A connecting circuitry is disclosed. The connecting circuitry is coupled to a storage device, a first motherboard and a second motherboard, and controlled by a first control signal and a second control signal to switch over to a first mode, to a second mode and to a third mode. The connecting circuitry includes a first exchanging unit; a second exchanging unit; and a first multiplexing unit, electrical connected to the first exchanging unit and the second exchanging unit; wherein the first mode is the storage device being only accessed by the first motherboard, the second mode is the storage device being only accessed by the second motherboard, and the third mode is the storage device being accessed by both the first motherboard and the second motherboard.

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Номер записи: 65
05-01-2017 дата публикации

MEMORY CARD CONNECTOR FOR ELECTRONIC DEVICES

Номер: US20170003717A1
Автор: Ling Yun, Srivastava Amit Kumar, Yang Feng, YEW Teong Guan
Принадлежит: Intel Corporation

In one example a electronic device comprises a body, a receptacle in the body comprising an opening to receive a memory card, wherein the receptacle comprises a first set of connectors configured to connect with pins on a memory card configured in accordance with a first standard and a second set of connectors configured to connect with pins on a memory card configured in accordance with a second standard. Other examples may be described. 1. An electronic device , comprising:a body; a first set of connectors configured to connect with pins on a memory card configured in accordance with a first standard; and', 'a second set of connectors configured to connect with pins on a memory card configured in accordance with a second standard., 'a receptacle in the body comprising an opening to receive a memory card, wherein the receptacle comprises2. The electronic device of claim 1 , wherein:the first set of connectors is disposed on a first side of the receptacle; andthe second set of connectors is disposed on a second side of the receptacle.3. The electronic device of claim 2 , wherein:the first set of connectors is configured to connect with pins on a secure digital (SD) memory card; andthe second set of connectors is configured to connect with pins on a universal flash storage (UFS) memory card.4. The electronic device of claim 3 , wherein at least one connector in the first set of connectors is connected to at least one connector in the second set of connectors.5. The electronic device of claim 4 , further comprising:a coupling sensor to detect when a memory card is inserted into the receptacle.6. The electronic device of claim 5 , wherein the coupling sensor comprises at least one of:a mechanical switch; oran electrical circuit.7. The electronic device of claim 5 , further comprising logic claim 5 , at least partly including hardware logic claim 5 , to: determine a type of memory card inserted into the receptacle; and', 'initiate a communication with the memory card., ...

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Номер записи: 66
05-01-2017 дата публикации

Add-on device and server using the same

Номер: US20170004105A1
Автор: Bo Tian, Kang Wu
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

An add-on device includes an interface, an identification module, an enable module, and a function module. The identification module is used to output an identification signal. The enable module is used to receive an enable signal. The function module is used to process signals. The enable module activates the function module to operate when the enable module receives the enable signal.

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Номер записи: 67
07-01-2016 дата публикации

Computer System and A Computer Device

Номер: US20160004652A1
Автор: Glickman Jonathan
Принадлежит:

A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system. 1. A computer system comprising:a first board having an I/O controller hub including a main communication chipset;a common bus; and a memory operative to host a Sibling operating system, and', 'at least one CPU coupled to said memory, said Sibling board configured without a Sibling chipset;, 'a plurality of Sibling boards coupled to said first board by said common bus, each of the Sibling boards comprising,'}wherein at least one of the plurality of Sibling boards functions as a processing unit of said first board, and at least one of said Sibling boards is coupled to and shares said I/O controller hub.2. The computer system of claim 1 , wherein said I/O controller hub includes a main network device; and wherein at least one of said Sibling boards is coupled to and shares said main network device.3. The computer system of claim 2 , wherein at least one of said Sibling boards is directly coupled to and shares said main network device claim 2 , and is without an external I/O circuit.4. The computer system of claim 1 , wherein said common bus physically and electrically connects the plurality of said Sibling boards to said first board.5. The computer system of claim 1 , wherein said common bus couples the plurality of ...

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Номер записи: 68
07-01-2016 дата публикации

USB DEVICE AND METHOD FOR PROCESSING DATA BY USB DEVICE

Номер: US20160004658A1
Автор: CHEN Kefeng
Принадлежит:

A universal serial bus device receives a data packet from a host. The universal serial bus device includes a first virtual device, a second virtual device and a data-assigning device. The data-assigning device performs a determination operation, including: transmitting data corresponding to the a first logical address to the first virtual device, when the first logical address is the same as an address of the first virtual device wherein the data corresponding to the first logical address and the first logical address are recorded in the data packet; transmitting data corresponding to the a second logical address to the first virtual device, when the first logical address is the same as an address of the first virtual device wherein the data corresponding to the second logical address and the second logical address are recorded in the data packet. 1. A universal serial bus device , receiving a data packet from a host , the universal serial bus device comprising:a first virtual device;a second virtual device; anda data-assigning device, coupled to the first virtual device and the second virtual device, and performing a first determination operation,wherein the first determination operation comprising:transmitting data, which corresponds to a first logical address and is recorded in the data packet, to the first virtual device, when the first logical address, which is recorded in the data packet, is the same as the address of the first virtual device, such that the first virtual device communicates with the host; andtransmitting data, which is corresponding to a second logical address and is recorded in the data packet, to the second virtual device, when the second logical address, which is recorded in the data packet, is the same as the address of the second virtual device, such that the second virtual device communicates with the host.2. The universal serial bus device as claimed in claim 1 , wherein the data-assigning device is a virtual root Hub claim 1 , the ...

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Номер записи: 69
07-01-2016 дата публикации

MEMORY SYSTEM AND DATA STORAGE DEVICE

Номер: US20160004660A1
Автор: LEE Hak Dae
Принадлежит:

A memory system includes a first memory device and a second memory device suitable for outputting and receiving signals through first and second sub input/output lines, respectively, a controller suitable for outputting and receiving signals to and from the first memory device and the second memory device, through a main input/output line and a selection unit suitable for electrically coupling the main input/output line with one of the first and the second sub input/output lines, through which an activated one of the first memory and the second memory devices outputs and receives signals. 1. A memory system comprising:a first memory device and a second memory device suitable for outputting and receiving signals through a first and a second sub input/output lines, respectively;a controller suitable for outputting and receiving signals to and from the first memory device and the second memory device, through a main input/output line; anda selection unit suitable for electrically coupling the main input/output line with one of the first and the second sub input/output lines, through which an activated one of the first memory and second memory devices outputs and receives signals.2. The memory system according to claim 1 , wherein the selection unit selects the one of the first and second sub input/output lines to be electrically coupled with the main input/output line claim 1 , based on a first select signal for activating the first memory device and a second select signal for activating the second memory device.3. The memory system according to claim 1 , wherein the controller outputs a control signal or data claim 1 , or receives data from the activated one of the first memory and second memory devices claim 1 , through the main input/output line and the one of the first and second sub input/output lines.4. The memory system according to claim 1 , wherein the selection unit is electrically coupled with the controller through the main input/output line claim 1 , ...

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Номер записи: 70
07-01-2016 дата публикации

WIRELESS TRANSMISSION AND VIDEO INTEGRATED APPARATUS

Номер: US20160004662A1
Автор: CHANG Nai-Chien
Принадлежит:

A wireless transmission and video integrated apparatus includes a hub module, a video module and a wireless module. The hub module includes a hub unit, a first expansion interface, a second expansion interface and a transmission interface. The video module includes a first connection interface, an image processing unit, an image acquisition unit and a microphone unit. The video module is electrically connected to the first expansion interface of the hub module through the first connection interface. The wireless module includes a second connection interface, a wireless communication unit and an antenna unit. The wireless module is electrically connected to the second expansion interface of the hub module through the second connection interface. The video module and the wireless module are integrated as a whole through the hub module, and then electrically connected to an electronic apparatus through the transmission interface to help with the assembly. 1. A wireless transmission and video integrated apparatus assembled to an electronic apparatus and electrically connected to a main board of the electronic apparatus , the wireless transmission and video integrated apparatus comprising:a video module having a first circuit board, an image acquisition unit, an image processing unit, a microphone unit and a first connection interface, the image acquisition unit electrically connected to the first circuit board and acquiring an image signal, the image processing unit electrically connected to the first circuit board and the image acquisition unit, the image processing unit processing the image signal with an analog-to-digital conversion, the microphone unit electrically connected to the first circuit board and acquiring an audio signal, the first connection interface electrically connected to the first circuit board, the image processing unit and the microphone unit, the first connection interface receiving and outputting the image signal and the audio signal;a wireless ...

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Номер записи: 71
04-01-2018 дата публикации

METHODS FOR INTELLIGENT LOAD BALANCING AND HIGH SPEED INTELLIGENT NETWORK RECORDERS

Номер: US20180004435A1
Автор: Allen Maxwell John, Coddington Anthony, Donnelly Stephen Frank, Earl David William
Принадлежит: Endace Technology Limited

A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device. 131-. (canceled)32. A high speed intelligent network recording system for recording a plurality of flows of network packets into a computer network , the high speed intelligent network recording system comprising: an enclosure,', 'a backplane printed board (PCB) mounted in the enclosure, and', 'a plurality of controller cards mounted in the enclosure coupled to the backplane PCB;', 'and, 'a controller unit having'} an enclosure,', 'a backplane printed board (PCB) mounted in the enclosure,', 'a plurality of drive trays mounted in the enclosure coupled to the backplane PCB, and', 'a plurality of pluggable storage drives coupled to each of the plurality of drive trays;, 'a storage unit coupled in communication to the controller unit, the storage unit including'}wherein each controller card in the controller unit includes a first microcomputer coupled in communication with a plurality of storage devices in the storage unit.33. The high speed intelligent network recording system of claim 32 , whereinthe enclosure of the controller unit us a 1U sized computer enclosure and the storage unit is inclusively between a 3U sized computer enclosure and a 6U sized computer enclosure.34. The high speed intelligent network recording system of claim 32 , further comprising:a high speed network switch coupled between the controller unit and the storage unit to couple the controller unit and the storage unit in communication together.35. The high speed ...

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Номер записи: 72
04-01-2018 дата публикации

Front End Traffic Handling In Modular Switched Fabric Based Data Storage Systems

Номер: US20180004615A1
Автор: Breakstone Jason, Cannata James Scott, Long Christopher R.
Принадлежит: Liqid Inc.

Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage system is provided that includes storage drives each comprising a PCIe interface, and configured to store data and retrieve the data stored on associated storage media responsive to data transactions received over a switched PCIe fabric. The data storage system includes processors configured to each manage only an associated subset of the storage drives over the switched PCIe fabric. A first processor is configured to identify first data packets received over a network interface associated with the first processor within a network buffer of the first processor as comprising a storage operation associated with at least one of the plurality of storage drives managed by a second processor, and responsively transfer the first data packets into a network buffer of the second processor. 1. A data storage system , comprising:a plurality of processors configured to each manage an associated subset of a plurality of storage devices coupled over a Peripheral Component Interconnect Express (PCIe) fabric; receive data packets comprising storage operations over a network interface associated with the at least one processor;', 'identify when ones of the storage operations are directed to at least one of the plurality of storage devices managed by a target processor; and', 'transfer over the PCIe fabric associated data packets comprising the ones of the storage operations into a network buffer of the target processor for handling of the ones of the storage operations by the target processor., 'at least one processor configured to2. The data storage system of claim 1 , comprising:the target processor configured to process the associated data packets up a network stack of the target processor for handling of the ones of the storage operations.3. The data storage system of claim 1 , wherein the network buffer of the target processor comprises a layer 2 network ...

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Номер записи: 73
04-01-2018 дата публикации

METHOD AND SYSTEM FOR VALID MEMORY MODULE CONFIGURATION AND VERIFICATION

Номер: US20180004658A1
Автор: Bucaro Edward Alfonso
Принадлежит: ORACLE INTERNATIONAL CORPORATION

Aspects of the present disclosure involve a system and method for verifying and validating accurate memory module placement on a printed circuit board. In one embodiment, the printed circuit board is configured to include actuating elements that can be used to verify correct memory module location placement on the printed circuit board. In another embodiment, the actuating elements can be used to validate accurate memory module placement. The actuating elements can be in the form of buttons that may be depressed and configured to trigger light emitting diodes (LEDs) that correspond to the slots on the printed circuit board. 1. An apparatus comprising:a first memory slot supported on a printed circuit board, the first memory slot configured to receive a first memory module;a second memory slot supported on the printed circuit board, the second memory slot configured to receive a second memory module;a third memory slot supported on the printed circuit board, the third memory slot configured to receive a third memory module;a first indicating element supported on the printed circuit board proximate the first memory slot;a second indicating element supported on the printed circuit board proximate the second memory slot;a third indicating element supported on the printed circuit board proximate the third memory slot;at least one actuating element in electrical communication with the first indicating element, the second indicating element, and the third indicating element, the actuation of the at least one actuating element causing activation of the first indicating element in association with a first memory configuration where the first memory module is in the first memory slot or causing the activation of the second indicating element and the third indicating element in association with a second memory configuration providing more computer memory than the first memory configuration, and where the second memory module is in the second memory slot and the third memory ...

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Номер записи: 74
04-01-2018 дата публикации

EFFICIENT LOW COST ON-DIE CONFIGURABLE BRIDGE CONTROLLER

Номер: US20180004685A1
Автор: BHATT SUKETU U., Chellappan Satheesh, PAPPU LAKSHMINARAYANA
Принадлежит:

Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value. 1. An apparatus comprising:an interface comprising a line-state output; anda state machine to set the line-state output to a value that is one of: a single-ended-zero-state (SE0-state) value, a J-state value, or a K-state value,wherein the state machine is to have a line-state state that is one of: a reset state, a full-speed-detect state, a low-speed-detect state, a host-drive-SE0 state, a device-response-K state, a device-response-SQ state, a host-response-JK state, an idle-done state, or a full-speed-low-speed-reset state; andwherein the value of the line-state output is based at least in part upon the line-state state.2. The apparatus of claim 1 , wherein the interface is a first interface claim 1 , and the apparatus comprising:a first translation circuitry to process a transaction received on the first interface and to generate a transaction for a second interface.3. The apparatus of claim 2 , comprising:a second translation circuitry to process a transaction received on the second interface and to generate a transaction for the first interface.4. The apparatus of claim 1 ,wherein the state machine is to set the line-state output to the SE0-state value when the line-state state is any of: the host- ...

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Номер записи: 75
04-01-2018 дата публикации

REMOTE MEMORY OPERATIONS

Номер: US20180004687A1
Автор: Guim Bernat Francesc, Kumar Karthik, Ranganathan Narayan, Vogt Pete D., Willhalm Thomas
Принадлежит:

An extension of node architecture and proxy requests enables a node to expose memory computation capability to remote nodes. A remote node can request execution of an operation by a remote memory computation resource, and the remote memory computation resource can execute the request locally and return the results of the computation. The node includes processing resources, a fabric interface, and a memory subsystem including a memory computation resource. The local execution of the request by the memory computation resource can reduce latency and bandwidth concerns typical with remote requests. 1. A node in a network of nodes , comprising:a fabric interface to couple to the network of nodes;a processor to execute operations at the node; anda memory subsystem with a memory computation resource separate from the processor;wherein the memory subsystem to receive a request from a remote node processor for a memory computation, and in response to the request, to perform the computation locally at the memory subsystem and send the result of the computation to the remote node.2. The node of claim 1 , wherein the node comprises a node of a server in a data center.3. The node of claim 1 , wherein the fabric interface comprises a host fabric interface (HFI) to couple to a host switching fabric.4. The node of claim 1 , wherein the fabric interface is to receive the request tunneled through a fabric protocol claim 1 , and to tunnel the result to the remote node through the fabric protocol.5. The node of claim 1 , wherein the memory subsystem further comprises a memory controller claim 1 , the memory controller to register a capability of the memory computation resource with the fabric interface.6. The node of claim 5 , wherein the fabric interface is to expose the capability of the memory computation resource to other nodes in the network.7. The node of claim 1 , wherein the fabric interface is to expose a universal unique identifier (UUID) corresponding to a capability of the ...

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Номер записи: 76
04-01-2018 дата публикации

LOAD REDUCED NONVOLATILE MEMORY INTERFACE

Номер: US20180004688A1
Автор: CHUNG Emily, Hady Frank T., VERGIS George
Принадлежит:

A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both. 1. A system , comprising:a group of nonvolatile memory (NVM) devices;a storage controller coupled to the group of NVM devices, the storage controller to manage reading and writing to the NVM devices; anda data buffer coupled between the group of NVM devices and the storage controller on a data bus, the data buffer to re-drive data signals on the data bus, and synchronize data signals to a clock signal.2. The system of claim 1 , wherein the storage controller is to first send a command signal to the group of NVM devices claim 1 , and next send a control signal to the data buffer claim 1 , wherein the control signal is to trigger the data buffer to transfer the data signals to the group of NVM devices.3. The system of claim 1 , wherein the NVM devices are to operate in a burst mode claim 1 , to transfer data over 2N cycles claim 1 , and the data buffer is to operate to transfer data over N cycles claim 1 , wherein the storage controller is to issue consecutive commands to the data buffer to cause the data buffer to operate for 2N cycles in response to the consecutive commands.4. The system of claim 3 , wherein the data buffer is to eliminate stall cycles internally to produce 2N cycles of continuous data transfer in response to the consecutive commands.5. The system of claim 1 , wherein the data buffer comprises a host interface to the storage controller and a memory interface to the group of NVM devices claim ...

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Номер записи: 77
04-01-2018 дата публикации

RISER CARD

Номер: US20180004695A1
Автор: CHANG Kai, CHEN Chih-Yu, Cheng Chia-Feng, Chu Wei-Yi
Принадлежит:

An apparatus having a first interface of a first type supporting a plurality of data ports, a second interface of a second type supporting at least a portion of the plurality data ports, and a third interface of the second type. The apparatus also including a switching module coupled to a control port of the first interface and configured for selectably coupling the plurality of data ports to at least one of the second interface and the third interface based on a signal at the control port. 1. An apparatus , comprising:a first interface of a first type supporting a plurality of data ports;a second interface of a second type supporting at least a portion of the plurality data ports;a third interface of the second type; anda switching module coupled to a control port of the first interface and configured for selectably coupling the plurality of data ports to at least one of the second interface and the third interface based on a signal at the control port.2. The apparatus of claim 1 , wherein the signal indicates one of a first routing mode and a second routing mode for the switching module.3. The apparatus of claim 2 , wherein the first routing mode comprises routing the signals for the plurality of data ports at the first interface to the second interface claim 2 , and wherein the second routing mode comprising routing signals for a portion of the plurality of data ports to the second interface and routing signals for a remaining portion of the plurality of data ports to the third interface.4. The apparatus of claim 2 , wherein the plurality of data ports comprises four data ports claim 2 , and wherein the portion of the plurality of data ports comprises a first two of the plurality of data ports.5. The apparatus of claim 1 , wherein the first interface comprises a U.2 interface and wherein each of the second interface and the third interface comprises a M.2 interface.6. The apparatus of claim 1 , wherein each of the second interface and third interface are ...

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Номер записи: 78
04-01-2018 дата публикации

METHOD FOR DETERMING ROLE OF ELECTRONIC DEVICE AND ELECTRONIC DEVICE THEREOF

Номер: US20180004696A1
Автор: LEE Woo-Kwang, LIM Ho-Yeong, SHIN Dong-Rak, SON Dong-Il
Принадлежит:

The present disclosure provides methods and devices for determining a role of an electronic device for an external electronic device upon connecting the electronic device with the external electronic device. An electronic device may comprise a first circuit configured to provide first power to a first external electronic device, a second circuit configured to receive second power from the first external electronic device or a second external electronic device, a connector configured to be electrically connected to the first external electronic device or the second external electronic device, the connector including a configuration pin configured to selectively connect to the first circuit or the second circuit based on a first connection setting, and a processor configured to control the connector, the processor may be further configured to determine a second connection setting to be used for connection of the configuration pin to the first external electronic device or the second external electronic device based on, at least, context information related to the electronic device, context information related the first external electronic device, or context information related to the second external electronic device and to selectively connect the configuration pin to the first circuit or the second circuit based on the second connection setting. 1. An electronic device , comprising:a first circuit configured to provide first power to a first external electronic device;a second circuit configured to receive second power from the first external electronic device or a second external electronic device;a connector configured to be electrically connected to the first external electronic device or the second external electronic device, the connector including a configuration pin configured to selectively connect to the first circuit or the second circuit based on a first connection setting; anda processor configured to control the connector, the processor further ...

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Номер записи: 79
04-01-2018 дата публикации

CONTROL SYSTEM AND CONTROL METHOD THEREOF

Номер: US20180004697A1
Автор: HUANG Li-Hong, YUAN Jiang-Tao
Принадлежит:

A control system includes a first expander board and a second expander board. The first expander board selects a first data segment from a first data signal according to a first clock signal. The second expander board is electrically connected to the first expander board. The second expander board is configured to receive the first data segment and the first clock signal of the first expander board. The second expander board selects a second data segment from a second data signal according to a second clock signal and sequentially outputs the first data segment and the second data segment. The sequentially output form of the first data segment and the second data segment from the second expander board is a serial data signal. 1. A control system , comprising:a first expender board configured to select a first data segment from a first data signal according to a first clock signal; anda second expender board coupled to the first expender board and configured to receive the first data segment and the first clock signal and select a second data segment from a second data signal according to a second clock signal and sequentially output the first data segment and the second data segment;wherein sequentially output form of the first data segment and the second data segment from the second expender board is a serial data signal.2. The control system according to claim 1 , wherein the first data segment is in a first time interval claim 1 , the second data segment is in a second time interval claim 1 , the second expander board outputs the first data segment in the first time interval and outputs the second data segment in the second time interval.3. The control system according to claim 1 , wherein the first data segment comprises a first identification code claim 1 , the second data segment comprises a second identification code.4. The control system according to claim 3 , further comprising:a first hardware component corresponding to the first identification code;a ...

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Номер записи: 80
04-01-2018 дата публикации

NETWORK-ACCESSIBLE DATA VOLUME MODIFICATION

Номер: US20180004698A1
Автор: Arumugam Nachiappan, Brouwer Pieter Kristian, Olson Marc Stephen, Rajavenkateswaran Vijay Prasanth, Thacker Michael, Tripathi Arpit, Wei Danny
Принадлежит:

A user can set or modify operational parameters of a data volume stored on a network-accessible storage device in a data center. For example, the user may be provided access to a data volume and may request a modification to the operational parameters of the data volume. Instead of modifying the existing data volume, the data center can provision a new data volume and migrate data stored on the existing data volume to the new data volume. While the data migration takes place, the existing data volume may block input/output (I/O) requests and the new data volume may handle such requests instead. If a request is received for data not yet migrated to the new data volume, then the new data volume prioritizes a migration of the requested data. 1. A computer-implemented method comprising: receiving a request to modify a first data volume;', 'causing a computing device to provision a second data volume responsive to the request;', 'causing the second data volume to execute input/output (I/O) requests in place of the first data volume before all data chunks from the first data volume are stored on the second data volume;', 'causing the second data volume to retrieve and store a plurality of the data chunks stored in the first data volume;', 'receiving a request from a host system for a first data chunk;', 'determining that the first data chunk is not stored in the second data volume;', 'causing prioritization of a transfer of the first data chunk over a second data chunk in the plurality of data chunks responsive to the determination that the first data chunk is not stored in the second data volume; and', 'causing the second data volume to transmit the first data chunk to the host system once the first data chunk is retrieved from the first data volume., 'as implemented by one or more computing devices configured with specific executable instructions,'}2. The computer-implemented method of further comprising causing the first data volume to execute one or more I/O requests ...

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Номер записи: 81
07-01-2021 дата публикации

Stacked Semiconductor Device Assembly in Computer System

Номер: US20210004340A1
Автор: Best Scott C.
Принадлежит:

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device. 1. A stacked semiconductor device assembly , comprising: a master interface;', 'a channel master circuit coupled to the master interface;', 'a slave interface;', 'a channel slave circuit coupled to the slave interface;', 'a memory core coupled to the channel slave circuit; and', 'selection circuitry configured to determine whether the IC chip is to communicate data using the channel master circuit or the channel slave circuit., 'a plurality of stacked integrated circuit (IC) chips, each IC chip further comprising2. The stacked semiconductor device assembly of claim 1 , wherein for one of the plurality of stacked IC chips claim 1 , the selection circuitry receives an input claim 1 , and is configured to determine whether the one of the plurality of stacked IC chips is to communicate data using the channel master or slave circuit based on a voltage level of the input.3. The stacked semiconductor device assembly of claim 2 , wherein the one of the plurality of IC chips is physically offset from other IC chips in the stacked semiconductor device assembly.4. The stacked semiconductor device assembly of claim ...

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Номер записи: 82
07-01-2021 дата публикации

APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPLICATIONS

Номер: US20210004347A1
Автор: LANKA Narasimha, Pasdast Gerald S., Seshan Lakshmipriya, Wu Zuoguo
Принадлежит: Intel Corporation

Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met. 1. A device comprising:a link including multiple lanes to connect the device to a receiving device, the multiple lanes including first lanes and second lanes; and receive original data comprising first bits and second bits to be transmitted in a new clock cycle, wherein the first bits are to be transmitted via the first lanes, respectively, and the second bits are to be transmitted via the second lanes, respectively;', 'determine whether a first criterion associated with the first bits is met;', 'determine whether a second criterion associated with the second bits is met; and', 'determine whether to transmit an inverted version of the original data via the multiple lanes based, at least in part, on determining whether the first criterion is met and whether the second criterion is met., 'circuitry coupled to the link, the circuitry to2. The device of claim 1 , wherein:determining that the first criterion is met is to include determining that a majority of the first lanes have respective previous bit values that are required to transition based on at least some of the first bits; anddetermining that the second criterion ...

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Номер записи: 83
02-01-2020 дата публикации

MANAGING ACCELERATORS IN APPLICATION-SPECIFIC INTEGRATED CIRCUITS

Номер: US20200004702A1
Автор: Carey James E., Chen Jim C., Schardt Paul E., Thompson Lance G.
Принадлежит:

An accelerator manager monitors usage of accelerators by one or more computer programs, and generates a historical log from the monitored usage. The accelerator manager determines from the historical log which of the plurality of accelerators to implement on one or more application-specific integrated circuits. Each application-specific integrated circuit can include implemented accelerators and accelerator images that can be deployed to external programmable devices. Once one or more accelerators are implemented on one or more application-specific integrated circuits, the accelerator manager can direct one of the application-specific integrated circuits to provide a needed accelerator. An application-specific integrated circuit can provide the needed accelerator either using an accelerator implemented in the application-specific integrated circuit, or by deploying an accelerator image in the application-specific integrated circuit to an external programmable device. 1. An apparatus comprising:at least one processor;a memory coupled to the at least one processor;a plurality of accelerators in a plurality of programmable devices coupled to the at least one processor; andan accelerator manager residing in the memory and coupled to the at least one processor, the accelerator manager monitoring usage of the plurality of accelerators by at least one computer program and generating from the monitored usage a historical log, wherein the historical log comprises a list of computer programs and when each computer program called each of the plurality of accelerators, and determining from the historical log which of the plurality of accelerators to implement on a first application-specific integrated circuit based on at least one threshold.2. The apparatus of wherein each of the plurality of programmable devices comprises an Open Coherent Accelerator Processor Interface (OpenCAPI) coupled to the at least one processor.3. The apparatus of wherein the historical log further ...

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Номер записи: 84
02-01-2020 дата публикации

Adaption Apparatus, And Device Identification Method And Apparatus

Номер: US20200004709A1
Автор: Feng Liu, Jiangtao YANG, Jianjun Xu
Принадлежит: Huawei Technologies Co Ltd

Example adaption apparatus are described. An example adaption apparatus includes a first USB interface and a second USB interface. A power signal of the first USB interface is electrically connected to a power signal of the second USB interface. A first channel configuration signal of the first USB interface is electrically connected to an ID signal of the second USB interface using a first resistor. The ID signal of the second USB interface is electrically connected to the power signal of the second USB interface using a second resistor. A resistance value of the first resistor meets a criterion followed by a first device to identify a UFP device according to the USB Type-C protocol. A sum of the resistance value of the first resistor and a resistance value of the second resistor meets a criterion followed by the first device to identify a DFP device according to the USB Type-C protocol.

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Номер записи: 85
02-01-2020 дата публикации

MEMORY WITH ALTERNATIVE COMMAND INTERFACES

Номер: US20200004714A1
Автор: Gopalakrishnan Liji, Lu Yi, Shaeffer Ian
Принадлежит:

A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose. 1. (canceled)2. A memory device for storing and retrieving data responsive to memory commands , the memory device comprising:a memory core having sub-banks of memory banks;a first command port;a second command port; and in a first mode, to disable the first command port and to provide access to the sub-banks of memory banks responsive to the memory commands from the second command port; and', 'in a second mode, to disable the second command port and to provide access to the sub-banks of memory banks responsive to the memory commands from the first command port., 'control logic coupled to the memory core and selectively coupled to the first command port and the second command port, the control logic3. The memory device of claim 2 , the memory core further comprising a first data queue and a second data queue coupled to the sub-banks of memory banks.4. The memory device of claim 3 , wherein the control logic activates only one of the first data queue and the second data queue in the first mode and both of the first data queue and the second data queue in the second mode.5. The memory device of claim 2 , further comprising a mode register to store a value that sets one of the first mode and the second mode.6. The memory device of claim 2 , the control logic to access each and every one of the sub-banks of memory banks responsive to the commands received on either of the first command port and the second command port.7. The memory device of claim 2 , wherein the memory ...

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Номер записи: 86
02-01-2020 дата публикации

Information processing apparatus, control method of information processing, and non-transitory computer-readable storage medium for storing program

Номер: US20200004715A1
Автор: Hidetoshi Matsumura
Принадлежит: Fujitsu Ltd

An information processing apparatus includes: a programmable circuit including a plurality of reconfigurable regions in which logic is reconfigurable; and a processor coupled to the programmable circuit, the processor being configured to (a): execute an extraction process that includes extracting, from the plurality of reconfigurable regions, one or more installable regions in which any of a plurality of first circuits is installable, (b): execute a first determination process that includes determining whether each of a plurality of second circuits is installable in a first reconfigurable region, (c): execute a second determination process that includes determining a first installation circuit and a first installation region based on the determination executed by the first determination process, and (d): execute an installation process that includes installing the first installation circuit determined by the second determination process in the first installation region determined by the second determination process.

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Номер записи: 87
02-01-2020 дата публикации

PCIE SWITCH FOR AGGREGATING A LARGE NUMBER OF ENDPOINT DEVICES

Номер: US20200004716A1
Автор: COSBY DAVID W., Hinkle Jonathan R., Vojnovich Theodore B.
Принадлежит:

An apparatus includes a root port for coupling to a root complex, and a plurality of endpoint ports for coupling to endpoint devices, wherein each endpoint port is associated with a function number. A downstream buffer queues transaction layer packets (TLPs) received from the root port, wherein each TLP in the downstream buffer is directed to an endpoint port associated with the identified function number. An upstream buffer queues TLPs received from each endpoint port, and directs the queued TLPs to the root port. A method includes associating a function number with each endpoint port of a switch, wherein each endpoint port is adapted for coupling to an endpoint device. The method further includes receiving a first TLP from a root complex, identifying a function number within the first TLP, and directing the first TLP to an endpoint device through the endpoint port associated with the identified function number. 1. A method , comprising:associating a function number with each of a plurality of endpoint ports of a switch, wherein each endpoint port is adapted for coupling to an endpoint device via a serial communication link;receiving a first transaction layer packet from a root complex;identifying a function number within the first transaction layer packet; anddirecting the first transaction layer packet to an endpoint device through the endpoint port that is associated with the identified function number.2. The method of claim 1 , further comprising:advertising the available function numbers to the root complex; andthe root complex storing endpoint data identifying, for each of the plurality of endpoint ports, the associated function number.3. The method of claim 1 , further comprising:prior to providing the first transaction layer packet to an endpoint device, setting the function number in the first transaction layer packet equal to zero.4. The method of claim 1 , further comprising:the endpoint port that is associated with the identified function number ...

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Номер записи: 88
13-01-2022 дата публикации

UTILIZING INTEGRATED LIGHTING TO STREAMLINE SYSTEM SETUP AND DEBUGGING

Номер: US20220012204A1
Автор: Berhane Abaynesh, Kirkpatrick Peter E., Kurbanova Kholida, Lam Huong Thi
Принадлежит:

A system setup data structure comprising cable couplings between a first plurality of ports of a first electrical component and a second plurality of ports of a second electrical component is received. A first illumination component associated with a first port of the first plurality of ports and a second illumination component associated with a second port of the second plurality of ports are activated, wherein the first port and the second port correspond to one of the cable couplings included in the system setup data structure. A determination is made as to whether a cable has been coupled to the first port and the second port. In response to determining that the cable has been coupled to the first port and the second port, a visual indication is provided that the cable has been correctly coupled at the first electrical component and the second electrical component. 1. A system comprising:a first storage unit comprising a first plurality of ports, wherein the first storage unit comprises a first plurality of storage devices having erase blocks that are directly mapped; and receive a system setup data structure comprising cable couplings between the first plurality of ports of the first storage unit and the second plurality of ports of the second storage unit;', 'activate a first illumination component associated with a first port of the first plurality of ports and a second illumination component associated with a second port of the second plurality of ports, wherein the first port and the second port correspond to one of the cable couplings included in the system setup data structure;', 'determine whether a cable has been coupled to the first port and the second port; and', 'provide a visual indication that the cable has been correctly coupled at the first storage unit and the second storage unit upon determining that the cable has been coupled to the first port and the second port., 'a second storage unit comprising a second plurality of ports, wherein the ...

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Номер записи: 89
05-01-2017 дата публикации

ELECTRONIC DEVICE

Номер: US20170005138A1
Автор: KIM Kyung-Wan
Принадлежит:

An electronic device includes a semiconductor memory. The semiconductor memory includes a line-type first electrode layer having at least one protrusion and extending in a first direction, and a plurality of memory elements, each memory element including a variable resistance layer and a second electrode, the variable resistance layers of the memory elements being disposed over a top surface and two parallel side surfaces of the protrusion, respectively, the two parallel side surfaces of the protrusion being arranged in the first direction, the second electrodes of the memory elements being disposed over the variable resistance layers of the memory elements, respectively. 1. An electronic device comprising a semiconductor memory , the semiconductor memory comprising:a line-type first electrode layer having at least one protrusion and extending in a first direction; anda plurality of memory elements, each memory element comprising a variable resistance layer and a second electrode, the variable resistance layers of the memory elements being disposed over a top surface and two parallel side surfaces of the protrusion, respectively, the two parallel side surfaces of the protrusion being arranged in the first direction, the second electrodes of the memory elements being disposed over the variable resistance layers of the memory elements, respectively.2. The electronic device of claim 1 , wherein the first electrode comprises:a line-type body part extending in the first direction; anda plurality of protrusions arranged over the line-type body part so as to be spaced away from each other at predetermined intervals in the first direction.3. The electronic device of claim 2 , wherein each of the variable resistance layers of the memory elements that are disposed over the two parallel side surfaces of the protrusion further includes an additional portion extending along a top surface of the line-type body part in the first direction by a predetermined width from a ...

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Номер записи: 90
03-01-2019 дата публикации

TECHNOLOGIES FOR OPTIMIZING RESUME TIME FOR MEDIA AGNOSTIC USB

Номер: US20190004819A1
Автор: Davidson Tal, Glik Michael, Levy Elad, Maevsky Miron, Wielicki Rafal
Принадлежит:

A method for operating a media agnostic universal serial bus (MAUSB) device includes a compute device having a link connection manager, a USB manager, and a state manager. The compute device establishes a link with a MAUSB device and a session with the MAUSB device. Subsequently to receipt of a sleep command for the compute device, the compute device transitions to a sleep state and terminates the link with the MAUSB device while keeping intact the session with the MAUSB device. The compute device transitions back to an active state in response to receipt of a wake command for the compute device. The compute device sends a wake request to the MAUSB device. If the MAUSB device responds to the wake request with an acceptance, then the compute device reestablishes the previous session with the MAUSB device. If instead an error is received, the compute device terminates the session. 1. A compute device for operating a media agnostic universal serial bus (MAUSB) device , the compute device comprising:a link connection manager to establish a link with the MAUSB device;a universal serial bus (USB) manager to establish an MAUSB session with the MAUSB device;an enumeration manager to perform an enumeration the MAUSB device; anda state manager to receive a sleep command for the compute device,wherein the USB manager is further to send, in response to receipt of the sleep command, a sleep request to the MAUSB device,wherein the link connection manager is further to terminate the link with the MAUSB device in response to receipt of the sleep command,wherein the USB manager is further to maintain the MAUSB session after termination of the link with the MAUSB device, wherein to maintain the MAUSB session comprises to maintain the enumeration of the MAUSB device,wherein the state manager is further to (i) transition, in response to receipt of the sleep command, the compute device into a sleep state; (ii) receive a wake command for the compute device, and (iii) transition, in ...

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Номер записи: 91
04-01-2018 дата публикации

MAINTENANCE SYSTEM, AND COMPUTER READABLE RECORDING MEDIUM STORING A MAINTENANCE PROGRAM

Номер: US20180005104A1
Автор: KAWAGUCHI Tomoya
Принадлежит:

A maintenance system includes an IC card unique to a service person, a general purpose mobile terminal device, an image forming apparatus as a maintenance target, and an authentication server. In the general purpose mobile terminal device, the maintenance authentication processing unit (a) obtains IC card identification information from the IC card using an IC card reader, (b) transmits the obtained IC card identification information to the authentication server, (c) receives user rank information corresponding to the IC card identification information from the authentication server, and (d) transmits the received user rank information to the image forming apparatus using a peripheral device interface. The image forming apparatus receives the user rank information from the general purpose mobile terminal device, determines a usage permission range corresponding to the received user rank information, and permits usage of a maintenance function restricted to the usage permission range. 1. A maintenance system , comprising:an IC card unique to a service person;a general purpose mobile terminal device;an image forming apparatus as a maintenance target; andan authentication server;wherein the general purpose mobile terminal device comprises:a wireless communication unit capable of communicating with the authentication server;a peripheral device interface capable of communicating with the image forming apparatus;an IC card reader configured to obtain IC card identification information of the IC card; anda maintenance authentication processing unit;wherein the maintenance authentication processing unit (a) obtains the IC card identification information using the IC card reader, (b) transmits the obtained IC card identification information to the authentication server using the wireless communication unit, (c) receives user rank information corresponding to the IC card identification information from the authentication server, and (d) transmits the received user rank ...

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Номер записи: 92
02-01-2020 дата публикации

SCHEDULER AND SIMULATOR FOR A AREA-EFFICIENT, RECONFIGURABLE, ENERGY-EFFICIENT, SPEED-EFFICIENT NEURAL NETWORK SUBSTRATE

Номер: US20200005155A1
Автор: Datta Pallab, Modha Dharmendra S.
Принадлежит:

Mapping of logical neural cores to physical neural cores is provided. In various embodiments, a neural network description describing a plurality of logical cores is read. A plurality of precedence relationships is determined among the plurality of logical cores. Based on the plurality of precedence relationships, a directed acyclic graph among the plurality of logical cores is generated. By breadth first search of the directed acyclic graph, a schedule is generated. The schedule maps each of the plurality of logical cores to one of a plurality of physical cores at one of a plurality of time slices. Execution of the schedule is simulated. 1. A method comprising:reading a neural network description describing a plurality of logical cores;determining a plurality of precedence relationships among the plurality of logical cores;based on the plurality of precedence relationships, generating a directed acyclic graph among the plurality of logical cores;by breadth first search of the directed acyclic graph, generating a schedule, the schedule mapping each of the plurality of logical cores to one of a plurality of physical cores at one of a plurality of time slices.2. The method of claim 1 , further comprising:executing the plurality of logical cores by the plurality of physical cores according to the schedule.3. The method of claim 1 , wherein each of the plurality of logical cores comprises a crossbar template claim 1 , the crossbar template comprising synaptic weights for the logical core.4. The method of claim 3 , wherein generating the schedule comprises maximizing crossbar template reuse for the plurality of physical cores.5. The method of claim 1 , wherein generating the schedule comprises minimizing scheduling delay.6. The method of claim 1 , wherein the plurality of logical cores number more than the plurality of physical cores.7. The method of claim 2 , wherein said executing buffering input activations at each of the plurality of physical cores.8. The method of ...

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Номер записи: 93
04-01-2018 дата публикации

MULTI-MODE USB INTERFACE

Номер: US20180005207A1
Автор: Laucks Joseph, Wade Jeremy
Принадлежит: Square, Inc.

A merchant device has a USB interface that includes an ID pin and a voltage pin. When the merchant device receives an oscillating signal at the ID pin, it connects the voltage pin to a power supply of the merchant device. The merchant device also includes a download switch coupled to the ID pin. When it is desired to reprogram a device connected by the USB interface, the download switch provides a programming voltage to the ID pin. 1. A system for providing multiple functionalities over a single pin of a USB interface , comprising: a merchant terminal USB interface comprising a merchant terminal voltage pin, a merchant terminal ground pin, a plurality of merchant terminal data pins, and a merchant terminal ID pin;', 'a merchant terminal power supply, wherein the merchant terminal power supply provides a merchant terminal supply voltage to a plurality of components of the merchant terminal;', 'a merchant terminal power supply switch coupled to the merchant terminal voltage pin and the merchant terminal power supply, wherein the merchant terminal power supply switch is configured to couple the merchant terminal voltage pin to the merchant terminal power supply when an enabling signal is received at a merchant terminal power supply switch input;', 'a merchant terminal oscillator input circuit coupled to the merchant terminal ID pin, wherein the merchant terminal oscillator input circuit is configured to cause the enabling signal to be provided to the merchant terminal power supply switch input when an oscillating signal is received at the merchant terminal ID pin; and', 'a download switch coupled to the merchant terminal ID pin, wherein the download switch is configured to selectively provide a programming voltage to the merchant terminal ID pin, and wherein the programming voltage is based on the merchant terminal supply voltage; and, 'a merchant terminal, comprising a customer terminal USB interface comprising a customer terminal voltage pin, a customer terminal ...

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Номер записи: 94
05-01-2017 дата публикации

METHOD AND APPARATUS FOR CHARGING ELECTRONIC DEVICE WITH USB CONNECTION

Номер: US20170005495A1
Автор: CAO Longbo, Qu Dongsheng, YANG Yuanhuai
Принадлежит:

A method and an apparatus for charging an electronic device with USB connection are provided. The method comprises, at the side of the first electronic device which is charged by a second electronic device, the steps of: receiving a power supply at a first voltage level from the second electronic device (); detecting whether there is data communication on the USB connection (), if there is no data communication on the USB connection, transmitting a message to the second electronic device to request for being charged at a second voltage level which is greater than the first voltage level (); and receiving a power supply at the second voltage level from the second electronic device. 115-. (canceled)16. A method for charging a first electronic device by a second electronic device with a connection which can also provide data communication thereon , comprising , at the side of the first electronic device , the steps of:receiving a power supply at a first voltage level from the second electronic device;detecting whether there is data communication on the connection,if there is no data communication on the connection, transmitting a message to the second electronic device to request for being charged at a second voltage level which is greater than the first voltage level; andreceiving a power supply at the second voltage level from the second electronic device.17. The method according to claim 16 , wherein the connection is in conformity with the universal serial bus (USB) protocol.18. The method according to claim 17 , further comprising detecting there is no data communication on the USB connection when the USB_DP and USB_DN pins of a USB port of the second electronic device are shorted.19. The method according to claim 17 , wherein the first voltage level is 5V DC and the second voltage level is 12V DC.20. The method according to claim 17 , further comprising transmitting the message via the USB_DP pin of a USB port of the first electronic device.21. The method ...

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Номер записи: 95
03-01-2019 дата публикации

SECURING A HOST MACHINE AGAINST DIRECT MEMORY ACCESS (DMA) ATTACKS VIA EXPANSION CARD SLOTS

Номер: US20190005273A1
Автор: Mortensen James L., Taylor Kenneth C.
Принадлежит:

Approaches for securing a host machine against security attacks conducted using Direct Memory Access (DMA). Platform firmware does not enable bus mastering during PCI bus enumeration. When the platform firmware determines that an expansion card has been plugged into an expansion card slot of the host machine, the platform firmware determines whether the expansion card slot has been approved by a user of the host machine for permitting Direct Memory Access (DMA) with the host machine. Unless the expansion card slot has been determined to be approved by the user for permitting Direct Memory Access (DMA) with the host machine, the platform firmware does not allow drivers that might enable DMA to connect to the device and does not grant permission to the expansion card slot and any upstream bridges to conduct Direct Memory Access (DMA) with the host machine. 1. One or more non-transitory computer-readable storage mediums storing one or more sequences of instructions for securing a host machine comprising platform firmware , which when executed , cause: the platform firmware forbearing enablement of bus mastering during PCI bus enumeration,', 'upon the platform firmware determining that an expansion card has been plugged into an expansion card slot of the host machine, the platform firmware determining whether the expansion card slot has been approved by a user of the host machine for permitting Direct Memory Access (DMA) with the host machine, and', 'unless the expansion card slot has been determined to be approved by the user for permitting Direct Memory Access (DMA) with the host machine, forbearing a grant of permissions to the expansion card slot to conduct Direct Memory Access (DMA) with said host machine., 'the platform firmware securing the host machine against security attacks conducted using Direct Memory Access (DMA) by2. The one or more non-transitory computer-readable storage mediums of claim 1 , wherein execution of the one or more sequences of instructions ...

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Номер записи: 96
07-01-2021 дата публикации

SIGNAL TRANSMISSION CIRCUIT

Номер: US20210006248A1
Автор: MAO WEN-YI, TAN Li-Li
Принадлежит:

A signal transmission circuit is provided. A tri-state logic circuit includes an enabling terminal, an input terminal and an output terminal, and is conducted and unconducted when the enabling terminal is at a high and a low state respectively. A pull-up circuit pulls up a voltage level of the output terminal. A first and a second multiplexers respectively output an enabling signal and an output signal to the enabling terminal and the input terminal according to a first status of a selection signal and respectively output a high state signal according to a second status of the selection signal. A selection circuit generates the selection signal having the first status when the voltage level is not larger than a first threshold value, having the second status after the voltage level is larger than the first threshold value and having the first status afterwards. 1. A signal transmission circuit , comprising:a tri-state logic circuit comprising an enabling terminal, an input terminal and an output terminal and configured to be conducted when the enabling terminal is at a high state and unconducted when the enabling terminal is at a low state;a pull-up circuit electrically coupled to the output terminal and configured to pull up a voltage level of the output terminal;a first multiplexer and a second multiplexer respectively configured to output an enabling signal to the enabling terminal and output an output signal having a low state to the input terminal according to a first status of a selection signal, and respectively configured to output a high state signal to the enabling terminal and output the high state signal to the input terminal according to a second status of the selection signal opposite to the first status; anda selection circuit configured to generate the selection signal having the first status when the voltage level of the output terminal is not larger than a first threshold value, generate the selection signal having the second status during a ...

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Номер записи: 97
07-01-2021 дата публикации

IDENTIFICATION NUMBER NUMBERING METHOD AND MULTIPOINT COMMUNICATION SYSTEM

Номер: US20210006429A1
Автор: Shen Yi-Jhou, Wu Zhone-Yang
Принадлежит: E Ink Holdings Inc.

The present invention discloses an identification number numbering method and a multipoint communication system. The identification number numbering method includes the following steps: sending an identification number packet to a multipoint communication bus by a master device; receiving the identification number packet via the multipoint communication bus, and temporarily storing an identification number according to the identification number packet by a first slave device; changing a voltage level of a master device control output pin of the master device; and when the first slave device determines that a voltage level of a first control input pin coupled to the master device control output pin is correspondingly changed, updating a first slave device identification number of the first slave device according to the identification number. 1. An identification number numbering method for a multipoint communication system , comprising:sending an identification number packet by a master device to a multipoint communication bus;receiving the identification number packet via the multipoint communication bus by a first slave device, and temporarily storing an identification number by the first slave device according to the identification number packet;changing a voltage level of a master device control output pin of the master device; andwhen the first slave device determines that a voltage level of a first control input pin coupled to the master device control output pin is correspondingly changed, updating a first slave device identification number of the first slave device by the first slave device according to the identification number.2. The identification number numbering method according to claim 1 , further comprising:after the first slave device updates the first slave device identification number, sending a first confirmation packet to the multipoint communication bus and a second slave device by the first slave device; andchanging a voltage level of a first ...

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Номер записи: 98
03-01-2019 дата публикации

Remote Hardware Acceleration

Номер: US20190007334A1
Автор: DOSHI Kshitij A., Guim Bernat Francesc, LEUNG JOHN CHUN KWOK, Ranganathan Narayan, Schmisseur Mark A.
Принадлежит: Intel Corporation

A host fabric interface (HFI) apparatus, including: an HFI to communicatively couple to a fabric; and a remote hardware acceleration (RHA) engine to: query an orchestrator via the fabric to identify a remote resource having an accelerator; and send a remote accelerator request to the remote resource via the fabric. 1. An HFI apparatus , comprising:a fabric interface to communicatively couple to a fabric; and query an orchestrator via the fabric to identify a remote resource having an accelerator; and', 'send a remote accelerator request to the remote resource via the fabric., 'a remote hardware acceleration (RHA) engine to2. The HFI apparatus of claim 1 , wherein querying the orchestrator comprises receiving an interface format for the remote accelerator request.3. The HFI apparatus of claim 1 , wherein the HFI apparatus is on-chip with at least one core.4. The HFI apparatus of claim 1 , further providing a local bus interface to communicatively couple the HFI apparatus to a host.5. The HFI apparatus of claim 1 , wherein the remote hardware acceleration (RHA) engine is to:register the accelerator with an orchestrator;receive via the HFI a remote accelerator access request from a remote node;perform an accelerated action according to the remote accelerator access request; andsend a result to the remote node via the HFI.6. The HFI apparatus of claim 5 , wherein the result comprises an ACK.7. The HFI apparatus of claim 5 , wherein the result comprises a payload.8. A computing system comprising a processor claim 1 , a memory claim 1 , and the HFI of .9. A system on a chip comprising a processor and the HFI of .10. An integrated circuit comprising a processor and the HFI of .11. A multi-chip package comprising a processor claim 1 , support circuitry claim 1 , and the HFI of .12. One or more tangible claim 1 , non-transitory computer-readable storage mediums having stored thereon instructions for providing a remote hardware acceleration (RHA) engine to:query an ...

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Номер записи: 99
03-01-2019 дата публикации

Data cable, electronic system and method for transmitting mipi signal

Номер: US20190007647A1
Автор: Jian Xiong, YUAN Wen
Принадлежит: Mediatek Singapore Pte Ltd

A data cable, electronic system and method for transmitting MIPI signals are provided. The electronic system includes a first electronic device configured to generate at least one pair of MIPI (Mobile Industry Processor Interface) differential signals, and a data cable and a second electronic device connected to the first electronic device via the data cable. The data cable is configured to receive the at least one pair of MIPI differential signals from the first electronic device, and perform impedance matching and shielded grounding processing on the at least one pair of MIPI differential signals, and transmit the processed at least one pair of MIPI differential signals to the second electronic device.

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Номер записи: 100