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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 6682. Отображено 100.
23-02-2012 дата публикации

Card type peripheral apparatus and host apparatus

Номер: US20120047290A1
Автор: Junko Nagata, Kenichi Nakanishi, Kenichi Satori, Naohiro Adachi, Noriyuki Hosoe, Tamaki Konno
Принадлежит: Sony Corp

A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.

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Номер записи: 1
01-03-2012 дата публикации

Method for finding starting bit of reference frames for an alternating-parity reference channel

Номер: US20120054388A1
Автор: Howard RIDEOUT
Принадлежит: Avalon Microelectronics Inc

The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.

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Номер записи: 2
15-03-2012 дата публикации

Use of pci express for cpu-to-cpu communication

Номер: US20120066430A1
Автор: Braden Michael Cooper, Stephen Dale Cooper
Принадлежит: Individual

CPUs that generate PCIe auxiliary signals and changing clock signals nevertheless communicate with each other using PCIe owing to PCIe switch assemblies that are disposed in the communication paths to isolate and terminate the auxiliary signals from reaching other CPUs and to isolate changing clock signals, communicating with each other using a fixed clock derived from one of the changing clock signals. Also, the CPUs directly access the memories of CPUs to which they wish to write data so that data is directly written from one CPU memory to another without store-and-forward operations being needed in the network.

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Номер записи: 3
24-05-2012 дата публикации

Configuring an input/output adapter

Номер: US20120131232A1
Автор: John R. Oberly, III, Sean T. Brownlow
Принадлежит: International Business Machines Corp

A computer-implemented method includes initializing a driver associated with an input/output adapter in response to receiving an initialize driver request from a client application. The input/output adapter may be initialized to enable adapter capabilities of the input/output adapter to be determined. The computer-implemented method also includes determining the adapter capabilities of the input/output adapter and determining slot capabilities of a slot associated with the input/output adapter. The computer-implemented method further includes setting configurable capabilities of the input/output adapter based on the adapter capabilities and the slot capabilities.

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Номер записи: 4
21-06-2012 дата публикации

Semiconductor device

Номер: US20120159020A1
Автор: Daijiro Harada, Takashi Utsumi
Принадлежит: Renesas Electronics Corp

There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

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Номер записи: 5
19-07-2012 дата публикации

Computer architectures using shared storage

Номер: US20120185725A1
Автор: David D. Bettger, Dennis L. Kuehn, Kevin A. Stone, Marc A. Peters
Принадлежит: Boeing Co

A method includes providing a persistent common view of a virtual shared storage system. The virtual shared storage system includes a first shared storage system and a second shared storage system, and the persistent common view includes information associated with data and instructions stored at the first shared storage system and the second shared storage system. The method includes automatically updating the persistent common view to include third information associated with other data and other instructions stored at a third shared storage system in response to adding the third shared storage system to the virtual shared storage system.

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Номер записи: 6
16-08-2012 дата публикации

Method and apparatus for plug and play, networkable iso 18000-7 connectivity

Номер: US20120207141A1
Автор: John Peter Norair
Принадлежит: Blackbird Technology Holdings Inc

A device may comprise a Universal Serial Bus (USB) interface and a wireless interface operable to communicate in accordance with the ISO 18000-7 standard. The device may be operable to receive a command via the USB interface and transmit the command via the wireless interface. The device may be operable to receive data via the wireless interface and transmit the data via the USB interface. A form factor of the USB device may be such that it can be plugged directly into a USB port without any external cabling between the USB device and said USB port.

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Номер записи: 7
27-09-2012 дата публикации

Configurable health-care equipment apparatus

Номер: US20120246375A1
Автор: Ian K. Edwards, Jon R. Salvati, Raymond A. Lia, Robert J. Wood, Robert L. Vivenzio, Scott A. Martin, Thaddeus J. Wawro
Принадлежит: Welch Allyn Inc

An apparatus, system and method for providing health-care equipment in a plurality of customizable configurations. A configuration includes a selection and arrangement of health-care equipment modules that each provide specialized support for the provision of health care, including the measurement of physiological parameters. Various types of configurations include those adapted to be mounted upon a desk top or a wall surface, or adapted for wheel mounting or hand-carriable mobile configurations.

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Номер записи: 8
03-01-2013 дата публикации

System and method for improving ecc enabled memory timing

Номер: US20130007320A1
Автор: Saya Goud Langadi
Принадлежит: Texas Instruments Inc

A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

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Номер записи: 9
04-07-2013 дата публикации

BRIDGE BETWEEN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE AND A UNIVERSAL SERIAL BUS 3.0 DEVICE

Номер: US20130173838A1
Автор: Chen Shao-Hung, Hsu Shih-Min
Принадлежит: ETRON TECHNOLOGY, INC.

A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane. 1. A bridge between a Peripheral Component Interconnect Express interface and a Universal Serial Bus 3.0 device , the bridge comprising:a Peripheral Component Interconnect Express (PCI-E) interface supporting at least two lanes for coupling to a host, wherein each lane of the at least two lanes provides a highest data transmission speed;an Extensible Host Controller Interface (xHCI) coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface; anda Universal Serial Bus (USB) 3.0 root hub comprising a first controller and a second controller, wherein the first controller and the second controller are used for controlling data transmission of four ports;wherein a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.2. The bridge of claim 1 , wherein the first controller is used for controlling data transmission of two ports of the four ports claim 1 , and the second controller is used for controlling ...

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Номер записи: 10
15-08-2013 дата публикации

Inter-component communication including slave component initiated transaction

Номер: US20130212311A1
Автор: Mikal C. Hunsaker, Ricardo E. James, Su Wei Lim
Принадлежит: Intel Corp

Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed. A component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. Other embodiments may be disclosed or claimed.

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Номер записи: 11
29-08-2013 дата публикации

Unified System Area Network And Switch

Номер: US20130227193A1
Автор: Jayanta Kumar Maitra
Принадлежит: RJ Intellectual Properties LLC

A network switch, based on the PCI Express protocol, is disclosed. The switch includes a processor, local memory and a plurality of non-transparent bridges. By configuring the non-transparent bridges appropriately, the network switch can facilitate a number of different communication mechanisms, including TCP/IP communication between servers, server clusters, and virtualized I/O device utilization. For example, the network switch may configure the non-transparent bridges so as to have access to the physical memory of every server attached to it. It can then move data from the memory of any server to the memory of any other server. In another embodiment, the network switch is connected to an I/O device, and multiple servers are given access to that I/O device via virtualized connections.

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Номер записи: 12
14-11-2013 дата публикации

Multi-mode adapter

Номер: US20130304942A1
Автор: Gregg J. Golembeski, Jason Yew, Shyam S. Toprani
Принадлежит: Apple Inc

An adapter can be used to connect a portable electronic device to an accessory in instances where the portable electronic device and the accessory have incompatible connectors. The adapter provides two connectors, one compatible with the portable electronic device and the other compatible with the accessory. The adapter has several modes of operation. The portable electronic device selects the appropriate mode of operation for the adapter once it receives information about the accessory connected to the adapter. The portable electronic device instructs the adapter to switch to the selected mode and in response the adapter configures its internal circuitry to enable the selected mode. The portable electronic device can then communicate with the accessory via the adapter. The presence of the adapter can be transparent to the accessory.

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Номер записи: 13
21-11-2013 дата публикации

Flexray Gateway and Method for Operating a Flexray Gateway

Номер: US20130311695A1
Автор: Augustin Olav, BRAUN Jochen, Fischer Markus, Gossner Martin
Принадлежит: Vector Informatik GmbH

A Flexray gateway comprising a first and a second bus interface for connecting a first and a second Flexray bus, wherein the Flexray gateway comprises coupling means for coupling a first and a second Flexray bus and for transmitting bus messages between the first and the second Flexray bus, wherein the Flexray gateway comprises a Flexray controller with a first and a second channel interface for transmitting and receiving bus messages of a first and a second channel type of a Flexray bus. 1. A Flexray gateway comprising a first bus interface for connecting a first Flexray bus and a second bus interface for connecting a second Flexray bus , wherein the Flexray gateway comprises coupling means for coupling a first Flexray bus to a second Flexray bus and for transmitting bus messages between the first and the second Flexray bus , wherein the Flexray gateway comprises a Flexray controller with a first channel interface for transmitting and receiving bus messages of a first channel type of a Flexray bus and a second channel interface for transmitting and receiving bus messages of a second channel type of a Flexray bus , and wherein the coupling means are configured for coupling a channel connection of the first bus interface , which is provided for transmitting bus messages of the first channel type to a channel connection of the second bus interface , which is likewise provided for transmitting bus messages of the first channel type , and wherein the coupling means comprise at least one adapting module for adapting bus messages of the first channel type received at the second bus interface to bus messages of the second channel type and for relaying them to the second channel interface of the Flexray controller and/or for adapting bus messages of the second channel type transmitted via the second channel interface of the Flexray controller to bus messages of the first channel type and for relaying them to the second bus interface.2. A Flexray gateway according to claim 1 ...

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Номер записи: 14
05-12-2013 дата публикации

Method And Apparatus For Virtualizing Hardware Dongle Over A Wireless Connection

Номер: US20130326095A1
Автор: Jon Edney
Принадлежит: Atmel Wi Fi Solutions Inc

In a computer system configured to handle I/O signals received by the computer system from input devices and/or output signals output by the computer system, a virtual attachment module includes logic for selecting such that program code for coupling can alter the operating system's selection of I/O devices used for particular I/O device operations, coupling to a wireless I/O device at least for determining whether the wireless I/O device is available, and causing redirection of I/O signals destined to a default I/O device to be to the wireless I/O device, if the program code for coupling determines that the wireless I/O device is available. A virtual connection module could be used to intercept system messages indicating a wireless device is present and connected, determine whether the wireless device is present and/or connected, and determine which intercepted messages to forward, drop, delay or reformulate.

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Номер записи: 15
13-02-2014 дата публикации

COMPUTING APPARATUS WITH ENHANCED PARALLEL I/O FEATURES

Номер: US20140047153A1
Автор: Jung Myung-June, Lee Ju-Pyung
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided is a parallel I/O computing apparatus that includes a plurality of computing devices that may have different response characteristics depending on a number of parallel I/Os that are processed by the computing devices. The computing apparatus also includes an I/O dispatcher that distributes a different number of I/Os to one or more of the computing devices based on characteristics of the computing devices. 1. A parallel input/output (I/O) computing apparatus comprising:a plurality of computing devices that comprise different response characteristics based on a number of parallel I/Os processed by the plurality of computing devices; andan I/O dispatcher connected to the computing devices and configured to distribute a different number of parallel I/Os to at least one of the computing devices based on characteristics of the plurality of computing devices.2. The parallel I/O computing apparatus of claim 1 , wherein the plurality of computing devices comprise a plurality of solid-state disks.3. The parallel I/O computing apparatus of claim 1 , wherein the I/O dispatcher is further configured to redirect I/O traffic from an external device to the plurality of computing devices based on a mapping table that stores a parallel I/O dispatch for optimizing an overall parallel I/O performance.4. The parallel I/O computing apparatus of claim 1 , wherein the I/O dispatcher comprises:an information collector configured to collect information about characteristics of the plurality of computing devices; andan adaptive dispatcher configured to allocate the parallel I/Os to the plurality of computing devices based on the collected characteristic information about the plurality of computing devices.5. The parallel I/O computing apparatus of claim 4 , wherein the information collector comprises a response characteristic information collector configured to collect response characteristic information that varies based on the number of parallel I/Os performed by each of the ...

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Номер записи: 16
20-03-2014 дата публикации

Method and server for managing redundant arrays of independent disks cards

Номер: US20140082245A1
Автор: Chih-Huang WU
Принадлежит: Hon Hai Precision Industry Co Ltd

In a method for managing redundant arrays of independent disks (RAID) cards and a server for executing the method, the server calculates a theoretical percentage of a load of each RAID card according to a number of the RAID cards, and loads an actual percentage of the load of each RAID card through a multi input output (MIO) interface, and detects peripheral component interconnect-express (PCI-E) bandwidth of each RAID card. When the load of each RAID card is unbalanced or the PCI-E bandwidth of the RAID card is saturated, the server transfers the load from a RAID card having a greater actual percentage of the load into a RAID card having a less actual percentage of the load, and transfers the load from a RAID card whose PCI-E bandwidth is saturated into a RAID card whose PCI-E bandwidth is unsaturated according to differential signals through the MIO interface.

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Номер записи: 17
27-03-2014 дата публикации

INTERFACE BETWEEN A HOST AND A PERIPHERAL DEVICE

Номер: US20140089553A1
Автор: Ma Kenneth
Принадлежит: BROADCOM CORPORATION

Disclosed are various embodiments for an interface between a host device and one or more peripheral devices in a computing system. A peripheral-side controller, a host-side controller, and a peripheral-side translator are located on a peripheral device that is in communication with a host device. The peripheral-side translator transfers data from an internal bus in the peripheral device to an external interface for the peripheral device. The internal bus is associated with a first bus protocol, and the external interface is associated with a second bus protocol. 1. A system , comprising: a bus fabric associated with a first bus protocol; and', 'a host-side translator in communication with the bus fabric, the host-side translator configured to provide data from the bus fabric to an external interface for the host device, the external interface being associated with a second bus protocol; and, 'a host device comprising a peripheral-side translator in communication with the external interface, the peripheral-side translator configured to provide data from the external interface to an internal bus in the peripheral device, the internal bus being associated with a third bus protocol; and', 'a host-side controller configured to obtain data from the internal bus., 'a peripheral device comprising2. The system of claim 1 , wherein the peripheral device further comprises a peripheral-side controller for the peripheral device claim 1 , the peripheral-side controller being in communication with the host-side controller.3. The system of claim 1 , wherein:the host-side translator is configured to convert the data from being in accordance with the first bus protocol to being in accordance with the second bus protocol; andthe peripheral-side translator is configured to convert the data from being in accordance with the second bus protocol to being in accordance with the third bus protocol.4. The system of claim 1 , wherein:the host device comprises an additional host-side ...

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Номер записи: 18
06-01-2022 дата публикации

CLUSTER IDENTIFIER REMAPPING FOR ASYMMETRIC TOPOLOGIES

Номер: US20220004439A1
Автор: Abraham Vinit Mathew, Enamandram Anand K., Nallusamy Eswaramoorthi
Принадлежит: Intel Corporation

A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks and determine whether the actual topology matches the desired topology as described in the cluster remapping table. 1. A non-transitory machine-readable storage medium with instructions stored thereon , the instructions executable by a machine to cause the machine to:access a cluster remapping register stored in computer memory;determine, from the cluster remapping register, a mapping of a first integrated circuit block in a first chip to a first cluster identifier, wherein the first cluster identifier is different than an assigned cluster identifier for the first integrated circuity block;determine, from the cluster remapping register, a mapping of a second integrated circuit block in the first chip to a second cluster identifier from the cluster remapping register;identify a first interconnect link to couple the first integrated circuit block in the first chip to a third integrated circuit block in a second chip;identify a second interconnect link to couple the second integrated circuit block in the first chip to a fourth integrated circuit block in the second chip; anddetermine whether connections made by the first and second interconnect links match connections defined in the cluster remapping register.2. The storage medium of claim 1 , wherein the instructions are further executable to:identify a mapping of the third integrated circuit block to a third cluster identifier;identify a mapping of the ...

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Номер записи: 19
06-01-2022 дата публикации

PCIe Device Peer-To-Peer Communications

Номер: US20220004512A1
Автор: Cannata James Scott, Long Christopher R., Puri Sumit, Schramm Bryan
Принадлежит: Liqid Inc.

Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers. 1. A system comprising:a user interface configured to receive instructions to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device;wherein the communication arrangement is configured to redirect a transfer from the first PCIe device based on an address corresponding to an address range of the second PCIe device without passing the transfer through a host processor that executes an application initiating the transfer.2. The system of claim 1 , wherein the communication arrangement is established in a PCIe fabric comprising one or more PCIe switch circuits.3. The system of claim 1 , wherein the first PCIe device comprises a Graphics Processing Unit (GPU) and the second PCIe device comprises a storage device.4. The system of claim 1 , wherein the communication arrangement is further established to detect an additional transfer from the second PCIe device to one or more addresses corresponding to an address range for the first PCIe device claim 1 , and redirect the additional transfer to the first PCIe device without passing the additional transfer through the host processor that initiates the additional transfer.5. The system of claim 1 , wherein the address range of the second PCIe device is in addition to a memory mapped address range assigned to the second PCIe device within a memory space ...

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Номер записи: 20
05-01-2017 дата публикации

Add-on device and server using the same

Номер: US20170004105A1
Автор: Bo Tian, Kang Wu
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

An add-on device includes an interface, an identification module, an enable module, and a function module. The identification module is used to output an identification signal. The enable module is used to receive an enable signal. The function module is used to process signals. The enable module activates the function module to operate when the enable module receives the enable signal.

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Номер записи: 21
07-01-2016 дата публикации

CACHING SYSTEMS AND METHODS WITH SIMULATED NVDRAM

Номер: US20160004653A1
Автор: Purkayastha Saugata Das, Sampathkumar Kishore Kaniyar
Принадлежит:

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. The HBA is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority. 1. A system , comprising:a host processor;a host memory communicatively coupled to the host processor and sectioned into pages;a host bus adapter (HBA) communicatively coupled to the host processor and comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations andan HBA driver operable on the host processor,wherein the DRAM is sectioned into pages mapped to pages of the host memory and the SSD is sectioned into pages mapped to pages of the DRAM,wherein the SSD is further sectioned into regions comprising one or more pages of the SSD, andwherein the HBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by the host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of a region of the page of the other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.2. The system of claim 1 , further comprising:a storage device comprising an operating system executable by the host processor, wherein the operating system comprises an application that is operable to change priorities of the regions of the SSD.3. The system of claim 2 , wherein:the ...

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Номер записи: 22
07-01-2016 дата публикации

SYSTEM FOR MIGRATING STASH TRANSACTIONS

Номер: US20160004654A1
Автор: Dutta Yashpal, GOEL Himanshu, Sethi Varun
Принадлежит: Freescale Semiconductor, Inc.

A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core. 1. A system for migrating at least one stash transaction between a plurality of processor cores , wherein each of the plurality of processor cores includes a cache register , the system comprising:a main memory, for storing a plurality of data frames and an input/output memory management unit (IOMMU) mapping table that includes a mapping between a logical input/output (I/O) device number (LIODN) corresponding to an I/O device and a corresponding stash transaction destination identification (ID), wherein the stash transaction destination ID includes a cache register ID associated with a cache register of one of the processor cores of the plurality of processor cores;a first I/O device, connected to the main memory, for generating the plurality of data frames and initiating direct memory access (DMA) transactions for storing the plurality of data frames in the main memory, and generating a stash transaction request corresponding to each data frame of the plurality of data frames;a queue manager, connected to the first I/O device, for receiving and storing a first stash transaction request ...

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Номер записи: 23
07-01-2016 дата публикации

MEMORY SYSTEM AND DATA STORAGE DEVICE

Номер: US20160004660A1
Автор: LEE Hak Dae
Принадлежит:

A memory system includes a first memory device and a second memory device suitable for outputting and receiving signals through first and second sub input/output lines, respectively, a controller suitable for outputting and receiving signals to and from the first memory device and the second memory device, through a main input/output line and a selection unit suitable for electrically coupling the main input/output line with one of the first and the second sub input/output lines, through which an activated one of the first memory and the second memory devices outputs and receives signals. 1. A memory system comprising:a first memory device and a second memory device suitable for outputting and receiving signals through a first and a second sub input/output lines, respectively;a controller suitable for outputting and receiving signals to and from the first memory device and the second memory device, through a main input/output line; anda selection unit suitable for electrically coupling the main input/output line with one of the first and the second sub input/output lines, through which an activated one of the first memory and second memory devices outputs and receives signals.2. The memory system according to claim 1 , wherein the selection unit selects the one of the first and second sub input/output lines to be electrically coupled with the main input/output line claim 1 , based on a first select signal for activating the first memory device and a second select signal for activating the second memory device.3. The memory system according to claim 1 , wherein the controller outputs a control signal or data claim 1 , or receives data from the activated one of the first memory and second memory devices claim 1 , through the main input/output line and the one of the first and second sub input/output lines.4. The memory system according to claim 1 , wherein the selection unit is electrically coupled with the controller through the main input/output line claim 1 , ...

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Номер записи: 24
07-01-2016 дата публикации

Usb transceiver

Номер: US20160004661A1
Автор: Parul K. Sharma, Ravi Dixit
Принадлежит: FREESCALE SEMICONDUCTOR INC

A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal.

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Номер записи: 25
07-01-2021 дата публикации

MESSAGE PASSING FRAMEWORK FOR AUDIO/VIDEO STREAMING IN A TOPOLOGY OF DEVICES

Номер: US20210004191A1
Автор: Kambhatla Srikanth
Принадлежит: Intel Corporation

Resources may be managed in a topology for audio/video streaming. The topology includes audio/video sources and sinks and intervening branch devices. Messages between these sources, sinks, and branch devices may be used for resource management. 124-. (canceled)25. A storage device comprising instructions that , when executed , cause a processor to at least:obtain a first global unique identifier (GUID) via an auxiliary channel from a topology of devices, the first GUID corresponding to a first function;obtain a second GUID via the auxiliary channel from the topology of devices, the second GUID corresponding to a second function; anddetermine that the first function and the second function are part of a same one of the devices when the first GUID corresponding to the first function matches the second GUID corresponding to the second function, the same one of the devices to include the first GUID in a first GUID register, the first GUID register being one of first DisplayPort configuration data (DPCD) registers, and the same one of the devices to include the second GUID in a container descriptor of the second function.26. The storage device of claim 25 , wherein the first function is a sink function.27. The storage device of claim 26 , wherein the second function is a universal serial bus (USB) function.28. The storage device of claim 27 , wherein the USB function corresponds to a USB hub in the same one of the devices.29. The storage device of claim 25 , wherein the same one of the devices is a branch device.30. The storage device of claim 25 , wherein the same one of the devices is a sink device.31. The storage device of claim 25 , wherein the container descriptor is in an address space of the second function.32. An apparatus comprising:a transmitter;a receiver;memory; and obtain a first global unique identifier (GUID) via an auxiliary channel from a topology of devices, the first GUID corresponding to a first function;', 'obtain a second GUID via the auxiliary ...

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Номер записи: 26
04-01-2018 дата публикации

NETWORK-ACCESSIBLE DATA VOLUME MODIFICATION

Номер: US20180004698A1
Автор: Arumugam Nachiappan, Brouwer Pieter Kristian, Olson Marc Stephen, Rajavenkateswaran Vijay Prasanth, Thacker Michael, Tripathi Arpit, Wei Danny
Принадлежит:

A user can set or modify operational parameters of a data volume stored on a network-accessible storage device in a data center. For example, the user may be provided access to a data volume and may request a modification to the operational parameters of the data volume. Instead of modifying the existing data volume, the data center can provision a new data volume and migrate data stored on the existing data volume to the new data volume. While the data migration takes place, the existing data volume may block input/output (I/O) requests and the new data volume may handle such requests instead. If a request is received for data not yet migrated to the new data volume, then the new data volume prioritizes a migration of the requested data. 1. A computer-implemented method comprising: receiving a request to modify a first data volume;', 'causing a computing device to provision a second data volume responsive to the request;', 'causing the second data volume to execute input/output (I/O) requests in place of the first data volume before all data chunks from the first data volume are stored on the second data volume;', 'causing the second data volume to retrieve and store a plurality of the data chunks stored in the first data volume;', 'receiving a request from a host system for a first data chunk;', 'determining that the first data chunk is not stored in the second data volume;', 'causing prioritization of a transfer of the first data chunk over a second data chunk in the plurality of data chunks responsive to the determination that the first data chunk is not stored in the second data volume; and', 'causing the second data volume to transmit the first data chunk to the host system once the first data chunk is retrieved from the first data volume., 'as implemented by one or more computing devices configured with specific executable instructions,'}2. The computer-implemented method of further comprising causing the first data volume to execute one or more I/O requests ...

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Номер записи: 27
07-01-2021 дата публикации

SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM

Номер: US20210004341A1
Автор: Amer Maher, Takefman Michael L., Trojanowski Bart
Принадлежит:

A method of implementing a multi-threaded device driver for a computer system is disclosed. A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread. 1. (canceled)2. A chip comprising:a first processor core;a second processor core; and the first driver thread is to execute a first operation on a device during a pre-determined time slot configured for the first driver thread, the device having one of a first state indicating that the device is unscouted and inactive, a second state, a third state, or a fourth state, the first driver thread executing the first operation while the device is in the fourth state, the fourth state indicating that the first driver threshold has an exclusive ownership of the device;', 'the second driver thread is to determine that the device has transitioned from the fourth state to the second state, the second state indicating that the device is still controlled by the first driver thread while executing the first operation on the device;', 'the first driver thread is to determine that the device has transitioned from the second state to the fourth state, the transition from the second state to the fourth state indicating that the second driver thread will claim the exclusive ownership of the device after the first driver thread completes ...

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Номер записи: 28
07-01-2021 дата публикации

Switching Device, Peripheral Component Interconnect Express System, and Method for Initializing Peripheral Component Interconnect Express System

Номер: US20210004343A1
Автор: Fang Hongcan
Принадлежит:

A switching system includes a first switching device and a second switching device. The first switching device and the second switching device are coupled using a network. The first switching device includes a plurality of PCIe upstream ports configured to connect to at least one host, the second switching device comprises at least one PCIe downstream port configured to connect to at least one input/output (I/O) device, and the second switching device is configured to receive a first data packet from the first switching device using the network, convert the first data packet to a second data packet complying with a PCIe protocol, and transmit the second data packet to a target I/O device of the second data packet. 1. A switching device comprising:Peripheral Component Interconnect Express (PCIe) upstream ports configured to couple to a host;a PCIe downstream port coupled to the PCIe upstream ports and configured to couple to an input/output (I/O) device;an internal connection line; and transmit a configuration read/write packet to the PCIe downstream port using the internal connection line,', 'receive, from the PCIe downstream port, in response to the configuration read/write packet, and using the internal connection line, a configuration read/write response packet comprising a completer identification, and', 'determine, according to the completer identification, that the switching device is coupled to the I/O device whose identification is the completer identification., 'an internal processing apparatus coupled to the PCIe downstream port using the internal connection line and configured to2. The switching device of claim 1 , wherein the internal processing apparatus is further configured to:store PCIe configuration content of the I/O device;virtualize a function of the I/O device; andimplement a mapping between a first PCIe domain corresponding to the host and a second PCIe domain corresponding to the I/O device.3. The switching device of claim 2 , wherein the ...

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Номер записи: 29
02-01-2020 дата публикации

Communication system

Номер: US20200004717A1
Автор: Rikuya UEKAJI, Tsuyoshi Tagashira
Принадлежит: Kawasaki Jukogyo KK

A communication system, first and second device-side connectors and cable-side connectors are configured such that, when the first device-side and first cable-side connector are connected to each other, a communication line connection portion of the first device-side connector and the first cable-side connector are connected to each other, and when the second device-side and second cable-side connector are connected to each other, a communication line connection portion of the second device-side connector and second cable-side connector are connected to each other, and a valid/invalid switching circuit is configured to: in a case where the first and second cable-side connectors are connected to the first and second device-side connectors, respectively, render a connection of a termination resistor to a pair of conductors of an internal communication line invalid; and in other cases, render the connection of the termination resistor to the pair of conductors of the internal communication line valid.

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Номер записи: 30
01-01-2015 дата публикации

Extending functionality in multimedia presentation device

Номер: US20150007247A1
Автор: Robin Dua
Принадлежит: Robin Dua

Functionality of a multimedia presentation device is enhanced by establishing a communication path through an electrical connector that is selectively separable from the multimedia presentation device. Output streaming media are conveyed to the multimedia presentation device over the established communication path. A wireless communication channel is established over which input streaming media are received from a multimedia source device. Multimedia data of the input streaming media are stored in a memory that is selectively separable from the multimedia presentation device at the electrical connector. A processor, which is also selectively separable from the multimedia presentation device at the electrical connector, retrieves the multimedia data stored in the memory and the retrieved multimedia data are conveyed to the multimedia presentation device as the output streaming media on the communication path to the multimedia presentation device through the electrical connector.

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Номер записи: 31
02-01-2020 дата публикации

Multi-signal realignment for changing sampling clock

Номер: US20200005819A1
Автор: Jason Bellorado, Marcus Marrow, Zheng Wu
Принадлежит: SEAGATE TECHNOLOGY LLC

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

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Номер записи: 32
14-01-2016 дата публикации

EFFICIENT SEARCH KEY CONTROLLER WITH STANDARD BUS INTERFACE, EXTERNAL MEMORY INTERFACE, AND INTERLAKEN LOOKASIDE INTERFACE

Номер: US20160011987A1
Автор: Bouley Rick
Принадлежит:

A device includes a Standard Bus Interface Circuit (SBIC), a memory interface circuit, a Direct Memory Access (DMA) controller, and an Interlaken Look-Aside (ILA) interface circuit. A search key data set including multiple search keys is received via the SBIC and is written to an external memory via the memory interface circuit. The DMA controller receives a descriptor via the SBIC, generates a search key data request, receives the search key data set, and selects a single search key from the set. The ILA interface circuit receives the search key from the DMA controller, generates and ILA packet including the search key, and sends the ILA packet to an external transactional memory device that generates a result data value. The DMA controller receives the result data value via the ILA interface circuit, writes the result data value to the external memory, and sends a DMA completion notification. 1. An apparatus , comprising:a standard bus interface port;a memory interface port;an Interlaken Look Aside (ILA) interface port;a Standard Bus Interface Circuit (SBIC) that receives a descriptor and a search key data set onto the apparatus via the standard bus interface port, wherein the search key data set includes a plurality of search keys;a memory interface circuit that receives the search key data set from the SBIC and that writes the search key data set to an external memory via the memory interface port;a Direct Memory Access (DMA) controller that (i) receives the descriptor from the SBIC, (ii) generates a search key data request in response to receiving the descriptor, (iii) receives the search key data set from the external memory via the memory interface circuit and the memory interface port, (iv) selects a first search key from the search key data set, and (v) outputs the first search key; andan ILA interface circuit that receives the first search key from the DMA controller and supplies an ILA packet to an external transactional memory device via the ILA ...

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Номер записи: 33
14-01-2016 дата публикации

ISLAND-BASED NETWORK FLOW PROCESSOR WITH EFFICIENT SEARCH KEY PROCESSING

Номер: US20160011995A1
Автор: Bouley Rick
Принадлежит:

A Island-Based Network Flow Processor (IBNFP) includes a memory and a processor located on a first island, a Direct Memory Access (DMA) controller located on a second island, and an Interlaken Look-Aside (ILA) interface circuit and an interface circuit located on a third island. A search key data set including multiple search keys is stored in the memory. A descriptor is generated by the processor and is sent to the DMA controller, which generates a search key data request, receives the search key data set, and selects a single search key. The ILA interface circuit receives the search key, generates and ILA packet including the search key that is sent to an external transactional memory device that generates a result data value. The DMA controller receives the result data value via the ILA interface circuit, writes the result data value to the memory, and sends a DMA completion notification. 1. An Island-Based Network Flow Processor (IBNFP) integrated circuit , comprising:a bus; a memory; and', 'a processor that writes a search key data set into the memory, wherein the search key data set comprises a plurality of search keys;', 'a second island, comprising:, 'a first island, comprisinga Direct Memory Access (DMA) controller that (i) receives the descriptor from the processor in the first island via the bus, (ii) generates a search key data request in response to receiving the descriptor and communicates the search key data request to the memory in the first island via the bus, (iii) receives the search key data set from the memory in the first island via the bus, (iv) selects a first search key from the search key data set, (v) generates header information, and (vi) outputs the first search key and the header information; and an Interlaken Look Aside (ILA) interface circuit that receives the first search key and the header information from the DMA controller and outputs an ILA packet; and', 'an interface circuit, wherein the interface circuit receives the ILA packet ...

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Номер записи: 34
14-01-2016 дата публикации

Connection interface switching device for multiple portable devices

Номер: US20160012001A1
Автор: Yi-Cheng Chang
Принадлежит: Good Way Tech Co Ltd

A connection interface switching device for multiple portable devices provides a communication channel between an I/O peripheral set and for a plurality of portable devices which are bundled with a default control program installed in the portable devices, and switches among the portable devices to establish a communication channel selected between one portable device and the I/O peripheral set according to a switch instruction generated by the default control program of the portable device. The connection interface switching device includes plural I/O ports, a controller, a memory module, a storage module and an I/O peripheral port, and an origin of the computer signal is controlled and switched to achieve the effect of sharing the same I/O peripheral set among multiple portable devices through the communication channel.

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Номер записи: 35
14-01-2016 дата публикации

INTERCONNECTION NETWORK TOPOLOGY FOR LARGE SCALE HIGH PERFORMANCE COMPUTING (HPC) SYSTEMS

Номер: US20160012002A1
Автор: ARIMILLI BABA L., DENZEL WOLFGANG, Heidelberger Philip, HERRERA GERMAN RODRIGUEZ, JOHNSON CHRISTOPHER J., LAMBRECHT LONNY, Minkenberg Cyriel, PRISACARI BOGDAN
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A multiprocessor computer system includes a plurality of processor nodes and at least a three-tier hierarchical network interconnecting the processor nodes. The hierarchical network includes a plurality of routers interconnected such that each router is connected to a subset of the plurality of processor nodes; the plurality of routers are arranged in a hierarchy of n≧3 tiers (T, . . . , T); the plurality of routers are partitioned into disjoint groups at the first tier T, the groups at tier Tbeing partitioned into disjoint groups (of complete Tgroups) at the next tier Tand a top tier Tincluding a single group containing all of the plurality of routers; and for all tiers 1≦i≦n, each tier-Tsubgroup within a tier Tgroup is connected by at least one link to all other tier-Tsubgroups within the same tier Tgroup. 1. A method of constructing a multiprocessor computer system comprising:providing a plurality of processor nodes; and each router is connected to a subset of the plurality of processor nodes;', {'sub': 1', 'n, 'the plurality of routers are arranged in a hierarchy of n tiers (T, . . . , T) where n is at least three;'}, {'sub': 1', 'i', 'i+1', 'n, 'the plurality of routers are partitioned into disjoint groups at a first tier T, groups of routers at each intermediate tier Tare partitioned into disjoint groups at a next higher tier T, and a top tier Tincludes a single group containing all of the plurality of routers;'}, {'sub': i−1', 'i', 'i−1', 'i, 'for all tiers 1≦i≦n , each tier-Tsubgroup within a tier Tgroup is connected by at least one link to all other tier-Tsubgroups within a same tier Tgroup.'}], 'coupling the plurality of processor nodes with a multi-tier hierarchical interconnection network including a plurality of routers, such that2. The method of claim 1 , wherein the coupling includes connecting each group of at least one specific tier Tto each other group within a same tier Tby a plurality of links claim 1 , such that multiple but less than all ...

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Номер записи: 36
14-01-2016 дата публикации

INPUT/OUTPUT ACCELERATION IN VIRTUALIZED INFORMATION HANDLING SYSTEMS

Номер: US20160012003A1
Автор: Chawla Gaurav, HORMUTH ROBERT WAYNE, IYER SHYAM T., MOLLOY MICHAEL KARL
Принадлежит:

Methods and systems for I/O acceleration on a virtualized information handling system include loading a storage virtual appliance as a virtual machine on a hypervisor. The hypervisor may execute using a first processor and a second processor. The storage virtual appliance is accessed by the hypervisor using a PCI-E device driver that is mapped to a first PCI-E NTB logical endpoint at the first processor. A second PCI-E device driver may be loaded on the storage virtual appliance that accesses the hypervisor and is mapped to a second PCI-E NTB logical endpoint at the second processor. A data transfer operation may be executed between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint. The data transfer operation may be a read or a write operation. 1. A method executed using at least two processors , including a first processor and a second processor , the method comprising:loading a storage virtual appliance as a virtual machine on a hypervisor executing using the first processor and the second processor, wherein the storage virtual appliance is accessed by the hypervisor using a first Peripheral Component Interconnect Express (PCI-E) device driver that is mapped to a PCI-E non-transparent bridge (NTB) at a first PCI-E NTB logical endpoint at the first processor;loading a second PCI-E device driver on the storage virtual appliance that accesses the hypervisor and is mapped to the PCI-E NTB at a second PCI-E NTB logical endpoint at the second processor; andexecuting a data transfer operation between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint,wherein the hypervisor executes in the first memory space,wherein the storage virtual appliance executes in the second memory space, andwherein the PCI NTB provides address translation between the first memory ...

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Номер записи: 37
14-01-2016 дата публикации

INTERCONNECTION NETWORK TOPOLOGY FOR LARGE SCALE HIGH PERFORMANCE COMPUTING (HPC) SYSTEMS

Номер: US20160012004A1
Автор: ARIMILLI BABA L., DENZEL WOLFGANG, Heidelberger Philip, HERRERA GERMAN RODRIGUEZ, JOHNSON CHRISTOPHER J., LAMBRECHT LONNY, Minkenberg Cyriel, PRISACARI BOGDAN
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A multiprocessor computer system includes a plurality of processor nodes and at least a three-tier hierarchical network interconnecting the processor nodes. The hierarchical network includes a plurality of routers interconnected such that each router is connected to a subset of the plurality of processor nodes; the plurality of routers are arranged in a hierarchy of n≧3 tiers (T, . . . , T); the plurality of routers are partitioned into disjoint groups at the first tier T, the groups at tier Tbeing partitioned into disjoint groups (of complete Tgroups) at the next tier Tand a top tier Tincluding a single group containing all of the plurality of routers; and for all tiers 1≦i≦n, each tier-Tsubgroup within a tier Tgroup is connected by at least one link to all other tier-Tsubgroups within the same tier Tgroup. 1. A multiprocessor computer system comprising:a plurality of processor nodes; and each router is connected to a subset of the plurality of processor nodes;', {'sub': 1', 'n, 'the plurality of routers are arranged in a hierarchy of n tiers (T. . . , T) where n is at least three;'}, {'sub': 1', 'i', 'i+1', 'n, 'the plurality of routers are partitioned into disjoint groups at a first tier T, groups of routers at each intermediate tier Tare partitioned into disjoint groups at a next higher tier T, and a top tier T, includes a single group containing all of the plurality of routers;'}, {'sub': i−1', 'i', 'i−1', 'i, 'for all tiers 1≦i≦n, each tier-Tsubgroup within a tier Tgroup is connected by at least one link to all other tier-Tsubgroups within a same tier Tgroup.'}], 'a multi-tier hierarchical network interconnecting the processor nodes, wherein the multi-tier hierarchical network includes a plurality of routers, wherein2. The multiprocessor computer system of claim 1 , wherein each group of at least one specific tier Tis connected to each other group within a same tier Tgroup by a plurality of links claim 1 , such that multiple but less than all Trouters from one ...

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Номер записи: 38
11-01-2018 дата публикации

High performance interconnect link layer

Номер: US20180011759A1
Автор: Jeff Willey, Jeffrey C. Swanson, Robert G. Blankenship, Robert J. Safranek
Принадлежит: Intel Corp

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

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Номер записи: 39
11-01-2018 дата публикации

INFORMATION PROCESSING APPARATUS

Номер: US20180011812A1
Автор: Morishita Satoshi, NOMURA Shimpei, Okada Mitsuhiro, Suzuki Akifumi
Принадлежит:

An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface. 1. An information processing apparatus , comprising:a processor;a memory;at least one accelerator;at least one storage device; anda network configured to couple the processor, the at least one accelerator, and the at least one storage device to one another, an initial setting interface configured to receive an initialization instruction from the processor; and', 'an I/O interface configured to issue an I/O command, and, 'wherein the at least one storage device compriseswherein the processor is configured to notify the at least one accelerator of one of an address of the initial setting interface and an address of the I/O interface.2. The information processing apparatus according to claim 1 , a first I/O interface configured to receive an I/O command from the processor; and', 'at least one second I/O interface configured to receive an I/O command from the at least one accelerator, and, 'wherein the I/O interface compriseswherein the at least one storage device is capable of receiving the I/O command separately from the processor and the at least one accelerator.3. The information processing apparatus according to claim 1 ,wherein the processor is configured to issue a data processing command to the at least one accelerator for instruction to process data stored in the at least one storage device,wherein the at least one accelerator, which has received the data processing command, is configured to ...

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Номер записи: 40
14-01-2021 дата публикации

SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEVICES VIA A MAIN MEMORY SYSTEM

Номер: US20210011661A1
Автор: Amer Maher, BADALONE Riccardo, Takefman Michael L.
Принадлежит:

A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. 1. (canceled)2. A memory module comprising:one or more memory devices; and a first interface to couple to a host system;', 'a second interface coupled to the one or more memory devices; and', receive a command from the host system;', 'store the command received from the host system in the command buffer;', 'determine whether the command is complete;', 'generate direct memory access (DMA) descriptors in response to the command being complete; and', 'communicate the DMA descriptors on the second interface., 'control circuitry comprising a command buffer, wherein the control circuitry is coupled to the first interface and the second interface, wherein the control circuitry is to], 'a device coupled to the one or more memory devices, the device comprising3. The memory module of claim 2 , wherein the control circuitry comprises:a command processor configured to generate the DMA descriptors; anda buffer check logic configured to determine whether the command is complete.4. The memory module of claim 3 , wherein the buffer check logic is configured to read one or more bits from each portion of a plurality of portions of the command and to determine that the one or more bits read from each portion together match a predetermined pattern.5. The memory module of claim 3 , wherein the buffer check logic is configured to read a first bit and a second bit from each portion of a plurality of portions of the command and to determine that the first bit read from each portion is a non-zero value and the second bit read from each portion is a zero value.6. The memory module ...

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Номер записи: 41
14-01-2021 дата публикации

System and method for ensuring command order in a storage controller

Номер: US20210011662A1
Автор: Barry J. Debbins, Derek R. Palmerton, Sucharita Sriram
Принадлежит: ATTO Tech Inc

A novel storage router with an acceleration gate is disclosed. The storage router includes one or more network interfaces for receiving storage traffic and a hardware engine for processing data storage commands. The hardware engine transfers commands and data to target storage devices by means of more than one storage interface, the storage interfaces having unequal processing latencies. The hardware engine contains an acceleration gate for storing the number of outstanding commands to each storage interface on a per-target-device basis. If the target device is not idle, the hardware engine uses the acceleration gate count to automatically route commands to the lowest latency path with outstanding commands for the target device.

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Номер записи: 42
09-01-2020 дата публикации

FLIT-BASED PARALLEL-FORWARD ERROR CORRECTION AND PARITY

Номер: US20200012555A1
Автор: Das Sharma Debendra
Принадлежит: Intel Corporation

A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors. 1. A device , comprising:a processor; and receive information from the processor;', 'generate one or more transaction layer packets based on the information;', 'generate one or more flits comprising the transaction layer packets, individual of the flits protected by a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction (FEC) scheme; and', 'transmit the one or more flits across one or more lanes of a link to a receiving device., 'a protocol stack to2. The device of claim 1 , wherein individual of the flits comprise one or more flit-level FEC codes to implement the flit-level FEC scheme claim 1 , the protocol stack to further transmit the one or more flit-level FEC codes across at least one of the one or more lanes.3. The device of claim 1 , wherein the protocol stack is further to store transmitted flits that are not null flits in a replay buffer.4. The device of claim 3 , wherein the protocol stack is further to:receive a retry request from the receiving device to retransmit at least one retry flits of the one or more flits; detecting the presence of a non- ...

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Номер записи: 43
19-01-2017 дата публикации

Multi-processor startup system

Номер: US20170017495A1
Автор: James Lawrence Mangin, Russell K. Mukai, Vinay SAWAL, Vivek Dharmadhikari
Принадлежит: Dell Products LP

A switch includes a PCI bus. A line card processor is coupled to a line card memory system and includes a line card processor port connected to the PCI bus. A management processor is coupled to a management memory system and includes a management processor port connected to the PCI bus and associated with a register. The management processor retrieves an OS image and stores the OS image in the management memory system. The management processor then configures the register with a mapping between the management memory system and the line card memory system. The management processor then provides a write instruction to write the OS image to an address range included in the management memory system, and the management processor port converts the write instruction using the address mapping such that the OS image is written over the PCI bus to the line card memory system.

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Номер записи: 44
21-01-2016 дата публикации

AUTOMATICALLY ADJUSTABLE, CHARGE-ONLY, USB ADAPTER

Номер: US20160018865A1
Автор: Higgins Christopher Thomas, Johar Hardeep Singh, Silva Joseph Craig
Принадлежит: SparqEE Technologies, L.L.C.

A system and method provides a way to sever the data connection between a USB port and a client device, while still allowing the client device to charge. Typical connections between a client device and a USB port involve a USB cable. However, the device described herein is used in series with the client device and USB port. The device automatically detects the allowed charging current from the USB port and presents that information to the client device. During this exchange, no data transfer is allowed between the client device and USB port in either direction. Once the client device is provided, and charging information presented by the device, the client device begins to charge. 1. A system for charging a device , comprising:a physical interface capable of connection between a chargeable client device and data-port of a host device, the host device and client device capable of exchanging data;an adapter included with the physical interface capable of:(a) detecting an allowed charging current from the port of the host device;(b) presenting the allowed charging current to the client device;(c) removing data transfer capability through the physical interface; and(d) passing through charge to the client device based on the allowed charging current.2. The system of claim 1 , wherein the port comprises a universal serial bus (USB) port.3. The system of claim 2 , wherein the adapter comprises a USB adapter.4. The system of claim 1 , wherein the adapter comprises a gated power channel.5. The system of claim 1 , wherein the adapter comprises an input/output block.6. The system of claim 1 , wherein the adapter comprises a processing block.7. The system of claim 1 , wherein the adapter comprises a full cable claim 1 , included in a hub.8. The system of claim 1 , wherein the adapter comprises a data stage that detects and analyzes the allowed charging current.9. The system of claim 1 , wherein the adapter comprises two connecters that feed two USB data blocks and a USB power ...

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Номер записи: 45
19-01-2017 дата публикации

FIRMWARE UPDATING METHOD

Номер: US20170017596A1
Автор: GAO Yang, JANG Jiing-Shyang, YANG MENG-LIANG
Принадлежит:

A firmware updating method in just a bunch of disks includes the following blocks. A motherboard is coupled to a first primary storage extension chip or to a second primary storage extension chip. The first primary storage extension chip and the second primary storage extension chip are coupled to each other. At least one secondary storage extension chip is coupled to the first primary storage extension chip. At least one secondary storage extension chip is coupled to the second primary storage extension chip. A signal sent to the first primary storage extension chip or to the second primary storage extension chip by the motherboard causes firmware of each storage extension chip to be updated. 1. A firmware updating method comprising:coupling a first primary storage extension chip or a second primary storage extension chip to a motherboard;coupling the first primary storage extension chip to the second primary storage extension chip;coupling at least one secondary storage extension chip to the first primary storage extension chip;coupling at least one secondary storage extension chip to the second primary storage extension chip;sending a signal to the first primary storage extension chip or the second primary storage extension chip by the motherboard;updating a firmware of the first primary storage extension chip and the second primary storage extension chip; andupdating each secondary storage extension chips by the first primary storage extension chip or the second primary storage extension chip.2. The updating method of claim 1 , further comprising: when sending the signal to the first primary storage extension chip claim 1 , updating the firmware of each secondary storage extension chips which is coupled to the first or second primary storage extension chips by the first primary storage extension chip claim 1 , and when sending the signal to the second primary storage extension chip claim 1 , updating the firmware of each secondary storage extension chips which ...

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Номер записи: 46
19-01-2017 дата публикации

Multigig Solution on Conventional SGMII and XFI Capable System

Номер: US20170017597A1
Автор: Ajith Chandran, Chandra Sekhara Rao Vempali, Kabiraj Sethi, Neha Agarwal
Принадлежит: Cisco Technology Inc

Methods and systems are disclosed which may provide MultiGig capability to a system where a physical layer device (PHY) or a network device does not have the capacity to support all available line speeds while operating in a single system-interface mode between MAC and PHY devices.

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Номер записи: 47
19-01-2017 дата публикации

SYSTEM TRANSPARENT RETIMER

Номер: US20170017604A1
Автор: Chen Jian, Lee KC, Ouyang Qing, Qu Ming, Yuan Zhengyu
Принадлежит:

A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration. 1. A method for managing an operational state of a retimer circuit included in an interconnect between a host system and a device system , the method comprising:monitoring, during a first retimer operation state, a detection status of a first receiver included in the host system and coupled to a first port of the retimer circuit and a detection status of a second receiver included in a device system and coupled to a second port of the retimer circuit;responsive to the detection status of the first receiver and the detection status of the second receiver indicating the presence of the first and second receivers, transitioning from the first retimer operation state to a second retimer operation state; monitoring at a first specified monitoring interval the detection status of the first receiver and the detection status of the second receiver,', 'detecting a control signal, wherein the detected control signal is associated with a ping message and a polling message,', 'decoding the polling message responsive to detecting the control signal in the absence of an occurrence of the ping message within the first specified ...

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Номер записи: 48
21-01-2016 дата публикации

Methods and Systems for Multiple Bus Generator and Load Control

Номер: US20160018878A1
Автор: DUSTMAN William J.
Принадлежит:

Multiple bus generator and load control monitoring system for electrical switchgear is provided. In one arrangement, the system is designed to allow for the increased functionality of a single bus system to be used in multiple bus systems wherein the multiple buses are separated or combined together to act as a single bus. Each bus within the multiple bus system may be able to utilize increased functionality of a typical generator bus and load control system independently if separated. Separate bus structures may be separated by some sort of isolation device, for example: a circuit breaker, transfer switch, or the like. If the bus segments are connected together via isolation devices, then the combination of the overall connected bus structure will act as a single entity, while containing enhanced automation functions. 1. A bus and load monitoring and control system , the system comprising: a first engine generator for providing emergency power to a first bus;', 'a first isolation device operatively connecting the first engine generator to the first bus; and', 'a first plurality of loads coupled to the first bus;', 'and, 'A. a first bus system for providing power to a first plurality of loads, the first bus system comprising a first engine generator for providing emergency power to a second bus;', 'a first isolation device operatively connecting the first engine generator to the second bus;, 'B. a second bus system for providing power to a second plurality of loads, the second bus system comprisingC. a third isolation device connecting the first bus system to the second bus system, andD. a system controller for monitoring and controlling operation of the first and the second bus systems, receiving information from the first bus system;', 'injecting the first bus information into a core code;', 'running the first bus information through the core code;', 'receiving information from the second bus system;', 'injecting second bus information into the core code;', ' ...

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Номер записи: 49
19-01-2017 дата публикации

Data processing system and data processing method

Номер: US20170017607A1
Автор: Guangyu Shi, Huawei Liu, Jian He, Norbert Egi, Xiancai Li, Xiaoke Ni, Yu Liu
Принадлежит: Huawei Technologies Co Ltd

Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.

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Номер записи: 50
21-01-2016 дата публикации

TIME MULTIPLEXING AT DIFFERENT RATES TO ACCESS DIFFERENT MEMORY TYPES

Номер: US20160019171A1
Автор: Shaeffer Ian
Принадлежит:

A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.

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Номер записи: 51
21-01-2016 дата публикации

Universal Serializer Architecture

Номер: US20160019174A1
Автор: Kulkarni Gururaj, Muddamsetty Chandan, Sreenath Somasunder Kattepura, Ubbala Pradeep Kumar
Принадлежит:

Systems and methods for a universal Serializer-Deserializer (SerDes) architecture are described. In various implementations, a transceiver may include: a first plurality of data flip- flops coupled to a data lookup circuit of a SerDes interface; a second plurality of data flip-flops coupled to the data lookup circuit; a plurality of latches, each latch of the plurality of latches coupled to a corresponding data flip-flop of the second plurality of data flip-flops; and a plurality of multiplexers coupled to the plurality of latches, to the first plurality of data flip-flops, and to a transmitter circuit.

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Номер записи: 52
15-01-2015 дата публикации

Providing A Sideband Message Interface For System On A Chip (SoC)

Номер: US20150019788A1
Автор: Adler Robert P., Fanning Blaise, Hunsaker Mikal C., Klinglesmith Michael T., Lakshmanamurthy Sridhar, Tamari Eran
Принадлежит:

According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed. 1. An apparatus comprising: a plurality of agents including an endpoint; and', 'a fabric to couple the plurality of agents, the fabric including at least one router to provide sideband communication between at least some of the plurality of agents, the sideband communication to include transmission of one or more of on-chip power management control information, shadow configuration register information, test mode information or device configuration space information, the at least one router to couple to the endpoint of corresponding ones of the plurality of agents via a sideband message interface, the sideband message interface to communicate at least one put signal, an end of message signal, at least one credit signal, and a message payload between the endpoint and the at least one router, wherein at least one of the plurality of agents is to maintain transaction level ordering rules with respect to the sideband communication in which a posted message and a completion message are to be treated as a common message type, and, 'a semiconductor die including but not limited towherein a subsequently issued posted message or a subsequently issued completion message is to be allowed to pass a previously issued non-posted message.2. The apparatus of claim 1 , wherein the at least one router is to send a first completion message directed from a first agent to a second agent to the second agent ...

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Номер записи: 53
03-02-2022 дата публикации

Disaggregation of system-on-chip (soc) architecture

Номер: US20220036500A1
Автор: Altug Koker, Binoj Xavier, Eric Finley, Iqbal Rajwani, Josh Mastronarde, Lakshminarayanan Striramassarma, Lance CHENEY, Melaku Teshome, Naveen MATAM, Sanjeev Jahagirdar, Varghese George, Vikranth Vemulapalli
Принадлежит: Intel Corp

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

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Номер записи: 54
21-01-2021 дата публикации

INITIALIZATION METHODS AND ASSOCIATED CONTROLLER, MEMORY DEVICE AND HOST

Номер: US20210019065A1
Автор: HSIEH CHAO-KUEI
Принадлежит:

The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds. 1. A method performed by a host for initializing a secure digital (SD) card , the SD card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode , the host comprising:a processor;a communication interface for coupling to the SD card, comprising:a first voltage supply contact for providing a first supply voltage;a second voltage supply contact for providing a second supply voltage lower than the first supply voltage;at least one ground contact for coupling to a ground;at least one clock contact for transmitting a clock signal to the SD card; anda command contact for transmitting a command to the SD card, (a) providing the first supply voltage to the SD card through the first voltage supply contact;', '(b) providing the second supply voltage to the SD card through the second voltage supply contact;', '(c) performing a PCIe linkup process after step (b);', '(d) determining that the PCIe linkup process succeeds or fails;', '(e) determining that the SD card enters the PCIe mode if the PCIe linkup process succeeds; and', '(f) transmitting a CMD0 command to the SD card ...

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Номер записи: 55
26-01-2017 дата публикации

Management of allocation for alias devices

Номер: US20170024150A1
Автор: Beth A. Peterson, Dale F. Riedy, David M. Shackelford, Deborah A. Furman, Harry M. Yudenfriend, Ilene A. GOLDMAN, John R. Paveza, Matthew J. Kalos, Scott B. Compton, Susan K. Candelaria
Принадлежит: International Business Machines Corp

Embodiments of the present invention provide systems, methods, and computer program products for managing computing devices to handle an input/output (I/O) request. In one embodiment, the I/O request may eligible for performance throttling based, at least in part, on the associated importance level for performing the received I/O request and one or more characteristics of the received I/O request. Embodiments of the present invention provide systems, methods, and computer program products for throttling the I/O request and transmitting the I/O request to a storage controller.

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Номер записи: 56
17-04-2014 дата публикации

Supplemental power system for power excursions

Номер: US20140108846A1
Автор: George G. Richards, III, Mark Muccini, Stuart Allen Berke
Принадлежит: Dell Products LP

A supplemental power system for IHS power excursions includes a processor and a memory coupled to the processor. A power system is coupled to the processor and a plurality of power supply paths. A first power supply path is operable to supply power at a first voltage from the power system to the processor. A second power supply path is operable to store power from the power system at a second voltage that is greater than the first voltage, and the second power supply path is further operable to supply the power stored at the second voltage to the processor during power excursions by the processor. In some embodiments, the second power supply path may include a boost converter to increase power at the first voltage to the second voltage, or may receive power output at the second voltage from a supplemental power rail in the power system.

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Номер записи: 57
26-01-2017 дата публикации

Inter-component communication including posted and non-posted transactions

Номер: US20170024343A1
Автор: Mikal C. Hunsaker, Ricardo E. James, Su Wei Lim
Принадлежит: Intel Corp

Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

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Номер записи: 58
26-01-2017 дата публикации

BACKBOARD FOR HARD DISK DRIVE AND ELECTRONIC DEVICE USING THE BACKBOARD

Номер: US20170024351A1
Автор: GAO Yang, WU KANG
Принадлежит:

A backboard applied in an electronic device includes a storage extended chip, a serial attached small computer system interface (SAS) hard disk drive (HDD) connector, a convertor, a first election unit, and a second election unit. An input pin of the convertor is coupled to a plurality of input pins of the SAS HDD, to receive the data signal from the SAS HDD connector. The first election unit is coupled to a first ground pin of the SAS HDD connector, enable pins of the convertor and the storage extended chip. The second election unit is coupled to the first ground pin of the SAS HDD connector and an enable pin of the storage extended chip. When the SAS HDD connector is coupled to a SATA HDD or a SAS HDD, the storage extended chip operates and receives a SAS signal from the SAS HDD connector. 1. A backboard comprising:a storage extended chip comprising an enable pin, an input pin, and an output pin;a serial attached small computer system interface (SAS) hard disk drive (HDD) connector comprising a plurality of input pins and a plurality of ground pins, and a data output;a convertor comprising an input pin, an enable pin, and an output pin, wherein the input pin of the convertor is coupled to the plurality of input pins of the SAS HDD, to receive data from the data output;an election unit comprising an input terminal, a first election unit, and a second election unit, wherein the first election unit is coupled to a first ground pin of the SAS HDD connector, the enable pin of the convertor, and the enable pin of the storage extended chip, the second election unit is coupled to the first ground pin of the SAS HDD connector and the enable pin of the storage extended chip.2. The backboard of claim 1 , wherein when the SAS HDD connector is coupled to a SATA HDD claim 1 , the first ground pin of the SAS HDD connector outputs a digital high level signal to the input terminal of the election unit claim 1 , the first election unit operates claim 1 , the second election does ...

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Номер записи: 59
28-01-2016 дата публикации

SYSTEM AND METHOD FOR BUS WIDTH CONVERSION IN A SYSTEM ON A CHIP

Номер: US20160026588A1
Автор: CHRISTANTO Neil Evan, CHU Jeffrey Hao
Принадлежит:

Various embodiments of methods and systems for precompensated bus width conversion (“PBWC”) in a portable computing device (“PCD”) are disclosed. Because starting memory addresses for data transfers emanating from a processing engine in a system on a chip (“SoC”) may be misaligned with a starting memory address of a main bus on the SoC, PBWC solutions seek to precompensate data transfers to align the starting addresses. Advantageously, by doing so PBWC embodiments may significantly reduce the amount of “filler” data chunks that are transferred through the main bus, thereby optimizing band width utilization of the main bus. 1. A method for compensating bus misalignment when undergoing bus width conversion in a system on a chip (“SoC”) in a portable computing device (“PCD”) , the method comprising: the processing engine is associated with a native bus having a bus width that is less than a bus width of a main bus; and', 'the data transfer request is a series of data bursts each comprised of a plurality of data chunks;, 'receiving a data transfer request from a processing engine, whereindetermining that a native bus starting memory address for the data transfer is misaligned with a main bus starting memory address;precompensating the data transfer by aligning the native bus starting memory address with the main bus starting memory address; andperforming a bus width conversion of the data transfer to transmit the data transfer through the main bus.2. The method of claim 1 , wherein:precompensating the data transfer comprises disassociating a first data chunk from a first data burst of the series of data bursts; andperforming a bus width conversion of the data transfer to transmit the data transfer through the main bus comprises implementing a first transaction on the main bus of the disassociated first data chunk and a filler data chunk.3. The method of claim 2 , wherein:precompensating the data transfer further comprises disassociating a first data chunk from a second ...

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Номер записи: 60
28-01-2016 дата публикации

Adaptive Circuit Board Assembly and Flexible PCI Express Bus

Номер: US20160026589A1
Автор: Kolor Daniel John, Rollins William Leo, Walker Robert
Принадлежит:

A system and method for adaptive bus configuration operable to respond to hardware changes and other configuration changes is disclosed. In an embodiment, the computing system includes a circuit assembly having at least one processing resource coupled to a respective set of bus traces, at least one peripheral device socket coupled to a respective set of bus traces, and a bus switch coupled to the bus traces of the processing resource and the bus traces of the peripheral device. The bus switch implements a set of connections between the bus traces of the processing resource and the bus traces of the peripheral device sockets according to an instruction. The instruction may specify an allocation of peripheral device sockets to processing resources based on the number of installed processing resources so that no peripheral device is connected to a bus without an attached processor. 1. A computing system comprising: at least one processing resource, wherein each of the at least one processing resource is coupled to a respective set of bus traces;', 'at least one peripheral device socket operable to receive a peripheral device, wherein each of the at least one peripheral device socket is coupled to a respective set of bus traces; and', 'a bus switch coupled to each set of bus traces of the at least one processing resource and to each set of bus traces of the at least one peripheral device socket, wherein the bus switch is operable to receive an instruction and, based on the instruction, to implement a set of connections between each set of bus traces of the at least one processing resource and each set of bus traces of the at least one peripheral device socket., 'a circuit assembly having coupled to and disposed thereupon2. The computing system of claim 1 , wherein the bus switch is operable to communicatively couple the at least one peripheral device socket to the at least one processing resource such that each peripheral device of the computing system is communication ...

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Номер записи: 61
28-01-2016 дата публикации

SYSTEMS, DEVICES, AND METHODS FOR SELECTIVE COMMUNICATION THROUGH AN ELECTRICAL CONNECTOR

Номер: US20160026596A1
Автор: Klein Dean A.
Принадлежит:

Electrical systems and related methods are disclosed. An electrical system comprises an electronic device configured to communicate through an electrical connector using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the electrical connector from a another electronic device. The other electronic device is configured to provide a protocol indicator that indicates a particular communication protocol with which the other electronic device is configured to communicate through an electrical connector of the electronic device. A method includes receiving a protocol indicator from another electronic device through an electrical connector. The protocol indicator indicates a communication protocol. The method also includes communicating with the other electronic device through the electrical connector using the indicated communication protocol. 1. An electrical system , comprising an electronic device configured to communicate through a memory socket using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the memory socket from another electronic device.2. The electrical system of claim 1 , wherein the electronic device includes a computer interface board comprising the memory socket and a central processing unit (CPU).3. The electrical system of claim 2 , wherein the computer interface board further comprises a chipset programmed to receive the indication of the one of the plurality of different communication protocols and activate a communication module corresponding to the one of the plurality of different communication protocols.4. The electrical system of claim 1 , wherein the memory socket comprises a dual in-line memory module (DIMM) socket.5. The electrical system of claim 1 , wherein the plurality of different communication protocols ...

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Номер записи: 62
28-01-2016 дата публикации

MODE SELECTIVE BALANCED ENCODED INTERCONNECT

Номер: US20160026597A1
Автор: Falconer Maynard C., Hall Stephen H., Leddige Michael W., Oluwafemi Olufemi B., Sreerama Chaitanya, Zenteno Ramirez Antonio
Принадлежит:

An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix. 1. An apparatus , comprising:a plurality of conductors, wherein at least one conductor is a common-mode conductor;an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is to be limited and a data speed of other conductors is to be maximized according to an encoding matrix.2. The apparatus of claim 1 , wherein the other conductors have a balanced encoding from the encoding matrix.3. The apparatus of claim 1 , wherein the common-mode conductor corresponds to all positive or all negative weights in the encoding matrix.4. The apparatus of claim 1 , wherein the common-mode conductor is limited according to a routing density of the plurality of conductors.5. The apparatus of claim 1 , wherein a nibble-to-nibble spacing of the plurality of conductors is equal to spacing between each conductor of the plurality of conductors.6. The apparatus of claim 1 , comprising a signaling module claim 1 , wherein the signaling module is coupled to a plurality of digital inputs.7. The apparatus of claim 1 , wherein the plurality of conductors are routed on packages claim 1 , printed circuit boards (PCBs) claim 1 , multi-chip modules (MCMs) claim 1 , multi-chip packages (MCPs) claim 1 , or any combination thereof.8. An electronic device claim 1 , comprising:a bus comprising a plurality of signal lines, where at least one signal line is a common-mode signal line;an encoder to encode data to be transmitted on the bus, wherein a data speed of the common-mode signal line is limited and a data speed of other signal lines is maximized ...

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Номер записи: 63
28-01-2016 дата публикации

STORAGE CONTROL DEVICES AND INVOKING METHOD THEREOF

Номер: US20160026598A1
Автор: ZHAO WEI-GUO
Принадлежит:

A storage control device comprises a storage control module and a memory module. The storage control module is coupled between a central processing unit and a plurality of hard disk drives. The memory module is coupled with the storage control module and keeps a plurality of configuration files and a firmware for being executed by the storage control module. In one embodiment, the storage control module comprises at least one general-purpose input/output (GPIO) port and selects, according to whether the GPIO port is at a logical high or low electric potential, one of the configuration files to configure the firmware. The selected configuration file is invoked from a memory area of the memory module. In one embodiment, the storage control device further comprises at least one jumper point and selects, according to an open/close status of the jumper point, one of the configuration files to configure the firmware. 1. An invoking method for a storage control device to invoke a configuration file of the storage control device , the storage control device comprising a memory module and at least one general-purpose input/output (GPIO) port , the invoking method comprising:determining whether the GPIO port is at a logical high electric potential or a logical low electric potential to generate a result; andselecting according to the result to invoke the configuration file from one of a plurality of memory areas of the memory module;wherein the storage control device is based on Serial Attached SCSI.2. A storage control device , comprising:a storage control module comprising at least one general-purpose input/output (GPIO) port and coupled between a central processing unit and a plurality of hard disk drives; anda memory module coupled with the storage control module and keeping a plurality of configuration files and a firmware, the firmware adapted for being executed by the storage control module;wherein the storage control module selects, according to whether the at least ...

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Номер записи: 64
28-01-2016 дата публикации

Method and System for Communication of Device Information

Номер: US20160026602A1
Автор: Narayana Srilatha, Venkatasubba Karthik
Принадлежит:

The system comprises a device, the device comprising a physical port. The device is configured to communicate with a controller through a communication medium. The controller is situated on a circuit board. The physical port is not configured to communicate with the communication medium. The device is also configured to communicate with a processor through the circuit board, but the physical port is not configured to communicate with the processor through the circuit board. The device is additionally configured to create a first packet comprising information corresponding to first device information. The first device information is formatted in a protocol associated with the physical port. The device is further configured to transmit the first packet to the controller through the communication medium. 1. A system , comprising: communicate with a controller through a communication medium, the controller situated on a circuit board, the physical port is not configured to communicate with the communication medium;', 'communicate with a processor through the circuit board, the physical port is not configured to communicate with the processor through the circuit board;', 'create a first packet comprising information corresponding to first device information, the first device information formatted in a protocol associated with the physical port; and', 'transmit the first packet to the controller through the communication medium., 'a device, the device comprising a physical port, the device configured to2. The system of claim 1 , wherein the device is further configured to:receive a second packet from the controller through the communication medium;extract second device information from the second packet, the second device information formatted in a protocol associated with the physical port, the second device information comprising a command; andprocess the second device information.3. The system of claim 1 , wherein the communication medium is selected from the group ...

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Номер записи: 65
22-01-2015 дата публикации

Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits

Номер: US20150026373A1
Автор: Chu William W. Y.
Принадлежит: ACQIS LLC

A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. 1. A computer , comprising:an integrated central processing unit and interface controller in a single chip;a first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller to convey address bits, data bits, and byte enable information bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial bit stream, wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; anda system memory directly coupled to the integrated central processing unit and interface controller.2. The computer of claim 1 , wherein the interface controller further comprises Phase-Locked Loop (PLL) clock circuitry capable of generating different clock frequencies; andwherein the interface controller configures the first LVDS channel to convey the PCI bus transaction at different data transfer rates based on the different clock frequencies generated by the PLL clock circuitry.3. The computer of claim 2 , wherein the interface controller configures the first LVDS channel with different numbers of unidirectional differential signal pairs to ...

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Номер записи: 66
10-02-2022 дата публикации

METHOD, APPARATUS, DEVICE AND SYSTEM FOR CAPTURING TRACE OF NVME HARD DISC

Номер: US20220043728A1
Автор: Sun Yixin
Принадлежит:

A system for capturing a trace of an NVME hard disc can include a BMC, a BIOS, a protocol analysis instrument, and a fixture plate comprising a processor and a dial switch. The BIOS is configured to acquire register error information of the PCIe link when an error occurs to a PCIe link where the NVME hard disc is located, and send the register error information to the BMC, and the BMC is configured to send the received information to the fixture plate, and the fixture plate is configured to trigger the protocol analysis instrument to capture a PCIe trace of the NVME hard disc when a current error type corresponding to the dial switch is consistent with the error type of the register error information parsed by a processor of the fixture plate. 1. A system for capturing a trace of a Non-Volatile Memory Express (NVME) hard disc , the system comprising:a Baseboard Management Controller (BMC);a Basic Input Output System (BIOS);a fixture plate; anda protocol analysis instrument, wherein the BMC is connected with the fixture plate and the BIOS, respectively, and the fixture plate is connected with the protocol analysis instrument;wherein the BIOS is configured to acquire register error information of a peripheral component interconnect express (PCIe) link in which the NVME hard disc is located, and send the register error information to the BMC when an error occurs in the PCIe link;and the BMC is configured to send the register error information to the fixture plate; andwherein the fixture plate comprises a processor and a dial switch, and is configured to trigger the protocol analysis instrument to capture a PCIe trace of the NVME hard disc when a current error type corresponding to the dial switch is consistent with an error type of the register error information parsed by the processor.2. The system of claim 1 , wherein a Basic Input Output System (GPIO) pin of the fixture plate is connected with a trigger connector of the protocol analysis instrument claim 1 , andthe ...

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Номер записи: 67
28-01-2021 дата публикации

Methods and apparatus for boot time reduction in a processor and programmable logic device enviroment

Номер: US20210026652A1
Автор: Tung Lun Loo, Vincent Zimmer, Yah Wen Ho
Принадлежит: Intel Corp

Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

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Номер записи: 68
28-01-2021 дата публикации

STORAGE DEVICE AUTHENTICATED MODIFICATION

Номер: US20210028942A1
Автор: Dover Lance W.
Принадлежит:

Devices and techniques for authenticated modification of a storage device are described herein. A data transmission, received at an interface of the storage device, can be decoded to obtain a command, a set of input identifications, and a first signature corresponding to data identified by the input identifications. Members of the set of input identifications can be marshalled to produce an input set. A cryptographic engine of the storage device can be invoked on the input set to produce a second signature from the input set. The first signature is and the second signature are compared to determine a match. In response to the match, the input set can be written to a secure portion of the storage device. 1. A storage device that implements an authenticated modify , the storage device comprising:a cryptographic engine;an interface;a decoder to parse a command, a set of input identifications, and a first signature from a data transmission received at the interface; and collect members of the set of input identifications to produce an input set;', 'instruct the cryptographic engine to produce a second signature from the input set;', 'compare the first signature and the second signature to determine a match; and', 'write the input set to a secure portion of the storage device in response to the match., 'a controller to2. The storage device of claim 1 , wherein the set of input identifications define an address range of an unsecure portion of the storage device.3. The storage device of claim 1 , wherein the data transmission includes an identification of the secure portion.4. The storage device of claim 1 , wherein the secure portion of the storage device is readable to an external entity via the interface to the storage device.5. The storage device of claim 4 , wherein the controller is to create a third signature of the secure portion in response to a read operation.6. The storage device of claim 5 , wherein the controller is to provide the third signature to the ...

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Номер записи: 69
29-01-2015 дата публикации

MANAGING DATA COMMUNICATION BETWEEN A PERIPHERAL DEVICE AND A HOST

Номер: US20150032920A1
Автор: Caballero Aldo
Принадлежит:

Management of data communication between a peripheral device and host computer system is provided. A peripheral device exposes to a host computer system multiple interfaces for data communication between the peripheral device and the host computer system. The multiple interfaces are exposed over a single physical interface between the peripheral device and the host computer system, for communicating data between the peripheral device and multiple applications executing on the host computer system. The multiple interfaces can include a data collection interface facilitating collection of data from the peripheral device by an application of the multiple applications executing on the host computer system. 1. A method for managing data communication , comprising:exposing, using a processor of a peripheral device, multiple interfaces for data communication between the peripheral device and multiple applications executing on a host computer system over a single physical interface;wherein the multiple applications executing on the host computer system comprise a management application; andwherein the multiple interfaces comprise a dedicated management interface facilitating management of the peripheral device by the management application.2. The method of claim 1 , wherein:the multiple applications executing on the host computer system comprise a line of business application;the multiple interfaces comprise a line of business interface for data communication between the peripheral device and the line of business application; andthe dedicated management interface and the line of business interface are exposed separately to the host computer system to facilitate peripheral device management across the dedicated management interface in parallel with data collection across the line of business interface by the line of business application.3. The method of claim 1 , wherein the peripheral device is selectably configurable to expose any of the multiple interfaces to the host ...

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Номер записи: 70
29-01-2015 дата публикации

COUPLING DEVICE AND METHOD FOR DYNAMICALLY ALLOCATING USB ENDPOINTS OF A USB INTERFACE, AND EXCHANGE TRADING SYSTEM TERMINAL WITH COUPLING DEVICE

Номер: US20150032923A1
Автор: Albert Elmar, Selmeczi Andras
Принадлежит: Unify GmbH & Co. KG

The invention relates to a method and a coupling device () for dynamically allocating USB endpoints () of a USB interface (), which can be accessed using at least two applications, comprising: a USB interface () that has at least two ports (P P P), each of which comprises at least one USB endpoint (); and a control device () for dynamically allocating the USB endpoints (). The control device is designed so as to preconfigure each USB endpoint () which is required for the at least two applications by means of an initialization process, and thus the control device can switch the allocation of the endpoints according to the access using at least one of the applications without the USB endpoints () affected by the switch having to be deactivated. 1103132333430. Coupling device () for dynamic allocation of USB endpoints ( , , , ) of a USB interface () , which can be accessed by at least two applications , comprising:{'b': 30', '0', '2', '4', '31', '32', '33', '34, 'a USB interface () with at least two ports (P, P, P) each comprising at least one USB endpoint (, , , ),'}{'b': 20', '31', '32', '33', '34', '31', '32', '33', '34', '31', '32', '33', '34, 'a control element () for dynamic allocation of the USB endpoints (, , , ), which allows for preconfiguring and initializing the USB endpoints (, , , ), which are used for at least two applications. Therefore the access can be switched by at least one of the applications without deactivating the relevant USB endpoints (, , , ).'}210. Coupling device () according to claim 1 ,{'b': '4', 'characterized in that at least one of the ports (P) is bidirectional.'}310. Coupling device () according to claim 1 ,{'b': '20', 'characterized in that the control device () is designed so that it can perform the dynamic switching without having to rerun an enumeration process.'}410. Coupling device () according to claim 1 ,characterized in that it comprises an audio device which includes at least one loudspeaker, and preferably a microphone. ...

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Номер записи: 71
29-01-2015 дата публикации

Handling Atomic Operations For A Non-Coherent Device

Номер: US20150032924A1
Автор: Saripalli Ramakrishna
Принадлежит:

In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed. 1. A root complex comprising:receive logic configured to couple to a non-coherent link that is to couple to a device, the receive logic to receive from the device an incoming transaction that is to reference a non-coherent atomic operation;translation logic to map the non-coherent atomic operation to a coherent atomic operation in response to the receipt of the incoming transaction; andtransmit logic configured to be coupled to a coherent link, the transmit logic to transmit an outgoing transaction that is to reference the coherent atomic operation to a processor that is to couple to the coherent link, in response to the translation logic mapping the non-coherent atomic operation to the coherent atomic operation, wherein the non-coherent atomic operation is of a protocol that calls for the root complex to be the completer of the incoming transaction.2. The root complex of claim 1 , wherein the non-coherent link is a Peripheral Component Interconnect Express (PCIe™) compliant link.3. The root complex of claim 1 , wherein the coherent link is a Quick Path Interconnect (QPI) compliant link.4. The root complex of claim 1 , wherein the translation logic includes a mapping table having a plurality of entries each to map a non-coherent transaction to a coherent transaction claim 1 , at least some of the entries including a mapping between a non-coherent atomic operation code and a corresponding coherent atomic operation code.5. The root complex of claim 4 , wherein the root ...

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Номер записи: 72
29-01-2015 дата публикации

APPARATUS, ELECTRONIC DEVICES AND METHODS ASSOCIATED WITH AN OPERATIVE TRANSITION FROM A FIRST INTERFACE TO A SECOND INTERFACE

Номер: US20150032927A1
Автор: Albini Giulio, Confalonieri Emanuele
Принадлежит:

Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes. 125-. (canceled)26. An apparatus comprising:memory; anda controller configured to determine a locking state of a block of the memory associated with a first interface based on a locking state of the block of the memory associated with a second interface,wherein locking states of the first interface comprise a locked down state, wherein the locked down state of the first interface is based on a write protect logic state, andwherein locking states of the second interface comprise a locked down state, wherein the locked down state of the second interface is not based on the write protect logic state.27. The apparatus of claim 26 , wherein the locking state associated with the first interface has a different associated locking bit from the locking state of the second interface claim 26 , the different locking bit associated with the write protect logic state.28. The apparatus of claim 26 , wherein the controller is further configured to determine the locking state associated with the first interface responsive to an operative transition from the second interface to the first interface.29. The apparatus of claim 26 , wherein the controller is further configured to determine the locking state based on a priority scheme associated with at least one of the interfaces.30. The apparatus of claim 26 , further comprising:a register,wherein the controller is further configured to selectively program at least a portion of the register to indicate the locking state associated with the first interface.31. The apparatus of claim 26 , wherein the controller is further configured to: ...

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Номер записи: 73
04-02-2016 дата публикации

Physical Layer for Peripheral Interconnect with Reduced Power and Area

Номер: US20160034025A1
Автор: Dabral Sanjay, Polzin R. Stephen
Принадлежит:

An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments. 1. An integrated circuit having a peripheral interconnect to communicate with a peripheral device according to an industry standard specification , the integrated circuit comprising:a controller circuit configured to provide a media access control layer interface to the peripheral interconnect that complies with the industry standard specification; and drive and receive signals on the peripheral interconnect; and', 'drive an idle symbol on the signals when the peripheral interface is idle using a single non-toggling idle symbol in place of at least two alternating idle symbols specified by the industry standard specification., 'a physical interface layer circuit coupled to the controller circuit, wherein the physical interface layer circuit is configured to2. The integrated circuit as recited in wherein the physical layer interface circuit implements single-ended signaling for the signals on the peripheral interface.3. The integrated circuit as recited in wherein the single-ended signaling includes a clock to which the signals are referenced.4. The integrated circuit as recited in wherein the single-ended signaling includes a strobe to which the signals are referenced.5. The integrated circuit as recited in further comprising a second physical ...

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Номер записи: 74
04-02-2016 дата публикации

SYSTEM-ON-CHIP AND DRIVING METHOD THEREOF

Номер: US20160034409A1
Автор: KIM WOO-JIN, LEE HEE-SEONG, SEONG NAK-HEE
Принадлежит:

A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO. 1. A system-on-chip (SoC) , comprising:a master;a slave; andan asynchronous interface having a first-in first-out (FIFO) memory connected to the master and the slave, wherein a write operation of the FIFO memory is controlled based on a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based on a comparison of a read pointer and an expected read pointer of the FIFO memory.2. The system-on-chip of claim 1 , wherein the FIFO memory comprises a first FIFO and a second FIFO claim 1 , and the asynchronous interface comprises a slave interface and a master interface claim 1 , wherein the slave interface comprises a slave transmitter claim 1 , a slave clock domain crossing (CDC) block having the first FIFO and a slave receiver claim 1 , the master interface comprises a master transmitter claim 1 , a master clock domain crossing (CDC) block having the second FIFO connected to the master and the slave claim 1 , and a master receiver.3. The system-on-chip of claim 2 , wherein the asynchronous interface is configured to generate a write enable signal to control the write operation of the FIFO memory based on the comparison result of the write pointer and the expected write pointer.4. The system-on-chip of claim 3 , wherein the FIFO memory is configured to store data at an address pointed by the write pointer when the write enable signal is activated.5. The system-on-chip of claim 2 , wherein the asynchronous interface generates a read enable signal ...

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Номер записи: 75
04-02-2016 дата публикации

PCI EXPRESS CLUSTER

Номер: US20160034412A1
Автор: FELDMAN BORIS, FELDMAN Michael
Принадлежит:

PCI Express Cluster dedicated for system expansion through installation of up to four high-performance PCI Express boards (example: graphics processing units—GPU). 1. A PCI Express Cluster comprising a backplane , a cluster power supply and a chassis;said backplane comprises a printed circuit board (PCB), a power connector to connect said backplane to an cluster power supply; a control unit and four PCI Express connectors intended for installing high-performance PCI Express boards; said backplane wherein:(a) said four PCI Express connectors are mounted on said PCB in parallel to each other;(b) two of four said PCI Express connectors are mounted on the top side of said PCB, and other two of four said PCI Express connectors are mounted on the bottom side of said PCB:(c) each two of said four PCI Express connectors that are mounted on one side of said PCB (top or bottom) are oriented to opposite each other directions along said PCB;(d) said four PCI Express connectors are oriented, thereby that all component sides of said our PCI Express boards, in case when said boards are inserted into said PCI Express connectors, will he directed outward.2. The cluster according to claim 1 , wherein an arrangement of said PCI Express connectors on said backplane and said chassis is adapted for easy installation of said high-performance PCI Express boards chosen from the group claim 1 , including at least the followings: GPU hoards claim 1 , Video boards claim 1 , Special data processing boards claim 1 , Motherboard in PCI Express hoard form factor.3. The cluster according to claim 1 , wherein said chassis comprises two sections claim 1 , each of which includes at least three shelves: lower claim 1 , middle and top shelves claim 1 , located on three different levels and three said shelves in each section are parallel to each other and connected in series like an incremental staircase;said cluster, comprising said chassis, wherein said outer shelves (lower and top) belonging to said ...

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Номер записи: 76
01-02-2018 дата публикации

CONTROL CIRCUIT BOARD, MICRO-SERVER, CONTROL SYSTEM AND CONTROL METHOD THEREOF

Номер: US20180032461A1
Автор: Zhang Song
Принадлежит:

A control system includes a host device, a plurality of computing nodes of micro-servers, a first switch and a first processor. The first switch is electrically connected to the plurality of computing nodes of micro-servers and the host device. The first processor is electrically connected to the plurality of computing nodes of micro-servers, the host device and the first switch. The first processor is configured to process a first GPIO signal provided by the host device and generate a first control command according to the result of processing the first GPIO signal. The first processor selectively turns on the data path from the first switch to one of the plurality of computing nodes of micro-servers and sends a second GPIO signal to one of the plurality of computing nodes of micro-servers. 1. A control circuit board , comprising:a host device providing a first general purpose input/output (GPIO) signal;a first switch electrically connected to the host device; anda first processor electrically connected to the first switch and the host device, processing the first GPIO signal, generating a first control command according to a result of processing the first GPIO signal, and selectively conduct a data path from the first switch to one of a plurality of computing nodes of a micro-server according to the first control command.2. The control circuit board according to claim 1 , wherein the result of processing the first GPIO signal includes a code claim 1 , the first processor distinguishes one of the plurality of computing nodes and generates the first control command according to the code.3. A micro-server claim 1 , comprising: a plurality of baseboard management controllers;', 'a second switch electrically connected to the plurality of baseboard management controllers; and', 'a second processor electrically connected to the second switch, processing a second GPIO signal, generating a second control command according to a result of processing the second GPIO signal, ...

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Номер записи: 77
01-02-2018 дата публикации

APPARATUS AND METHOD FOR IDENTIFYING AND MANAGING INPUT/OUTPUT (I/O) CHANNEL SPARES FOR CONTROL AND INSTRUMENTATION SYSTEMS IN INDUSTRIAL PLANTS

Номер: US20180032468A1
Автор: Dutta Manas, Ganapathi Ramakrishnan, Nikhra Abhishek
Принадлежит:

A method includes identifying input/output (I/O) channels in a control and instrumentation system associated with an industrial plant. The method also includes identifying which of the I/O channels are not in use by the control and instrumentation system. The method further includes generating a graphical user interface identifying the I/O channels not in use by the control and instrumentation system. An indication that at least one I/O channel not in use by the control and instrumentation system is being reserved for use could be received, and the at least one I/O channel can be reserved. An indication that at least one I/O channel in use by the control and instrumentation system is now not in use by the control and instrumentation system could also be received, and the at least one I/O channel could be released so the at least one I/O channel is available for reservation or other use. 1. A method comprising:identifying input/output (I/O) channels in a control and instrumentation system associated with an industrial plant;identifying which of the I/O channels are not in use by the control and instrumentation system; andgenerating a graphical user interface identifying the I/O channels not in use by the control and instrumentation system.2. The method of claim 1 , further comprising:receiving, via the graphical user interface, an indication that at least one of the I/O channels not in use by the control and instrumentation system is being reserved for use; andreserving the at least one I/O channel3. The method of claim 2 , further comprising:receiving, via the graphical user interface, at least one of a project and a comment associated with the at least one I/O channel being reserved for use; andassociating the at least one the project and the comment with the at least one I/O channel.4. The method of claim 1 , further comprising:receiving, via the graphical user interface, an indication that at least one of the I/O channels in use by the control and instrumentation ...

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Номер записи: 78
17-02-2022 дата публикации

METHOD AND SYSTEM FOR PERFORMING READ/WRITE OPERATION WITHIN A COMPUTING SYSTEM HOSTING NON-VOLATILE MEMORY

Номер: US20220050770A1
Автор: Das Purkayastha Saugata, VISHNOI Suresh
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method for performing a write operation includes selecting, by a host, at least a free write buffer from a plurality of write buffers of a shared memory buffer (SMB) by accessing a cache structure within the SMB for tracking the free write buffer; sending, by the host, at least a logical address accessed from the cache structure with respect to the selected write buffer to issue a write-command to a non-volatile memory; receiving a locking instruction of the selected write buffer from the non-volatile memory; updating a status of the selected write buffer within the cache structure based on the received locking instruction; and allowing the non-volatile memory to extract contents of one or more locked write buffers including the selected write buffer. 1. A method for performing a write operation , the method comprising:selecting, by a host, at least a free write buffer from a plurality of write buffers of a shared memory buffer (SMB) by accessing a cache structure within the SMB for tracking the free write buffer;sending, by the host, at least a logical address accessed from the cache structure with respect to the selected write buffer to issue a write-command to a non-volatile memory;receiving a locking instruction of the selected write buffer from the non-volatile memory;updating a status of the selected write buffer within the cache structure based on the received locking instruction; andallowing the non-volatile memory to extract contents of one or more locked write buffers including the selected write buffer.2. The method of claim 1 , wherein selecting of at least one free write buffer from the plurality of write buffers includes initializing the selected write buffer.3. The method of claim 1 , wherein the cache structure is a data structure for tracking a logical address of data and statuses within the plurality of write buffers claim 1 , the data structure including claim 1 , for each write buffer claim 1 , an entry includinga logical block address (LBA) of ...

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Номер записи: 79
17-02-2022 дата публикации

INTER-DEVICE PROCESSING SYSTEM WITH CACHE COHERENCY

Номер: US20220050786A1
Автор: Chen Yen-Kuang, DUAN Lide, Liu Hongyu, Zheng Hongzhong
Принадлежит:

The devices within an inter-device processing system maintain data coherency in the last level caches of the system as a cache line of data is shared between the devices by utilizing a directory in one of the devices that tracks the coherency protocol states of the memory addresses in the last level caches of the system. 1. A processing system comprising:a first device having a first cache, the first device to output a first request to read requested data associated with a memory address when the first cache of the first device does not have a valid version of the requested data;a second device coupled to the first device, the second device having a coherence directory, the second device to check the coherence directory in response to the first request and, when the coherence directory indicates that no device has a cache line with a valid copy of the requested data, output a first fetch command to fetch data, the first request being output by the first device to only the second device; anda third device coupled to the first and second devices, the third device having a third cache and a non-cache memory, the third device to output the requested data to only the second device from the non-cache memory in response to the first fetch command,wherein the second device to forward the requested data to the first device, and update a coherence status of the memory address in the coherence directory from invalid to shared to indicate that the first device shares a copy of the requested data.2. The processing system of claim 1 , wherein the first device updates a coherence status from invalid to shared to indicate that the first device shares a valid copy of the requested data.3. The processing system of claim 1 , further comprising a fourth device having a fourth cache claim 1 , the fourth device to output a second request to only the second device to read the requested data associated with the memory address when the fourth cache of the fourth device does not have a valid ...

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Номер записи: 80
30-01-2020 дата публикации

FAST PROTECTION SWITCHING IN DISTRIBUTED SYSTEMS

Номер: US20200033910A1
Автор: Baidas Zaher, den Broeder Ernst JG, Goldin Leonid
Принадлежит:

A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal. 1. A method of switching timing cards , comprising:receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card;receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card;producing a clock signal from the first pulse-width modulated clock signal; andswitching to producing the clock signal from the second pulse-width modulated clock signal based on the information encoded in the first pulse-width modulated clock signal.2. The method of claim 1 , wherein the information regarding the status of the first line card includes one or more of loss of signal claim 1 , loss of connection claim 1 , and frequency offset.3. The method of claim 1 , further including providing a GPIO output signal from data received on one or more of the first pulse-width modulated clock signal and the second pulse-width modulated clock signal.4. A timing card claim 1 , comprising:a ...

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Номер записи: 81
30-01-2020 дата публикации

STORAGE RESERVATION POOLS FOR VIRTUAL INFRASTRUCTURE

Номер: US20200034179A1
Автор: BUDIGERE VIJAYA KUMAR KAUSHIK, DUBEY ANKIT, HAJARE APURVA, PATEL AKANKSHA, SATTIRAJU AKHIL RAM SAi, VAIDYA ANKIT
Принадлежит:

A method to allocate storage includes assigning a quota on space from a storage reservation pool, allocating an epoch specific storage space to a virtual disk, creating a memory map for the virtual disk to track used space. For every write to the virtual disk during an epoch, the method includes updating the memory map, determining if the used space is greater than a threshold of the epoch specific storage space based on the memory map. When the used space is greater than the threshold, the method includes predicting additional space for future writes to the virtual disk in the epoch, determining if the additional space is available from the storage reservation pool, and, when the additional space is available, increasing the epoch specific storage and proceeding with the write to the virtual disk. 1: A method for a computing system to allocate storage from a storage reservation pool to virtual disks of virtual machines , the method comprising:assigning a quota on available space from the storage reservation pool;adding the virtual disks to the storage reservation pool; allocating an epoch specific storage space to the virtual disk based on the available space in the storage reservation pool;', 'creating a memory map for the virtual disk to track space used by the virtual disk;', updating the memory map with information about the write request, including a write location and an amount of data written;', 'based on the memory map and without querying the storage reservation pool, determining if the used space consumed by the virtual disk is greater than a threshold of the epoch specific storage space; and', predicting additional space that will be consumed by future writes to the virtual disk in the epoch;', 'determining if the additional space is available from the storage reservation pool; and', 'when the additional space is available from the storage reservation pool:', 'increasing the epoch specific storage space by the additional space; and', 'proceeding with the ...

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Номер записи: 82
05-02-2015 дата публикации

NETWORK INTERFACE CARD FOR A COMPUTING NODE OF A PARALLEL COMPUTER ACCELERATED BY GENERAL PURPOSE GRAPHICS PROCESSING UNITS, AND RELATED INTER-NODE COMMUNICATION METHOD

Номер: US20150039793A1
Автор: Rossetti Davide
Принадлежит:

A Network Interface Card (NIC) for a cluster node for parallel calculation on multi-core GPU is described. The NIC has a cluster network including a host and a host memory, a graphics processing unit (GPU) with a GPU memory, a bus and the NIC. The NIC has a transmission network connection block and a reception network connection block. The NIC further includes the following blocks: a transmission block, a reception block, and a GPU memory management block for a direct exchange between the GPU memory and the network through the NIC. An inter-nodal communication method of a nodes cluster, which uses the NIC is also described. 1. A Network Interface Card (NIC) for parallel calculation of a cluster node on multi-core Graphical Processing Units (GPU) , the cluster node including a host and a host memory , whereon a calculation application can be installed , a GPU with a GPU memory , a bus and the NIC , the NIC comprising:a transmission network connection block,a reception network connection block,a transmission block which comprises means configured to receive data from the GPU memory and metadata from the host through said bus, and to route the data towards said transmission network connection block;a reception block, which comprises means configured to receive data from said reception network connection block and to provide the data to the GPU memory through said bus, anda GPU memory management block, which comprises means configured to send metadata to the GPU to control the reading or writing of data from/into the memory of the same GPU, on the basis of metadata received respectively from said reception block or said transmission block,wherein realizing a direct exchange between the GPU memory and a network through the NIC, and avoiding passing data through the host.2. The Network Interface Card according to claim 1 , further comprising an events queue management block claim 1 , which comprises a circular memory buffer configured to write events queues in said host ...

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Номер записи: 83
05-02-2015 дата публикации

PCI Express Data Transmission

Номер: US20150039804A1
Автор: LEI Chuan Hua, Volkening Ingo, Xu Bing Tao
Принадлежит:

PCIe devices and corresponding methods are provided wherein a length of data to be transferred is aligned to a multiple of a double word length. 1. A Peripheral Component Interconnect express (PCIe) device , comprising:a transfer adjustment device adapted to align a length of data to be transferred via a PCIe link to a multiple of a double word (DWORD) length.2. The device of claim 1 , wherein the transfer adjustment device is adapted to operate above a transaction layer of the PCIe device.3. The device of claim 1 , wherein the device comprises a PCIe endpoint device.4. The device of claim 1 , wherein aligning the length comprises modifying a descriptor.5. The device of claim 4 , wherein the transfer adjustment device is adapted to adjust the descriptor to an original length of the data after the transfer claim 4 , and provide the adjusted descriptor for further processing of the data after the transfer.6. The device of claim 1 , wherein the device comprises a direct memory access (DMA) device adapted to perform the transfer based on the aligned length.7. The device of claim 1 , wherein the transfer adjustment device is adapted to align the length by adding a number of dummy bytes to data to be transferred.8. The device of claim 7 , wherein the number of dummy bytes is between 1 and 3.9. The device of claim 1 , wherein the aligning comprises dynamically aligning the length of data to be transferred via a PCIe link to the multiple of a double word (DWORD) length.10. A method claim 1 , comprising:in a Peripheral Component Interconnect express device, aligning a length of data to be transferred to an integer multiple of a double word (DWORD) length.11. The method of claim 10 , wherein the aligning comprises modifying a descriptor.12. The method of claim 11 , wherein the method comprises transferring the data based on the modified descriptor.13. The method of claim 12 , further comprising claim 12 , after the transferring claim 12 , adjusting the modified descriptor to ...

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Номер записи: 84
04-02-2021 дата публикации

Universal Bracket for Multiple Form Factors of PCIe Cards in OCP Sled Environments

Номер: US20210034097A1
Автор: JANGILI GANGA Siva Prasad, Madsen Christopher M.
Принадлежит:

A universal bracket includes a first wall, a second wall, and a third wall. The first wall is configured to be fixed to a first circuit card and a second circuit card. The first circuit card and the second circuit card include any of at least two different standardized types of circuit cards. The second wall is opposite the first wall. The third wall extends between the first wall and the second wall and is configured to be fixed to a riser card having a first connector for receiving a first mating connector of the first circuit card and a second connector for receiving a second mating connector of the second circuit card. 1. A universal bracket comprising:a first wall configured to be fixed to a first circuit card and a second circuit card, wherein the first circuit card and the second circuit card include any of at least two different standardized types of circuit cards;a second wall opposite the first wall; anda third wall extending between the first wall and the second wall and being configured to be fixed to a riser card having a first connector for receiving a first mating connector of the first circuit card and a second connector for receiving a second mating connector of the second circuit card.2. The universal bracket of claim 1 , wherein the at least two different standardized types of circuit cards includes six standardized circuit cards and the first and second circuit cards are selected from a group including a half-length low-profile PCIe card claim 1 , a three-quarter-length low-profile PCIe card claim 1 , a full-length low-profile PCIe card claim 1 , a half-length standard-profile PCIe card claim 1 , a three-quarter-length standard-profile PCIe card claim 1 , or a full-length standard-profile PCIe card.3. The universal bracket of claim 1 , wherein at least one of the first circuit card and the second circuit card includes a full-length PCIe card and the full-length PCIe card engages the second wall.4. The universal bracket of claim 3 , wherein the ...

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Номер записи: 85
04-02-2021 дата публикации

IMPLEMENTING MANAGEMENT COMMANDS UTILIZING AN IN-BAND INTERFACE

Номер: US20210034548A1
Автор: Jesionowski Lee, Peipelman Jason L.
Принадлежит:

A computer-implemented method according to one embodiment includes receiving, at a peripheral device via an in-band interface, a predetermined command; determining, by the peripheral device, a predetermined identifier within the predetermined command; and implementing, by the peripheral device, parameter data associated with the predetermined identifier, in response to the determining. 1. A computer-implemented method , comprising:receiving, at a peripheral device via a fiber channel transport layer, a predetermined command, where the peripheral device includes a data storage device; a predetermined identifier indicating that one or more management actions are to be performed within the peripheral device, and', 'parameter data including the one or more management actions; performing, by the peripheral device, the one or more management actions; and, 'identifying, by the peripheral device within the predetermined commandlogging the parameter data in association with the predetermined identifier.2. The computer-implemented method of claim 1 , wherein the predetermined command is received from a computing device separate from the peripheral device.3. The computer-implemented method of claim 1 , wherein:the predetermined command is in ASCII text,the predetermined command is received by the peripheral device as a command descriptor block (CDB),the parameter data includes a request for a physical status of the peripheral device, andthe parameter data is created utilizing a representational state transfer (REST) application programming interface (API).4. The computer-implemented method of claim 1 , further comprising sending a confirmation and results of the one or more management actions to a computing device; wherein:the predetermined command is in ASCII text,the parameter data includes arguments in an extensible markup language (XML) format.5. The computer-implemented method of claim 1 , wherein the predetermined command includes a SCSI write buffer command or a SCSI ...

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Номер записи: 86
04-02-2021 дата публикации

Secure Collaboration Between Processors And Processing Accelerators In Enclaves

Номер: US20210034788A1
Автор: Northup Eric, Savagaonkar Uday
Принадлежит: Google LLC

Aspects of the disclosure relate to providing a secure collaboration between one or more PCIe accelerators and an enclave. An example system may include a PCIe accelerator apparatus. The PCIs accelerator apparatus may include the one or more PCIe accelerators and a microcontroller configured to provide a cryptographic identity to the PCIe accelerator apparatus. The PCIe accelerator apparatus may be configured to use the cryptographic identity to establish communication between the PCIe accelerator apparatus the enclave. 1. A system for providing a secure collaboration between one or more PCIe accelerators and an enclave , the system comprising: the one or more PCIe accelerators; and', 'a microcontroller configured to provide a cryptographic identity to the PCIe accelerator apparatus, wherein the PCIe accelerator apparatus is configured to use the cryptographic identity to establish communication between the PCIe accelerator apparatus the enclave., 'an PCIe accelerator apparatus including2. The system of claim 1 , further comprising a circuit board on each of the one or more PCIe accelerators and the microcontroller are arranged.3. The system of claim 1 , wherein each of the one or more PCIe accelerators is a tensor processing unit.4. The system of claim 1 , wherein each of the one or more PCIe accelerators is a graphical processing unit.5. The system of claim 1 , wherein the PCIe accelerator apparatus further comprises an application processor configured to communicate with the enclave.6. The system of claim 5 , wherein the application processor is incorporated into the microcontroller.7. The system of claim 5 , wherein the application processor further includes a dedicated function for communicating with an operating system of a computing device on which the enclave resides.8. The system of claim 7 , wherein the dedicated function is configured to enable a communication path between the application processor and the enclave via the computing device.9. The system of ...

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Номер записи: 87
31-01-2019 дата публикации

DATA TRANSMISSION METHOD BETWEEN A ROTARY ENCODER AND A MOTOR CONTROL DEVICE OR AN EVUALATION UNIT

Номер: US20190036731A1
Автор: Buecher Johann, Klaiber Wolfgang, Linden Martin
Принадлежит:

Method for digital, bidirectional data transmission between a position measuring system (-) and a motor control device () and/or an evaluation unit based on the transmission of frames () of a predefined bit length in chronologically sequential time slots (-), wherein a primary master () communicates via a two wire bus line () with the position measuring system (-) and/or the motor unit () and/or the evaluation unit with a primary slave () disposed there, and that additional sub-slaves () can be coupled in parallel to the primary slave (), which sub-slaves communicate on the same bus line (), which the primary master () uses with the primary slave (). 1. Method for digital , bidirectional data transmission between a position measuring system and a motor control system and/or an evaluation unit based on the transmission of frames of a predefined bit length in chronologically sequential time slots , wherein a primary master communicates via a two wire bus line with the position measuring system and/or the motor unit and/or the evaluation unit with a primary slave disposed there , and that additional sub-slaves can be coupled in parallel to the primary slave , which sub-slaves communicate on the same bus line , which the primary master uses with the primary slave.2. Method according to claim 1 , wherein at least one sub-master is attached to the primary master on the same bus line.3. Method according to claim 1 , wherein the sub-slaves connected in parallel to the primary slave have sensor inputs and actuator outputs.4. Method according to claim 1 , wherein the sub-slaves connected in parallel to the primary slave carry out a data communication with each other via the central bus line that connects them.5. Method according to claim 1 , wherein a first sub-master is parallel to the primary master and the first sub-master communicates with an internet based or device based cloud and supplies the data generated by the primary master to the cloud.6. Method according to ...

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Номер записи: 88
11-02-2016 дата публикации

MEMORY STORAGE WITH BATTERY AND SOLAR CELLS

Номер: US20160041932A1
Автор: Hokari Toshihide
Принадлежит:

A portable storage device can include a memory and one or more connectors for connecting to other devices. During use, a user can connect a remote device such as a smartphone, tablet, or the like to the portable storage device in order to transfer data from the remote device to the memory of the portable storage device. The portable storage device can include a rechargeable power source configured to provide the necessary electrical current for establishing communication between the remote device and the memory of the portable storage device. The portable storage device can further include one or more photovoltaic devices for generating electrical energy and recharging the rechargeable power source of the portable storage device. 1. A portable storage device comprising:a memory;a rechargeable power source;a first connector connectable to a remote device and capable of providing two-way communication between the memory of the portable storage device and the remote device; anda second connector connectable to an external device and capable of providing two-way data transfer between the memory of the portable storage device and the external device and electrical current from the external device to the rechargeable power source of the portable storage device; whereinthe rechargeable power source provides electrical current to establish two-way communication between the memory of the portable storage device and the remote device when the remote device is connected to the portable storage device via the first connector.2. The portable storage device of claim 1 , further comprising one or more photovoltaic devices electrically coupled to the rechargeable power source claim 1 , wherein the one or more photovoltaic devices provide electrical energy to the rechargeable power source when light is incident on the one or more photovoltaic devices.3. The portable storage device of claim 2 , wherein the memory comprises flash memory or a hard drive.4. The portable storage device ...

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Номер записи: 89
11-02-2016 дата публикации

SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM

Номер: US20160041933A1
Автор: Amer Maher, Takefman Michael L., Trojanowski Bart
Принадлежит:

A method of implementing a multi-threaded device driver for a computer system is disclosed. According to one embodiment, a polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread. 1. A method of partitioning a polling device driver into a plurality of driver threads for controlling a device of a computer system , the method comprising:checking a first device state of the device, the first device state having an unscouted state and a scouted state;determining that the first device state of the device is in the unscouted state;changing the first state of the device to the scouted state;checking a second device state of the device, the second device state having an inactive state and an active state;determining that the second device state of the device is in the inactive state;changing the second state of the device to the active state;executing an operation on the device during a pre-determined time slot configured for a first driver thread of the plurality of driver threads; andchanging the first state of the device to the unscouted state after the pre-determined time slot expires.2. The method of claim 1 , wherein the device is in one of four device states claim 1 , wherein the four device states comprise an unscouted/inactive state claim 1 , an unscouted/active state ...

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Номер записи: 90
09-02-2017 дата публикации

COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE

Номер: US20170039156A1
Автор: Calvin James G., Parvarandeh Pirooz, Rooyakkers Albert
Принадлежит:

A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. 1. A communications control system comprising:a control module;a plurality of input/output modules coupled with the control module;a serial communications interface configured for connecting the plurality of input/output modules to the control module in parallel, the serial communications interface configured for transmitting information between the plurality of input/output modules and the control module; anda parallel communications interface configured for separately connecting the plurality of input/output modules to the control module, the parallel communications interface configured for transmitting information between the plurality of input/output modules and the control module, and transmitting information between individual ones of the plurality of input/output modules, each one of the plurality of input/output modules identifying itself to the control module using a unique identification upon connecting to the control module, the control module maintaining a routing table with the unique identification for each input/output module connected to the control module, the ...

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Номер записи: 91
09-02-2017 дата публикации

DATA PROCESSING DEVICE, DATA PROCESSING SYSTEM AND METHOD

Номер: US20170039160A1
Автор: Hashimoto Ryoji, Kaya Toshiyuki, SUGIMOTO Takahiko, Ueda Hiroshi, UNE Tomohiro
Принадлежит:

A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal. 1. A data processing device comprising:a data selector circuit that divides a group of data including a plurality of types of data into the plurality of types of data;a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data; anda data transmission circuit that transmits the plurality of types of compressed data to a terminal.2. The data processing device according to claim 1 , wherein a first compression circuit among the plurality of compression circuits compresses a first type of data among the plurality of types of data in a first format claim 1 , and a second compression circuit among the plurality of compression circuits compresses a second type of data among the plurality of types of data in a second format different from the first format.3. The data processing device according to claim 2 , wherein the first format is an irreversible compression format claim 2 , and the second format is a reversible compression format.4. The data processing device according to claim 3 , wherein the first type of data is data to be viewed by a user in the terminal claim 3 , and the second type of data is data to be computed in the terminal.5. The data processing device according to claim 1 , whereineach of the plurality of compression circuits outputs a data transmission request signal to the ...

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Номер записи: 92
08-02-2018 дата публикации

OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS

Номер: US20180039593A1
Автор: DEBBAGE Mark, Mutha Yatin M.
Принадлежит: Intel Corporation

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control. 1. A method comprising:partitioning memory space in a Programmed Input/Output (PIO) send memory into a plurality of send contexts, each send context associated with a memory buffer including a plurality of send blocks configured to store packet data;implementing a storage scheme using a First-in, First-out (FIFO) scheme for each send context under which each send block occupies a respective FIFO slot in a FIFO buffer having a FIFO order and data for a given packet is stored in one or more send blocks occupying one or more respective sequential FIFO slots in a FIFO order;filling send blocks in a send context with packet data;egressing send blocks containing filled packet data from a send context; detecting one or more FIFO slots that have been freed;', 'detecting when one or more FIFO slots that have been freed occupies a lowest slot in the FIFO order for the send context for which credit return indicia has not been ...

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Номер записи: 93
08-02-2018 дата публикации

SYSTEM, APPARATUS AND METHOD FOR EXPANDING COMMUNICATION PORT

Номер: US20180039595A1
Автор: Chang Li-Jen, Kao Kuo-Feng, Yu Hsiang-Jui
Принадлежит: ATEN INTERNATIONAL CO., LTD.

The present invention provides an apparatus for expanding a serial communication port. The apparatus includes a first serial port, a second serial port and a processing and control module. The first serial port is used to transmit a first signal, and the second serial port is used to transmit a second signal. The processing and control module is coupled between the first serial port and the second serial port. The processing and control module includes a first serial bus host controller, a second serial bus host controller, a data forwarding unit and an expansion unit. The apparatus is connected between an electronic device and multiple peripheral devices, so that via the expansion unit, each peripheral device generates its own communication port on the electronic device. 1. A serial communication expansion device , comprising:a first serial connection port, for transmitting a first signal;a second serial connection port, for transmitting a second signal; and a first serial bus host controller, coupled to the first serial connection port;', 'a second serial bus host controller, coupled to the second serial connection port;', 'a data forwarding unit, coupled between the first and second serial bus host controllers, for converting between the first signal and the second signal; and', 'an expansion unit, coupled between the first and second serial bus host controllers, wherein the expansion unit is a communication host controller., 'a processing and control module, coupled between the first serial connection port and the second serial connection port, the processing and control module comprising2. The serial communication expansion device of claim 1 , further comprising a wireless communication unit for providing at least two signal channels claim 1 , wherein the wireless communication unit includes a Bluetooth communication interface claim 1 , the first serial connection port includes a Universal Serial Bus (USB) interface claim 1 , and the second serial connection ...

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Номер записи: 94
24-02-2022 дата публикации

Command memory buffer systems and methods

Номер: US20220058137A1
Автор: Changyou Xu, FAN YANG, Lingqi Zeng, Peirong Ji
Принадлежит: PetaIO Inc

Example storage control systems and methods are described. In one implementation, a storage drive controller includes a non-volatile memory subsystem that processes multiple commands. The storage drive controller also includes a controller memory buffer (CMB) memory management unit coupled to the non-volatile memory subsystem. The CMB memory management unit manages CMB-related tasks including caching and storage of data associated with the storage drive controller.

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Номер записи: 95
12-02-2015 дата публикации

OBTAINING MULTIMEDIA DATA IN AN EXTENDED CONNECTIVITY MULTIMEDIA APPARATUS FOR PRESENTATION ON A MULTIMEDIA PRESENTATION DEVICE

Номер: US20150046608A1
Автор: DUA Robin
Принадлежит:

To present multimedia data, a communication path is established through a selectively separable electrical connector over which encoded multimedia data are conveyed to a multimedia presentation device. An order for a multimedia data file is transmitted to a multimedia source device through a wireless communication interface that is selectively separable from the multimedia presentation device at the electrical connector. The multimedia data file is received over a wireless communication channel through the wireless communication interface upon successful completion of a financial transaction for payment of the multimedia data file. A processor that is selectively separable from the multimedia presentation device at the electrical connector encodes the multimedia data of the received multimedia data file into a format compatible with presentation capabilities of the multimedia presentation device. The encoded multimedia data are conveyed to the multimedia presentation device via the communication path established through the electrical connector. 1. An extended connectivity multimedia apparatus for a multimedia presentation device , the apparatus comprising:an electrical connector to mechanically couple with and be selectively separable from a corresponding connector of the multimedia presentation device and to provide thereby an electrical communication path to the multimedia presentation device;a wireless communication interface selectively separable from the multimedia presentation device at the electrical connector; and transmit an order to a multimedia source device for a multimedia data file, the multimedia source device being accessed by the processor through the wireless communication interface;', 'receive the multimedia data file over a wireless communication channel through the wireless communication interface upon successful completion of a financial transaction for payment of the multimedia data file;', 'encode the multimedia data of the received ...

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Номер записи: 96
12-02-2015 дата публикации

NETWORKING APPARATUS AND A METHOD FOR NETWORKING

Номер: US20150046613A1
Автор: Hurd Matthew, MCDAID Scott, Snowdon David, Thomas Charles
Принадлежит:

This specification discloses a protocol agnostic networking apparatus and method of networking. The networking apparatus receives physical layer signal through a plurality of communications ports that interface with external computing systems. A dynamic routing module interconnects the communications ports with discrete reconfigurable data conduits. Each of the data conduits defines a transmission pathway between predetermined communications ports. A management module maintains the data conduits based on routing commands received from an external computing system. The management module interfaces with the dynamic routing module to make and/or break data conduits responsive to received routing commands. 1. A networking apparatus comprising:a plurality of communications ports that interface with external computing systems to channel physical layer signals,a dynamic routing module comprising a crosspoint switch that interconnects communications ports with discrete reconfigurable data conduits and redirects physical layer signals between interconnected communications ports, each of the data conduits defining a transmission pathway between predetermined communications ports for physical layer signals, anda management module that maintains a plurality of data conduits based on routing commands received from an external computing system, the management module interfacing with the dynamic routing module to make and/or break data conduits responsive to received routing commands.2. The networking apparatus of comprising a plurality of clock and data recovery modules that facilitate signal conditioning for low latency signal transmission claim 1 , each of the communications ports being associated with a dedicated clock and data recovery module.3. The networking apparatus of comprising a plurality of AC couplings that connect the dynamic routing module to each of the clock and data recovery modules.4. The networking apparatus of or comprising a centralized reference clock that ...

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Номер записи: 97
07-02-2019 дата публикации

SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE

Номер: US20190041898A1
Автор: Das Sharma Debendra, Froelich Daniel S., Harriman David J., Stalley Sean O.
Принадлежит:

Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration. 1. A method for operating a downstream port of an upstream component connected to one or more downstream components across a Peripheral Component Interconnect Express (PCIe)-compliant link , the method comprising:determining that the downstream port supports one or more Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode selection mechanisms;determining a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link;setting an SRIS mode in the downstream port; andtransmitting data across the link from the downstream port using the determined system clock configuration.2. The method of claim 1 , wherein setting the SRIS mode in the downstream port comprises setting the SRIS mode based claim 1 , at least in part claim 1 , on the determination of the system clock configuration.3. The method of claim 1 , further comprising communicating the SRIS mode to one or more upstream ports connected to the downstream port across the PCIe-compliant link.4. The method of claim 3 , wherein the one or more upstream ports comprise a pseudo port of a retimer.5. The method of claim 1 , wherein determining that the downstream port supports one or more SRIS mode selection mechanisms comprises determining that an SRIS mode selection mechanism bit is set in ...

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Номер записи: 98
07-02-2019 дата публикации

GLOBALLY ADDRESSABLE MEMORY FOR DEVICES LINKED TO HOSTS

Номер: US20190042455A1
Автор: Agarwal Ishwar, Sankaran Rajesh M., Van Doren Stephen R.
Принадлежит: Intel Corporation

Systems, methods, and devices can include ports comprising hardware to support the multilane link, wherein the multi-lane link comprises a first set of bundled lanes configured in a first direction and a second set of bundled lanes configured in a second direction, the second direction is opposite to the first direction, the first set of bundled lanes comprises an equal number of lanes as the second set of bundled lanes. An input/output (I/O) bridge logic implemented at least partially in hardware can receive across the multilane link an cache invalidation request received on a port compliant with an I/O protocol. A memory controller logic implemented at least partially in hardware can invalidate a cache line based on receiving the cache invalidation request on the I/O protocol. The memory controller can transmit across the multilane link a memory invalidation response message on a port compliant with a device-attached memory access protocol. 1. An apparatus comprising a multilane link , the apparatus comprising:one or more ports comprising hardware to support the multilane link, wherein the multi-lane link comprises a first set of bundled lanes configured in a first direction and a second set of bundled lanes configured in a second direction, the second direction is opposite to the first direction, the first set of bundled lanes comprises an equal number of lanes as the second set of bundled lanes, the apparatus comprising:input/output (I/O) bridge logic implemented at least partially in hardware, the I/O bridge logic to receive across the multilane link an cache invalidation request received on a port compliant with an I/O protocol; and invalidate a cache line based on receiving the cache invalidation request on the I/O protocol, and', 'transmit across the multilane link a memory invalidation response message on a port compliant with a device-attached memory access protocol., 'memory controller logic implemented at least partially in hardware to2. The apparatus of ...

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Номер записи: 99
07-02-2019 дата публикации

ENHANCED STORAGE ENCRYPTION WITH TOTAL MEMORY ENCRYPTION (TME) AND MULTI-KEY TOTAL MEMORY ENCRYPTION (MKTME)

Номер: US20190042474A1
Автор: EDIRISOORIYA Samantha, PAPP Robert Z.
Принадлежит:

This disclosure is directed to a processing device including a memory to store data, processing circuitry to process data, the processing circuitry including a memory controller to control access to the memory and encryption circuitry to encrypt and decrypt data, and I/O circuitry. The I/O circuitry includes an I/O port to write data to a storage device and to read data from the storage device and an enable encryption bit associated with the I/O port, the I/O port to receive a request to read data from the memory, to send a read command to the memory controller with an enable encryption attribute set when the enable encryption bit is set, and to send a read command to the memory controller with the enable encryption attribute not set when the enable encryption bit is not set. The memory controller is configured to get the data from the memory, to forward the data to the I/O port without decrypting the data when the enable encryption attribute is set, and to cause the encryption circuitry to decrypt the data and to forward the decrypted data to the I/O port when the enable encryption attribute is not set. 1. A device comprising:a memory to store data;processing circuitry to process data, the processing circuitry including a memory controller to control access to the memory and encryption circuitry to encrypt and decrypt data; andI/O circuitry including an I/O port to write data to a storage device and to read data from the storage device and an enable encryption bit associated with the I/O port, the I/O port to receive a request to read data from the memory, to send a read command to the memory controller with an enable encryption attribute set when the enable encryption bit is set, and to send a read command to the memory controller with the enable encryption attribute not set when the enable encryption bit is not set;wherein the memory controller to get the data from the memory, to forward the data to the I/O port without decrypting the data when the enable ...

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Номер записи: 100