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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 224. Отображено 156.
11-05-2017 дата публикации

System and Method of Transferring Data over Available Pins

Номер: US20170133082A1
Автор: Vadhiraj Sankaranarayanan, Stuart Allen Berke, Bhyrav M. Mutnury, SANKARANARAYANAN VADHIRAJ, BERKE STUART ALLEN, MUTNURY BHYRAV M, Sankaranarayanan Vadhiraj, Berke Stuart Allen, Mutnury Bhyrav M.
Принадлежит:

A system includes a memory device and a memory controller. The memory device has a data pin and a first available pin. The memory controller has a data pin coupled to the data pin of the memory device, and has a first available pin coupled to the first available pin of the memory device. The memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device. 1. A system for improving memory performance , comprising:a memory device having a data pin and a first available pin; anda memory controller having a data pin coupled to the data pin of the memory device, and having a first available pin coupled to the first available pin of the memory device;wherein the memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device.2. The system of claim 1 , wherein the memory device is a dynamic random access memory (DRAM).3. The system of claim 2 , wherein the DRAM is a double data rate 4 DRAM.4. The system of claim 2 , wherein the memory controller is mounted on a motherboard of a server computer.5. The system of claim 4 , wherein the DRAM is mounted on a dual in-line memory module claim 4 , the dual in-line memory module inserted into a socket on the motherboard.6. The system of claim 3 , wherein the first available pin is a termination data strobe true (TDQS_t) pin.7. The system of claim 6 , wherein the TDQS_t pin outputs data in double data rate mode.8. The system of claim 1 , further comprising a de-multiplexer to de-multiplex in time a double data rate data stream in the memory controller claim 1 , to create a first single data rate stream output on the data pin of the memory controller claim 1 , and to create a second single data rate stream output on the first available pin of the memory controller.9. The system of claim 1 , further ...

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Номер записи: 1
29-05-2014 дата публикации

SYSTEM AND METHOD FOR SELECTIVE ERROR CHECKING

Номер: US20140149833A1
Автор: William Sauber, Ayedin Nikazm, Stuart Allen Berke, SAUBER WILLIAM, NIKAZM AYEDIN, BERKE STUART ALLEN
Принадлежит: Dell Products L.P.

A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information. 1. An information handling system (IHS) , comprising:a memory system that includes a first memory portion that supports error checking and a second memory portion that supports error checking; receive a write request that includes write data and that is directed to one of the first memory portion and second memory portion;', 'determine, in response to the write request being directed to the first memory portion, that the memory controller system memory segmentation information indicates that data associated with the first memory portion should be subject to error checking and, in response, generate error check data and provide the error check data along with the write data to the first memory portion; and', 'determine, in response to the write request being directed to the second memory portion, that the memory controller system memory segmentation information indicates that data associated with the second memory portion should be free of error checking and, in response, provide the write data to the second memory portion without generating error check data., 'a memory controller system that is coupled to the memory system, wherein the memory controller system includes memory ...

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Номер записи: 2
16-07-2020 дата публикации

System and Method of Asymmetric System Description for Optimized Scheduling

Номер: US20200226093A1
Автор: Andrew Butcher, Stuart Allen Berke, BUTCHER ANDREW, BERKE STUART ALLEN, Butcher, Andrew, Berke, Stuart Allen
Принадлежит:

An information handling system includes processors disposed in sockets, and interconnect links providing point-to-point links between the sockets. One of the processors determines an arrangement of the processors, memories and the interconnect links, and determines a value for each of the processors, each of the memories, and each of the interconnect links. The processor calculates interconnect link bandwidth values for each of the interconnect links based at least in part on the determined value and the arrangement of the processors, the memories and the interconnect links. The processor also populates an interconnect bandwidth table using the interconnect link bandwidth values. 1. An information handling system comprising:a system board having a plurality of sockets;a plurality of processors, each processor disposed in a respective socket;a plurality of interconnect links providing point-to-point links between at least some of the sockets; anda plurality of memories corresponding to the processors; determine an arrangement of the processors, the memories and the interconnect links;', 'determine a value for each of the processors, each of the memories, and each of the interconnect links;', 'calculate interconnect link bandwidth values for each of the interconnect links based at least in part on the determined value and the arrangement of the processors, the memories and the interconnect links; and', 'populate an interconnect bandwidth table using the interconnect link bandwidth values., 'wherein one of the processors is operable to2. The information handling system of claim 1 , wherein each of the processors has a local memory that is accessible to all of the processors.3. The information handling system of claim 1 , wherein the interconnect link bandwidth values are further based on an architecture of the information handling system.4. The information handling system of claim 1 , wherein the arrangement of the processors claim 1 , the memories and the interconnect ...

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Номер записи: 3
18-05-2021 дата публикации

Memory device failure recovery system

Номер: US0011010250B2
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, BERKE STUART ALLEN, MUTNURY BHYRAV M, Berke, Stuart Allen, Mutnury, Bhyrav M.
Принадлежит: Dell Products L.P., DELL PRODUCTS LP

A memory device failure recovery system includes a memory device management engine that is coupled to a first memory device via a first memory device slot, and a memory device management database. The memory device management engine identifies that the first memory device has experienced a failure in a configuration region of the first memory device during a current boot operation and, in response, retrieves memory device component information and memory device configuration information that is stored in the memory device management database and that was retrieved as part of a prior boot operation from a memory device that was connected to the first memory device slot. During the current boot operation, the memory device management engine determines whether first memory device components on the first memory device correspond to the memory device component information and, if so, uses the memory device configuration information to configure the first memory device.

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Номер записи: 4
25-01-2024 дата публикации

METHOD FOR CXL FALLBACK IN A CXL SYSTEM

Номер: US20240028438A1
Автор: Isaac Q. Wang, Stuart Allen Berke, Jordan Chin
Принадлежит:

An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.

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Номер записи: 5
28-05-2020 дата публикации

System and Method for Providing Per Channel Frequency Optimization in a Double Data Rate Memory System

Номер: US20200167275A1
Автор: Stuart Allen Berke, Vadhiraj Sankaranarayanana, Bhyrav M. Mutnury, BERKE STUART ALLEN, SANKARANARAYANANA VADHIRAJ, MUTNURY BHYRAV M, Berke, Stuart Allen, Sankaranarayanana, Vadhiraj, Mutnury, Bhyrav M.
Принадлежит:

An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed. 1. An information handling system , comprising:a first dual in-line memory module (DIMM) on a first memory channel of the information handling system;a second DIMM on a second memory channel of the information handling system; and train the first memory channel to a first speed based upon a first performance level of the first DIMM;', 'train the second memory channel to a second speed based upon a second performance level of the second DIMM, the first speed different from the second speed;', 'launch a first application;', 'allocate a first portion of the first DIMM to the first application based upon the first speed;', 'ascribe a first priority level to the first DIMM based upon first speed information for the first memory channel in an Advanced Configuration and Power Interface (ACPI) table and a second priority level to the second DIMM based upon second speed information for the second memory channel in the ACPI table, wherein the first priority level is higher than the second priority level., 'a processor configured to2. The information handling system of claim 1 , wherein claim 1 , prior to ascribing the first and second priority levels claim 1 , the processor is further configured to:receive the first speed information;receive the second speed information; andstore the first and second speed information to the ACPI table.3. The information handling system of claim 2 , the processor further configured to:receive a memory allocation ...

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Номер записи: 6
19-07-2016 дата публикации

Power management system

Номер: US0009395790B2
Автор: Stuart Allen Berke, George G. Richards, III, BERKE STUART ALLEN, RICHARDS III GEORGE G, RICHARDS, III GEORGE G.
Принадлежит: Dell Products L.P., DELL PRODUCTS LP, DELL PRODUCTS L.P.

A power management system includes a power system. A powered component is coupled to the power system. A power detect circuit is coupled to the power system. A power system controller is coupled to the power system, the powered component, and the power detect circuit. The power system controller is operable, for each of at least one workload run using the powered component, to program the power detect circuit with a first threshold for a first system operation setting and determine that the first threshold was not exceeded while the workload was running. The power system controller is then operable to program the power detect circuit with a second threshold for the first system operation setting, determine that the second threshold was exceeded while the workload was running and, in response, use the second threshold to allocate power from the power system.

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Номер записи: 7
28-06-2016 дата публикации

Adjustable heat sink supporting multiple platforms and system configurations

Номер: US0009377828B2
Автор: Eric M. Tunks, Stuart Allen Berke, TUNKS ERIC M, BERKE STUART ALLEN, TUNKS ERIC M.
Принадлежит: Dell Products L.P., DELL PRODUCTS LP, DELL PRODUCTS L.P.

An adjustable heat sink which allows factory, service, or customers to adjust the width of the heat sink to take advantage of some or all available unpopulated DIMM space to optimize cooling and performance. Such an adjustable heat sink addresses many of the limitations of other heat sinks and is advantageous for reducing part numbers within a platform and across platforms. Such an adjustable heat sink also simplifies field upgrades when either adding or removing populated DIMMs to an information handling system thus enhancing performance without a need to change CPU Heat sinks.

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Номер записи: 8
11-04-2019 дата публикации

System and Method for Post-Package Repair Across DRAM Banks and Bank Groups

Номер: US20190108892A1
Автор: Stuart Allen Berke, Vadhiraj Sankaranarayanan, BERKE STUART ALLEN, SANKARANARAYANAN VADHIRAJ, Berke, Stuart Allen, Sankaranarayanan, Vadhiraj
Принадлежит: Dell Products LP

A dynamic random access memory (DRAM) device includes a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells. The DRAM device further includes a post-package repair (PPR) storage array arranged as a plurality of entries, wherein the DRAM device is configured to map a first row failure in a first bank group to a first entry of the PPR storage array, and to map a second row failure in a second bank group to a second entry of the PPR storage array.

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Номер записи: 9
28-02-2023 дата публикации

System and method for determining physical orientation of a memory module using on-board thermal sensors

Номер: US0011593244B2
Автор: Stuart Allen Berke
Принадлежит: Dell Products L.P., DELL PRODUCTS, LP

An information handling system includes a memory module having a first thermal sensor for a first memory channel, and a second thermal sensor for a second memory channel. A processor receives a first temperature from the first thermal sensor and a second temperature from the second thermal sensor, and performs a first high bandwidth access of the first memory channel. In response to a predetermined amount of time ending, the processor: receives a third temperature from the first thermal sensor and a fourth temperature from the second thermal sensor; determines a first temperature delta based on a difference between the third and first temperatures; and determines a second temperature delta based on a difference between the fourth and second temperatures. Based on the first and second temperature deltas, the processor determines whether the first or second memory channel is an upstream memory channel.

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Номер записи: 10
12-11-2019 дата публикации

System and method for controlling cache flush size

Номер: US0010474583B2
Автор: John E. Jenne, Stuart Allen Berke, Vadhiraj Sankaranarayanan, JENNE JOHN E, BERKE STUART ALLEN, SANKARANARAYANAN VADHIRAJ, Jenne, John E., Berke, Stuart Allen, Sankaranarayanan, Vadhiraj
Принадлежит: Dell Products L.P., DELL PRODUCTS LP

An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy.

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Номер записи: 11
08-11-2018 дата публикации

Server Display for Displaying Server Component Information

Номер: US20180324973A1
Автор: Corey D. Hartman, Stuart Allen Berke, HARTMAN COREY D, BERKE STUART ALLEN, Hartman, Corey D., Berke, Stuart Allen
Принадлежит:

A server includes slots for adding peripheral devices, and a server chassis having a openings corresponding to the slots. A display mounted on the server chassis proximate the opening displays slot characteristics, slot status information, or user defined information corresponding to the slots. 1. A server comprising:a set of slots for adding peripheral devices to the server;a server chassis having a set of openings corresponding to the set of slots; anda display mounted on the server chassis proximate the openings, the display configured to display slot characteristics, slot status information, or user defined information corresponding to the set of slots.2. The server of claim 1 , wherein the display is a part of a display housing and the display housing is mounted to the server chassis.3. The server of claim 2 , further comprising a display mount positioned on the server chassis claim 2 , wherein the display housing is mounted on the display mount.4. The server of claim 1 , further comprising a baseboard management controller (BMC) claim 1 , wherein the display is connected to the BMC to be controlled by the BMC.5. The server of claim 1 , wherein the set of openings includes a first opening corresponding to a first slot of the set of slots claim 1 , and a first portion of the display proximate the first opening displays information regarding the first slot.6. The server of claim 5 , wherein the set of openings includes a second opening corresponding to a second slot of the set of slots claim 5 , and a second portion of the display proximate the second opening displays information regarding the second slot.7. The server of claim 1 , wherein each slot includes a peripheral card connector.8. The server of claim 1 , wherein slot characteristics include a communication protocol supported by the slot.9. An information handling system comprising:a set of slots for adding peripheral devices to the information handling system;a chassis having a set of openings ...

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Номер записи: 12
18-11-2010 дата публикации

System and Method for Optimizing Performance of an Information Handling System Component

Номер: US20100293367A1
Автор: Stuart Allen Berke, William F. Sauber
Принадлежит: DELL PRODUCTS L.P.

Systems and methods for optimizing performance of an information handling system component communicatively coupled to the information handling system are disclosed. An information handling system may include a data gathering module and an operating condition controller module. The data gathering module may be configured to retrieve an operating condition characterization value from the component. That operating condition characterization value may be substantially based on a predetermined characteristic of the component. The operating condition controller module may be configured to modify an operating condition of the component based at least on the retrieved operating condition characterization value.

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Номер записи: 13
30-03-2017 дата публикации

System and Method of Selective Encoding for Enhanced Serializer/Deserializer Throughput

Номер: US20170093521A1
Автор: Minchuan Wang, Stuart Allen Berke, Bhyrav M. Mutnury, WANG MINCHUAN, BERKE STUART ALLEN, MUTNURY BHYRAV M, Wang Minchuan, Berke Stuart Allen, Mutnury Bhyrav M.
Принадлежит:

A serial communication link including first and second components. The first component includes a first management module and a first encoder that provides A-bit/B-bit encoded data to a first channel, where A Подробнее

Номер записи: 14
16-08-2018 дата публикации

System and Method for Providing a Back Door Communication Path Between Channels on Dual-Channel DIMMs

Номер: US20180232171A1
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, Vadhiraj Sankaranarayanan
Принадлежит:

A dual-channel Dual In-Line Memory Module (DIMM) is configured to provide memory transactions on a first memory channel and a second memory channel. The dual-channel DIMM includes a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel, a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel, and a plurality of back door communication paths, each back door communication path being between a data bit of the first bank of DRAM devices and a corresponding data bit of the second bank of DRAM devices. 1. A dual-channel Dual In-Line Memory Module (DIMM) configured to provide memory transactions on a first memory channel and a second memory channel , the dual-channel DIMM comprising:a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel;a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel; anda plurality of back door communication paths, each back door communication path being between a data bit of the first bank of DRAM devices and a corresponding data bit of the second bank of DRAM devices.2. The dual-channel DIMM of claim 1 , wherein the dual-channel DIMM is configured to provide the first memory transaction on the second memory channel in response to determining that the first memory channel has failed to provide the first memory transaction claim 1 , wherein data associated with the first memory transaction is communicated between the first bank of DRAM devices and the second bank of DRAM devices to the second memory channel via the plurality of back door communication paths.3. The dual-channel DIMM of claim 2 , further comprising: receive first command and address information associated with the first transaction on the first memory channel,', 'provide the first command and address information to the ...

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Номер записи: 15
03-12-2019 дата публикации

System and method of utilizing memory modules

Номер: US0010496477B1
Автор: Stuart Allen Berke, Vadhiraj Sankaranarayanan, Bhyrav M. Mutnury, BERKE STUART ALLEN, SANKARANARAYANAN VADHIRAJ, MUTNURY BHYRAV M, Berke, Stuart Allen, Sankaranarayanan, Vadhiraj, Mutnury, Bhyrav M.
Принадлежит: Dell Products L.P., DELL PRODUCTS LP

In one or more embodiments, one or more systems, methods, and/or processes may determine that a first memory unit (MU) and a second MU of a first channel of a memory module are associated with an issue; may configure a control device to utilize a third MU in place of the first MU; and may configure the control device to utilize a fourth MU, of a second channel of the memory module, in place of the second MU. In one or more embodiments, multiple MUs of the first channel, other than the first and second MUs, may store a first portion of data; the fourth MU may store a second portion of the data; the multiple MUs, other than the first and second MUs, may provide the first portion of the data to a processor; and the fourth MU may provide the second portion of the data to the processor.

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Номер записи: 16
23-03-2017 дата публикации

Power Aware Receiver/Transmitter Adaptation for High Speed Serial Interfaces

Номер: US20170085400A1
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, Minchuan Wang
Принадлежит:

A receiver includes first and second equalization modules adapted to provide first and second compensations to a data signal, and a control module including a list that identifies the first equalization module as being less efficient than the second. The control module provides first and second compensation levels of the first and second compensations, such that the first and second compensations operate on the data signal to meet a bit error rate (BER) target, lowers the first compensation to reduce the power consumption of the receiver based on the list, and determines whether, in response to an increase in the level of the second compensation the BER target is met. 1. A receiver , comprising:a first equalizer that provides a first compensation to a data signal received by the receiver;a second equalizer that provides a second compensation to the data signal; and provides a first compensation level of the first compensation and a second compensation level of the second compensation, such that the first compensation level and the second compensation level combine to operate on the data signal to meet a bit error rate (BER) target;', 'sets the level of the first compensation from the first compensation level to a third compensation level; and', 'determines whether, in response to an increase in the level of the second compensation from the second compensation level to a fourth compensation level, a combination of the third compensation level and the fourth compensation level operate on the data signal to meet the BER target., 'control logic that2. The receiver of claim 1 , wherein the control logic further:sets the level of the second compensation from the second level to the fourth level when the third compensation level and the fourth compensation level combine to operate on the data signal to meet the BER target.3. The receiver of claim 1 , wherein the control logic further:determines that the first compensation level is greater than a first threshold for the ...

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Номер записи: 17
11-07-2017 дата публикации

System and method for providing kernel intrusion prevention and notification

Номер: US0009703725B2
Автор: Stuart Allen Berke, Mi Wang, Vivek Dharmadhikari, BERKE STUART ALLEN, WANG MI, DHARMADHIKARI VIVEK, Berke Stuart Allen, Wang Mi, Dharmadhikari Vivek
Принадлежит: DELL PRODUCTS, LP, DELL PRODUCTS LP, Dell Products, LP

A memory protection module includes comparison logic that has a write-once window CSR that stores a memory address range, and window protection logic. The comparison logic receives a memory write transaction, determines a memory address of the memory write transaction, and provides an indication as to whether or not the memory address is included in the memory address range. The window protection logic receives the memory transaction, receives the indication from the comparison logic, allows the memory write transaction to proceed in response to the indication indicating that the memory address is not included in the memory address range, and drops the memory write transaction in response to the indication indicating that the memory address is included in the memory address range.

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Номер записи: 18
28-08-2014 дата публикации

SYSTEMS AND METHODS FOR FREQUENCY SHIFTING RESONANCE OF AN UNUSED VIA IN A PRINTED CIRCUIT BOARD

Номер: US20140238733A1
Автор: Bhyrav M. Mutnury, Sandor Farkas, Stuart Allen Berke, MUTNURY BHYRAV M, FARKAS SANDOR, BERKE STUART ALLEN, MUTNURY BHYRAV M.
Принадлежит: DELL PRODUCTS L.P.

In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location. 1. A circuit board , comprising:a first trace formed in a first layer of the circuit board;a second trace formed in a second layer of the circuit board;a via configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via; anda termination pad formed at an end of the via stub opposite at least one of the first location and the second location.2. The circuit board of claim 1 , the termination pad formed such that an effective impedance of the via stub is approximately equal to a desired impedance.3. The circuit board of claim 2 , the termination pad formed with a size such that the effective impedance of the via stub is approximately equal to the desired impedance.4. The circuit board of claim 3 , wherein the size is a radius of the termination pad.5. The circuit board of claim 2 , wherein the desired impedance comprises at least one of a desired capacitance and a desired inductance.6. The circuit board of claim 2 , wherein the desired ...

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Номер записи: 19
08-10-2020 дата публикации

System and Method of Rerouting an Inter-Processor Communication Link Based on a Link Utilization Value

Номер: US20200320029A1
Автор: Stuart Allen Berke, Wade Andrew Butcher, BERKE STUART ALLEN, BUTCHER WADE ANDREW, Berke, Stuart Allen, Butcher, Wade Andrew
Принадлежит:

In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces. 1. An information handling system , comprising:a plurality of semiconductor packages, each of the plurality of packages includes a plurality of processor cores and an input/output (I/O) communication fabric; anda memory medium, coupled to a processor core of a first semiconductor package of the plurality of semiconductor packages, that stores instructions executable by the processor core of the first semiconductor package, which when executed by the processor core of the first semiconductor package, cause the information handling system to:configure a plurality of link registers, of the first semiconductor package, that configure the I/O communication fabric of the first semiconductor package to route communications of a plurality of components of the first semiconductor package to a plurality of inter-processor communication link interfaces of the first semiconductor package; communicate with a second semiconductor package of the plurality ...

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Номер записи: 20
01-03-2016 дата публикации

Date adjusted power budgeting for an information handling system

Номер: US0009274581B2
Автор: Stuart Allen Berke, John E. Jenne
Принадлежит: Dell Products, LP

An information handling system determines a system configuration including a hardware module, and determines an adjusted power budget for the hardware module. The adjusted power budget is based on a calculation including a difference between a date code read from the hardware module and a baseline date, a baseline power budget, a power reduction period and a power reduction interval. The calculation may optionally include a risk factor. In alternate embodiments, an adjusted power budget for a hardware module may be calculated by an order processing system for information handling systems, or by a planning tool for a data center which contains information handling systems.

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Номер записи: 21
01-09-2020 дата публикации

System and method for setting equalization for communication between a processor and a device

Номер: US0010762031B2
Автор: Sandor Farkas, Stuart Allen Berke, Bhyrav M. Mutnury
Принадлежит: Dell Products, L.P.

An information handling system may include a central processing unit (CPU) and a device. The CPU may have an I/O system and be configured to host a BIOS. The device may be communicatively connected to the I/O system of the CPU by a connection. The BIOS may determine a communication protocol used by the device for communication and set an equalization of the I/O system for communication with the device based on the communication protocol used by the device.

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Номер записи: 22
18-07-2017 дата публикации

Methods of power supply unit rotating in an information handling system

Номер: US0009710051B2
Автор: Mark A. Muccini, Mehran Mirjafari, William Draper, Ashish Razdan, Lei Wang, John Evren Jenne, Stuart Allen Berke
Принадлежит: Dell Products, L.P.

A method of power supply unit rotating in an information handling system (IHS) may include a control unit dividing a power loading of an IHS into N sections, where N corresponds to a number of power supply units coupled to the IHS. The control unit may configure a first power supply unit to an active state and configure one or more remaining power supply units to a suspended state during a first time period. The control unit may configure the first power supply unit to the suspended state and configure a second power supply unit to the active state in response to a second time period being reached. The control unit may rotate the active state among the power supply units in response to sequential time periods being reached. In an embodiment the control unit may rotate the active state sequentially between each of the subsequent power supplies.

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Номер записи: 23
29-08-2013 дата публикации

SYSTEMS AND METHODS FOR PROVIDING COMPONENT CHARACTERISTICS

Номер: US20130226481A1
Автор: Stuart Allen Berke
Принадлежит:

Systems and methods are disclosed for providing a signal indicative of one or more types of individual measurable device characteristic/s that are unique to a given electronic device by providing a signal indicative of the measurable and unique device characteristic/s in a passive manner from the electronic device. The signal indicative of one or more types of individual measurable device characteristic/s may be so provided without requiring operational power to be applied to any active electronic circuitry of the device, and without requiring any power to be generated by the device. 1. An information handling system , comprising: at least one first electronic component coupled to a first circuit path of the electronic device and having a measurable device characteristic that is unique to the electronic component, the device characteristic being an electronic characteristic of circuitry of the first electronic component that is measurable by circuitry external to the electronic device using the first circuit path of the electronic device, and', 'at least one passive circuit component that is separate and different from the first electronic component, the passive circuit component coupled to a second circuit path of the electronic device that is separate and different from the first circuit path, the passive circuit component having a passive electrical characteristic that is discernible by circuitry external to the electronic device using a second circuit path of the electronic device,', 'where the passive electrical characteristic is selected to be indicative of the measurable device characteristic of the first electronic component; and, 'at least one electronic device comprisingmeasurement circuitry external to the at least one electronic device and coupled to the second circuit path of the electronic device and configured to discern the passive electrical characteristic.2. The system of claim 1 , where the first electronic component comprises active circuitry; ...

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Номер записи: 24
06-10-2020 дата публикации

System and method for setting communication channel equalization of a communication channel between a processing unit and a memory

Номер: US0010795592B2
Автор: Bhyrav M. Mutnury, Stuart Allen Berke, MUTNURY BHYRAV M, BERKE STUART ALLEN, Mutnury, Bhyrav M., Berke, Stuart Allen
Принадлежит: Dell Products, L.P., DELL PRODUCTS LP, DELL PRODUCTS, LP

An information handling system includes a processing unit that is coupled to a memory device by a communication channel. The processing unit includes a memory controller and is configured to host a basic input output system (BIOS). The memory device, which may include a dual in-line memory module (DIMM), stores serial presence detect (SPD) information. In an embodiment, the BIOS obtains the SPD information and parameters of the communication channel, such as channel impedance and channel length. In this embodiment, the BIOS uses a look-up table to determine an equalization of the communication channel based on the obtained SPD information and the obtained parameters of the communication channel, and utilizes the memory controller to set the equalization of the communication channel, such as by setting or controlling settings of transmission and reception components of the memory controller.

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Номер записи: 25
04-12-2014 дата публикации

VERIFYING OEM COMPONENTS WITHIN AN INFORMATION HANDLING SYSTEM USING ORIGINAL EQUIPMENT MANUFACTURER (OEM) IDENTIFIER

Номер: US20140358792A1
Автор: Stuart Allen Berke, Mukund Purshottam Khatri, BERKE STUART ALLEN, KHATRI MUKUND PURSHOTTAM
Принадлежит:

A method validates whether a component/device installed within an information handling system (IHS) is an OEM (original equipment manufacturer) programmed device, by: reading identification (ID) data and an identifier code from the target device; generating a unique encrypted sequence using the ID data; providing a unique validation check code based on the ID data; generating a component validation code corresponding to the target device via a decryption process involving the unique encrypted sequence; and comparing the component validation code to the validation check code. The method further includes: in response to the component validation code matching the validation check code, identifying the target device as an OEM programmed device with a valid identifier code stored as the identifier code; and enabling certain processes reserved for only verified OEM programmed devices. The decryption process reverses an encryption process utilized when generating the unique OEM identifier code of the target device. 1. A method for determining whether a target device installed within an information handling system (IHS) is an OEM (original equipment manufacturer) programmed device , the method comprising:reading identification (ID) data and an identifier code from the target device;generating a unique encrypted sequence using the ID data read from the target device;providing a validation check code based on the ID data, where the validation check code is exclusive for that specific ID data;generating a component validation code corresponding to the target device by performing a decryption process involving the unique encrypted sequence, wherein said decryption process is a reverse process of an encryption process that is used during device manufacture within a secure OEM environment to generate a unique OEM identifier code that is assigned to an OEM programmed device having a same ID data as the ID data read from the target device;comparing the component validation code to ...

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Номер записи: 26
04-08-2020 дата публикации

System and method to monitor component wear on high speed serial interfaces

Номер: US0010735227B1
Автор: Robert G. Bassman, Stuart Allen Berke, Bhyrav M. Mutnury, BASSMAN ROBERT G, BERKE STUART ALLEN, MUTNURY BHYRAV M, Bassman, Robert G., Berke, Stuart Allen, Mutnury, Bhyrav M.
Принадлежит: Dell Products, L.P., DELL PRODUCTS LP, DELL PRODUCTS, LP

A receiver includes signal lanes to receive associated data bit streams, and a control module. The signal lanes each include configurable equalization modules to provide a selectable compensation value to the associated data bit stream. The control module performs back channel adaptations on each data bit stream to achieve a target bit error rate for the associated signal lane, determines a most common set of compensation values from the performance of the back channel adaptations, determines whether the compensation value is within a predetermined boundary for that selectable compensation value, and provides an alert when a first compensation value of the most common set of compensation values is not within the predetermined boundary for the first compensation value.

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Номер записи: 27
10-03-2016 дата публикации

POWER MANAGEMENT SYSTEM

Номер: US20160070328A1
Автор: Stuart Allen Berke, George G. Richards, III
Принадлежит:

A power management system includes a power system. A powered component is coupled to the power system. A power detect circuit is coupled to the power system. A power system controller is coupled to the power system, the powered component, and the power detect circuit. The power system controller is operable, for each of at least one workload run using the powered component, to program the power detect circuit with a first threshold for a first system operation setting and determine that the first threshold was not exceeded while the workload was running. The power system controller is then operable to program the power detect circuit with a second threshold for the first system operation setting, determine that the second threshold was exceeded while the workload was running and, in response, use the second threshold to allocate power from the power system. 1. A power management system , comprising:a power system;a power detect circuit coupled to the power system; and provide the power detect circuit with a first threshold for a system operation setting;', 'determine that the first threshold for the system operation setting was not exceeded during the running of a workload and, in response, provide the power detect circuit with a second threshold for the system operation setting that is less than the first threshold; and', 'determine that the second threshold for the system operation setting was exceeded during the running of the workload and, in response, use the second threshold for the system operation setting to manage system operations such that the capabilities of the power system are not exceeded., 'a power system controller coupled to the power system and the power detect circuit, wherein the power system controller is configured to2. The power management system of claim 1 , wherein the first threshold and the second threshold are based on at least one of a power magnitude claim 1 , a power width claim 1 , a power area claim 1 , and a power slew rate.3. The ...

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Номер записи: 28
24-05-2022 дата публикации

System and method for providing per channel frequency optimization in a double data rate memory system

Номер: US0011341037B2
Автор: Stuart Allen Berke, Vadhiraj Sankaranarayanana, Bhyrav M. Mutnury
Принадлежит: Dell Products L.P., DELL PRODUCTS, LP

An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.

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Номер записи: 29
07-03-2013 дата публикации

System and Method for Controller Independent Faulty Memory Replacement

Номер: US20130060996A1
Автор: Stuart Allen Berke
Принадлежит: DELL PRODUCTS L.P.

In accordance with the present disclosure, a system and method for controller independent faulty memory replacement is described. The system includes a system memory component with a system memory component architecture. The system also includes a memory buffer coupled to the system memory component. The memory buffer may include at least one spare memory location corresponding to a faulty memory location of the system memory component. Additionally, the system memory component architecture may receive a read command directed to an address of the system memory component containing the faulty memory location and output, in response to the read command, data corresponding to the address from both the system memory component and the at least one spare memory component. 1. A system for controller independent faulty memory replacement , comprising:a system memory component comprising a system memory component architecture; anda memory buffer coupled to the system memory component, wherein the memory buffer is operable to include at least one spare memory location corresponding to a faulty memory location of the system memory component;wherein the system memory component architecture is operable to receive a read command directed to an address of the system memory component containing the faulty memory location and output, in response to the read command, data corresponding to the address from both the system memory component and the at least one spare memory component.2. The system of claim 1 , wherein the memory buffer comprises one of a buffer in a load-reduced dual in-line memory module (LRDIMM) claim 1 , a Buffer on Board claim 1 , or a Buffer on Riser.3. The system of claim 1 , wherein the system memory component comprises a double data rate (DDR) dynamic random access memory (DRAM).4. The system of claim 3 , wherein the memory buffer comprises a buffer integrated within the DDR DRAM.5. The system of claim 1 , wherein the memory buffer comprises a 3DS/through- ...

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Номер записи: 30
14-04-2016 дата публикации

Power Aware Receiver/Transmitter Adaptation for High Speed Serial Interfaces

Номер: US20160105296A1
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, Minchuan Wang
Принадлежит:

A receiver includes first and second equalization modules adapted to provide first and second compensations to a data signal, and a control module including a list that identifies the first equalization module as being less efficient than the second. The control module provides first and second compensation levels of the first and second compensations, such that the first and second compensations operate on the data signal to meet a bit error rate (BER) target, lowers the first compensation to reduce the power consumption of the receiver based on the list, and determines whether, in response to an increase in the level of the second compensation the BER target is met. 1. A receiver , comprising:a first equalization module adapted to provide a first compensation to a data signal received by the receiver;a second equalization module adapted to provide a second compensation to the data signal; and provide a first compensation level of the first compensation and a second compensation level of the second compensation, such that the first compensation level and the second compensation level combine to operate on the data signal to meet a bit error rate (BER) target;', 'set the level of the first compensation from the first compensation level to a third compensation level to reduce a power consumption of the receiver based on the first list identifying the first equalization module as being less efficient than the second equalization module; and', 'determine whether, in response to an increase in the level of the second compensation from the second compensation level to a fourth compensation level, a combination of the third compensation level and the fourth compensation level operate on the data signal to meet the BER target., 'a control module including a first list that identifies the first equalization module as being less efficient than the second equalization module, the control module adapted to2. The receiver of claim 1 , wherein the control module is further ...

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Номер записи: 31
18-06-2013 дата публикации

System and method for reducing power consumption of memory

Номер: US0008468295B2
Автор: Stuart Allen Berke, William Sauber, BERKE STUART ALLEN, SAUBER WILLIAM
Принадлежит: Dell Products L.P., BERKE STUART ALLEN, SAUBER WILLIAM, DELL PRODUCTS LP, DELL PRODUCTS L.P.

Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.

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Номер записи: 32
31-05-2018 дата публикации

System and Method for Communicating over a Connector Device based on Component Characteristics Stored with the Components of the Connector Device

Номер: US20180150429A1
Автор: Minchuan Wang, Bhyrav M. Mutnury, Stuart Allen Berke, Harry C. Heinisch
Принадлежит:

An information handling system may include a first computing device, a second computing device, a connector device connecting the first computing device and the second computing device, and a controller. The connector device may be assembled from a set of components, where one or more of the components have a memory storing signal integrity characteristics for the component. The controller may be connected to the component memories, and may also be connected to the first computing device and the second computing device. 1. An information handling system , comprising:a first computing device;a second computing device;a connector device connecting the first computing device and the second computing device, the connector device assembled from a set of components, each component of the set of components having a memory storing signal integrity characteristics for the component; anda controller connected to each of the memories, connected to the first computing device, and connected to the second computing device.2. The information handling system of claim 1 , wherein the information handling system is a server system.3. The information handling system of claim 1 , wherein the controller is configured to access one or more of the memories and read signal integrity characteristics for the set of components from the memories.4. The information handling system of claim 3 , wherein the controller is configured to determine one or more signal integrity characteristics of the connector device from the signal integrity characteristics read from the memories.5. The information handling system of claim 4 , wherein the first computing device comprises a first transmitter and the second computing device includes a second receiver.6. The information handling system of claim 5 , wherein the first transmitter is configured to transmit over a first channel provided by the connector device according to a communication standard based on the one or more signal integrity characteristics of ...

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Номер записи: 33
30-07-2015 дата публикации

SYSTEMS AND METHODS FOR FREQUENCY SHIFTING RESONANCE OF AN UNUSED VIA IN A PRINTED CIRCUIT BOARD

Номер: US20150211837A1
Автор: Bhyrav M. Mutnury, Sandor Farkas, Stuart Allen Berke
Принадлежит:

In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location. 1. A circuit board , comprising:a first trace formed in a first layer of the circuit board;a second trace formed in a second layer of the circuit board;a via configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via;a first termination pad formed at an end of the via stub opposite at least one of the first location and the second location; andone or more second termination pads formed at one or more layers of the circuit board other than the first layer and the second layer, wherein the one or more second termination pads are smaller in size than the first termination pad.2. The circuit board of claim 1 , the first termination pad formed such that an effective impedance of the via stub is approximately equal to a desired impedance.3. The circuit board of claim 2 , the first termination pad and the one or more second termination pads each formed with a respective size such that the effective impedance of the via stub is approximately ...

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Номер записи: 34
02-07-2019 дата публикации

System and method to blacklist equalization coefficients in a high-speed serial interface

Номер: US0010339088B2
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, BERKE STUART ALLEN, MUTNURY BHYRAV M, Berke, Stuart Allen, Mutnury, Bhyrav M.
Принадлежит: Dell Products, LP, DELL PRODUCTS LP

A serial interface comprises a receiver including a first input compensation module with a first setting that selects a first value from among a plurality of first values for a first input characteristic of the receiver, a memory to store a first blacklist value from among the first values, and a control module to select each of the first values, except for the first blacklist value, to evaluate an indication of a performance level of the receiver for each of the selected first values, and to select a particular first value based upon the indications of the performance level of the receiver.

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Номер записи: 35
19-09-2019 дата публикации

System and Method to Optimize Equalization Coefficients in a High-Speed Serial Interface

Номер: US20190288881A1
Автор: Stuart Allen Berke, Minchuan Wang, Bhyrav M. Mutnury, BERKE STUART ALLEN, WANG MINCHUAN, MUTNURY BHYRAV M, Berke, Stuart Allen, Wang, Minchuan, Mutnury, Bhyrav M.
Принадлежит:

A high-speed serial data system includes a transmitter and a receiver. The receiver includes a compensation module, a memory, and a control module. The compensation module includes a setting that selects a compensation value from among a plurality of compensation values for a characteristic of the receiver. The memory stores a whitelist value from among the compensation values. The control module determines that a performance level of the receiver is below a performance level threshold. In response to determining that the performance level is below the performance level threshold, the control module uses the whitelist value to reevaluate the performance level of the receiver, and applies the whitelist value to the compensation module when the reevaluated performance level is above the performance level threshold. 1. A high-speed serial data system , comprising:a transmitter confi ured to provide a selectable output impedance, the output impedance being selectable from a plurality of output impedance values; and a first compensation module with a first setting that selects a first value from among a plurality of first values for a first characteristic of the receiver;', 'a memory to store a first whitelist value from among the first values; and', 'a control module to determine that a performance level of the receiver is below a performance level threshold, and in response to determining that the performance level is below the performance level threshold 1) to use the first whitelist value to reevaluate the performance level of the receiver, and 2) to apply the first whitelist value to the first compensation module when the reevaluated performance level is above the performance level threshold., 'a receiver including2. The serial data system of claim 1 , the receiver further including:a second compensation module with a second setting that selects a second value from among a plurality of second values for a second characteristic of the receiver; the memory is further ...

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Номер записи: 36
26-09-2017 дата публикации

System and method of read/write control for dual channel memory modules for robust performance

Номер: US0009772913B1
Автор: Bhyrav M. Mutnury, Stuart Allen Berke, Vadhiraj Sankaranarayanan, MUTNURY BHYRAV M, BERKE STUART ALLEN, SANKARANARAYANAN VADHIRAJ, Mutnury Bhyrav M., Berke Stuart Allen, Sankaranarayanan Vadhiraj
Принадлежит: DELL PRODUCTS, LP, DELL PRODUCTS LP

A memory controller for dual-channel DDR DIMMs comprises a first memory channel configured to execute a first memory transaction with a first memory device of a dual-channel DDR DIMM, and a second memory channel configured to execute a second memory transaction with a second memory device of the dual-channel DDR DIMM. The memory controller is configured to determine that the first memory channel is experiencing a degraded performance level in executing the first memory transaction with the first device, and to prevent read-write memory transactions and write-read memory transactions on the first and second memory channels in response to determining that the first memory channel is experiencing the degraded performance level.

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Номер записи: 37
31-03-2020 дата публикации

Systems and methods for frequency shifting resonance of an unused via in a printed circuit board

Номер: US0010605585B2
Автор: Bhyrav M. Mutnury, Sandor Farkas, Stuart Allen Berke, MUTNURY BHYRAV M, FARKAS SANDOR, BERKE STUART ALLEN, Mutnury, Bhyrav M., Farkas, Sandor, Berke, Stuart Allen
Принадлежит: Dell Products L.P., DELL PRODUCTS LP

In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

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Номер записи: 38
01-02-2018 дата публикации

Configurable Multi-Rail Voltage Regulation with Coupled Inductor Power Steering

Номер: US20180034374A1
Автор: John J. Breen, Guangyong Zhu, Stuart Allen Berke, Abey K. Mathew
Принадлежит:

A voltage regulator circuit comprises a plurality of voltage regulator phases, a first load output coupled to the plurality of voltage regulator phases for providing a first output voltage, a first coupling inductor having a first winding and a second winding, the first winding coupled in series between a first voltage regulator phase of the plurality of voltage regulator phases and the first load output, a second load output coupled to the second winding for providing a second output voltage, and a first switch coupled in series with the second winding. A method comprises detecting a startup event; determining an installed processor type; retrieving a configuration parameter value; providing a first output voltage at a first load output; providing, at a second load output coupled to the second winding, a second output voltage; and controlling a first duty cycle of a first switch coupled in series with the second winding. 1. A voltage regulator circuit comprising:a plurality of voltage regulator phases;a first load output coupled to the voltage regulator phases for providing a first output voltage;a first coupling inductor having a first winding and a second winding, the first winding coupled in series between a first voltage regulator phase of the voltage regulator phases and the first load output;a second load output coupled to the second winding for providing a second output voltage; anda first switch coupled in series with the second winding.2. The voltage regulator circuit of claim 1 , wherein the second output voltage is controlled by controlling a first duty cycle of the first switch.3. The voltage regulator circuit of claim 1 , further comprising:a second coupling inductor having a third winding and a fourth winding, the third winding coupled in series between a second voltage regulator phase of the plurality of voltage regulator phases and the first load output, the second load output coupled to the fourth winding; anda second switch coupled in series with ...

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Номер записи: 39
08-02-2022 дата публикации

System and method for optimizing system power and performance with high power memory modules

Номер: US0011243586B2
Автор: Stuart Allen Berke, Hasnain Shabbir
Принадлежит: Dell Products L.P.

An information handling system includes a processor that runs a maximum memory stress test of a memory module with a refresh rate of memory devices set to a first refresh rate. Then, the processor may receive a power consumption of the memory module. Also, the processor may receive the temperature of the memory devices, and may set the refresh rate to a second refresh rate. The processor may continuously receive both the power consumption of the memory module and the temperature of the memory devices. Based on the continuously received temperature, the processor may determine whether the temperature of the memory devices exceeds a second threshold temperature. If so, the processor may store a first setting as a refresh setting for the memory module. Otherwise, the processor may store a second setting as the refresh setting for the memory module.

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Номер записи: 40
01-02-2024 дата публикации

RUNTIME DE-INTERLEAVE AND RE-INTERLEAVE OF SYSTEM MEMORY

Номер: US20240037030A1
Автор: Stuart Allen Berke
Принадлежит:

An information handling system includes a first memory device that provides a first system physical address (SPA) space for the information handling system having a first capacity. Data is stored on the first memory device with a first interleave configuration. A second memory device provides a second SPA space for the information handling system that has a second capacity that is greater than or equal to the first capacity. Without rebooting the information handling system and without halting a process, the system de-interleaves the data stored on the first memory device, stores the data on the second memory device, and re-interleaves the data.

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Номер записи: 41
03-03-2016 дата публикации

System and Method of Simulation for Next Generation Memory Technology

Номер: US20160064100A1
Автор: Bhyrav M. Mutnury, Douglas S. Winterberg, Stuart Allen Berke
Принадлежит:

A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design, multiplying an input spectrum with each of the transfer functions to provide a plurality of results, summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal. 1. A method comprising:modeling a design of a memory channel to provide a plurality of transfer functions associated with the design;multiplying, by an information handling system, an input spectrum with each of the transfer functions to provide a plurality of results;summing, by the information handling system, the results to provide an output spectrum for the design;performing, by the information handling system, an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design; anddetermining, by the information handling system, a bit error rate (BER) for the design based on the output signal.2. The method of claim 1 , wherein the plurality of transfer functions comprise a forward memory channel transfer function claim 1 , a memory channel cross-talk transfer function claim 1 , a voltage regulator transfer function claim 1 , a power plane resonance transfer function claim 1 , and a broadside coupling transfer function.3. The method of claim 2 , further comprising:receiving the forward memory channel transfer function, the memory channel cross-talk transfer function, the voltage regulator transfer function, the power plane resonance transfer function, and the broadside coupling transfer function from a circuit simulation of the design.4. The method of claim 1 , further comprising:providing an eye diagram from the output signal;wherein determining the BER for the design is based upon the eye diagram.5. The method of claim 1 , further ...

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Номер записи: 42
02-11-2017 дата публикации

System and Method for Performance Optimal Partial Rank/Bank Interleaving for Non-Symmetrically Populated DIMMs Across DDR Channels

Номер: US20170315911A1
Автор: Stuart Allen Berke
Принадлежит:

An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor. 1. A method comprising:determining, by a processor, that a plurality of dual inline memory modules are populated non-symmetrically across a plurality of memory channels; anddividing, by the processor, the dual inline memory modules by bank to create a plurality of interleave groups, wherein each of the interleave groups spans across all of the memory channels, and consecutive accesses to a single interleave group are to banks of different dual inline memory modules on different memory channels.2. The method of claim 1 , wherein each of the interleave groups has the same performance level as the other interleave groups.3. The method of claim 1 , wherein the dual inline memory modules are populated non-symmetrically across the memory modules in response to a first memory channel having more dual inline memory modules populated than the other memory channels have populated.4. The method of claim 1 , wherein the dual inline memory modules are populated non-symmetrically across the memory modules in response to a first memory channel having a different type of dual inline memory module than the other memory channels have populated.5. The method of claim 1 , further comprising:allocating all banks of a first dual inline memory module to a single interleave group.6. The method of claim 1 , further comprising:receiving a user request to have consistent performance across all interleave groups prior to allocating the first and second interleave groups.7. An information handling system comprising:a processor including a plurality of memory channels; anda plurality ...

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Номер записи: 43
26-08-2021 дата публикации

SYSTEM AND METHOD FOR DETERMINING PHYSICAL ORIENTATION OF A MEMORY MODULE USING ON-BOARD THERMAL SENSORS

Номер: US20210263820A1
Автор: Stuart Allen Berke
Принадлежит:

An information handling system includes a memory module having a first thermal sensor for a first memory channel, and a second thermal sensor for a second memory channel. A processor receives a first temperature from the first thermal sensor and a second temperature from the second thermal sensor, and performs a first high bandwidth access of the first memory channel. In response to a predetermined amount of time ending, the processor: receives a third temperature from the first thermal sensor and a fourth temperature from the second thermal sensor; determines a first temperature delta based on a difference between the third and first temperatures; and determines a second temperature delta based on a difference between the fourth and second temperatures. Based on the first and second temperature deltas, the processor determines whether the first or second memory channel is an upstream memory channel. 1. An information handling system , comprising: a first memory channel including a first plurality of memory devices;', 'a first thermal sensor located in a middle of the first memory devices;', 'a second memory channel including a second plurality of memory devices; and', 'a second thermal sensor located in a middle of the second memory devices; and, 'a memory module including receive a first temperature captured by the first thermal sensor;', 'receive a second temperature captured by the second thermal sensor;', 'perform a first high bandwidth access of memory devices within the first memory channel for a predetermined amount of time;', 'receive a third temperature from the first thermal sensor after the predetermined amount of time;', 'receive a fourth temperature from the second thermal sensor after the predetermined amount of time;', 'calculate a first temperature delta based on a difference between the third temperature and the first temperature;', 'calculate a second temperature delta based on a difference between the fourth temperature and the second temperature ...

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Номер записи: 44
28-11-2019 дата публикации

System and Method of Utilizing Memory Modules

Номер: US20190361773A1
Автор: Stuart Allen Berke, Vadhiraj Sankaranarayanan, Bhyrav M. Mutnury
Принадлежит:

In one or more embodiments, one or more systems, methods, and/or processes may determine that a first memory unit (MU) and a second MU of a first channel of a memory module are associated with an issue; may configure a control device to utilize a third MU in place of the first MU; and may configure the control device to utilize a fourth MU, of a second channel of the memory module, in place of the second MU. In one or more embodiments, multiple MUs of the first channel, other than the first and second MUs, may store a first portion of data; the fourth MU may store a second portion of the data; the multiple MUs, other than the first and second MUs, may provide the first portion of the data to a processor; and the fourth MU may provide the second portion of the data to the processor. 1. An information handling system , comprising:at least one processor;a memory medium that is coupled to the at least one processor, that includes instructions executable by the at least one processor, and that includes one or more memory modules; determine that a first memory unit and a second memory unit of a first channel, of a memory module of the one or more memory modules, are associated with an issue;', configure a control device of the memory module to utilize a third memory unit, of the first channel, in place of the first memory unit; and', 'configure the control device to utilize a fourth memory unit, of a second channel of the memory module, in place of the second memory unit;, 'in response to determining that the first memory unit and the second memory unit are associated with the issue], 'wherein the instructions, when executed by the at least one processor, cause the information handling system to receive at least a first portion of data via the first channel;', 'store the at least the first portion of the data via a plurality of memory units of the first channel, other than the first memory unit and the second memory unit;', 'receive a second portion of the data via the ...

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Номер записи: 45
25-05-2017 дата публикации

SYSTEMS AND METHODS FOR A MULTI-RAIL VOLTAGE REGULATOR WITH CONFIGURABLE PHASE ALLOCATION

Номер: US20170147050A1
Автор: Stuart Allen Berke, John J. Breen, BERKE STUART ALLEN, BREEN JOHN J, Berke Stuart Allen, Breen John J.
Принадлежит: Dell Products L.P.

In accordance with embodiments of the present disclosure, an information handling system may include a processor and a power system comprising a plurality of voltage regulator phases, wherein at least one of the plurality of voltage regulator phases comprises an allocable voltage regulator phase that is configured to be selectively allocated to one of at least a first voltage rail and a second voltage rail of the information handling system based on a hardware configuration of the information handling system. 1. An information handling system comprising:a processor; anda power system comprising a plurality of voltage regulator phases, wherein at least one of the plurality of voltage regulator phases comprises an allocable voltage regulator phase that is configured to be selectively allocated to one of at least a first voltage rail and a second voltage rail of the information handling system based on a hardware configuration of the information handling system.2. The information handling system of claim 1 , wherein at least one of the plurality of voltage regulator phases comprises a statically-allocated voltage regulator phase that is configured to be allocated to the first voltage rail regardless of the hardware configuration.3. The information handling system of claim 1 , further comprising a power controller configured to claim 1 , based on the hardware configuration:determine a number of power rails to be allocated to information handling resources of the information handling system;determine a number of voltage regulator phases to be allocated for each of the power rails to be allocated; andselectively allocate the allocable voltage regulator phase to one of at least the first voltage rail and the second voltage rail based on the number of power rails to be allocated and the number of voltage regulator phases to be allocated to each of the power rails to be allocated.4. The information handling system of claim 1 , wherein the hardware configuration comprises an ...

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Номер записи: 46
23-06-2016 дата публикации

System and Method for Performance Optimal Partial Rank/Bank Interleaving for Non-Symmetrically Populated DIMMs Across DDR Channels

Номер: US20160179374A1
Автор: Stuart Allen Berke, BERKE STUART ALLEN
Принадлежит:

An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor. 1. A method comprising:determining, by a processor, that a plurality of dual inline memory modules are populated non-symmetrically across a plurality of memory channels; anddividing, by the processor, the dual inline memory modules by bank to create a plurality of interleave groups, wherein each of the interleave groups spans across all of the memory channels.2. The method of claim 1 , wherein each of the interleave groups has the same performance level as the other interleave groups.3. The method of claim 1 , wherein the dual inline memory modules are populated non-symmetrically across the memory modules in response to a first memory channel having more dual inline memory modules populated than the other memory channels have populated.4. The method of claim 1 , wherein the dual inline memory modules are populated non-symmetrically across the memory modules in response to a first memory channel having a different type of dual inline memory module than the other memory channels have populated.5. The method of claim 4 , further comprising:dividing all of the plurality of dual inline memory modules of a first type by bank to create a plurality of interleave groups, wherein each of the interleave groups that include the dual inline memory modules of the first type spans across all of the memory channels; andcreating a separate interleave group for a first dual inline memory module of the dual inline memory modules in response to the first dual inline memory module being a second type of dual inline memory module.6. The method of claim 1 , further comprising: ...

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Номер записи: 47
08-11-2018 дата публикации

System and Method for Setting Communication Channel Equalization of a Communication Channel between a Processing Unit and a Memory

Номер: US20180321845A1
Автор: Bhyrav M. Mutnury, Stuart Allen Berke, MUTNURY BHYRAV M, BERKE STUART ALLEN, Mutnury, Bhyrav M., Berke, Stuart Allen
Принадлежит:

An information handling system may include a processing unit and a memory device. The processing unit includes a memory controller and is configured to host a BIOS. The memory device is communicatively connected to the memory controller by a communication channel and stores memory device information. The BIOS obtains the memory device information and sets an equalization of the communication channel based on the memory device information. The BIOS may further set the equalization of the communication channel based on parameters of the communication channel. 1. An information handling system comprising:a processing unit with a memory controller and configured to host a BIOS; anda first memory device communicatively connected to the memory controller by a first communication channel and having a first set of first memory device information stored on the first memory device, wherein the BIOS obtains the first set of first memory device information and sets an equalization of the first communication channel based on the first set of first memory device information by setting transmission and reception components of the memory controller.2. The information handling system of claim 1 , further comprising a second memory device communicatively connected to the memory controller by the first communication channel and having a second set of second memory device information stored on the second memory device claim 1 , wherein the BIOS obtains the second set of second memory device information and sets the equalization of the first communication channel based on the second set of second memory device information by setting the transmission and reception components of the memory controller.3. The information handling system of claim 2 , wherein the BIOS sets the equalization of the first communication channel based on parameters of the first communication channel.4. The information handling system of claim 2 , wherein the first memory device includes a first non-volatile memory ...

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Номер записи: 48
02-05-2013 дата публикации

SYSTEM AND METHOD FOR SELECTIVE ERROR CHECKING

Номер: US20130111308A1
Автор: William Sauber, Ayedin Nikazm, Stuart Allen Berke
Принадлежит: DELL PRODUCTS L.P.

A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information. 1. A method of selectively enabling error checking in an information handling system (IHS) that includes a memory controller and a system memory , comprising:receiving, at the memory controller, information indicating that data associated with a first memory portion in the system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory;receiving, at the memory controller, a memory access request directed to one of the first and second memory portions;transmitting data between the memory controller and the system memory in response to the memory access request; andselectively performing an error checking technique on the transmitted data based on the information, the selectively performing including performing the error checking technique if the memory access request is directed to the first memory portion and including transmitting the data without performing the error checking technique if the memory access request is directed to the ...

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Номер записи: 49
19-03-2013 дата публикации

Configurable memory controller/memory module communication system

Номер: US0008402208B2
Автор: Stuart Allen Berke, BERKE STUART ALLEN
Принадлежит: Dell Products L.P., BERKE STUART ALLEN, DELL PRODUCTS LP, DELL PRODUCTS L.P.

A memory system includes a first memory module and a second memory module. A memory controller is coupled to the first and second memory modules and reads configuration information from the first and second memory modules using a memory channel. The controller also configures a switch coupled between the controller and one of the memory modules to communicate using either a chip select line or a memory address line.

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Номер записи: 50
24-04-2018 дата публикации

Structure to dampen barrel resonance of unused portion of printed circuit board via

Номер: US0009955568B2
Автор: Stuart Allen Berke, Sandor Farkas, Bhyrav M. Mutnury, BERKE STUART ALLEN, FARKAS SANDOR, MUTNURY BHYRAV M, Berke, Stuart Allen, Farkas, Sandor, Mutnury, Bhyrav M.
Принадлежит: Dell Products, LP, DELL PRODUCTS LP

A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

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Номер записи: 51
25-01-2024 дата публикации

PROVIDING CACHE LINE METADATA OVER MULTIPLE CACHE LINES

Номер: US20240028453A1
Автор: Stuart Allen Berke
Принадлежит:

An information handling system utilizes data with a cache line size. A memory module is coupled to a memory controller by a memory bus, and stores and retrieves data with a memory line size. The cache line size is an integer multiple of the memory line size. The memory controller calculates error correction code data for each memory line of user data, and generates metadata related to the user data for chunks of data that are equal to an integer number (N) of cache lines, where N is greater than one.

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Номер записи: 52
26-05-2016 дата публикации

SYSTEMS AND METHODS FOR EXTENSION OF POWER SUPPLY HOLD-UP TIME

Номер: US20160149495A1
Автор: Stuart Allen Berke, Mehran Mirjafari, Lei Wang, BERKE STUART ALLEN, MIRJAFARI MEHRAN, WANG LEI
Принадлежит:

In accordance with embodiments of the present disclosure, a voltage rectifier may include an alternating-current-to-direct-current (AC/DC) converter configured to convert an alternating current (AC) source voltage to a first direct current (DC) voltage and a direct-current-to-direct-current (DC/DC) converter configured to convert the first DC voltage to a second DC voltage for delivery to a load of the voltage rectifier, wherein the DC/DC converter is configured to operate in a plurality of operating modes in response to a failure of the AC source voltage. The plurality of operating modes may include a first hold-up mode in which a gain of the DC/DC converter is a first gain and a second hold-up mode in which the gain of the DC/DC converter is a second gain. 1. A voltage rectifier comprising:an alternating-current-to-direct-current (AC/DC) converter configured to convert an alternating current (AC) source voltage to a first direct current (DC) voltage; a first hold-up mode in which a gain of the DC/DC converter is a first gain; and', 'a second hold-up mode in which the gain of the DC/DC converter is a second gain., 'a direct-current-to-direct-current (DC/DC) converter configured to convert the first DC voltage to a second DC voltage for delivery to a load of the voltage rectifier, wherein the DC/DC converter is configured to operate in a plurality of operating modes in response to a failure of the AC source voltage, the plurality of operating modes comprising2. The voltage rectifier of claim 1 , wherein the first gain is approximately equal to the gain of the DC/DC converter in the absence of a failure of the AC source voltage.3. The voltage rectifier of claim 1 , wherein the DC/DC converter increases its gain from the first gain to the second gain by reducing an amount of power delivered from the voltage rectifier to the load.4. The voltage rectifier of claim 3 , wherein the amount of power delivered from the voltage rectifier to the load is reduced by throttling ...

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Номер записи: 53
29-05-2012 дата публикации

System and method for optimizing performance of an information handling system component

Номер: US0008190873B2
Автор: Stuart Allen Berke, William F. Sauber, BERKE STUART ALLEN, SAUBER WILLIAM F, SAUBER WILLIAM F.
Принадлежит: Dell Products L.P., BERKE STUART ALLEN, SAUBER WILLIAM F, DELL PRODUCTS LP, SAUBER WILLIAM F., DELL PRODUCTS L.P.

Systems and methods for optimizing performance of an information handling system component communicatively coupled to the information handling system are disclosed. An information handling system may include a data gathering module and an operating condition controller module. The data gathering module may be configured to retrieve an operating condition characterization value from the component. That operating condition characterization value may be substantially based on a predetermined characteristic of the component. The operating condition controller module may be configured to modify an operating condition of the component based at least on the retrieved operating condition characterization value.

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Номер записи: 54
06-06-2017 дата публикации

System and method of selective encoding for enhanced serializer/deserializer throughput

Номер: US0009673931B2
Автор: Minchuan Wang, Stuart Allen Berke, Bhyrav M. Mutnury, WANG MINCHUAN, BERKE STUART ALLEN, MUTNURY BHYRAV M, Wang Minchuan, Berke Stuart Allen, Mutnury Bhyrav M.
Принадлежит: DELL PRODUCTS, LP, DELL PRODUCTS LP, Dell Products, LP

A serial communication link including first and second components. The first component includes a first management module and a first encoder that provides A-bit/B-bit encoded data to a first channel, where A Подробнее

Номер записи: 55
08-01-2013 дата публикации

System and method for safe handling of information resources by monitoring thermal properties and controlling operation of a cooling fan

Номер: US0008350711B2
Автор: Stuart Allen Berke, Dominick Lovicott, Hasnain Shabbir, William Coxe, BERKE STUART ALLEN, LOVICOTT DOMINICK, SHABBIR HASNAIN, COXE WILLIAM
Принадлежит: Dell Products L.P., DELL PRODUCTS LP, BERKE STUART ALLEN, LOVICOTT DOMINICK, SHABBIR HASNAIN, COXE WILLIAM, DELL PRODUCTS L.P.

Systems and methods for safe handling of information handling resources are provided. In some embodiments, a method is provided. The method may include detecting occurrence of a power down sequence and in response to detecting of the power down sequence, controlling operation of a cooling fan coupled to information handling resources based at least on a first criteria of a predetermined policy. The method may include receiving a signal from a sensor, the signal indicating a thermal property of a particular information handling resource coupled to the sensor. The method may include determining if the thermal property satisfies a second criteria of the predetermined policy, the second criteria comprising a safe temperature range for handling the particular information handling resource. If the thermal property meets the second criteria, the method may provide an alert via an indicator to a user indicating the particular information handling resource is safe for handling.

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Номер записи: 56
03-03-2020 дата публикации

System and method for mapping physical memory with mixed storage class memories

Номер: US0010579392B2
Автор: Vadhiraj Sankaranarayanan, Stuart Allen Berke, Jeffrey Guo, SANKARANARAYANAN VADHIRAJ, BERKE STUART ALLEN, GUO JEFFREY, Sankaranarayanan, Vadhiraj, Berke, Stuart Allen, Guo, Jeffrey
Принадлежит: Dell Products, LP, DELL PRODUCTS LP, DELL PRODUCTS, LP

An information handling system includes a plurality of storage class memory (SCM) devices and a processor. Each SCM device is configured to determine a health indication of the SCM device. The processor is configured to execute code to provide a basic input/output system (BIOS). The BIOS receives the health indications, ranks the SCMs based upon the health indications, determines that a first BIOS function has a first quality of service level, and allocates the first BIOS function to a first SCM based upon the first quality of service level, wherein the first SCM has a highest rank of the SCMs.

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Номер записи: 57
12-04-2016 дата публикации

System aware transmitter adaptation for high speed serial interfaces

Номер: US0009313056B1
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, BERKE STUART ALLEN, MUTNURY BHYRAV M, MUTNURY BHYRAV M.
Принадлежит: DELL PRODUCTS, LP, DELL PRODUCTS LP

A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver.

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Номер записи: 58
25-01-2024 дата публикации

DISTRIBUTED REGION TRACKING FOR TIERED MEMORY SYSTEMS

Номер: US20240028209A1
Автор: Stuart Allen Berke, William Price Dawkins
Принадлежит:

An information handling system includes a processor having a first data storage device in a first memory tier, a second data storage device in a second memory tier, and a tiering manager. The first tier exhibits first data storage attributes and the second tier exhibits second data storage attributes. The tiering manager receives first memory access information from the first data storage device and second memory access information from the second data storage device, makes a determination that a first performance level of the information handling system when first data is stored in the first data storage device can be improved to a second performance level of the information handling system by swapping the first data to the second data storage device based upon the first memory access information and the second memory access information, and swaps the first data to the second data storage device in response to the determination.

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Номер записи: 59
08-08-2017 дата публикации

System and method of training optimization for dual channel memory modules

Номер: US0009728236B1
Автор: Vadhiraj Sankaranarayanan, Bhyrav M. Mutnury, Stuart Allen Berke, SANKARANARAYANAN VADHIRAJ, MUTNURY BHYRAV M, BERKE STUART ALLEN, Sankaranarayanan Vadhiraj, Mutnury Bhyrav M., Berke Stuart Allen
Принадлежит: Dell Products, LP, DELL PRODUCTS LP, DELL PRODUCTS, LP

A memory channel includes a dual channel double data rate (DDR) memory device having a first bank of memory accessed by a first data bus and a first command/address (C/A) bus, and a second bank of memory accessed by a second data bus and a second C/A bus, and a memory controller configured to train the first and second C/A busses with both the first and second C/A busses active, and to train one of the first and second C/A busses with the other of the first and second C/A busses idle.

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Номер записи: 60
05-11-2019 дата публикации

System and method to optimize equalization coefficients in a high-speed serial interface

Номер: US0010469291B2
Автор: Stuart Allen Berke, Minchuan Wang, Bhyrav M. Mutnury, BERKE STUART ALLEN, WANG MINCHUAN, MUTNURY BHYRAV M, Berke, Stuart Allen, Wang, Minchuan, Mutnury, Bhyrav M.
Принадлежит: Dell Products, LP, DELL PRODUCTS LP, DELL PRODUCTS, LP

A high-speed serial data system includes a transmitter and a receiver. The receiver includes a compensation module, a memory, and a control module. The compensation module includes a setting that selects a compensation value from among a plurality of compensation values for a characteristic of the receiver. The memory stores a whitelist value from among the compensation values. The control module determines that a performance level of the receiver is below a performance level threshold. In response to determining that the performance level is below the performance level threshold, the control module uses the whitelist value to reevaluate the performance level of the receiver, and applies the whitelist value to the compensation module when the reevaluated performance level is above the performance level threshold.

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Номер записи: 61
16-08-2016 дата публикации

Systems and methods for data alignment in a memory system

Номер: US0009417802B1
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, Vadhiraj Sankaranarayanan, BERKE STUART ALLEN, MUTNURY BHYRAV M, SANKARANARAYANAN VADHIRAJ, Berke Stuart Allen, Mutnury Bhyrav M., Sankaranarayanan Vadhiraj
Принадлежит: Dell Products L.P., DELL PRODUCTS LP

A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.

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Номер записи: 62
13-04-2017 дата публикации

System and Method to Proactively Screen Component Wear Through Time Domain Response Profiling

Номер: US20170102756A1
Автор: Minchuan Wang, Stuart Allen Berke, Bhyrav M. Mutnury, WANG MINCHUAN, BERKE STUART ALLEN, MUTNURY BHYRAV M, Wang Minchuan, Berke Stuart Allen, Mutnury Bhyrav M.
Принадлежит:

A receiver of a serial communication channel including a memory to store an initial channel characteristic of the serial communication channel, a detector to measure a current channel characteristic of the serial communication channel, and a processor to compare the initial channel characteristic to the current channel characteristic, and to provide an indication when the difference between the initial channel characteristic to the current channel characteristic is greater than a threshold. 1. A receiver of a serial communication channel , comprising:a memory to store an initial channel characteristic of the serial communication channel;a detector to measure a current channel characteristic of the serial communication channel; anda processor to compare the initial channel characteristic to the current channel characteristic, and to provide an indication when the difference between the initial channel characteristic and the current channel characteristic is greater than a threshold.2. The receiver of claim 1 , the processor further to generate a frequency domain representation of a signal received by the receiver claim 1 , the current channel characteristic being based on the signal.3. The receiver of claim 1 , the processor further to generate a time domain representation of a signal received by the receiver claim 1 , the current channel characteristic being based on the signal.4. The receiver of claim 3 , the processor further to determine a degraded component based upon the time domain representation of the signal.5. The receiver of claim 4 , wherein the indication includes an identification of the degraded component.6. The receiver of claim 1 , wherein the initial channel characteristic is obtained based upon a training sequence provided to the receiver at a production test of the receiver in an information handling system.7. The receiver of claim 6 , wherein the current channel characteristic is obtained based upon the training sequence provided to the receiver ...

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Номер записи: 63
20-03-2018 дата публикации

Systems and methods for a multi-rail voltage regulator with configurable phase allocation

Номер: US0009921629B2
Автор: Stuart Allen Berke, John J. Breen, BERKE STUART ALLEN, BREEN JOHN J, Berke Stuart Allen, Breen John J.
Принадлежит: Dell Products L.P., DELL PRODUCTS LP

In accordance with embodiments of the present disclosure, an information handling system may include a processor and a power system comprising a plurality of voltage regulator phases, wherein at least one of the plurality of voltage regulator phases comprises an allocable voltage regulator phase that is configured to be selectively allocated to one of at least a first voltage rail and a second voltage rail of the information handling system based on a hardware configuration of the information handling system.

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Номер записи: 64
12-05-2022 дата публикации

MEMORY THERMAL MANAGEMENT DURING INITIALIZATION OF AN INFORMATION HANDLING SYSTEM

Номер: US20220147126A1
Автор: Jordan Chin, Stuart Allen Berke
Принадлежит: Dell Products L.P.

A memory of an information handling system may determine a memory test pattern for execution on the memory during a memory self-test procedure. The memory may execute the test pattern on the memory. While executing the test pattern on the memory, the memory may determine that a temperature of the memory has exceeded a predetermined temperature threshold. The memory may throttle execution of the test pattern based, at least in part, on the determination that the temperature of the memory has exceeded the first temperature threshold. 1. A method for managing thermal performance of a memory of an information handling system , comprising:determining, by the memory, a first test pattern to be executed on the memory during a memory self-test procedure;executing, by the memory, the first test pattern on the memory;determining, by the memory during execution of the first test pattern, that a first temperature of the memory has exceeded a first predetermined temperature threshold; andthrottling execution of the first test pattern based, at least in part, on the determination that the memory has exceeded the first predetermined temperature threshold.2. The method of claim 1 , further comprising determining a maximum time period for the self-test procedure claim 1 , wherein the first test pattern is determined for execution during a first portion of the maximum time period for the self-test procedure claim 1 , and wherein a length of the first portion of the maximum time period is less than a length of the maximum time period.3. The method of claim 2 , wherein throttling execution of the first test pattern comprises reducing a speed of execution of the first test pattern such that execution of the first test pattern will be completed within the maximum time period for the self-test procedure.4. The method of claim 2 , further comprising:determining, by the memory, a second test pattern to be executed on the memory during the memory self-test procedure, wherein the second test ...

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Номер записи: 65
30-01-2024 дата публикации

Providing cache line metadata over multiple cache lines

Номер: US0011886291B1
Автор: Stuart Allen Berke
Принадлежит: Dell Products L.P., DELL PRODUCTS L.P.

An information handling system utilizes data with a cache line size. A memory module is coupled to a memory controller by a memory bus, and stores and retrieves data with a memory line size. The cache line size is an integer multiple of the memory line size. The memory controller calculates error correction code data for each memory line of user data, and generates metadata related to the user data for chunks of data that are equal to an integer number (N) of cache lines, where N is greater than one.

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Номер записи: 66
28-07-2020 дата публикации

System and method of rerouting an inter-processor communication link based on a link utilization value

Номер: US0010725946B1
Автор: Stuart Allen Berke, Wade Andrew Butcher, BERKE STUART ALLEN, BUTCHER WADE ANDREW, Berke, Stuart Allen, Butcher, Wade Andrew
Принадлежит: Dell Products L.P., DELL PRODUCTS LP

In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor ...

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Номер записи: 67
22-02-2018 дата публикации

STORAGE CLASS MEMORY (SCM) MEMORY MODE CACHE SYSTEM

Номер: US20180052767A1
Автор: Stuart Allen Berke, John E. Jenne
Принадлежит:

An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored. 1. A Storage Class Memory (SCM) memory mode persistent memory cache system , comprising:a first Storage Class Memory (SCM) subsystem that provides first data communication speeds;a persistent memory subsystem that includes at least one non-volatile memory device and that provides second data communication speeds that are greater than the first data communication speeds; and write a plurality of data to the persistent memory subsystem and, in response, update a cache tracking database;', 'write a first subset of the plurality of data to the first SCM subsystem subsequent to the writing of the plurality of data to the persistent memory subsystem and, in response, update the cache tracking database; and', 'receive a shutdown signal and, in response, copy the cache tracking database to the persistent memory subsystem, wherein the persistent memory subsystem is configured to store at least some of the plurality of data and the cache tracking database in the at least one non-volatile memory device during a shutdown associated ...

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Номер записи: 68
22-09-2011 дата публикации

SYSTEMS AND METHODS FOR IMPROVING RELIABILITY AND AVAILABILITY OF AN INFORMATION HANDLING SYSTEM

Номер: US20110231697A1
Автор: Stuart Allen Berke, Mukund Purshottam Khatri, BERKE STUART ALLEN, KHATRI MUKUND PURSHOTTAM
Принадлежит: DELL PRODUCTS L.P.

In one aspect, a method for improving reliability and availability of an information handling system is disclosed. Operational data associated with an operating margin may be captured. A threshold specified by a pre-defined profile may be identified. The pre-defined profile may be useable in adjusting the operating margin. The captured operational data may be compared to the pre-defined threshold. A parameter specified by the pre-defined profile may be identified. The operation of a component of the information handling system may be modified based, at least in part, on the identified parameter specified by the pre-defined profile. The modification may result in adjusting the operating margin.

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Номер записи: 69
26-08-2021 дата публикации

SYSTEM AND METHOD FOR OPTIMIZING SYSTEM POWER AND PERFORMANCE WITH HIGH POWER MEMORY MODULES

Номер: US20210263574A1
Автор: Stuart Allen Berke, Hasnain Shabbir
Принадлежит:

An information handling system includes a processor that runs a maximum memory stress test of a memory module with a refresh rate of memory devices set to a first refresh rate. Then, the processor may receive a power consumption of the memory module. Also, the processor may receive the temperature of the memory devices, and may set the refresh rate to a second refresh rate. The processor may continuously receive both the power consumption of the memory module and the temperature of the memory devices. Based on the continuously received temperature, the processor may determine whether the temperature of the memory devices exceeds a second threshold temperature. If so, the processor may store a first setting as a refresh setting for the memory module. Otherwise, the processor may store a second setting as the refresh setting for the memory module. 1. An information handling system , comprising: a plurality of memory devices; and', 'a plurality of thermal sensors; and, 'a memory module including run a maximum memory stress test of the memory module with a refresh rate of the memory devices set to a first refresh rate;', receive a power consumption of the memory module;', 'receive, from the thermal sensors, the temperature of the memory devices within the memory module; and, 'in response to a temperature of the memory devices being substantially equal to a first threshold temperature, the processor to, 'set the refresh rate of the memory devices to a second refresh rate;, 'a processor to communicate with the memory module and with the cooling fan, the processor to continuously receive the power consumption of the memory module;', 'continuously receive, from the thermal sensors, the temperature of the memory devices within the memory module;', 'based on the continuously received temperature of the memory devices, determine whether the temperature of the memory devices exceeds a second threshold temperature;', 'in response to the temperature of the memory devices ...

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Номер записи: 70
26-06-2014 дата публикации

Systems And Methods For Support Of Non-Volatile Memory On A DDR Memory Channel

Номер: US20140181364A1
Автор: Stuart Allen Berke, Shawn J. Dube, BERKE STUART ALLEN, DUBE SHAWN J, DUBE SHAWN J.
Принадлежит: Dell Products L.P.

Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system.

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Номер записи: 71
12-09-2017 дата публикации

Repeatable backchannel link adaptation for high speed serial interfaces

Номер: US0009762418B2
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, Minchuan Wang, BERKE STUART ALLEN, MUTNURY BHYRAV M, WANG MINCHUAN, Berke Stuart Allen, Mutnury Bhyrav M., Wang Minchuan
Принадлежит: Dell Products, LP, DELL PRODUCTS LP

A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured to perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values.

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Номер записи: 72
14-12-2017 дата публикации

Repeatable Backchannel Link Adaptation for High Speed Serial Interfaces

Номер: US20170359205A1
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, Minchuan Wang
Принадлежит:

A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured to perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values. 1. A receiver , comprising:a first signal processing chain including a first equalization circuit of a first type and a second equalization circuit of a second type, the first equalization circuit configurable to provide a selectable first compensation value to a data bitstream received by the receiver and the second equalization circuit configurable to provide a selectable second compensation value to the data bitstream; anda second signal processing chain including a third equalization circuit of the first type, a fourth equalization circuit of the second type, and a slicer, the third equalization circuit configurable to provide a selectable third compensation value to the data bitstream, the fourth equalization circuit configurable to provide a selectable fourth compensation value to the data bitstream, and the slicer configured to determine a characteristic of the data bitstream as compensated by the third and fourth equalization circuits.2. The receiver of claim 1 , wherein the characteristic comprises an eye height of the data bitstream as compensated by the third and fourth equalization circuits.3. The receiver of claim 2 , wherein the slicer includes a voltage offset input to determine the eye height.4. The receiver of claim 2 , wherein the characteristic further comprises an eye width of the data bitstream ...

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Номер записи: 73
17-11-2015 дата публикации

Power management system

Номер: US0009189045B2
Автор: Stuart Allen Berke, George G. Richards, III, BERKE STUART ALLEN, RICHARDS III GEORGE G, RICHARDS, III GEORGE G.
Принадлежит: Dell Products L.P., DELL PRODUCTS LP, DELL PRODUCTS L.P.

A power management system includes a power system. A powered component is coupled to the power system. A power detect circuit is coupled to the power system. A power system controller is coupled to the power system, the powered component, and the power detect circuit. The power system controller is operable, for each of at least one workload run using the powered component, to program the power detect circuit with a first threshold for a first system operation setting and determine that the first threshold was not exceeded while the workload was running. The power system controller is then operable to program the power detect circuit with a second threshold for the first system operation setting, determine that the second threshold was exceeded while the workload was running and, in response, use the second threshold to allocate power from the power system.

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Номер записи: 74
12-08-2014 дата публикации

System and method for creating and dynamically maintaining system power inventories

Номер: US0008806254B2
Автор: Stuart Allen Berke, Mukund P. Khatri
Принадлежит: Dell Products L.P.

In accordance with the present disclosure, a system and method for creating and dynamically maintaining power inventories of an information handling system is presented. A system for creating and dynamically maintaining power inventories of an information handling system may include a memory and a processor. The processor may be operable to generate power inventories for the information handling system and save the power inventories in the memory. Each of the power inventories may correspond to one of the power states of the information handling system. The processor may also be operable to dynamically update each of the saved power inventories in response to changes in the information handling system.

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Номер записи: 75
06-03-2008 дата публикации

Spacing device for modular system

Номер: US20080055877A1
Автор: Stuart Allen Berke, Jeffrey Michael Lewis
Принадлежит:

A spacing device for adapting electronic modules for insertion into a system is disclosed. In one embodiment, the spacing device includes a body and guide features configured to align the body with mating guide features of electronic modules. The spacing device also includes a coupling portion having coupling arms, which is configured to secure the electronic modules to the body.

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Номер записи: 76
16-07-2013 дата публикации

System-wide time synchronization across power management interfaces and sensor data

Номер: US0008489775B2
Автор: Stuart Allen Berke, George Richards, III, Mark Muccini, BERKE STUART ALLEN, RICHARDS III GEORGE, MUCCINI MARK, RICHARDS, III GEORGE
Принадлежит: Dell Products L.P., BERKE STUART ALLEN, RICHARDS III GEORGE, MUCCINI MARK, DELL PRODUCTS LP, RICHARDS, III GEORGE, DELL PRODUCTS L.P.

A power management control system for an information handling system is disclosed. The power management control system includes a power management interface bus interfacing a plurality of devices, where one or more of the devices is each associated with a time clock. The power management control system further includes a management agent interfacing the power management interface bus. The management agent is configured to: receive a system time; synchronize the one or more time clocks based, at least in part, on the system time; and maintain synchronization of the one or more time clocks, at least in part, via a set of telemetric primitives.

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Номер записи: 77
09-03-2017 дата публикации

SYSTEMS AND METHODS FOR VIRTUAL CURRENT SHARING BETWEEN A POWER SUPPLY UNIT AND A BATTERY BACK-UP UNIT

Номер: US20170068294A1
Автор: Lei Wang, John Erven Jenne, Stuart Allen Berke, Sanjiv Catibog Sinha, WANG LEI, JENNE JOHN ERVEN, BERKE STUART ALLEN, SINHA SANJIV CATIBOG, Wang Lei, Jenne John Erven, Berke Stuart Allen, Sinha Sanjiv Catibog
Принадлежит:

In accordance with embodiments of the present disclosure, a battery back-up unit for supplying electrical energy to an information handling resource via a power bus in response to a power event affecting an ability of a power supply unit to deliver electrical energy to the information handling resource via the power bus may be configured to, in response to the power event and prior to the power supply unit ceasing to deliver electrical energy to the power bus monitor a current share bus having a current share signal driven at least in part by the power supply unit, the current share signal indicative of a first current driven by the power supply unit to the power bus, drive a second current to the power bus in accordance with the current share signal, and refrain from driving the current share bus. 1. An information handling system comprising:an information handling resource;a power supply unit for supplying electrical energy to the information handling resource via a power bus; and monitor a current share bus having a current share signal driven at least in part by the power supply unit, the current share signal indicative of a first current driven by the power supply unit to the power bus;', 'drive a second current to the power bus in accordance with the current share signal; and', 'refrain from driving the current share bus., 'a battery back-up unit for supplying electrical energy to the information handling resource via the power bus in response to a power event affecting an ability of the power supply unit to deliver electrical energy to the power bus, the battery back-up unit configured to, in response to the power event and prior to the power supply unit ceasing to deliver electrical energy to the power bus2. The information handling system of claim 1 , wherein the battery back-up unit comprises a diode arranged to prevent the battery back-up unit from driving the current share bus prior to the power supply unit ceasing to deliver electrical energy to the ...

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Номер записи: 78
13-08-2015 дата публикации

SUPPLEMENTAL POWER SYSTEM FOR POWER EXCURSIONS

Номер: US20150227184A1
Автор: Stuart Allen Berke, George G. Richards, III, Mark Muccini
Принадлежит: Dell Products LP

A supplemental power system includes a powered component, a removable module interface with a plurality of pins, and a plurality of system connections. A system controller detects a first type removable module coupled to the removable module interface and allows signals from the system connections to be transmitted to the first type removable module through the plurality of pins. The system controller detects a second type removable module coupled to the removable module interface and allows power from the second type removable module that is received through the plurality of pins to be transmitted to the powered component while not allowing signals from the system connections to be transmitted to the second type removable module through the plurality of pins. Power that is stored in the second type removable module may be provided to the powered component in response to a detected power excursion by the powered component.

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Номер записи: 79
10-04-2014 дата публикации

POWER MANAGEMENT SYSTEM

Номер: US20140101475A1
Автор: Stuart Allen Berke, George G. Richards, III, BERKE STUART ALLEN, RICHARDS III GEORGE G, RICHARDS, III GEORGE G.
Принадлежит: Dell Products L.P.

A power management system includes a power system. A powered component is coupled to the power system. A power detect circuit is coupled to the power system. A power system controller is coupled to the power system, the powered component, and the power detect circuit. The power system controller is operable, for each of at least one workload run using the powered component, to program the power detect circuit with a first threshold for a first system operation setting and determine that the first threshold was not exceeded while the workload was running. The power system controller is then operable to program the power detect circuit with a second threshold for the first system operation setting, determine that the second threshold was exceeded while the workload was running and, in response, use the second threshold to allocate power from the power system.

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Номер записи: 80
30-01-2018 дата публикации

System and method for enabling transportability of a non volatile dual inline memory module

Номер: US0009880754B2
Автор: Stuart Allen Berke, BERKE STUART ALLEN, Berke Stuart Allen
Принадлежит: DELL PRODUCTS, LP, DELL PRODUCTS LP, Dell Products, LP

A dual inline memory module includes a local memory and a non-volatile memory. The local memory stores data during normal operation of the dual inline memory module. The non-volatile memory includes a first portion and a second portion. The first portion stores the data located in the local memory in response to a power failure of an information handling system in communication with the dual inline memory module. The second portion stores configuration information for the dual inline memory module. The configuration information is utilized to set up the dual inline memory module in a new information handling system.

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Номер записи: 81
21-11-2017 дата публикации

System and method for optimizing link performance with lanes operating at different speeds

Номер: US0009825730B1
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, BERKE STUART ALLEN, MUTNURY BHYRAV M, Berke Stuart Allen, Mutnury Bhyrav M.
Принадлежит: DELL PRODUCTS, LP, DELL PRODUCTS LP

A serial communication link includes a receiver and a transmitter coupled to the receiver by a first serial communication lane operating at a first speed, and a second serial communication lane operating at a second speed. The second speed is slower than the first speed. The transmitter can include bit steering logic that receives a data stream, provides a first number of bits of the data stream to the first serial communication lane, and provides a second number of bits to the second serial communication lane. The proportion of the first number of bits to the second number of bits is the same as a proportion of the first speed to the second speed.

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Номер записи: 82
30-07-2020 дата публикации

Apparatus and Method of Optimizing Memory Transactions to Persistent Memory Using an Architectural Data Mover

Номер: US20200242040A1
Автор: Shyamkumar T. Iyer, Stuart Allen Berke, IYER SHYAMKUMAR T, BERKE STUART ALLEN, Iyer, Shyamkumar T., Berke, Stuart Allen
Принадлежит:

An information handling system with improved memory transactions includes a data mover configured to generate a transaction layer packet (TLP) hint when a descriptor includes a write operation to a persistent memory. A logic block may perform a persistent write based on the TLP hint. 1. An information handling system having optimized memory transactions , comprising:an application core of a processor, the application core is configured to create a descriptor;a data mover to communicate with the application core, the data mover including a management controller that is configured to generate a transaction layer packet (TLP) hint when the descriptor includes a write operation to a persistent memory; anda hardware logic block disposed between the data mover and a memory controller of the processor, the hardware logic block configured to perform an automatic persistent write based from the TLP hint associated with the write operation, wherein the automatic persistent write to the persistent memory is performed without the processor performing the write operation.2. The information handling system of claim 1 , wherein the descriptor is created for a move operation that includes a read operation to a source memory and the write operation to the persistent memory.3. The information handling system of claim 2 , wherein the read and write operations are performed using a peripheral component interconnect express (PCIe) interface.4. The information handling system of claim 2 , wherein the data mover injects the TLP hint during the write operation.5. The information handling system of claim 2 , wherein the source memory includes a volatile or a non-volatile memory.6. The information handling system of claim 1 , wherein the data mover uses a reserve bit in TLP prefixes to generate the TLP hint.7. The information handling system of claim 1 , wherein the data mover creates an additional bit on a TLP header to generate the TLP hint.8. The information handling system of claim 1 , ...

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Номер записи: 83
03-03-2020 дата публикации

System and method for providing per channel frequency optimization in a double data rate memory system

Номер: US0010579517B2
Автор: Stuart Allen Berke, Vadhiraj Sankaranarayanana, Bhyrav M. Mutnury, BERKE STUART ALLEN, SANKARANARAYANANA VADHIRAJ, MUTNURY BHYRAV M, Berke, Stuart Allen, Sankaranarayanana, Vadhiraj, Mutnury, Bhyrav M.
Принадлежит: Dell Products, LP, DELL PRODUCTS LP, DELL PRODUCTS, LP

An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.

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Номер записи: 84
23-02-2017 дата публикации

SYSTEMS AND METHODS TO OPTIMIZE BOOT FOR INFORMATION HANDLING SYSTEM COMPRISING PERSISTENT MEMORY

Номер: US20170052794A1
Автор: Stuart Allen Berke, Shane Michael Chiasson, BERKE STUART ALLEN, CHIASSON SHANE MICHAEL, Berke Stuart Allen, Chiasson Shane Michael
Принадлежит:

A basic input/output system may be configured to, during boot of an information handling system in a pre-operating system environment of the information handling system, calculate an amount of energy required to perform a persistent memory save operation in a persistent memory of the information handling system in order to transfer data from a volatile memory of the persistent memory communicatively coupled to the processor to a non-volatile memory of the persistent memory communicatively coupled to the volatile memory, cause charging of an energy storage device for providing electrical energy to perform persistent memory save operations at least until a charging level of the energy storage device satisfies the amount of energy, and boot to an operating system of the information handling system responsive to the charging level of the energy storage device satisfying the amount of energy. 1. An information handling system comprising:a processor; calculate an amount of energy required to perform a persistent memory save operation in a persistent memory of the information handling system in order to transfer data from a volatile memory of the persistent memory communicatively coupled to the processor to a non-volatile memory of the persistent memory communicatively coupled to the volatile memory;', 'cause charging of an energy storage device for providing electrical energy to perform persistent memory save operations at least until a charging level of the energy storage device satisfies the amount of energy; and', 'boot to an operating system of the information handling system responsive to the charging level of the energy storage device satisfying the amount of energy., 'a basic input/output system communicatively coupled to the processor and configured to, during boot of the information handling system in a pre-operating system environment of the information handling system2. The information handling system of claim 1 , wherein calculating the amount of energy ...

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Номер записи: 85
02-09-2021 дата публикации

SYSTEM AND METHOD FOR VARIABLE INPUT OUTPUT VOLTAGE ON DIFFERENT CHANNELS FOR INCREASING POWER EFFICIENCY

Номер: US20210271311A1
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, Douglas S. Winterberg
Принадлежит:

An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (Vddq) setting for bidirectional communications with the CPU.

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Номер записи: 86
06-04-2010 дата публикации

Multiple cell computer systems and methods

Номер: US0007694064B2
Автор: Mark Shaw, Russ William Herrell, Stuart Allen Berke, SHAW MARK, HERRELL RUSS WILLIAM, BERKE STUART ALLEN
Принадлежит: Hewlett-Packard Development Company, L.P., HEWLETT PACKARD DEVELOPMENT CO, HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

In an embodiment, a multi-processor computer system includes multiple cells, where a cell may include one or more processors and memory resources. The system may further include a global crossbar network and multiple cell-to-global-crossbar connectors, to connect the multiple cells with the global crossbar network. In an embodiment, the system further includes at least one cell-to-cell connector, to directly connect at least one pair of the multiple cells. In another embodiment, the system further includes one or more local crossbar networks, multiple cell-to-local-crossbar connectors, and local input/output backplanes connected to the one or more local crossbar networks.

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Номер записи: 87
02-08-2018 дата публикации

Structure to Dampen Barrel Resonance of Unused Portion of Printed Circuit Board Via

Номер: US20180220527A1
Автор: Stuart Allen Berke, Sandor Farkas, Bhyrav M. Mutnury
Принадлежит:

A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer. 1. A method , comprising:determining a length of an unused portion of a first via in a signal path of a printed circuit board;determining a Nyquist frequency of a signal communicated on the signal path;estimating a resonant frequency of the first via based on the length of the unused portion of the first via; andin response to determining that the Nyquist frequency is approximately equal to the resonant frequency, plating a wall of the first via with a high resistivity conductive material.2. The method of claim 1 , wherein:the printed circuit board includes a conductive layer;the signal path includes a trace in the conductive layer coupled to the first via; andthe conductive layer is composed of a material other than the high resistivity conductive material.3. The method of claim 1 , further comprising:plating the wall of a second via of the printed circuit board with a material other than the high resistivity conductive material.4. The method of claim 1 , further comprising:plating the wall of the first via with a second material.5. The method of claim 1 , wherein the high resistivity conductive material is tin.6. The method of claim 1 , further comprising:selecting the high resistivity conductive material based on a property of the signal.7. A method claim 1 , comprising:providing a first trace in a first conductive layer of a printed circuit board;providing a second trace in a second conductive layer of the printed circuit board;plating a wall of a via with a third conductive layer to interconnect the ...

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Номер записи: 88
25-01-2024 дата публикации

OPTIMAL MEMORY TIERING OF LARGE MEMORY SYSTEMS USING A MINIMAL NUMBER OF PROCESSORS

Номер: US20240028201A1
Автор: Stuart Allen Berke
Принадлежит:

An information handling system includes a compute express link (CXL) multi-port controller (MPC). A first processor includes first memory modules coupled to the first processor. A second processor includes second memory modules coupled to the second processor. The CXL MPC is coupled via a first CXL port to the first processor and is coupled via a second CXL port to the second processor. The CXL MPC includes third memory modules coupled to the CXL MPC. The first memory modules, the second memory modules, and the third memory modules comprise a common cache coherency domain.

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Номер записи: 89
16-06-2011 дата публикации

System and Method for Visually Indicating Unsafe Handling Temperature of an Information Handling System Component

Номер: US20110140898A1
Автор: Stuart Allen Berke, Shawn P. Hoss
Принадлежит: Dell Products L.P.

Systems and methods for indicating the unsafe service handling temperature of an information handling system component are disclosed. A method may include sensing a surface temperature of the component and comparing the surface temperature to a first and second threshold temperatures. The method may further include displaying various temperature warning by multiple temperature indicators if the surface temperature is above or below the threshold temperatures.

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Номер записи: 90
19-05-2020 дата публикации

System and method to dynamically increase memory channel robustness at high transfer rates

Номер: US0010657009B2
Автор: Bhyrav M. Mutnury, Stuart Allen Berke, Vadhiraj Sankaranarayanan, MUTNURY BHYRAV M, BERKE STUART ALLEN, SANKARANARAYANAN VADHIRAJ, Mutnury, Bhyrav M., Berke, Stuart Allen, Sankaranarayanan, Vadhiraj
Принадлежит: Dell Products, L.P., DELL PRODUCTS LP, DELL PRODUCTS, LP

A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

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Номер записи: 91
25-07-2019 дата публикации

System and Method for Mapping Physical Memory with Mixed Storage Class Memories

Номер: US20190227809A1
Автор: Vadhiraj Sankaranarayanan, Stuart Allen Berke, Jeffrey Guo, SANKARANARAYANAN VADHIRAJ, BERKE STUART ALLEN, GUO JEFFREY, Sankaranarayanan, Vadhiraj, Berke, Stuart Allen, Guo, Jeffrey
Принадлежит:

An information handling system includes a plurality of storage class memory (SCM) devices and a processor. Each SCM device is configured to determine a health indication of the SCM device. The processor is configured to execute code to provide a basic input/output system (BIOS). The BIOS receives the health indications, ranks the SCMs based upon the health indications, determines that a first BIOS function has a first quality of service level, and allocates the first BIOS function to a first SCM based upon the first quality of service level, wherein the first SCM has a highest rank of the SCMs. 1. An information handling system , comprising:a plurality of storage class memory (SCM) devices, each SCM device configured to determine a health indication of the SCM device; and receive the health indications;', 'rank the SCMs based upon the health indications;', 'determine that a first application has a first quality of service level; and', 'allocate the first application to a first SCM based upon the first quality of service level, wherein the first SCM has a highest rank of the SCMs., 'a processor operable to execute code to provide an operating system configured to2. The information handling system of claim 1 , wherein the operating system is further configured to:determine that a second application has a second quality of service level, the second quality of service level lower than the first quality of service level; andallocate the second application to a second SCM based upon the second quality of service level, where the second SCM has a lower rank than the first SCM.3. The information handling system of claim 2 , wherein claim 2 , prior to allocating the second application to the second SCM claim 2 , the operating system is further configured to:determine that an available memory capacity of the first SCM is less than a demanded memory capacity of the second application, wherein allocating the second application to the second SCM is in response to determining ...

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Номер записи: 92
27-08-2020 дата публикации

System and Method to Dynamically Increase Memory Channel Robustness at High Transfer Rates

Номер: US20200272545A1
Автор: Bhyrav M. Mutnury, Stuart Allen Berke, Vadhiraj Sankaranarayanan, MUTNURY BHYRAV M, BERKE STUART ALLEN, SANKARANARAYANAN VADHIRAJ, Mutnury, Bhyrav M., Berke, Stuart Allen, Sankaranarayanan, Vadhiraj
Принадлежит:

A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level. 1. A dynamic random access memory (DRAM) device , comprising:an input to receive an on-die termination (ODT) signal and a WRITE signal; andODT circuitry to terminate an interface circuit in a select one of a plurality of impedance levels, the interface circuit to provide a data signal between a memory controller and the DRAM device; select a first impedance level in response to a first state of the ODT signal;', 'select a second impedance level in response to a second state of the ODT signal and to a first state of the WRITE signal;', 'select a third impedance level in response to the second state of the ODT and to a second state of the WRITE signal; and', 'when the WRITE signal is in the second state and the ODT signal transitions from the second state to the first state, to transition from the third impedance level to the first impedance level within a predetermined amount of time, wherein in transitioning from the third impedance level to the first impedance level, the ODT controller is further configured to a) terminate the interface circuit at a fourth impedance level at a particular time within the predetermined amount of ...

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Номер записи: 93
27-04-2021 дата публикации

System and method of asymmetric system description for optimized scheduling

Номер: US0010990562B2
Автор: Andrew Butcher, Stuart Allen Berke, BUTCHER ANDREW, BERKE STUART ALLEN, Butcher, Andrew, Berke, Stuart Allen
Принадлежит: Dell Products L.P., DELL PRODUCTS LP, DELL PRODUCTS, LP

An information handling system includes processors disposed in sockets, and interconnect links providing point-to-point links between the sockets. One of the processors determines an arrangement of the processors, memories and the interconnect links, and determines a value for each of the processors, each of the memories, and each of the interconnect links. The processor calculates interconnect link bandwidth values for each of the interconnect links based at least in part on the determined value and the arrangement of the processors, the memories and the interconnect links. The processor also populates an interconnect bandwidth table using the interconnect link bandwidth values.

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Номер записи: 94
07-04-2011 дата публикации

INFORMATION HANDLING SYSTEM MEMORY MODULE OPTIMIZATION

Номер: US20110082971A1
Автор: Stuart Allen Berke
Принадлежит: DELL PRODUCTS L.P.

A memory system includes a first memory module and a second memory module. A memory controller is coupled to the first and second memory modules and reads configuration information from the first and second memory modules using a memory channel. The controller also configures a switch coupled between the controller and one of the memory modules to communicate using either a chip select line or a memory address line.

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Номер записи: 95
28-03-2013 дата публикации

METHOD AND SYSTEM FOR MANAGING THE POWER CONSUMPTION OF AN INFORMATION HANDLING SYSTEM

Номер: US20130080799A1
Автор: Paul Artman, Stuart Allen Berke
Принадлежит:

A method for managing the power consumption of an information handling system including a processor and an associated cooling system. The method may include providing power to the cooling system based on a performance/power balance setting, accepting a user input to adjust the performance/power balance setting, and adjusting the power provided to the cooling system based on the adjusted performance/power balance setting. The performance/power balance setting may define a balance between performance of the processor and power consumption of the associated cooling system. 1. A method for managing the power consumption of an information handling system including a processor and an associated cooling system , the method comprising:providing power to the cooling system based on a performance/power balance setting, the performance/power balance setting correlating to a performance state for the processor and a power state for the cooling system;accepting a user input to adjust the performance/power balance setting; andadjusting the power provided to the cooling system based on the adjusted performance/power balance setting.2. The method of claim 1 , further comprising recommending to the user a selection for the performance/power balance setting based on the historical performance of the information handling system.3. The method of claim 1 , wherein the performance/power balance setting includes one or more processor thermal profiles associated with the processor.4. The method of claim 1 , wherein accepting a user input includes accepting a user change to one or more settings of a boot monitor associated with the information handling system.5. The method of claim 1 , wherein accepting a user input includes accepting a user change to one or more settings of an operating system associated with the information handling system.6. The method of claim 1 , wherein providing power to the cooling system is performed by a baseboard management controller.7. The method of claim 1 , ...

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Номер записи: 96
16-10-2012 дата публикации

Transportable cache module for a host-based raid controller

Номер: US0008291153B2
Автор: Stuart Allen Berke, Gary Benedict Kotzur, BERKE STUART ALLEN, KOTZUR GARY BENEDICT
Принадлежит: Dell Products L.P., BERKE STUART ALLEN, KOTZUR GARY BENEDICT, DELL PRODUCTS LP, DELL PRODUCTS L.P.

In accordance with the present disclosure, a system and method for an information handling system having transportable cache module is disclosed herein. The information handling system has a memory controller coupled to a central processing unit and a plurality of memory modules. The transportable cache module has a protected memory module, a nonvolatile memory module, a module controller, and an independent power source. The module controller is operative to copy a protected memory region from the protected memory module to a nonvolatile memory region on the nonvolatile memory module. The independent power source is operative to supply power to the protected memory module, the nonvolatile memory module, and the module controller.

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Номер записи: 97
21-05-2024 дата публикации

Method for CXL fallback in a CXL system

Номер: US0011989081B2
Автор: Isaac Q. Wang, Stuart Allen Berke, Jordan Chin
Принадлежит: Dell Products L.P., DELL PRODUCTS L.P.

An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.

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Номер записи: 98
09-04-2019 дата публикации

Systems and methods for providing grooved vias in high-speed printed circuit boards

Номер: US0010257931B2
Автор: Stuart Allen Berke, Bhyrav M. Mutnury, Sandor Farkas, BERKE STUART ALLEN, MUTNURY BHYRAV M, FARKAS SANDOR, Berke, Stuart Allen, Mutnury, Bhyrav M., Farkas, Sandor
Принадлежит: Dell Products, L.P., DELL PRODUCTS LP

Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.

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Номер записи: 99
29-02-2024 дата публикации

METHOD TO OFFLOAD MEMORY TIERING FROM THE CPU TO THE MEMORY DEVICE

Номер: US20240070065A1
Автор: Quy Ngoc Hoang, Stuart Allen Berke
Принадлежит:

An information handling system includes a memory controller coupled to a first memory device and to a second memory device. The first and second memory devices are configured to receive memory access requests addressed based upon a device physical address (DPA) space of the memory controller. The memory controller incudes a page redirection table having an entry for each page of a host physical address (HPA) space of the information handling system corresponding with the pages of the DPA space. Each entry of the page redirection table associates the particular page of the HPA space with a page within the DPA space. The memory controller receives memory access requests addressed with HPAs from a host processor, and fulfills the memory access requests from a selected one of the first and second memory devices based upon DPAs determined from the entries of the page redirection table.

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Номер записи: 100
11-10-2012 дата публикации

Memory buffer for buffer-on-board applications

Номер: US20120260137A1
Автор: Stuart Allen Berke
Принадлежит: Dell Products LP

Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times.

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Номер записи: 101
28-02-2013 дата публикации

MEMORY COMPATIBILITY SYSTEM AND METHOD

Номер: US20130054949A1
Автор: Berke Stuart Allen, Sauber William
Принадлежит: DELL PRODUCTS L.P.

An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system. 1. An apparatus , comprising:a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard;a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard;a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket;a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system; anda power regulation module communicatively coupled to the virtualization module and the second socket ...

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Номер записи: 102
16-05-2013 дата публикации

SYSTEM AND METHOD FOR SAFE HANDLING OF INFORMATION HANDLING RESOURCES

Номер: US20130120149A1
Автор: Berke Stuart Allen, Coxe, III William K., Lovicott Dominick, Shabbir Hasnain
Принадлежит:

Systems and methods for safe handling of information handling resources are provided. In some embodiments, a method is provided. The method may include detecting occurrence of a power down sequence and in response to detecting of the power down sequence, controlling operation of a cooling fan coupled to information handling resources based at least on a first criteria of a predetermined policy. The method may include receiving a signal from a sensor, the signal indicating a thermal property of a particular information handling resource coupled to the sensor. The method may include determining if the thermal property satisfies a second criteria of the predetermined policy, the second criteria comprising a safe temperature range for handling the particular information handling resource. If the thermal property meets the second criteria, the method may provide an alert via an indicator to a user indicating the particular information handling resource is safe for handling. 120-. (canceled)21. A system for safe handling of information handling resources , comprising:a cooling fan;a plurality of information handling resources associated with the cooling fan;a sensor communicatively coupled to at least one of the information handling resources; and detect an occurrence of a power down sequence;', 'control operation of the cooling fan based on a predetermined policy in response to detecting the occurrence of the power down sequence;', 'receive a signal from the sensor indicating a thermal property of a particular information handling resource communicatively coupled to the sensor;', 'determine if the thermal property of the particular information handling resource satisfies a criteria of the predetermined policy; and', 'provide an alert to a user indicating that the particular information handling resource is safe for handling if the thermal property satisfies the criteria., 'a controller communicatively coupled to the sensor, the controller configured to22. The system of ...

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Номер записи: 103
13-06-2013 дата публикации

Memory controller-independent memory mirroring

Номер: US20130151767A1
Автор: Stuart Allen Berke, William Sauber
Принадлежит: Dell Products LP

A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.

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Номер записи: 104
27-06-2013 дата публикации

CONFIGURABLE MEMORY CONTROLLER/MEMORY MODULE COMMUNICATION SYSTEM

Номер: US20130166836A1
Автор: Berke Stuart Allen
Принадлежит: DELL PRODUCTS L.P.

A memory system includes a first memory module and a second memory module. A memory controller is coupled to the first and second memory modules and reads configuration information from the first and second memory modules using a memory channel. The controller also configures a switch coupled between the controller and one of the memory modules to communicate using either a chip select line or a memory address line. 1. A memory system comprising:a first memory module;a second memory module;at least one switch coupled to at least one of the first memory module and the second memory module; anda memory controller coupled to each of the first memory module and the second memory module, wherein the memory controller is coupled to at least one of the first memory module and the second memory module through the least one switch via a plurality of signal lines, and wherein the memory controller is operable to determine a memory module type for at least one of the first memory module and the second memory module, and configure the at least one switch based on at least one memory module type requirement and the signaling needs of at least one of the first memory module and the second memory module to allow communication between the memory controller and at least one of the first memory module and the second memory module using at least one of the plurality of signals lines.2. The memory system of claim 1 , wherein at least one of the first memory module and the second memory modules includes a dual in-line memory module (DIMM).3. The memory system of claim 2 , wherein at least one of the first memory module and the second memory module includes an unbuffered DIMM (UDIMM) claim 2 , a registered DIMM (RDIMM) claim 2 , or a load reduced DIMM (LR-DIMM).4. The memory system of claim 1 , wherein the memory module is operable to determine the memory module type for at least one of the first memory module and the second memory module using serial presence detect (SPD) information.5. ...

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Номер записи: 105
26-09-2013 дата публикации

SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION OF MEMORY

Номер: US20130254474A1
Автор: Berke Stuart Allen, Sauber William
Принадлежит: DELL PRODUCTS L.P.

Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable. 1. A method for reducing power consumption in memory , comprising:tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use;setting, by the operating system, a Partial Array Self Refresh field of a mode register, the field indicating a portion of the logical units of the memory system that are in use; andrefreshing one or more of the one or more logical units of the memory system based on the Partial Array Self Refresh field.2. A method according to claim 1 , wherein each logical unit of the memory system is a bank of the memory system.3. (canceled)4. A method according to claim 1 , further comprising disabling claim 1 , by the operating system claim 1 , logical unit-level interleaving.5. A method according to claim 1 , further comprising disabling claim 1 , by the operating system claim 1 , reliability claim 1 , availability claim 1 , and serviceability features of a memory controller configured to control the one or more logical units.6. A method according to claim 1 , further comprising:analyzing the Partial Array Self Refresh field to determine if a particular logical unit is in use; andexecuting a reliability, availability, and serviceability operation on the particular logical unit in response to a determination that the Partial Array Self Refresh field indicated the particular logical ...

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Номер записи: 106
26-09-2013 дата публикации

MEMORY CONTROLLER-INDEPENDENT MEMORY SPARING

Номер: US20130254506A1
Автор: Berke Stuart Allen, Sauber William
Принадлежит: DELL PRODUCTS L.P.

An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations. 1. A memory device , comprising:a connection that is operable to transmit signals to and from a memory controller and firmware;a first memory region and a second memory region; anda memory buffer coupling the first memory region and the second memory region to the connection, wherein the memory buffer is operable, in response to operations performed by the firmware, to perform copy operations without instruction from the memory controller in order to copy data from the first memory region to the second memory region, and wherein the memory buffer is further operable to route requests from the memory controller to one of the first memory region and the second memory region.2. The memory device of claim 1 , wherein the first memory region is a failing memory region and the second memory region is a spare memory region.3. The memory device of claim 1 , wherein the operations performed by the firmware include an instruction provided by the firmware to the memory controller to produce at least one additional refresh operation time period and the ...

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Номер записи: 107
21-11-2013 дата публикации

SYSTEM-WIDE TIME SYNCHRONIZATION ACROSS POWER MANAGEMENT INTERFACES AND SENSOR DATA

Номер: US20130311805A1
Автор: Berke Stuart Allen, III George, Muccini Mark, Richards
Принадлежит:

A power management control system for an information handling system is disclosed. The power management control system includes a power management interface bus interfacing a plurality of devices, where one or more of the devices is each associated with a time clock. The power management control system further includes a management agent interfacing the power management interface bus. The management agent is configured to: receive a system time; synchronize the one or more time clocks based, at least in part, on the system time; and maintain synchronization of the one or more time clocks, at least in part, via a set of telemetric primitives. 1. A power management control system for an information handling system , the power management control system comprising:a power management interface bus interfacing a plurality of devices, wherein one or more of the devices is each associated with a time clock; anda management agent interfacing the power management interface bus, wherein the management agent is configured to:receive a system time;synchronize the one or more time clocks based, at least in part, on the system time; andmaintain synchronization of the one or more time clocks, at least in part, via a set of telemetric primitives.2. The power management control system of claim 1 , wherein the management agent is further configured to maintain synchronization of the one or more time clocks based claim 1 , at least in part claim 1 , on timestamp information received via the power management interface bus.3. The power management control system of claim 1 , wherein the one or more of the devices comprises at least two devices claim 1 , and wherein the management agent is further configured to synchronize the one or more time clocks based claim 1 , at least in part claim 1 , on a calibrated responder associated with one of the devices.4. The power management control system of claim 1 , wherein the management agent is further configured to maintain synchronization of the ...

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Номер записи: 108
06-03-2014 дата публикации

DYNAMIC POWER BUDGET ALLOCATION

Номер: US20140067139A1
Автор: Berke Stuart Allen, III George G., Richards
Принадлежит: DELL PRODUCTS L.P.

A dynamic power budget allocation system includes a plurality of powered subsystems. A power system controller is coupled to the plurality of powered subsystems. The power system controller is operable, for each of a plurality of time intervals, to retrieve power usage data from each of the plurality of subsystems during a current time interval. The power system controller is then operable to project power requirements for the plurality of subsystems for a subsequent time interval using the power usage data. The power system controller is then operable to determine at least one power setting for at least one of the plurality of subsystems using the power requirements, and program the at least one of the plurality of subsystems with the at least one power setting. Each powered subsystem may include a voltage regulator that provides the power usage data and is programmed with the at least one power setting. 1. A dynamic power budget allocation system , comprising:a plurality of powered subsystems; and retrieve power usage data from each of the plurality of powered subsystems during a current time interval;', 'project power requirements for the plurality of powered subsystems for a subsequent time interval using the power usage data;', 'determine at least one power setting for at least one of the plurality of powered subsystems using the power requirements; and', 'program the at least one of the plurality of powered subsystems with the at least one power setting., 'a power system controller coupled to the plurality of powered subsystems, wherein the power system controller is operable, for each of a plurality of time intervals, to2. The dynamic power budget allocation system of claim 1 , wherein each of the powered subsystems includes at least one powered subsystem component coupled to a powered subsystem voltage regulator claim 1 , and wherein the subsystem voltage regulator is operable to provide the power system controller with the power usage data and to be ...

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Номер записи: 109
14-01-2016 дата публикации

System and Method for Enabling Transportability of a Non Volatile Dual Inline Memory Module

Номер: US20160011802A1
Автор: Berke Stuart Allen
Принадлежит:

A dual inline memory module includes a local memory and a non-volatile memory. The local memory stores data during normal operation of the dual inline memory module. The non-volatile memory includes a first portion and a second portion. The first portion stores the data located in the local memory in response to a power failure of an information handling system in communication with the dual inline memory module. The second portion stores configuration information for the dual inline memory module. The configuration information is utilized to set up the dual inline memory module in a new information handling system. 1. A method comprising:storing, at a local memory of a dual in line memory module, data during normal operation of the dual inline memory module within an information handling system; andstoring, at a first portion of a non-volatile memory of the dual inline memory module, the data located in the local memory in response to a power failure of the information handling system in communication with the dual inline memory module; andstoring, at a second portion of the non-volatile memory, configuration information for the dual inline memory module, wherein the configuration information is utilized to set up the dual inline memory module after a loss of power.2. The method of claim 1 , further comprising:retrieving the configuration information from the second portion of the non-volatile memory after the dual inline memory module regains power, wherein the configuration information includes a dual inline memory module slot identifier, a non-volatile dual inline memory module set sequence number, and a system model number for the dual inline memory module;comparing a current dual inline memory module slot location in the information handling system with the dual inline memory module slot identifier of the dual inline memory module to validate that the dual inline memory module is populated in a correct dual inline memory module slot after the dual inline ...

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Номер записи: 110
14-01-2021 дата публикации

MEMORY DEVICE FAILURE RECOVERY SYSTEM

Номер: US20210011806A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M.
Принадлежит:

A memory device failure recovery system includes a memory device management engine that is coupled to a first memory device via a first memory device slot, and a memory device management database. The memory device management engine identifies that the first memory device has experienced a failure in a configuration region of the first memory device during a current boot operation and, in response, retrieves memory device component information and memory device configuration information that is stored in the memory device management database and that was retrieved as part of a prior boot operation from a memory device that was connected to the first memory device slot. During the current boot operation, the memory device management engine determines whether first memory device components on the first memory device correspond to the memory device component information and, if so, uses the memory device configuration information to configure the first memory device. 1. A memory device failure recovery system , comprising:a first memory device that is connected to a first memory device slot;a memory device management database; and identify, during a current boot operation, that the first memory device has experienced a failure in a configuration region of the first memory device;', 'retrieve, from the memory device management database and during the current boot operation, memory device component information and memory device configuration information that was retrieved as part of a prior boot operation from a memory device that was connected to the first memory device slot;', 'determine, during the current boot operation, whether first memory device components on the first memory device correspond to the memory device component information; and', 'use, during the current boot operation and in response to determining that the first memory device components on the first memory device correspond to the memory device component information, the memory device configuration ...

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Номер записи: 111
19-01-2017 дата публикации

METHODS OF POWER SUPPLY UNIT ROTATING IN AN INFORMATION HANDLING SYSTEM

Номер: US20170017293A1
Автор: Berke Stuart Allen, Draper William, Jenne John Evren, MIRJAFARI Mehran, MUCCINI MARK A., Razdan Ashish, Wang Wei
Принадлежит: Dell Products, L.P.

A method of power supply unit rotating in an information handling system (IHS) may include a control unit dividing a power loading of an IHS into N sections, where N corresponds to a number of power supply units coupled to the IHS. The control unit may configure a first power supply unit to an active state and configure one or more remaining power supply units to a suspended state during a first time period. The control unit may configure the first power supply unit to the suspended state and configure a second power supply unit to the active state in response to a second time period being reached. The control unit may rotate the active state among the power supply units in response to sequential time periods being reached. In an embodiment the control unit may rotate the active state sequentially between each of the subsequent power supplies. 1. A method of adjusting power supply modes , comprising:dividing, with a control unit, a power loading of an information handling system into N sections, wherein N corresponds to a number of power supply units coupled to the information handling system;configuring, with the control unit, a first power supply unit to an active state during a first time period;configuring, with the control unit, one or more of the remaining power supply units to a suspended state during the first time period;configuring, with the control unit, the first power supply to the suspended state in response to a second time period being reached;configuring, with the control unit, a second power supply to the active state in response to the second time period being reached; androtating, with the control unit, the active state among the power supply units in response to sequential time periods being reached.2. The method of claim 1 , wherein the suspended state comprises a sleep capable state.3. The method of claim 1 , wherein the suspended state comprises a sleep state.4. The method of claim 1 , further comprising rotating claim 1 , with the control ...

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Номер записи: 112
17-04-2014 дата публикации

Supplemental power system for power excursions

Номер: US20140108846A1
Автор: George G. Richards, III, Mark Muccini, Stuart Allen Berke
Принадлежит: Dell Products LP

A supplemental power system for IHS power excursions includes a processor and a memory coupled to the processor. A power system is coupled to the processor and a plurality of power supply paths. A first power supply path is operable to supply power at a first voltage from the power system to the processor. A second power supply path is operable to store power from the power system at a second voltage that is greater than the first voltage, and the second power supply path is further operable to supply the power stored at the second voltage to the processor during power excursions by the processor. In some embodiments, the second power supply path may include a boost converter to increase power at the first voltage to the second voltage, or may receive power output at the second voltage from a supplemental power rail in the power system.

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Номер записи: 113
01-02-2018 дата публикации

SYSTEM AND METHOD FOR CONTROLLING CACHE FLUSH SIZE

Номер: US20180032439A1
Автор: Berke Stuart Allen, Jenne John E., Sankaranarayanan Vadhiraj
Принадлежит:

An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy. 1. A method for controlling cache flush size in an information handling system , comprising:setting a threshold value for modified cache lines in a cache;writing to a cache line in the cache;determining whether or not the writing causes the cache line to transition to a modified state; incrementing a count of modified cache lines in the cache;', 'determining, dependent on the incremented count, whether or not the threshold value for modified cache lines in the cache is exceeded; and', 'flushing one or more modified cache lines in the cache to persistent memory, in response to determining that the threshold value for modified cache lines in the cache is exceeded., 'in response to determining that that the writing causes the cache line to transition to the modified state2. The method of claim 1 , wherein flushing one or more modified cache lines in the cache to the persistent memory comprises flushing all modified cache lines in the cache to the persistent memory.3. The method of claim 1 , wherein:flushing one or more modified cache lines in the cache to the persistent memory comprises flushing a ...

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Номер записи: 114
12-02-2015 дата публикации

Adjustable Heat Sink Supporting Multiple Platforms and System Configurations

Номер: US20150043160A1
Автор: Berke Stuart Allen, Tunks Eric M.
Принадлежит: DELL PRODUCTS L.P.

An adjustable heat sink which allows factory, service, or customers to adjust the width of the heat sink to take advantage of some or all available unpopulated DIMM space to optimize cooling and performance. Such an adjustable heat sink addresses many of the limitations of other heat sinks and is advantageous for reducing part numbers within a platform and across platforms. Such an adjustable heat sink also simplifies field upgrades when either adding or removing populated DIMMs to an information handling system thus enhancing performance without a need to change CPU Heat sinks. 1. A heat sink comprising:a main portion, the main portion comprising a heat sink base and a heat dissipation portion;an extendable portion thermally coupled to the main portion, the extendable portion comprising an adjustable heat sink base and a heat dissipation portion; and,an adjustment mechanism, the adjustment mechanism thermally and physically coupling the main portion and the extendable portion.2. The heat sink of wherein:the adjustment mechanism comprises a heat pipe, the heat pipe coupling the main portion and the extendable portion.3. The heat sink of wherein:the heat pipe is fixed to one of the main portion and the extendable portion and extends into the other of the main portion and the extendable portion via an aperture, the aperture allowing the other of the main portion and the extendable portion to slide along the heat pipe.4. The heat sink of further comprising:another extendable portion.5. The heat sink of wherein:the extendable portion and the another extendable portion are positioned on opposite sides of the main portion.6. The heat sink of wherein:the main portion heat dissipation portion and the extendable portion heat dissipation portion comprise respective the fin arrays.7. An information handling system comprising:a motherboard; a main portion, the main portion comprising a heat sink base and a heat dissipation portion;', 'an extendable portion thermally coupled to ...

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Номер записи: 115
07-02-2019 дата публикации

SYSTEMS AND METHODS FOR FREQUENCY SHIFTING RESONANCE OF AN UNUSED VIA IN A PRINTED CIRCUIT BOARD

Номер: US20190041184A1
Автор: Berke Stuart Allen, Farkas Sandor, MUTNURY BHYRAV M.
Принадлежит: DELL PRODUCTS L.P.

In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location. 123-. (canceled)24. A method comprising:determining a length of a via stub, the via stub corresponding to a first portion of a via not within a second portion of the via electrically coupling a first trace of a circuit board to a second trace of the circuit board;determining a Nyquist frequency of signals communicated on the via and one or more harmonic frequencies thereof;estimating a resonance frequency of the via stub based on the length; andin response to determining that the resonance frequency is approximately equal to the Nyquist frequency or one of the one or more harmonic frequencies, determine a size of a termination pad to be formed on an end of the via stub.25. The method of claim 24 , the size of the termination pad determined such that an effective impedance of the via stub having the termination pad formed thereon is approximately equal to a desired impedance.26. The method of claim 25 , wherein the desired impedance comprises at least one of a desired capacitance and a desired inductance.27. The method of claim 25 , wherein the desired impedance is selected such that the via stub has a desired effective resonant frequency.28. The method of claim 24 , wherein the size is a radius of the termination pad.29. The method ...

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Номер записи: 116
23-02-2017 дата публикации

SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION OF MEMORY

Номер: US20170052727A1
Автор: Berke Stuart Allen, Sauber William
Принадлежит:

Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents. 1. A method for improving performance and reducing power consumption in a memory hardware system , comprising:tracking, by a memory controller, whether individual units of the memory system are active or inactive, wherein an inactive individual unit is an individual unit that is in use, but not currently being accessed;placing, by the memory controller, inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents;filtering, by the memory controller, memory controller commands generated upstream of the memory controller, the filtering including blocking explicit refresh commands to an inactive individual unit of the memory system placed in the self-refresh mode; andplacing, by the memory controller, active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.2. A method according to claim 1 , wherein an individual unit of the memory system comprises one of a block claim 1 , a page claim 1 , a bank claim 1 , and a rank.3. A method according to claim 1 , wherein:each individual unit of the memory system comprises a page; ...

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Номер записи: 117
23-02-2017 дата публикации

Systems and methods for real-time cache flush measurements in an information handling system

Номер: US20170052791A1
Автор: Dit Charoen, John Erven Jenne, Stuart Allen Berke
Принадлежит: Dell Products LP

In accordance with embodiments of the present disclosure, a method may include, during boot of an information handling system, determining a first amount of energy required by the information handling system to flush a cache integral to the information handling system to memory integral to the information handling system in response to a power loss of one or more power supplies for supplying electrical energy to the information handling system, determining whether a second amount of energy available for hold-up of one or more power supplies in response to the power loss exceeds the first amount of energy, and responsive to determining whether the second amount of energy exceeds the first amount of energy, configuring the cache.

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Номер записи: 118
02-03-2017 дата публикации

INFORMATION HANDLING SYSTEM WITH PERSISTENT MEMORY AND ALTERNATE PERSISTENT MEMORY

Номер: US20170060697A1
Автор: Berke Stuart Allen, Chiasson Shane Michael, Jenne John Erven
Принадлежит:

In accordance with embodiments of the present disclosure, an information handling system may include a primary persistent memory comprising a volatile memory for storing data and a non-volatile memory for receiving data transferred from the volatile memory in response to a power loss of the information handling system. The information handling system may also include an alternate persistent memory instructions embodied in non-transitory computer readable media, the instructions for causing a processor communicatively coupled to the primary persistent memory and the alternate persistent memory to, responsive to a vulnerability of a persistence of the primary persistent memory, transfer application data from the primary persistent memory to the alternate persistent memory. 1. An information handling system comprising: a volatile memory for storing data; and', 'a non-volatile memory for receiving data transferred from the volatile memory in response to a power loss of the information handling system;, 'a primary persistent memory comprisingan alternate persistent memory; andinstructions embodied in non-transitory computer readable media, the instructions for causing a processor communicatively coupled to the primary persistent memory and the alternate persistent memory to, responsive to a vulnerability of a persistence of the primary persistent memory, transfer application data from the primary persistent memory to the alternate persistent memory.2. The information handling system of claim 1 , wherein the instructions comprise an application executing on an operating system executing on the processor claim 1 , and the application is configured to transfer the application data from the primary persistent memory to the alternate persistent memory.3. The information handling system of claim 1 , wherein the instructions comprise a portion of an operating system executing on the processor claim 1 , and the operating system is configured to transfer the application data from ...

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Номер записи: 119
02-03-2017 дата публикации

SYSTEMS AND METHODS FOR HIDDEN BATTERY CELL CHARGING AND CONDITIONING

Номер: US20170063108A1
Автор: Berke Stuart Allen, Wang Lei
Принадлежит:

In accordance with embodiments of the present disclosure, an information handling system may include at least one information handling resource and a battery for supplying electrical energy to the at least one information handling resource. The battery may include a plurality of series-coupled cells and a plurality of switching devices arranged with respect to the plurality of series-coupled cells, the plurality of switching devices configured to be selectively and independently activated and deactivated in order to simultaneously enable one or more of the plurality of series-coupled cells to generate a portion of an output voltage delivered to the at least one information handling resource and bypass one or more of the plurality of series-coupled cells. 1. An information handling system comprising:at least one information handling resource; and a plurality of series-coupled cells;', 'a plurality of switching devices arranged with respect to the plurality of series-coupled cells, the plurality of switching devices configured to be selectively and independently activated and deactivated in order to simultaneously enable one or more of the plurality of series-coupled cells to generate a portion of an output voltage delivered to the at least one information handling resource and bypass one or more of the plurality of series-coupled cells; and, 'a battery for supplying electrical energy to the at least one information handling resource, the battery comprisinga plurality of charger/dischargers, each charger/discharger associated with a respective one of the plurality of series-coupled cells, each charger/discharger configured to charge and discharge its respective series-coupled cell for testing or conditioning of such series-coupled cell when such series-coupled cell is bypassed and each cell charger/discharger isolated from the other of the plurality of charger/dischargers through an isolated converter/transformer comprising a power converter and a transformer.2. The ...

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Номер записи: 120
17-03-2016 дата публикации

Information Handling System Heat Sink Compatibility Management

Номер: US20160081231A1
Автор: Berke Stuart Allen, Kunnathur Ragupathi Dinesh
Принадлежит: DELL PRODUCTS L.P.

A thermal response engine on an information handling system compares a processor thermal response to a predetermined workload with an expected thermal response to the predetermined workload in order to validate that a heat sink disposed on the processor matches a heat sink used by a thermal controller profile to manage thermal conditions of the information handling system. If the heat sink thermal characteristics fail to match up with expected thermal characteristics, the thermal response engine provides the thermal controller with an appropriate thermal profile and alerts the end user of an incompatibility. 1. An information handling system comprising:a motherboard;a processor coupled to the motherboard and operable to execute instructions;memory interfaced with the processor and operable to store information;a heat sink coupled to the processor;a temperature sensor operable to sense a temperature; anda thermal response engine interfaced with the temperature sensor and operable to compare sensed temperatures against expected temperatures for a processor workload to identify the heat sink.2. The system of further comprising:a thermal response table relating a plurality of heats sink identifiers with expected temperatures for processor workloads; anda user interface operable to present an identified heat sink to an end user in response to a predetermined condition.3. The system of wherein the predetermined condition comprises a heat sink identified by the thermal response engine that fails to match a heat sink identifier stored as configuration information in non-volatile memory.4. The system of wherein the thermal response engine comprises firmware instructions executing on a baseboard management controller.5. The system of wherein the sensed temperatures comprise temperatures sensed within the processor.6. The system of wherein the predetermined condition comprises a heat sink identifier associated with restricted memory placement and a processor identifier having ...

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Номер записи: 121
29-03-2018 дата публикации

System Level Crosstalk Mitigation

Номер: US20180089125A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M., Sankaranarayanan Vadhiraj
Принадлежит:

An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration. 1. A method comprising:identifying a weakest lane of a plurality of high speed serial lanes;shifting a phase of a first signal transmitted on a second lane;deriving an eye margin for a second signal on the weakest lane;iteratively changing an amount of the shifting of the phase of the first signal in a first direction, and deriving the eye margin for the second signal after each iteration until the eye margin of the second signal remains the same from one iteration to a next iteration; andstoring a final phase value for the first signal in response to the eye margin of the second signal remaining the same from one iteration to the next iteration.2. The method of claim 1 , further comprising:iteratively changing a phase of a third signal transmitted on a third lane until the eye margin of the second signal remains the same from one iteration to the next iteration;in response to each iterative change of the phase of the third signal, deriving the eye margin for the second signal; andstoring a final phase value for the third signal in response to the eye margin of the second signal remaining ...

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Номер записи: 122
29-03-2018 дата публикации

Lossy Drain Wire on a High Speed Cable

Номер: US20180090243A1
Автор: Berke Stuart Allen, Farkas Sandor, MUTNURY BHYRAV M.
Принадлежит:

A dual axial cable includes first and second signal conductors, a shield, and a drain wire. The first and second signal conductors transmit a differential signal. The shield is spirally wrapped around the first and second conductors, and causes a resonant characteristic of the dual axial cable. The drain wire provides a return path for the differential signal in the dual axial cable. The drain wire is roughened to a specific amount of roughness, which reduces signal loss at resonant frequencies of the resonant characteristic caused by the shield. 1. A dual axial cable comprising:first and second signal conductors to transmit a differential signal;a shield spirally wrapped around the first and second conductors, wherein the shield causes a resonant characteristic of the dual axial cable; anda drain wire to provide a return path for the differential signal, the drain wire being roughened to a specific amount of roughness, wherein the specific amount of roughness causes a reduction of a signal loss at resonant frequencies of the resonant characteristic caused by the shield.2. The dual axial cable of claim 1 , further comprising:a first insulator surrounding the first conductor and in physical communication with the shield.3. The dual axial cable of claim 2 , further comprising:a second insulator surrounding the second conductor and in physical communication with the shield.4. The dual axial cable of claim 1 , wherein the specific amount of roughness is within a range of roughness from 25 μm to 250 μm.5. The dual axial cable of claim 1 , wherein the spiral wrapping of the shield causes overlaps in the shield.6. The dual axial cable of claim 5 , wherein the resonant frequencies are caused by the overlap in the shield.7. The dual axial cable of claim 1 , wherein the reduction of the signal loss at the resonant frequencies is independent from frequencies that the dual axial cable is operated.8. A dual axial cable comprising:first and second signal conductors to transmit a ...

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Номер записи: 123
30-03-2017 дата публикации

System and Method to Blacklist Equalization Coefficients in a High-Speed Serial Interface

Номер: US20170091137A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M.
Принадлежит:

A serial interface comprises a receiver including a first input compensation module with a first setting that selects a first value from among a plurality of first values for a first input characteristic of the receiver, a memory to store a first blacklist value from among the first values, and a control module to select each of the first values, except for the first blacklist value, to evaluate an indication of a performance level of the receiver for each of the selected first values, and to select a particular first value based upon the indications of the performance level of the receiver. 1. A serial interface , comprising: a first input compensation module with a first setting that selects a first value from among a plurality of first values for a first input characteristic of the receiver;', 'a memory to store a first blacklist value from among the first values; and', 'a control module to select each of the first values, except for the first blacklist value, to evaluate an indication of a performance level of the receiver for each of the selected first values, and to select a particular first value based upon the indications of the performance level of the receiver., 'a receiver including2. The serial interface of :the memory further to store a second blacklist value of the first values; andthe control module further to select each of the first values, except for the second blacklist value.3. The serial interface of :the receiver further including a second input compensation module with a second setting that selects a second value from among a plurality of second values for a second input characteristic of the receiver;the memory further to store a second blacklist value from among the second values, andthe control module further to select each of the second values, except for the second blacklist value, to evaluate the indication of the performance level of the receiver for each of the selected second values, and to select a particular second value based upon ...

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Номер записи: 124
11-04-2019 дата публикации

Systems and methods for providing post-package repair visibility to a host for memory reliability, availability, and serviceability

Номер: US20190108896A1
Автор: Bhyrav M. Mutnury, Stuart Allen Berke, Vadhiraj Sankaranarayanan
Принадлежит: Dell Products LP

An information handling system comprising a processor, a memory system communicatively coupled to the processor, the memory system comprising a plurality of spare rows for post-package repair of the memory system, and one or more instructions stored in non-transitory computer readable media and configured to, when executed, cause the processor to: communicate a command to the memory system requesting information associated with an availability of spare rows for post-package repair of the memory system and receive a response to the command, the command comprising the information associated with the availability.

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Номер записи: 125
04-05-2017 дата публикации

DYNAMIC POWER BUDGET ALLOCATION

Номер: US20170123482A1
Автор: Berke Stuart Allen, III George G., Richards
Принадлежит:

A dynamic power budget allocation system includes a plurality of powered subsystems. A power system controller is coupled to the plurality of powered subsystems. The power system controller is operable, for each of a plurality of time intervals, to retrieve power usage data from each of the plurality of subsystems during a current time interval. The power system controller is then operable to project power requirements for the plurality of subsystems for a subsequent time interval using the power usage data. The power system controller is then operable to determine at least one power setting for at least one of the plurality of subsystems using the power requirements, and program the at least one of the plurality of subsystems with the at least one power setting. Each powered subsystem may include a voltage regulator that provides the power usage data and is programmed with the at least one power setting. 1. A dynamic power budget allocation system , comprising:a plurality of powered subsystems; and retrieve, during a current time interval while that powered subsystem operates in a current operating mode, current power usage data from that powered subsystem;', 'determine, for a subsequent time interval via immediate transition by that powered subsystem from the current operating mode, a subsequent operating mode that is available to that powered subsystem;', 'retrieve, for the subsequent operating mode that is available to that powered subsystem, a peak power requirement;', 'determine, for the subsequent time interval using the current power usage data and the peak power requirement for the subsequent operating mode, a subsequent power requirement for that powered subsystem that provides an upper bound on a subsequent power demand of that powered subsystem in the subsequent time interval;, 'a power system controller that is coupled to the plurality of powered subsystems, wherein the power system controller is configured, for each of the plurality of powered ...

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Номер записи: 126
12-05-2016 дата публикации

SYSTEMS AND METHODS FOR SUPPORT OF NON-VOLATILE MEMORY ON A DDR MEMORY CHANNEL

Номер: US20160132240A1
Автор: Berke Stuart Allen, Dube Shawn J.
Принадлежит:

Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system. 120-. (canceled)21. An information handling system , comprising:at least one first processing device configured as a host processing device to execute an operating system (OS) and one or more OS write drivers configured to manage writes; anda double data rate (DDR)-based non-volatile memory (NVM) system comprising one or more NVM devices coupled to the host processing device under control of at least one second processing device that is coupled to the host processing device by a DDR memory channel and that is coupled to the DDR-based NVM system by a NVM channel;where the host processing device is configured to access the DDR-based NVM system across the DDR memory channel for data read and data write operations under control of the second processing device and through the NVM channel;where the second processing device is configured to control response to receipt of standard DDR read commands received across the DDR memory channel from the host processing device by controlling the performance of direct reads of data stored on the NVM memory devices across the NVM channel with no OS driver involvement and with no OS driver calls, and controlling providing the read data to the host processing device across the DDR memory channel; andwhere the second processing device is configured to control response to receipt of a series of DDR ...

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Номер записи: 127
12-05-2016 дата публикации

Repeatable Backchannel Link Adaptation for High Speed Serial Interfaces

Номер: US20160134443A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M., Wang Minchuan
Принадлежит:

A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values. 1. A receiver , comprising:a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver; and perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules;', 'determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations; and', 'determine an optimized set of compensation values based on the most common set of compensation values., 'a control module configured to2. The receiver of claim 1 , further comprising:an analog-to-digital converter adapted to convert a signal associated with the data bitstream to a digital representation of the signal, wherein the optimized set of compensation values is further based upon the digital representation of the signal.3. The receiver of claim 2 , wherein the digital representation of the signal is a receiver eye representation of the signal.4. The receiver of claim 3 , wherein the optimized compensation values is further based upon an eye height and an eye width.5. The receiver of claim 4 , wherein in determining the optimized set of compensation values claim 4 , the control ...

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Номер записи: 128
30-04-2020 дата публикации

Method and Apparatus to Provide Platform Power Peak Limiting based on Charge of Power Assist Unit

Номер: US20200133361A1
Автор: Berke Stuart Allen, Jenne John E., MUCCINI MARK A.
Принадлежит:

An information handling system includes a power assist unit (PAU) and a baseboard management controller (BMC). The PAU is coupled to a power rail and includes a power storage element, a converter coupled to the power storage element and the power rail, and a controller. The controller receives a current level indication indicating a current provided to a load of the information handling system, directs the converter to provide power from the power storage element to the power rail when the current level indication is greater than a threshold level, directs the converter charge the power storage element from the power rail when the current level indication is greater than the threshold level, and provides a charge level indication that indicates an amount of charge on the power storage unit. The BMC receives the charge level indication, and sets a peak power limit for the information handling system based on the charge level indication. 1. An information handling system , comprising: a power storage element;', 'a converter coupled to the power storage element and to the power rail; and', 'a controller configured to receive a current level indication indicating a current provided to a load of the information handling system, to direct the converter to provide power from the power storage element to the power rail when the current level indication is greater than a threshold level, to direct the converter to charge the power storage element from the power rail when the current level indication is less than the threshold level, and to provide a charge level indication that indicates an amount of charge on the power storage unit; and, 'a power assist unit coupled to a power rail, the power assist unit includinga baseboard management controller configured to receive the charge level indication, and to set a peak power limit for the information handling system based on the charge level indication.2. The information handling system of claim 1 , wherein setting the peak ...

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Номер записи: 129
31-05-2018 дата публикации

System and Method for Device Assembly based on Component Characteristics Stored with the Components

Номер: US20180150415A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M., Wang Minchuan
Принадлежит:

A process may involve assembling a device at a device assembler. The process may include receiving a set of components, where each component of the set of components may be associated with a respective memory storing a set of characteristics of the component. The process may include assembling the set of components into the device at the device assembler. The process may also include accessing each respective memory of the components to read the sets of characteristics stored in the respective memories, and determining from the sets of characteristics of the components the characteristics of the device. 1. A process for assembling a device , comprising:receiving a set of components, each component of the set of components associated with a respective memory storing a set of characteristics of the component;assembling the set of components into the device;accessing each respective memory of the components of the set of components to read the sets of characteristics stored in the respective memories; anddetermining from the sets of characteristics of the components the characteristics of the device.2. The process of claim 1 , further comprising:determining from the characteristics of the device the functionality of the device for one or more functions.3. The process of claim 1 , wherein the respective memories of the components are associated with the components by physical attachment to the components.4. The process of claim 3 , wherein the respective memories are EEPROMS.5. The process of claim 4 , wherein the EEPROMS are provided with power to access the EEPROMS.6. The process of claim 3 , wherein the respective memories are RFIDs.7. The process of claim 6 , the RFIDs are read without providing an external power supply to the RFIDs.8. The process of claim 1 , wherein the device is a computer connector device comprising at least one component from a group of components claim 1 , the group of components comprising:a cable component, a connector component, and a ...

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Номер записи: 130
28-08-2014 дата публикации

SYSTEMS AND METHODS FOR IMPEDANCE MATCHING FOR MULTI-DROP TOPOLOGIES

Номер: US20140244883A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M., Winterberg Douglas S.
Принадлежит: DELL PRODUCTS L.P.

In accordance with embodiments of the present disclosure, a system may include a driver, a plurality of drops, and a plurality of transmission lines, including one transmission line between the driver and one of the plurality of drops and one transmission line between successive adjacent drops. Each particular transmission line of the plurality of transmission lines may be manufactured to have a desired impedance based on a corresponding effective impedance as seen at a drop located on an end of the particular transmission line furthest from the driver in a direction away from the driver. 1. A system comprising:a driver;a plurality of drops; anda plurality of transmission lines, including one transmission line between the driver and one of the plurality of drops and one transmission line between successive adjacent drops;wherein each particular transmission line of the plurality of transmission lines is manufactured to have a desired impedance based on a corresponding effective impedance as seen at a drop located on an end of the particular transmission line furthest from the driver in a direction away from the driver.2. The system of claim 1 , wherein each particular transmission line is manufactured to have the desired impedance equal to its corresponding effective impedance.3. The system of claim 1 , wherein each particular transmission line is manufactured to have the desired impedance equal to one half of its corresponding effective impedance.4. The system of claim 1 , wherein each particular transmission line is manufactured to have the desired impedance further based on a second corresponding effective impedance as seen at the drop located on the end of the particular transmission line furthest from the driver in a direction towards the driver.5. The system of claim 4 , wherein each particular transmission line is manufactured to have the desired impedance equal to one-half of the sum of its corresponding effective impedance and its second corresponding ...

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Номер записи: 131
23-06-2016 дата публикации

System and Method for Providing Kernel Intrusion Prevention and Notification

Номер: US20160179704A1
Автор: Berke Stuart Allen, Dharmadhikari Vivek, Wang Mi
Принадлежит:

A memory protection module includes comparison logic that has a write-once window CSR that stores a memory address range, and window protection logic. The comparison logic receives a memory write transaction, determines a memory address of the memory write transaction, and provides an indication as to whether or not the memory address is included in the memory address range. The window protection logic receives the memory transaction, receives the indication from the comparison logic, allows the memory write transaction to proceed in response to the indication indicating that the memory address is not included in the memory address range, and drops the memory write transaction in response to the indication indicating that the memory address is included in the memory address range. 1. A memory protection module , comprising: the window CSR is configured as a write-once register; and', 'the window CSR stores a memory address range; and, 'comparison logic coupled to a memory interface and including a window control status register (CSR), whereinwindow protection logic coupled to the memory interface; [ receives a memory write transaction from the memory interface;', 'determines a memory address of the memory write transaction; and', 'provides a first indication as to whether or not the memory address is included in the memory address range; and, 'the comparison logic, receives the memory transaction from the memory interface;', 'receives the first indication from the comparison logic;', 'allows the memory write transaction to proceed in response to the first indication indicating that the memory address is not included in the memory address range; and', 'drops the memory write transaction in response to the first indication indicating that the memory address is included in the memory address range., 'the window protection logic], 'wherein2. The memory protection module of claim 1 , wherein the window protection logic further provides a second indication that the memory ...

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Номер записи: 132
21-07-2016 дата публикации

System Aware Transmitter Adaptation for High Speed Serial Interfaces

Номер: US20160211992A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M.
Принадлежит:

A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver. 1. A receiver for a high-speed serial interface , the receiver comprising:a compensation module that provides a selectable level of equalization to a data bitstream from a transmitter of the high-speed serial interface; andcontrol logic that directs the transmitter to successively select each of a plurality of tuning values for an output impedance of the transmitter, that successively selects each of the levels of equalization for each tuning value, that evaluates an indication of a performance level of the receiver for each level of equalization and each tuning value, and that selects a particular tuning value based upon the indications.2. The receiver of claim 1 , further comprising:an analog-to-digital converter module that provides a receiver eye height level for the data bitstream, wherein the performance level comprises a receiver eye height.3. The receiver of claim 2 , wherein the particular tuning value is selected when a particular indication associated with the particular tuning value includes an equalization level that produced a highest receiver eye height.4. The receiver of claim 2 , wherein the particular tuning value is selected ...

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Номер записи: 133
05-08-2021 дата публикации

SYSTEM AND METHOD FOR UTILIZING ENHANCED THERMAL TELEMETRY FOR DIFFERENTIAL STORAGE OF DATA ON A MEMORY MODULE

Номер: US20210240617A1
Автор: Berke Stuart Allen, Chin Jordan, RAO Balaji Bapu Gururaja
Принадлежит:

An information handling system includes first and second memory modules, and a central processing unit. The first memory module includes one or more memory ranks of memory devices, and a first plurality of thermal sensors. The second memory module includes one or more memory ranks of memory devices, and a second plurality of thermal sensors. The central processing unit receives first thermal telemetry data for the first memory module from the first thermal sensors, and second thermal telemetry data for the second memory module from the second thermal sensors. In response to the reception of the first thermal telemetry data, the central processing unit determines a first localized temperature of a first memory rank. In response to the first localized temperature exceeding a threshold temperature, the central processing unit re-maps access of data from the first memory rank to a second memory rank. 1. An information handling system , comprising: one or more memory ranks of memory devices; and', 'a first plurality of thermal sensors;, 'a first memory module including one or more memory ranks of memory devices; and', 'a second plurality of thermal sensors; and, 'a second memory module includinga central processing unit to communicate with the first and second memory modules, the central processing unit to receive first thermal telemetry data for the first memory module from the first thermal sensors, to receive second thermal telemetry data for the second memory module from the second thermal sensors, in response to the reception of the first thermal telemetry data, to determine a first localized temperature of a first memory rank, and in response to the first localized temperature exceeding a threshold temperature, to re-map access of data from the first memory rank to a second memory rank.2. The information handling system of claim 1 , in response to the reception of the second thermal telemetry data claim 1 , the central processing unit to determine a second ...

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Номер записи: 134
03-08-2017 дата публикации

SYSTEMS AND METHODS FOR MANAGEMENT CONTROLLER ENHANCED POWER SUPPLY UNIT CURRENT SHARING

Номер: US20170220089A1
Автор: Berke Stuart Allen, Gharpure Padmanabh R., Mathew Abey K.
Принадлежит: DELL PRODUCTS L.P.

A method may include, when a management controller is able to control a plurality of power supply units (PSUs): selecting a PSU of the plurality of PSUs as a master of a current share bus; driving, by the PSU selected as the master, a current share signal on the current share bus; and monitoring, by PSUs other than the power supply unit selected as the master, the current share signal. The method may also include, when the management controller is unable to control the plurality of PSUs: attempting, by each of the plurality of PSUs, to drive the current share signal on the current share bus; and monitoring, by each of the PSUs, the current share signal. Each of the PSUs may output current to the power bus in accordance with the current share signal. 1. (canceled)2. An information handling system , comprising:a processor;a management controller communicatively coupled to the processor; and receive an indication from the management controller whether such power supply unit is selected as a master of a current share bus;', 'if such power supply unit is selected as the master, drive a current share signal on the current share bus, the current share signal indicative of an output current driven by such power supply unit on the power bus; and', 'if such power supply unit is not selected as the master, monitor the current share signal and drive the output current to the power bus in accordance with the current share signal; and', 'attempt to drive the current share signal on the current share bus; and', 'monitor the current share signal and drive the output current to the power bus in accordance with the current share signal; and, 'when the management controller is able to control the plurality of power supply units, 'a plurality of power supply units communicatively coupled to the management controller for supplying electrical energy to one or more information handling resources of the information handling system via a power bus, each of the plurality of power supply ...

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Номер записи: 135
10-08-2017 дата публикации

System Aware Transmitter Adaptation for High Speed Serial Interfaces

Номер: US20170230208A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M.
Принадлежит:

A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver. 1. A high-speed serial interface , comprising:a transmitter including an output module with a first setting that selects a tuning value from among a plurality of tuning values for an output impedance of the output module; anda receiver including control logic that directs the transmitter to successively select each of the tuning values, that successively selects for each tuning value a level of equalization from a plurality of levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, selects a particular tuning value based upon the indications of the performance level of the receiver, and that communicates the particular tuning value to the transmitter;wherein the transmitter sets the first setting to select the particular tuning value.2. The high-speed serial interface of claim 1 , wherein the output module further includes a second setting that selects a target output impedance from among a plurality of target output impedances.3. The high-speed serial interface of claim 2 , wherein the second setting is set based ...

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Номер записи: 136
10-08-2017 дата публикации

Grooved vias for high-speed information handling systems

Номер: US20170231091A1
Автор: Bhyrav M. Mutnury, Sandor Farkas, Stuart Allen Berke
Принадлежит: Dell Products LP

Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.

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Номер записи: 137
25-07-2019 дата публикации

System and Method to Dynamically Increase Memory Channel Robustness at High Transfer Rates

Номер: US20190227885A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M., Sankaranarayanan Vadhiraj
Принадлежит:

A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level. 1. A dynamic random access memory (DRAM) device , comprising:an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller; andODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device;wherein the ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.2. The DRAM device of claim 1 , wherein the ODT circuitry comprises a plurality of switched impedances.3. The DRAM device of claim 2 , wherein in terminating the interface circuit at the first impedance level claim 2 , the ODT circuitry switches a first subset of the switched ...

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Номер записи: 138
01-08-2019 дата публикации

SYSTEMS AND METHODS FOR LOAD-BALANCING CACHE FLUSHES TO NON-VOLATILE MEMORY

Номер: US20190236029A1
Автор: Berke Stuart Allen, Butcher Wade Andrew, Sankaranarayanan Vadhiraj
Принадлежит: DELL PRODUCTS L.P.

An information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a memory controller. The memory controller may be configured to monitor memory input/output traffic to each of the plurality of non-volatile memories, determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring, and based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories. 1. An information handling system comprising:a processor;a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories; and monitor memory input/output traffic to each of the plurality of non-volatile memories;', 'determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring; and', 'based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories., 'a memory controller configured to2. The information handling system of claim 1 , wherein the memory controller may monitor the memory input/output traffic and determine the qualities of traffic using heuristics including at least one of flow-control credits available during input/output operation on each of the plurality of non-volatile memories and an amount of cache traffic targeted to specific memory channels coupling the non-volatile memories to the memory controller.3. The information handling system of claim 1 , wherein the memory controller is integral to the processor.4. ...

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Номер записи: 139
30-08-2018 дата публикации

System and Method for Providing Predictive Failure Detection on DDR5 DIMMs Using On-Die ECC

Номер: US20180246775A1
Автор: Berke Stuart Allen, Butcher Andrew, Sankaranarayanan Vadhiraj
Принадлежит:

An information handling system includes a memory controller and a Dual In-Line Memory Module (DIMM) including a Dynamic Random Access Memory (DRAM) device. The DRAM device is configured to detect an Error Correcting Code (ECC) bit error for a data transaction within the DRAM device, determine if the ECC bit error results in an ECC error threshold being exceeded, and provide an alert signal to the memory controller in response to determining that the ECC bit error resulted in the ECC error threshold being exceeded. 1. An information handling system , comprising:a memory controller configured to provide a memory channel; and detect an Error Correcting Code (ECC) bit error for a data transaction within the DRAM device;', 'determine if the ECC bit error results in an ECC error threshold being exceeded; and', 'provide an alert signal to the memory controller in response to determining that the ECC bit error resulted in the ECC error threshold being exceeded;, 'a Dual In-Line Memory Module (DIMM) including a Dynamic Random Access Memory (DRAM) device coupled to the memory channel, the DRAM device configured to retrieve correlation information from the DRAM device, wherein the correlation information includes a storage location associated with the ECC bit error; and', 'mitigate errors on the DRAM device based upon the correlation information., 'wherein in response to receiving the alert signal, the memory controller is configured to2. The information handling system of claim 1 , wherein the DRAM device is further configured to:store correlation information associated with the ECC bit error.3. The information handling system of claim 2 , wherein the correlation information comprises a storage location associated with the ECC bit error.4. (canceled)5. The information handling system of claim 1 , wherein in mitigating the errors on the DRAM device claim 1 , the memory controller is further configured to:lower a data transaction rate between the memory controller and the DIMM. ...

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Номер записи: 140
30-08-2018 дата публикации

System and Method for Data Restore Flexibility on Dual Channel NVDIMMs

Номер: US20180246790A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M., Sankaranarayanan Vadhiraj
Принадлежит:

A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device. 1. A Dual In-Line Memory Module (DIMM) , comprising:a first Dynamic Random Access Memory (DRAM) device configured to perform memory transactions for first memory locations associated with the first DRAM device via a first memory channel;a second DRAM device configured to perform memory transactions for second memory locations associated with the second DRAM device via a second memory channel;a non-volatile memory device; and store first data from the first memory locations and second data from the second memory locations to the non-volatile memory device in response to a save data operation from a memory controller;', 'receive a first indication that communication via the first memory channel has failed;', 'store the first data from the non-volatile memory device to the second DRAM device in response to the first indication and in response to a restore data operation from the memory controller;', 'provide a second indication that the first data is stored on the second DRAM device;', 'receive a third indication that the first data has been ...

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Номер записи: 141
04-12-2014 дата публикации

Secure Original Equipment Manufacturer (OEM) Identifier for OEM Devices

Номер: US20140359303A1
Автор: Berke Stuart Allen, Khatri Mukund Purshottam
Принадлежит: DELL PRODUCTS L.P.

An authorized information handling system (IHS) generates unique identifier codes for an OEM (programmable) device designed as a component for an IHS. An identifier generation and validation (IGV) controller in the authorized IHS generates a unique encrypted sequence by encrypting identification (ID) data read from the OEM device. The IGV controller generates a unique OEM identifier code by further encrypting the encrypted sequence using a first OEM proprietary code. The IGV controller writes the first identifier code to a pre-specified storage location of the OEM device. According to one embodiment, the IGV controller generates the unique OEM identifier code using a second reversible encryption-decryption component that comprises an Exclusive-OR (XOR) scrambler engine and generates the unique encrypted sequence using a first reversible encryption-decryption component that comprises an LFSR based scrambler, which utilizes polynomial coefficients that are securely generated and maintained. 1. A method for securely generating a unique original equipment manufacturer (OEM) identifier code for an OEM programmable device , the method comprising:an OEM authorized secure information handling system (IHS) generating a unique encrypted sequence by performing a first encryption on identification (ID) data read from the OEM programmable device;generating a unique OEM identifier code for the OEM programmable device by performing a second encryption on the unique encrypted sequence using an OEM proprietary code; andwriting the unique OEM identifier code to a pre-specified storage location of the OEM programmable device.2. The method of claim 1 , wherein:the generating a unique OEM identifier code for the OEM programmable device comprises generating the unique OEM identifier code using a second reversible encryption-decryption component that comprises an Exclusive-OR (XOR) scrambler engine.3. The method of claim 1 , wherein:the generating the unique encrypted sequence comprises ...

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Номер записи: 142
13-08-2020 дата публикации

System and Method of Rerouting an Inter-Processor Communication Link Based on a Link Utilization Value

Номер: US20200257640A1
Автор: Berke Stuart Allen, Butcher Wade Andrew
Принадлежит:

In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces. 1. An information handling system , comprising:a plurality of semiconductor packages, each of the plurality of packages includes a plurality of processor cores and an input/output (I/O) communication fabric; anda memory medium, coupled to a processor core of a first semiconductor package of the plurality of semiconductor packages, that stores instructions executable by the processor core of the first semiconductor package, which when executed by the processor core of the first semiconductor package, cause the information handling system to:configure a plurality of link registers, of the first semiconductor package, that configure the I/O communication fabric of the first semiconductor package to route communications of a plurality of components of the first semiconductor package to a plurality of inter-processor communication link interfaces of the first semiconductor package; communicate with a second semiconductor package of the plurality ...

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Номер записи: 143
05-10-2017 дата публикации

Storage class memory (scm) memory mode cache system

Номер: US20170286285A1
Автор: John E. Jenne, Stuart Allen Berke
Принадлежит: Dell Products LP

An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored.

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Номер записи: 144
25-12-2014 дата публикации

Date Adjusted Power Budgeting for an Information Handling System

Номер: US20140380069A1
Автор: Berke Stuart Allen, Jenne John E.
Принадлежит:

An information handling system determines a system configuration including a hardware module, and determines an adjusted power budget for the hardware module. The adjusted power budget is based on a calculation including a difference between a date code read from the hardware module and a baseline date, a baseline power budget, a power reduction period and a power reduction interval. The calculation may optionally include a risk factor. In alternate embodiments, an adjusted power budget for a hardware module may be calculated by an order processing system for information handling systems, or by a planning tool for a data center which contains information handling systems. 1. An information handling system comprising:a memory; and determine a system configuration of the information handling system, wherein the system configuration includes a first hardware module; and', read a date code from the first hardware module;', 'determine a baseline power budget for the first hardware module;', 'determine a baseline date of the baseline power budget; and', a time interval between the baseline date and the date code;', 'the baseline power budget;', 'a power reduction period; and', 'a power reduction factor., 'calculate the adjusted power budget for the first hardware module based on], 'determine an adjusted power budget for the first hardware module, wherein in determining the adjusted power budget the processor is operable to], 'a processor operable to2. The information handling system of claim 1 , wherein:the system configuration further includes a second hardware module of the information handling system; and [ read a second date code from the second hardware module;', 'determine a second baseline power budget for the second hardware module;', 'determine a second baseline date of the second baseline power budget; and', a second time interval between the second baseline date and the second date code;', 'the second baseline power budget;', 'the power reduction period; and', ...

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Номер записи: 145
12-10-2017 дата публикации

System and Method for Providing Kernel Intrusion Prevention and Notification

Номер: US20170293574A1
Автор: Berke Stuart Allen, Dharmadhikari Vivek, Wang Mi
Принадлежит:

A memory protection module includes comparison logic that has a write-once window CSR that stores a memory address range, and window protection logic. The comparison logic receives a memory write transaction, determines a memory address of the memory write transaction, and provides an indication as to whether or not the memory address is included in the memory address range. The window protection logic receives the memory transaction receives the indication from the comparison logic, allows the memory write transaction to proceed in response to the indication indicating that the memory address is not included in the memory address range, and drops the memory write transaction in response to the indication indicating that the memory address is included in the memory address range. 1. A memory protection module , comprising: the window CSR is configured as a rewritable register; and', 'the window CSR stores a memory address range; and, 'comparison logic coupled to a memory interface and including a window control status register (CSR), whereinwindow protection logic coupled to the memory interface; receives a memory write transaction from the memory interface;', 'determines a memory address of the memory write transaction;', 'provides a first indication as to whether or not the memory address is included in the memory address range;', 'clears the window CSR in response to a reset of the memory protection module;', 'receives the memory address range in response to the reset;', 'stores the memory address range in the window CSR in response to receiving the memory address range;', 'receives a lock window CSR transaction; and', 'locks the window CSR in response to receiving the lock window CSR transaction; and, 'wherein the comparison logic receives the memory transaction from the memory interface;', 'receives the first indication from the comparison logic;', 'allows the memory write transaction to proceed in response to the first indication indicating that the memory ...

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Номер записи: 146
19-09-2019 дата публикации

System and Method for Providing Per Channel Frequency Optimization in a Double Data Rate Memory System

Номер: US20190286554A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M., Sankaranarayanana Vadhiraj
Принадлежит:

An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed. 1. An information handling system , comprising:a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system;a second DIMM on a second memory channel of the information handling system; and train the first memory channel to a first speed based upon a first performance level of the first DIMM;', 'train the second memory channel to a second speed based upon a second performance level of the second DIMM, the first speed different from the second speed;', 'launch a first application; and', 'allocate a first portion of the first DIMM to the first application based upon the first speed., 'a processor configured to2. The information handling system of claim 1 , the processor further configured to:receive first speed information for the first memory channel;receive second speed information for the second memory channel; andstore the first and second speed information to an Advanced Configuration and Power Interface (ACPI) table.3. The information handling system of claim 2 , the processor further configured to:ascribe a first priority level to the first DIMM and a second priority level to the second DIMM based upon the first and second speed information in the ACPI table, wherein the first priority level is higher than the second priority level.4. The information handling system of claim 3 , the processor further configured to:receive a memory allocation request from the first application, the memory ...

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Номер записи: 147
03-11-2016 дата публикации

SYSTEMS AND METHODS FOR DATA ALIGNMENT IN A MEMORY SYSTEM

Номер: US20160321014A1
Автор: Berke Stuart Allen, MUTNURY BHYRAV M., Sankaranarayanan Vadhiraj
Принадлежит: DELL PRODUCTS L.P.

A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds. 1. A system comprising:a first device; anda second device communicatively coupled to the first device; anda plurality of buffers communicatively coupled to the second device via a plurality of back-side lanes and communicatively coupled to the first device via a plurality of front-side lanes; link train the back-side lanes;', 'link train the front-side lanes;', 'determine after link training of the back-side lanes and the front-side lanes whether signal integrity of data communicated over each of the front-side lanes exceeds one or more thresholds; and', 'responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modify timing of data communicated over one or more of the back-side lanes and the front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the one or more thresholds., 'wherein at least one of the first device and the second device is configured to, alone or in concert with the other2. The system of ...

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Номер записи: 148
17-12-2015 дата публикации

SYSTEMS AND METHODS FOR DISTINGUISHING INFORMATION HANDLING SYSTEM PROVIDER-SUPPORTED INFORMATION HANDLING RESOURCE VIA SYSTEM LICENSE

Номер: US20150363712A1
Автор: Berke Stuart Allen, Khatri Mukund Purshottam
Принадлежит:

In accordance with embodiments of the present disclosure, an information handling system comprising a processor, at least one information handling resource communicatively coupled to the processor, and a BIOS comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of the information handling system. The BIOS may be configured to record information regarding the at least one information handling resource, compare the information to a license for the information handling system to determine if the at least one information handling resource is supported by a provider of the information handling system, and responsive to determining that the information handling system is unsupported by the provider, initiate a remedial action with respect to at least one information handling resource. 1. An information handling system comprising:a processor;at least one information handling resource communicatively coupled to the processor; and record information regarding the at least one information handling resource;', 'compare the information to a license for the information handling system to determine if the at least one information handling resource is supported by a provider of the information handling system; and', 'responsive to determining that the information handling system is unsupported by the provider, initiate a remedial action with respect to at least one information handling resource., 'a basic input/output system (BIOS) comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of the information handling system, wherein the BIOS is configured to2. The information handling system of claim 1 , wherein the remedial action comprises at least one of:displaying an alert indicating that the at least one information handling resource is unsupported;recording an indication ...

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Номер записи: 149
24-12-2015 дата публикации

SYSTEMS AND METHODS FOR TEMPERATURE-BASED PERFORMANCE OPTIMIZATION OF MEMORY DEVICES

Номер: US20150373876A1
Автор: Berke Stuart Allen
Принадлежит:

In accordance with embodiments of the present disclosure, a memory system may include one or more memory modules and a memory controller communicatively coupled to one or more memory modules. The memory controller may be configured to determine a temperature associated with the memory system and determine if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater. The memory controller may also be configured to initiate one or more remedial actions to increase the temperature above the minimum threshold temperature if the temperature is below the minimum threshold temperature. 1. An information handling system comprising:a processor; and determine a temperature associated with the memory system;', 'determine if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater; and', 'if the temperature is below the minimum threshold temperature, initiate one or more remedial actions to increase the temperature above the minimum threshold temperature., 'a memory system communicatively coupled to the processor, the memory system configured to, alone or in concert with the processor2. The information handling system of claim 1 , the memory system further configured to claim 1 , alone or in combination with the processor:determine if the temperature is above the minimum threshold temperature and below a maximum threshold temperature; ...

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Номер записи: 150
13-12-2018 дата публикации

System and Method for Setting Equalization for Communication between a Processor and a Device

Номер: US20180357066A1
Автор: Berke Stuart Allen, Farkas Sandor, MUTNURY BHYRAV M.
Принадлежит:

An information handling system may include a central processing unit (CPU) and a device. The CPU may have an I/O system and be configured to host a BIOS. The device may be communicatively connected to the I/O system of the CPU by a connection. The BIOS may determine a communication protocol used by the device for communication and set an equalization of the I/O system for communication with the device based on the communication protocol used by the device. 1. An information handling system comprising:a central processing unit (CPU) with a first I/O system and configured to host a BIOS; anda first device communicatively connected to the first I/O system by a first connection, wherein the BIOS determines a first communication protocol used by the first device for communication and sets at least one type of equalization for communication with the first device based on the first communication protocol.2. The information handling system of claim 1 , further comprising a second device claim 1 , wherein the CPU further comprises a second I/O system and the second device is connected to the second I/O system by a second connection including a connector claim 1 , and wherein the BIOS determines a second communication protocol used by the second device for communication and sets the at least one type of equalization for communication with the second device based on the second communication protocol and one or more properties of the connector claim 1 , wherein the second communication protocol differs from the first communication protocol.3. The information handling system of claim 1 , wherein the CPU is a component of a server and the first device is a server device.4. The information handling system of claim 1 , wherein the first I/O system includes transmission and reception circuitry and setting the at least one type of equalization includes setting an amplification of the transmission and reception circuitry.5. The information handling system of claim 1 , wherein the ...

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Номер записи: 151
26-11-2020 дата публикации

FLEXIBLE MID-CHASSIS EXTENSION MODULE

Номер: US20200375056A1
Автор: Berke Stuart Allen, CURTIS Robert B.
Принадлежит: DELL PRODUCTS L.P.

An information handling system chassis may include a first chassis module for housing a first set of information handling resources of an information handling system, a second chassis module for housing a second set of information handling resources of the information handling system, the second chassis module having second mechanical features for mechanically coupling to first mechanical features of the first chassis module, and a mid-chassis extension module having third mechanical features for mechanically coupling to the first mechanical features of the first chassis module and having fourth mechanical features for mechanically coupling to the second mechanical features of the second chassis module in order to mechanically couple the mid-chassis extension module between the first chassis module and the second chassis module, the mid-chassis extension module further comprising a third set of information handling resources with functionality different from that of the first set of information handling resources and the second set of information handling resources. 1. An information handling system chassis comprising:a first chassis module for housing a first set of information handling resources of an information handling system;a second chassis module for housing a second set of information handling resources of the information handling system, the second chassis module having second mechanical features that are coupleable to first mechanical features of the first chassis module; anda mid-chassis extension module having third mechanical features for mechanically coupling to the first mechanical features of the first chassis module and having fourth mechanical features for mechanically coupling to the second mechanical features of the second chassis module in order to mechanically couple the mid-chassis extension module between the first chassis module and the second chassis module, the mid-chassis extension module further comprising a third set of information ...

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Номер записи: 152
12-10-2021 дата публикации

Method and apparatus to provide platform power peak limiting based on charge of power assist unit

Номер: US11144105B2
Автор: John E. Jenne, Mark A. Muccini, Stuart Allen Berke
Принадлежит: Dell Products LP

An information handling system includes a power assist unit (PAU) and a baseboard management controller (BMC). The PAU is coupled to a power rail and includes a power storage element, a converter coupled to the power storage element and the power rail, and a controller. The controller receives a current level indication indicating a current provided to a load of the information handling system, directs the converter to provide power from the power storage element to the power rail when the current level indication is greater than a threshold level, directs the converter charge the power storage element from the power rail when the current level indication is greater than the threshold level, and provides a charge level indication that indicates an amount of charge on the power storage unit. The BMC receives the charge level indication, and sets a peak power limit for the information handling system based on the charge level indication.

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Номер записи: 153
22-12-2020 дата публикации

Systems and methods for distinguishing information handling system provider-supported information handling resource via system license

Номер: US10872132B2
Автор: Mukund Purshottam Khatri, Stuart Allen Berke
Принадлежит: Dell Products LP

In accordance with embodiments of the present disclosure, an information handling system comprising a processor, at least one information handling resource communicatively coupled to the processor, and a BIOS comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of the information handling system. The BIOS may be configured to record information regarding the at least one information handling resource, compare the information to a license for the information handling system to determine if the at least one information handling resource is supported by a provider of the information handling system, and responsive to determining that the information handling system is unsupported by the provider, initiate a remedial action with respect to at least one information handling resource.

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Номер записи: 154
18-05-2010 дата публикации

Spacing device for modular system

Номер: US7719855B2
Автор: Jeffrey Michael Lewis, Stuart Allen Berke
Принадлежит: Hewlett Packard Development Co LP

A spacing device for adapting electronic modules for insertion into a system is disclosed. In one embodiment, the spacing device includes a body and guide features configured to align the body with mating guide features of electronic modules. The spacing device also includes a coupling portion having coupling arms, which is configured to secure the electronic modules to the body.

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Номер записи: 155
28-01-2015 дата публикации

Memory controller-independent memory sparing

Номер: EP2828756A1
Автор: Stuart Allen Berke, William Sauber
Принадлежит: Dell Products LP

An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.

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Номер записи: 156