УПРАВЛЕНИЕ ВЫПОЛНЕНИЕМ ПОТОКОВ В МНОГОПОТОЧНОМ ПРОЦЕССОРЕ

Изобретение относится к средствам управления выполнением потоков в многопоточном процессоре. Техническим результатом является возможность совместного использования контейнера потоками с разным приоритетом. Способ выполняется посредством потока, работающего на процессоре, включает операции: остановка выполнения других потоков на ядре процессора, в ответ на выполнение критической последовательности или другой последовательности, нуждающейся в ресурсах ядра процессора или в управлении ресурсами ядра процессора, причем остановка включает: выявление того, запрещает ли другой поток свою остановку, остановку выборки команд и выполнения на другом потоке, определение того, что выполнение другого потока в процессоре прекратилось, если выполнение другого потока на процессоре прекратилось, то получение для другого потока информации о состоянии, выполнение потоком операций в процессоре и разрешение выполнения другого потока в процессоре. Система реализует способ. 3 н. и 4 з.п. ф-лы, 12 ил.

DATENVERARBEITUNGSSCHALTUNGEN UND -SCHNITTSTELLEN

Datenverarbeitungsverfahren und -vorrichtung

Vorrichtung und Verfahren zur Steuerung von asynchronen Programmunterbrechungserreignissen in einem Datenverarbeitungssystem.

Bewertungseinheit für Merkerregister einer Einzelbefehl-Mehrdaten-Ausführungsmaschine

Verfahren, das aufweist: Speichern von Information in einem Merkerregister mit n Orten einer Einzelbefehl-Mehrdaten (SIMD)-Ausführungsmaschine mit n Kanälen, wobei die Information mehrere unabhängige m-Kanal-Vektoren darstellt, wobei n und m ganze Zahlen größer als Eins sind; und Erzeugen einer Ausgabe basierend auf der Information in dem Merkerregister, wobei die Ausgabe wenigstens einen Ort umfaßt, dessen Wert auf Information basiert, welche verschiedene unabhängige Vektoren darstellt.

Nachrichten-Warteschlangensystem für eine parallel integrierte Schaltkreisarchitektur und zugehöriges Betriebsverfahren

Integrierter Schaltkreis, der auf einen externen Speicher zugreift, aufweisend: a) einen Steuerprozessor; b) eine Mehrzahl von parallel geschalteten Vektorverarbeitungs-Engines (VPEs) (205), wobei jede der VPEs (205) aufweist: b1) eine Mehrzahl von Vektorverarbeitungs-Einheiten (VPUs) (207), wobei jede VPU eine Datenverarbeitungseinheit zum Ausführen mathematischer/logischer Operationen, einen lokalen Speicher (501) aufweisend einen Anweisungs- und einen Datenspeicher aufweist, b2) eine Mehrzahl von VPU-Steuereinheiten (VCUs) (206), wobei jede VCU ebenfalls einen lokalen Speicher (502) aufweisend einen Anweisungs- und einen Datenspeicher aufweist und funktionelle Aspekte der Gesamt-Speichersteuerfunktion implementiert, b3) einen Zwischenspeicher ISM (505), der im Vergleich zu den lokalen Speichern große Mengen von Daten speichern kann, b4) eine Direct Memory Access (DMA)-Steuerung (503), die angepasst ist, um Datenübertragungen zwischen jedem der Speicher (501, 502, 505) in der VPE und ...

Apparatus having processing pipeline with first and second execution circuitry, and method

An apparatus comprises a processing pipeline with first and second execution circuits 40, 42, having different performance or energy consumption characteristics. Instruction supply circuitry 24, 6, 8, 10, 30 supports different instruction supply schemes with different energy consumption/performance characteristics. The instruction supply scheme in one mode may provide greater maximum throughput of instructions than in a second mode. Instruction supply circuitry may comprise fetch instructions which may fetch a wider block of instructions per cycle in a first supply scheme; predecode circuitry; decode circuitry; or branch prediction circuitry. The apparatus may support first and second branch prediction schemes with different performance or energy consumption characteristics, including in one scheme where branch prediction is initiated at an earlier stage of the processing pipeline than in the second scheme.

Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis

A processor where some registers are not available to compiler generated code

A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code. The applcation to combined scalar and vector processing is described.

Processor for a memory tag

This invention provides a processor 200, especially for use as the central processing unit of a memory tag 1200 such as an RFID tag. The processor 200 has a minimal footprint in Silicon or other suitable material. It also is driven by the data that it receives. The processor includes a plurality 206, 212, 214, 224 of registers configured to receive in parallel data that are input to the processor, and to process in parallel the received data, and a micro sequencer and instruction decoder module 202 adapted to select two or more of the plurality of registers to receive the data that are input to the processor, and to control the processing of the received data by the end or more selected registers.

Evalutation unit for single instruction, multiple data execution engine flag registers

Protected function calling across domains

Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form, e.g. a permitted branch target instruction 40. If the instruction within the new domain is not a permitted instruction then an access violation response is triggered 42. To assist with backward compatibility for legacy code the permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry. The memory address space may be a virtual memory address space associated with the memory and may comprise several domains each having respective programmable capabilities.

Data processing apparatus with external interface

Restarting translated instructions

Key based register locking mechanism

Primitives to enhance thread-level speculation

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

VECTOR REGISTER FILE

Suspending other threads to prevent access conflicts

Threads are executed concurrently in a computer system. They may be executed on separate processors or on a single processor with hardware support for simultaneous multithreading (SMT). The threads share a common view of the memory of the system. In order to allow a block of instructions to execute atomically, all but one of the threads are suspended. The threads may be suspended by writing a predefined value to a specified memory location. This may cause an interrupt, which suspends the threads. The threads may be suspended in response to a user level instruction. The processor may include hardware to support transactional memory, such as a buffer to store write data and an area to store read addresses.

Processing apparatus, trace unit and diagnostic apparatus for monitoring conditional processing operations

A processing circuit 4 is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag 22. A trace circuit 6 is provided for generating trace data elements indicative of operations performed by the processing circuit 4. When the processing circuit 4 processes at least one selected instruction, then the trace circuit 6 generates a trace data clement including a traced condition value indicating at least the subset of condition flags 22 required to determine the outcome of the conditional instruction. A corresponding diagnostic apparatus 12 uses the traced condition value to determine a processing outcome of the at least one conditional instruction. The generation of the traced condition value, and its contents, may be dependent on the presence of one or more control flags 26, which may be associated with an individual condition flag.

System,apparatus and method for segment register read and write regardless of privilege level

Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.

An apparatus and method for performing operations on capability metadata

Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure

A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

Register restoring branch instruction

An apparatus comprises processing circuitry for performing processing operations specified by program instructions, a target register 230 that stores a target program address, a value register 240 storing a data value, an architectural register (e.g. X17), and an instruction decoder which includes branch instruction decoding circuitry that decodes a register restoring branch instruction to cause the processing circuitry to determine whether the target program address and the data value are valid (step 9, e.g. checking flags 250, 260). If both are valid then the processing circuitry is caused to branch to the target program address (step 10, updating program counter 120) and update the architectural register to store the data value (step 11, e.g. the data value is a replacement value); otherwise an error action is taken. Valid flags 250, 260 may be cleared in response to an exception or interrupt.

Crytographic architecture with instruction masking and other techniques for thwarting differential power analysis

Crytoraphic architecture with instruction masking and other techniques for thw arting differential power analysis

Data processing circuits and interfaces

Register restoring branch instruction

Exchange of data between processor modules

An Apparatus and method for controlling access to a set of memory mapped control registers

Predicting table of contents pointer value responsive to branching to subroutine

Set table of contents (TOC) register instruction

Context data management

Code-specific affiliated register prediction

Code-specific affiliated register prediction. A determination is made as to whether a unit of code is a candidate for affiliated register prediction. The determining employs a code specific indicator specific to the unit of code. Based on determining the unit of code is a candidate for affiliated register prediction,an indication of an affiliated register is loaded into a selected location. Based on the loading, the affiliated register is employed in speculative processing.

Rendering optimisation

Transition disable indicator

Dedicated bound information register file for protecting against out-of-bounds memory references

A method, system and apparatus for protecting against out-of-bounds references, including storing an address of a buffer in a general register and storing bounds information (BI) for the buffer in a bounds information register, and when a content of the general register is used as an address in a load or store operation, using a content of the bounds information register to determine if the load or store is out of bounds.

Instruction handling for accumulation of register results in a microprocessor

A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Systems and methods for dynamic control of secure mode of operation in processor

A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.

SYSTEM WITH BROAD OPERAND ARCHITECTURE AND PROCEDURE

DIGITAL SIGNAL PROCESSOR WITH SEVERAL INDEPENDENT ASSIGNED PROCESSORS

REGISTER FOR DATA COMMUNICATION IN A MULTITHREADED PROCESSOR

CENTRAL PROCESSING UNIT FOR A DIGITAL COMPUTER.

RISC PROCESSOR WITH FLEXIBLE ARCHITECTURE

RISC PROCESSOR WITH EXPANDABLE ARCHITECTURE

Unit for processing numeric and logical operations, for use in processors (cpus)and in multicomputer systems

APPARATUS, METHOD AND SYSTEM FOR A SYNCHRONICITY INDEPENDENT, RESOURCE DELEGATING, POWER AND INSTRUCTION OPTIMIZING PROCESSOR

Delayed deallocation of an arithmetic flags register

REGISTER FILE INDEXING METHODS AND APPARATUS FOR PROVIDING INDIRECT CONTROL OF REGISTER ADDRESSING IN A VLIW PROCESSOR

A double indirect method of accessing a block of data in a register file (818) is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat or loop instructions. Rather, the technique, termed register file indexing (RFI) (820) allows full programmer flexibility in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility (814) is embedded in the iVLIW manArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions or being limited in use only with repeat or loop instructions. The use of RFI (820) in a processor containing multiple heterogeneous execution units (852 and 854) which operate in parallel, such as VLIW or iVLIW processors, allows for efficient pipelining ...

RISC PROCESSOR DEVICE AND METHOD OF SIMULATING FLOATING-POINT STACK OPERATION THEREOF

A RISC processor device and a method of simulating floating-point stack operation thereof, the processor device comprises: a floating-point register file containing a plurality of floating-point registers; a decoding section for decoding operation instructions of the RISC processor; a floating-point operation section connected to the decoding section; a control register for controlling the status of the floating-point registers and controlling the decoding section and the floating-point operation section to simulate a floating-point register stack using the floating-point register file. The decoding section includes a pointer register for maintaining a stack operation pointer and storing the value of the stack operation pointer; the floating-point operation section includes a pointer operation module for operating the pointer register, simulating the stack operation of the stack pointer of the pointer register, modifying and monitoring the phase of the stack pointer during simulating a ...

METHOD FOR THE GENERATION OF ISA SIMULATORS AND ASSEMBLERS FROM A MACHINE DESCRIPTION

A method for generating software development tools to be used in hardware and software development. The invention is utilized by processing a hardware description and a syntex description of programmable electronics, such as a microprocessor, and generating a set of development tools useful to a hardware and/or software developer. Some of these tools include, for example, simulators, assemblers, decoders, disassemblers, behavior semantics, and attribute grammars.

Datenverarbeitungsanlage mit einer Vorrichtung zum Entwickeln von Operandenadressen

Datenverarbeitungsanlage mit einem Speicher mit adressiebaren Speicherplätzen

Datenverarbeitungsanlage

Datenverarbeitungsanlage mit einer Zentraleinheit

PROCESSOR ELEMENT FOR PERFORMING ARITHMETIC AND LOGICAL OPERATIONS, INTENDED FOR USE IN CENTRAL PROCESSORS (CENTRAL), MUCH MACHINE SYSTEMS, STREAMING PROCESSORS (CS), DIGITAL PROCESSORS SIGNALS (GTLS), SYSTOLIC PROCESSORS AND PROGRAMMABLE VALVE MATRICES (PVM)

РЕКОНФИГУРИРУЕМЫЙ ПРОЦЕССОР И СПОСОБ УПРАВЛЕНИЯ РАБОТОЙ ПРОЦЕССОРНОЙ СИСТЕМЫ

... 1. Реконфигурируемый процессор, прежде всего центральный процессор (ЦП), потоковый процессор (ПП), цифровой процессор сигналов (ЦПС), систолический процессор и/или программируемая вентильная матрица (ПВМ), который для обработки обрабатываемых данных имеет множество конфигурируемых элементов-ячеек, которые выполнены с возможностью реконфигурирования их функции и их объединения в сеть в процессе их работы, отличающийся тем, что конфигурируемыми ячейками являются программируемые арифметико-логические устройства, имеющие операционное устройство для выполнения основных математических и/или логических операций и адресуемое средство (Ф-РЕГБЗП, М-РЕГБЗП) задания функций и/или параметров объединения в сеть, позволяющее независимо от обрабатываемых данных задавать конфигурируемую функцию и/или параметры объединения в сеть. 2. Процессор п.1, отличающийся тем, что операционное устройство выполнено в виде расширенного арифметико-логического устройства (РАЛУ), для управления которым предусмотрен конечный ...

Processor reduction unit for accumulation of multiple operands with or without saturation

DATA ELEMENT COMPARISON PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

DIGITAL COMPUTER WITH SEVERAL ACCUMULATOR REGISTERS

METHOD, PROCESSING UNIT AND DATA PROCESSING SYSTEM FOR MICROPROCESSOR COMMUNICATION IN A MULTI-PROCESSOR SYSTEM

HARDWARE INSTRUCTION TRANSLATION WITHIN A PROCESSOR PIPELINE

A processing system has an instruction pipeline (30) and a processor core. An instruction translator (42) for translating non-native instructions into native instruction operations is provided within the instruction pipeline downstream of the fetch stage (32). The instruction translator is able to generate multiple step sequences of native instruction operations in a manner that allows variable length native instruction operations sequences to be generated to emulate non-native instructions. The fetch stage is provided with a word buffer (62) that stores both a current instruction word and a next instruction word. Accordingly, variable length non-native instructions that span between instruction words read from the memory may be provided for immediate decode and multiple power consuming memory fetch avoided. © KIPO & WIPO 2007 ...

CALCULATION METHOD AND APPARATUS FOR SKIPPING CALCULATION REGARDING OPERATOR HAVING ZERO AS OPERAND

Disclosed are a calculation method for skipping calculations regarding an operator having a zero value as an operand and a calculation device thereof. In recent years, mobile and wearable devices employ specific micro-controller units (MCUs) such as a system on chip (SoC) to process data transmitted from various sensors. Embodiments of the present invention relate to a hardware accelerator capable of detecting a movement direction based on a six-axis sensor. The structure of the hardware accelerator can be designed based on profiling of a sensor fusion algorithm. According to the embodiments of the present invention, the hardware accelerator shows the execution time improved by 100% or more in a performance evaluation. COPYRIGHT KIPO 2017 (203) Control unit (204) Host interface (205) Matrix A buffer (206) Matrix B buffer (207) Matrix A - row (210) Result buffer (211) Zero comparer (212) Zero bit check buffer (213) Zero bit check unit (220) Embedded core (AA) Hardware accelerator ...

Apparatus and method for interpreting permissions related to qualification

Microprocessor with private microcode RAM

A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macro architecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the micro architecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency ...

Apparatus and method for handling exception events

Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store 35. When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry 40 selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry 4. When the processing circuitry 4 is a further exception state, the stack pointer selection circuitry 40 selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.

Microprocessor with multiple low power modes and emulation apparatus for said microprocessor

A microprocessor comprises a central processing unit receiving a first clock signal, a plurality of peripherals receiving a second clock signal a first select unit for selecting the first clock signal out of a plurality of clock signals and a second select unit for selecting the second clock signal out of the plurality of clock signals. The central processing unit comprises an execution unit which controls the select units upon execution of a low power mode instruction to select a clock signal for the central processing unit and the peripheral units.

SYSTEM AND METHOD TO REDUCE EXECUTION OF INSTRUCTIONS INVOLVING UNRELIABLE DATA IN A SPECULATIVE PROCESSOR

System and method to reduce execution of instructions involving unreliable data in a speculative processor. A method comprises identifying scratch values generated during speculative execution of a processor, and setting at least one tag associated with at least one data area of the processor to indicate that the data area holds a scratch value. Such data areas include registers, predicates, flags, and the like. Instructions may also be similarly tagged. The method may be executed by an execution engine in a computer processor.

PREDECODING INSTRUCTIONS TO DETERMINE STACK CHANGE INFORMATION

A system includes a CPU and a code translator. The CPU may execute instructions from a first instruction set, and the code translator may translate Java code sequences from Java bytecodes to code sequences having instructions defined in the first instruction set. The translated code sequences may be executed by the CPU. The Java instruction set is a stack-based instruction set, and the first instruction set may be a register-based instruction set. Accordingly, the code translator may translate stack operand references to register operand references. The code translator may predecode the Java bytecodes with stack change information to aid in the translation of stack operand references to register operand references. For example, the stack change information may include a number of pushes, a number of pops, and a stack pointer modification for each bytecode. By predecoding the stack change information, the translation process may be performed more rapidly. Furthermore, several instructions ...

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO CHECK AND STORE INDICATIONS OF WHETHER MEMORY ADDRESSES ARE IN PERSISTENT MEMORY

A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.

User opt-in processor feature control capability

A processor includes a feature control unit to enable or disable one or more processor features individually in response to a user selectable setting. The feature control unit is adapted to disable the processor feature(s) if the user setting has not been updated in accordance with an input regardless of the value of the user setting prior to the update and to enable or disable the processor feature(s) in accordance with the updated user setting after it has been updated. The feature control unit may also include a lock unit to prevent changes to the updated user setting and a software feature selection unit to enable or disable processor features in response to a software feature selection setting and, optionally, only enable or disable processor features whose corresponding updated user setting is user enabled. The feature control unit may also include mechanisms to detect illegal feature selection conditions.

INSTRUCTIONS FOR VECTOR MULTIPLICATION OF SIGNED WORDS WITH ROUNDING

Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

PARTITION IDENTIFIERS FOR PAGE TABLE WALK MEMORY TRANSACTIONS

Memory transactions can be tagged with a partition identifier selected depending on which software execution environment caused the memory transaction to be issued. A memory system component can control allocation of resources for handling the memory transaction or manage contention for said resources depending on a selected set of memory system component parameters selected depending on the partition identifier specified by the memory transaction, or can control, depending on the partition identifier specified by the memory transaction, whether performance monitoring data is updated in response to the memory transaction. Page table walk memory transactions may be assigned a different partition identifier to the partition identifier assigned to the corresponding data/instruction access memory transaction.

TARGET INJECTION SAFE METHOD FOR DYNAMICALLY INLINING BRANCH PREDICTIONS

A method for redirecting an indirect call in an operating system kernel to a direct call is disclosed. The direct calls are contained in trampoline code called an inline jump switch (IJS) or an outline jump switch (OJS). The IJS and OJS can operate in either a use mode, redirecting an indirect call to a direct call, a learning and update mode or fallback mode. In the learning and update mode, target addresses in a trampoline code template are learned and updated by a jump switch worker thread that periodically runs as a kernel process. When building the kernel binary, a plug-in is integrated into the kernel. The plug-in replaces call sites with a trampoline code template containing a direct call so that the template can be later updated by the jump switch worker thread.

Context state management for processor feature sets

Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

System and method for creating precise exceptions

A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.

Apparatus and method for masked move to and from flags register in a processor

A method and apparatus are provided for reading from and storing a flags register in a processor. In response to a macro instruction directing the read and store operation, such as a push flags macro instruction, a mask is generated using privilege level information (i.e., current operating privilege level) to specify those bits of the flags register that can be stored.r. The mask is then ANDed with contents of the flags register to yield a result and the result is stored on a stack in memory.

Module with a serialization unit and improved compatibility with deserialization units of different series

A module with a functional unit for generating a data stream with a data output for outputting the data stream to a serialization unit provided for receiving a data stream from a serialization unit of a first series. A serialization unit of a second series is set up to serialize the data stream and output it through the data output, and a configuration data input receives configuration data defining a first register configuration of a serialization unit. A mapping of register addresses of the serialization unit of the first series to register addresses of the serialization unit of the second series can be stored in a data memory of the module. The configuration unit is set up to read in the configuration data, to use the mapping, and to configure the registers of the serialization unit of the second series according to the configuration of the second register.

CONTROL OF MULTIPLE FUNCTIONAL UNITS WITH PARALLEL OPERATION IN A MICROCODED EXECUTION UNIT

Data processing system and method of permutation with replication within a vector register file

The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The specification of the control vector allows a vector-matrix operation to be performed on the input vectors by rearranging or replicating the input operand bytes in the bytes of the output register as a function of the control vector. This system provides a highly efficient register loading mechanism for data vectors misaligned in memory, and allows the computation of a serially dependent chain of binary ...

Data processing system and method thereof

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Data processor and method of controlling the same

There are provided a means for storing an instruction, a first control means for decoding and executing the instruction of said means for storing during a timing period which is used in said instruction, a means for computing an address data required for execution of said instruction, a first storage means having a plurality of registers for storing said computed address data, a means for selecting specific number resister in the first storage means, by controlling of the first control means during a timing period which is not used in said instruction, a second storage means for storing temporarily said address data in the specific number register selected by said means for selecting, a second control means for decoding the instruction before the first control means decoding and finding out the instruction to be branch instruction, and a means for outputting the address data from the second storage means as a target address data, when the register of the first storage means designated by ...

Prefetch instruction mechanism for processor

Accordingly, a prefetch instruction mechanism is desired for implementing a prefetch instruction which is non-faulting, non-blocking, and non-modifying of architectural register state. Advantageously, a prefetch mechanism described herein is provided largely without the addition of substantial complexity to a load execution unit. In one embodiment, the non-faulting attribute of the prefetch mechanism is provided though use of the vector decode supplied Op sequence that activates an alternate exception handler. The non-modifying of architectural register state attribute is provided (in an exemplary embodiment) by first decoding a PREFETCH instruction to an Op sequence targeting a scratch register wherein the scratch register has scope limited to the Op sequence corresponding to the PREFETCH instruction. Although described in the context of a vector decode embodiment, the prefetch mechanism can be implemented with hardware decoders and suitable modifications to decode paths will be appreciated ...

Methods and systems of stack renaming for superscalar stack-based data processors

Methods and systems are disclosed for exploring instruction-level parallelism in superscalar processors by renaming stack entries. In a first embodiment, the stack renaming is implemented in a parallel structure that renames the instructions in parallel. In a second embodiment, the stack renaming is implemented in a serial structure that renames the instructions serially. In a third embodiment, the stack renaming is implemented in a combined parallel-serial structure that renames the instruction partially in parallel and partially in series.

Instruction execution that broadcasts and masks data values at different levels of granularity

An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication ...

Processor architecture with wide operand cache

A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Parallel data processing apparatus

A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.

Processor with last branch record register storing transaction indicator

In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Last branch record indicators for transactional memory

In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Data element comparison processors, methods, systems, and instructions

A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Digital Camera System Incorporating VLIW Image Processor

A hand-held digital camera device includes a programmable processing circuitry incorporating a four-way parallel VLIW vector processor; an image sensor interface connected to the programmable processing circuitry and configured to receive signals from an image sensor and pass data representing the signals to the programmable processing circuitry; and a printhead interface connected to the programmable processing circuitry and configured to receive data from the programmable processing circuitry and generate control signals to be received by a printhead of a printing mechanism. The programmable processing circuitry, the image sensor interface and the printhead interface all form part of CMOS integrated circuitry provided on a common wafer. An instruction set of the VLIW vector processor is tuned for image manipulation processing.

Method, processing unit and data processing system for microprocessor communication in a multi-processor system

A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Controlling a clock frequency of a plurality of processors

A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to a respective clock input of one of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

SYSTEM AND METHOD FOR PERFORMING COMPUTATIONS FOR DEEP NEURAL NETWORKS

A computation unit for performing a computation of a neural network layer is disclosed. A number of processing element (PE) units are arranged in an array. First input values are provided in parallel in an input dimension of the array during a first processing period, and a second input values are provided in parallel in the input dimension during a second processing period. Computations are performed by the PE units based on stored weight values. An adder coupled to the first set of PE units generates a first sum of results of the computations by the first set of PE units during the first processing cycle, and generates a second sum of results of the computations during the second processing cycle. A first accumulator coupled to the first adder stores the first sum, and further shifts the first sum to a second accumulator prior to storing the second sum.

Method and device for modifying the memory contents of and reprogramming a memory

A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

METHOD AND APPARATUS FOR RENAMING SOURCE OPERANDS OF INSTRUCTIONS

A renaming unit configured to rename source operands of instructions in a group. A renaming register maintains architectural to physical register mappings. Architectural to physical register mappings propagate from the renaming register through a chain of update units (U) over bus lines denoted with the architectural registers 0 to L. Update units (U) sequentially, in program order, insert physical register identifiers PR(i) allocated to instructions I(i) with destination operands DOP(i) on bus lines denoted with the destination operands DOP(i). Source operands of an instruction I(i) may be renamed to physical register identifiers after physical register identifiers allocated to instructions older than I(i) are sequentially, in program order, inserted on the bus lines, but before physical register identifiers allocated to I(i) and younger instructions are inserted on the bus lines. A source operand SOP(i) is renamed to a physical register identifier that propagates on a bus line denoted ...

Low latency matrix multiply unit

Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.

Packed data operation mask concatenation processors, methods, systems and instructions

A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is stored in the destination in response to the packed data operation mask concatenation instruction. The result includes the first packed data operation mask concatenated with the second packed data operation mask. Other methods, apparatus, systems, and instructions are disclosed.

METHOD AND APPARATUS FOR EFFICIENTLY MANAGING OFFLOAD WORK BETWEEN PROCESSING UNITS

Apparatus and method for selectively saving and restoring execution state components in an inter-core work offload environment. For example, one embodiment of a processor comprises: a plurality of cores; an interconnect coupling the plurality of cores; and offload circuitry to transfer work from a first core of the plurality of cores to a second core of the plurality of cores without operating system (OS) intervention, wherein the second core is to reach a first execution state upon completing the offload work and to store results in a first memory location or register; the second core comprising: a decoder to decode a first instruction comprising at least one operand to identify one or more components of the first execution state; and execution circuitry to execute the first instruction to save the one or more components of the first execution state to a specified region in memory.

NEURAL NETWORK UNIT THAT PERFORMS CONVOLUTIONS USING COLLECTIVE SHIFT REGISTER AMONG ARRAY OF NEURAL PROCESSING UNITS

A neural network unit has a first memory that holds elements of a data matrix and a second memory that holds elements of a convolution kernel. An array of neural processing units (NPU) each have a multiplexed register that receives a corresponding element of a row from the first memory and that also receives the multiplexed register output of an adjacent NPU. A register receives a corresponding element of a row from the second memory. An arithmetic unit receives the outputs of the register, the multiplexed register and an accumulator and performs a multiply-accumulate operation on them. For each sub-matrix of a plurality of sub-matrices of the data matrix, each arithmetic unit selectively receives either the element from the first memory or the adjacent NPU multiplexed register output and performs a series of the multiply-accumulate operations to accumulate into the accumulator a convolution of the sub-matrix with the convolution kernel.

Retirement serialisation of status register access operations

A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20 . In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.

Sharing a fault-status register when processing vector instructions

The described embodiments provide a processor that executes vector instructions. In the described embodiments, the processor initializes an architectural fault-status register (FSR) and a shadow copy of the architectural FSR by setting each of N bit positions in the architectural FSR and the shadow copy of the architectural FSR to a first predetermined value. The processor then executes a first first-faulting or non-faulting (FF/NF) vector instruction. While executing the first vector instruction, the processor also executes one or more subsequent FF/NF instructions. In these embodiments, when executing the first vector instruction and the subsequent vector instructions, the processor updates one or more bit positions in the shadow copy of the architectural FSR to a second predetermined value upon encountering a fault condition. However, the processor does not update bit positions in the architectural FSR upon encountering a fault condition for the first vector instruction and the subsequent vector instructions.

Thread transition management

Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

Processor, and method of loop count control by processor

The present invention provides a processor comprising: a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued; a data memory that receives, from outside, data that is used for executing a process in the loop; a calculator that uses the data transferred to said data memory to execute the process in the loop; a data counter that increments said loop counter by 1 every time a certain amount of data is transferred from outside to said data memory; and a loop controller that decrements said loop counter by 1 and causes said calculator to execute the process in the loop when the loop count value of said loop counter is not 0.

Method, apparatus, and system for speculative execution event counter checkpointing and restoring

An apparatus, method, and system are described herein for providing programmable control of performance/event counters. An event counter is programmable to track different events, as well as to be checkpointed when speculative code regions are encountered. So when a speculative code region is aborted, the event counter is able to be restored to it pre-speculation value. Moreover, the difference between a cumulative event count of committed and uncommitted execution and the committed execution, represents an event count/contribution for uncommitted execution. From information on the uncommitted execution, hardware/software may be tuned to enhance future execution to avoid wasted execution cycles.

Region-Weighted Accounting of Multi-Threaded Processor Core According to Dispatch State

According to one embodiment of the present disclosure, an approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using the selected weighting value and a dispatch factor that indicates a weighting adjustment of the selected weighting value. In turn, a resource utilization value of the selected thread is computed using the dispatch weighting value.

Electronic Device and Method for Data Processing Using Virtual Register Mode

The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.

Multi-core processor for hand-held, image capture device

A multi-core processor for installation in a hand-held device that has first and second image sensors. The multi-core processor has a first sensor interface for receiving data from the first image sensor, and a second sensor interface for receiving data from the second image sensor. Multiple processing units in the multi-core processor are configured to operate in parallel for processing data from the first and second sensor interfaces. The multiple processing units and the first and second sensor interfaces are all integrated onto a single chip.

Portable imaging device with multi-core processor

A portable imaging device that has a CMOS image sensor, a color display for displaying an image sensed by the CMOS image sensor and a central processor. The central processor has an image sensor interface for receiving data from the CMOS image sensor, multiple processing units for parallel operation to simultaneously process the data, and an image display interface for sending processed data to the color display. The central processor is integrated onto a single chip.

Hand-held quad core processing apparatus

A hand-held apparatus is provided having a digital camera, a display, a miniature keyboard, a network interface, and four interconnected processing units arranged to jointly run programs for the operation of the digital camera, display, miniature keyboard, and network interface.

Tracking operand liveliness information in a computer system and performance function based on the liveliness information

Operand liveness state information is maintained during context switches for current architected operands of executing programs the current operand state information indicating whether corresponding current operands are any one of enabled or disabled for use by a first program module, the first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands, wherein a current operand is accessed by a machine instruction of said first program module, the accessing comprising using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.

Instruction set architecture with extended register addressing

A method and circuit arrangement selectively repurpose bits from a primary opcode portion of an instruction for use in decoding one or more operands for the instruction. Decode logic of a processor, for example, may be placed in a predetermined mode that decodes a primary opcode for an instruction that is different from that specified in the primary opcode portion of the instruction, and then utilize one or more bits in the primary opcode portion to decode one or more operands for the instruction. By doing so, additional space is freed up in the instruction to support a larger register file and/or additional instruction types, e.g., as specified by a secondary or extended opcode.

Processor for Executing Wide Operand Operations Using a Control Register and a Results Register

A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Exception handling in a data processing apparatus having a secure domain and a less secure domain

Processing circuitry can operate in a secure domain and a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, state saving of data from a first subset of registers is performed by exception control circuitry before triggering an exception handling routine, while the exception handling routine has responsibility for performing state saving of data from a second subset of registers. In response to a first exception causing a transition from the secure domain from a less secure domain, where the background processing was in the less secure domain, the exception control circuitry performs additional state saving of data from the second set of registers before triggering the exception handling routine. In response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception handling routine is triggered without performing an additional state saving.

Context state management for processor feature sets

Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

Run-time-instrumentation controls emit instruction

Embodiments of the invention relate to executing a run-time-instrumentation EMIT (RIEMIT) instruction. A processor is configured to capture the run-time-instrumentation information of a stream of instructions. The RIEMIT instruction is fetched and executed. It is determined if the current run-time-instrumentation controls are configured to permit capturing and storing of run-time-instrumentation information in a run-time-instrumentation program buffer. If the controls are configured to store run-time-instrumentation instructions, then a RIEMIT instruction specified value is stored as an emit record of a reporting group in the run-time-instrumentation program buffer.

Modifying run-time-instrumentation controls from a lesser-privileged state

Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control.

Computer system

There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU# 0 through VCPU# 2 each operate different OS's. VCPU# 0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU# 0 regardless of an execution sequence stored in schedule register A. VCPU# 0 reinitializes a bus where an error occurred.

Super multiply add (super madd) instruction

A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.

APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER

An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register. 1. A processor for detecting identical elements within a vector register comprising , the processor to execute one or more instructions to perform the operations of:reading each active element from a first vector register, each active element having a defined bit position within the first vector register;reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register;reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising ...

GRAPHICS PROCESSING UNIT

A graphics processing unit includes a sparse matrix detection unit, a register file, an assertion register, and a matrix calculation unit. The sparse matrix detection unit reads a plurality of matrices from a storage device and determines whether the matrices are zero matrices or non-zero matrices to output a determination result. The register file stores the plurality of matrices from the sparse matrix detection unit. The assertion register marks up the matrices according to the determination result, and outputs a mark result. The matrix calculation unit receives a matrix calculation instruction, reads the non-zero matrices in the plurality of matrices from the register file according to the mark result, and calculates the non-zero matrices. 1. A graphics processing unit , comprising:a sparse matrix detection unit, reading a plurality of matrices in a storage device, determining whether the plurality of matrices are zero matrices or non-zero matrices to output a determination result;a register file, storing the plurality of matrices from the sparse matrix detection unit;an assertion register, marking the plurality of matrices according to the determination result, and outputting a mark result;a matrix calculation unit, receiving a matrix calculation instruction, reading the non-zero matrices in the plurality of matrices from the register file according to the mark result, and performing matrix calculations on the non-zero matrices.2. The graphics processing unit as claimed in claim 1 , further comprising:a thread scheduling and instruction distribution unit, sending an integer calculation instruction and the matrix calculation instruction;an integer calculation unit, receiving the integer calculation instruction and the matrix calculation instruction; wherein the integer calculation unit executes an integer calculation according to the integer calculation instruction, and passes the matrix calculation instruction to the matrix calculation unit.3. The graphics ...

CLUSTER IDENTIFIER REMAPPING FOR ASYMMETRIC TOPOLOGIES

A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks and determine whether the actual topology matches the desired topology as described in the cluster remapping table. 1. A non-transitory machine-readable storage medium with instructions stored thereon , the instructions executable by a machine to cause the machine to:access a cluster remapping register stored in computer memory;determine, from the cluster remapping register, a mapping of a first integrated circuit block in a first chip to a first cluster identifier, wherein the first cluster identifier is different than an assigned cluster identifier for the first integrated circuity block;determine, from the cluster remapping register, a mapping of a second integrated circuit block in the first chip to a second cluster identifier from the cluster remapping register;identify a first interconnect link to couple the first integrated circuit block in the first chip to a third integrated circuit block in a second chip;identify a second interconnect link to couple the second integrated circuit block in the first chip to a fourth integrated circuit block in the second chip; anddetermine whether connections made by the first and second interconnect links match connections defined in the cluster remapping register.2. The storage medium of claim 1 , wherein the instructions are further executable to:identify a mapping of the third integrated circuit block to a third cluster identifier;identify a mapping of the ...

INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL MAJORITY VOTING FUNCTIONALITY

Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand. 1. A processor comprising:a vector register comprising a plurality of data fields to store values of vector elements;a decode stage to decode a first instruction specifying: a destination operand, a size of the vector elements, a portion of the data fields, and a source operand; and read a number of values from data fields of the size of the vector elements in the source operand; and', 'store a result value in the destination operand specified by the first instruction, wherein the result value is computed from most common values read from the number of the values from the data fields of the source operand., 'an execution unit, responsive to the decoded first instruction, to2. The processor of claim 1 , wherein the execution unit claim 1 , responsive to the decoded first instruction claim 1 , is to store the result value to corresponding data fields in the destination operand specified by the first instruction.3. The processor of claim 1 , wherein the first instruction specifies a mask identifying the portion of the data fields claim 1 , and wherein the number of the values read from the data fields in the source operand corresponds to vector elements in the source operand unmasked by the mask specified by the first instruction.4. The processor of claim 3 , wherein the result value is computed as a bitwise majority value ...

APPARATUS AND METHOD FOR REENTERING A TRANSACTIONAL SEQUENCE WITH HARDWARE TRANSACTIONAL MEMORY

An apparatus and method are described for reentering a transactional sequence for hardware transactional memory. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; execution circuitry within at least one of the cores to execute a transactional sequence of instructions; a mask value to identify a specified set of architectural state to be saved upon reaching a particular instruction within the transactional sequence of instructions; and a scratchpad memory within the execution circuitry to store the specified set of architectural state upon reaching the particular instruction within the sequence of instructions. 1. A processor comprising:one or more cores to execute instructions and process data;execution circuitry within at least one of the cores to execute a transactional sequence of instructions;one or more mask registers to store a mask value identifying a specified set of architectural state to be saved upon reaching a particular instruction within the transactional sequence of instructions; anda scratchpad memory within the execution circuitry to store the specified set of architectural state upon reaching the particular instruction within the sequence of instructions.2. The processor as in wherein the particular instruction is to be identified by a compiler or an application designer.3. The processor as in wherein the specified set of architectural state includes a specified set of register values and/or application-specific data.4. The processor as in further comprising:abort detection logic to detect an abort condition associated with the transactional sequence of instructions; andresteering logic to restore the architectural state from the scratchpad memory and to identify a next instruction within the transactional sequence of instructions from which transactional execution is to resume.5. The processor as in wherein the next instruction directly follows the particular instruction in the ...

Metadata Programmable Tags

A method comprises receiving a current instruction for metadata processing performed in a metadata processing domain that is isolated from a code execution domain including the current instruction. The method further comprises determining, by the metadata processing domain in connection with metadata for the current instruction, whether to allow execution of the current instruction in accordance with a set of one or more policies. The one or more policies may include a set of rules that enforces execution of a complete sequence of instructions in a specified order from a first instruction of the complete sequence to a last instruction of the complete sequence. The metadata processing may be implemented by a metadata processing hierarchy comprising a control module, a masking module, a hash module, a rule cache lookup module, and/or an output tag module.

HIGH PERFORMANCE EXPRESSION EVALUATOR UNIT

Devices and methods for limiting register usage through the use of fixed function processing is provided. The method may include receiving instructions executable by a processor. The method may also include that a set of the instructions is executable according to a restricted register mode when the set of the instructions relate to one or more single function operations, wherein the restricted register mode includes only a single access or no access to a register. The method may further include executing, by an expression evaluator, operations of the set of the instructions related to the one or more single function operations, wherein the executing is performed in the restricted register mode and in parallel with the processor performing additional operations of the instructions. 1. A method of computer processing , comprising:receiving instructions executable by a processor;determining, by the processor, that a set of instructions of the received instructions is executable according to a restricted register mode in which the set of instructions relate to one or more single function operations that require no access to a register during execution of the one or more single function operations; andexecuting, by an expression evaluator, operations of the set of instructions related to the one or more single function operations, wherein the executing is performed in the restricted register mode and in parallel with the processor performing arithmetic logic unit (ALU) operations of the instructions.2. The method of claim 1 , wherein determining the set of instructions is executable according to the restricted register mode includes identifying a syntax associated with the set of instructions that identifies that the set of instructions relate to the one or more single function operations.3. The method of claim 1 , wherein the single function operations are one or more of a single mathematical operand or a register copy operand.4. The method of claim 1 , further ...

CODE-SPECIFIC AFFILIATED REGISTER PREDICTION

Code-specific affiliated register prediction. A determination is made as to whether a unit of code is a candidate for affiliated register prediction. The determining employs a code specific indicator specific to the unit of code. Based on determining the unit of code is a candidate for affiliated register prediction, an indication of an affiliated register is loaded into a selected location. Based on the loading, the affiliated register is employed in speculative processing. 1. A computer system for facilitating processing within a computing environment , the computer system comprising:a memory; and determining for a unit of code whether the unit of code is a candidate for affiliated register prediction, wherein the determining employs a code specific indicator specific to the unit of code, wherein the code specific indicator specific to the unit of code is part of configuration information associated with the unit of code;', 'loading into a selected location a location identifier of an affiliated register, based on determining the unit of code is a candidate for affiliated register prediction; and', 'employing, based on the loading, the affiliated register in speculative processing., 'a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising2. The computer system of claim 1 , wherein another unit of code has another code specific indicator specific to the other unit of code to be used to determine whether the other unit of code is a candidate for affiliated register prediction.3. The computer system of claim 1 , wherein the selected location is selected from a group consisting of a machine state register claim 1 , a program status word claim 1 , a special purpose register claim 1 , a page table entry claim 1 , a segment table entry claim 1 , and a specific control register.4. The computer system of claim 1 , wherein the method further comprises:determining a context switch has occurred; ...

Determining and predicting derived values

A predicted value to be used in register-indirect branching is predicted. The predicted value is to be stored in one or more locations based on the prediction. An offset for a predicted derived value is obtained. The predicted derived value is to be used as a pointer to a reference data structure providing access to variables used in processing. The predicted derived value is generated using the predicted value and the offset. The predicted derived value is used to access the reference data structure during processing.

Information processing apparatus and control method in information processing apparatus

An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: measure power consumption of the processor; measure performance of the processor; detect a decrease in power efficiency of the processor, based on the power consumption of the processor measured during execution of a program; in response to detection of a decrease in the power efficiency, execute the program while changing an operation parameter of the processor; and determine a setting value of the operation parameter, based on the power consumption and the performance of the processor that are measured during execution of the program while the operation parameter is being changed.

CORE MAPPING

The disclosed technology is generally directed to peripheral access. In one example of the technology, stored configuration information is read. The stored configuration information is associated with mapping a plurality of independent execution environments to a plurality of peripherals such that the peripherals of the plurality of peripherals have corresponding independent execution environments of the plurality of independent execution environments. A configurable interrupt routing table is programmed based on the configuration information. An interrupt is received from a peripheral. The interrupt is routed to the corresponding independent execution environment based on the configurable interrupt routing table. 120-. (canceled)21. An apparatus , comprising:a plurality of processing cores;a plurality of peripherals; anda configurable interrupt routing table that selectively maps each of the plurality of peripherals to an individual processing core of the plurality of processing cores, wherein the mapping of each of the plurality of peripherals to the individual processing core is configurable while a lock bit of the apparatus is not set, wherein the mapping of each of the plurality of peripherals to the individual processing core is locked in response to the lock bit of the apparatus being set, and wherein, once locked, the mapping of each of the plurality of peripherals to the individual processing core remains locked until a reboot of the apparatus.22. The apparatus of claim 21 , wherein the configurable interrupt routing table includes a plurality of configuration registers.23. The apparatus of claim 21 , wherein a first processing core of the plurality of processing cores is associated with at least two independent execution environments.24. The apparatus of claim 23 , wherein a first independent execution environment associated with the first processing core is a Secure World operating environment of the first processing core claim 23 , and wherein a second ...

MULTISTATE REGISTER HAVING A FLIP FLOP AND MULTIPLE MEMRISTIVE DEVICES

A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices. 1. A multistate register , comprising:a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches;multiple memristive devices; andan interface coupled between the multiple memristive devices and the flip-flop;wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode;wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch;wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; andwherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the ...

TECHNIQUES FOR METADATA PROCESSING

Techniques are described for metadata processing that can be used to encode an arbitrary number of security policies for code running on a processor. Metadata may be added to every word in the system and a metadata processing unit may be used that works in parallel with data flow to enforce an arbitrary set of policies. In one aspect, the metadata may be characterized as unbounded and software programmable to be applicable to a wide range of metadata processing policies. Techniques and policies have a wide range of uses including, for example, safety, security, and synchronization. Additionally, described are aspects and techniques in connection with metadata processing in an embodiment based on the RISC-V architecture. 129-. (canceled)30. A method of processing instructions comprising:receiving a current instruction for metadata processing performed in a metadata processing domain that is isolated from a code execution domain including the current instruction, anddetermining, by the metadata processing domain in connection with metadata for the current instruction, whether to allow execution of the current instruction in accordance with a set of one or more policies, wherein the one or more policies include a set of rules that enforce execution of a complete sequence of instructions in a specified order from a first instruction of the complete sequence to a last instruction of the complete sequence.31. The method of claim 30 , further comprising:mapping a first shared physical page into a first virtual address space of a first process; andmapping the first shared physical page into a second virtual address space for a second process, said first shared physical page including a plurality of memory locations, wherein each of the plurality of memory locations is associated with one of a plurality of global metadata tags used in connection with rule processing in the metadata processing domain.32. The method of claim 31 , wherein the plurality of global metadata tags ...

TARGET INJECTION SAFE METHOD FOR INLINING REGISTRATION CALLS

A method of redirecting an indirect call in a callback list associated with a list of functions that are registered, includes the steps of: upon registering the list of functions, determining a list of function pointers, each of which corresponds to an address in an associated callback; for each function pointer in the list of function pointers, adding a direct call instruction to the registration trampoline corresponding to the associated callback of the function pointer; and upon invoking the associated callback of one of the function pointers in the list of function pointers, invoking the corresponding direct call instruction in the registration trampoline. 1. A method of redirecting an indirect call in a callback list associated with a list of functions that are registered , to a direct call in a registration trampoline , the method comprising:upon registering the list of functions, determining a list of function pointers, each of which corresponds to an address in an associated callback;for each function pointer in the list of function pointers, adding a direct call instruction to the registration trampoline corresponding to the associated callback of the function pointer; andupon invoking the associated callback of one of the function pointers in the list of function pointers, invoking the corresponding direct call instruction in the registration trampoline.2. The method of claim 1 , wherein determining the list of function pointers includes unrolling a loop to expose the address in the associated callback.3. The method of claim 1 , wherein the list of function pointers is registered by an operating kernel.4. The method of claim 1 , wherein the list of function pointers is a filter list.5. The method of claim 4 , wherein the filter list is derived from a system call filter.6. The method of claim 1 , wherein the registration trampoline is implemented as an instance trampoline.7. The method of claim 1 , further comprising:upon receiving a modification to the ...

MANAGING CONTROL DATA

There is provided a neural processing unit (NPU), including a primary processing node containing primary control registers and processing circuitry configured to write control data to the primary control registers, and multiple secondary processing nodes each having respective secondary control registers and being configured to process data in accordance with control data stored by the respective secondary control registers. The NPU also includes a bus interface for transmitting data between the primary processing node and the plurality of secondary processing nodes. The primary processing node is configured to transmit first control data to a given secondary control register of each of the plurality of secondary processing nodes. 1. A neural processing unit (NPU) comprising:a primary processing node comprising primary control registers and processing circuitry configured to write control data to the primary control registers;a plurality of secondary processing nodes each comprising respective secondary control registers and being configured to process data in accordance with control data stored by the respective secondary control registers; anda bus interface for transmitting data between the primary processing node and the plurality of secondary processing nodes,wherein the primary processing node is configured to transmit first control data to a given secondary control register of each of the plurality of secondary processing nodes.2. The NPU of claim 1 , wherein the bus interface is adapted to broadcast the first control data to the given secondary control registers.3. The NPU of claim 2 , wherein the bus interface is adapted to broadcast the first control data to the given secondary control registers in response to the processing circuitry setting an indicator to a first state.4. The NPU of claim 3 , wherein the indicator comprises an indicator bit transmitted by the processing circuitry in association with the first control data.5. The NPU of claim 4 , wherein ...

FLEXIBLE AND IN-LINE REGISTER COMPARISON FOR BUG ANALYSIS

A validation and testing method is provided. The validation and testing method is executable by a processor coupled to a memory. The validation and testing method includes inserting intermediary save points within an instruction stream. The method includes executing the instruction stream including the intermediary save points. The method includes executing a save operation for data in one or more registers at each of the one or more intermediary save points. 1. A validation and testing method comprising:inserting, by a processor coupled to a memory, one or more intermediary save points within an instruction stream;executing, by the processor, the instruction stream including the one or more intermediary save points; andexecuting, by the processor, a save operation for data in one or more registers at each of the one or more intermediary save points.2. The validation and testing method of claim 1 , wherein the inserting the one or more intermediary save points comprises:inserting one of the one or more intermediary save points after a predefined number of instructions are executed.3. The validation and testing method of claim 1 , wherein the inserting the one or more intermediary save points comprises:inserting one of the one or more intermediary save points based on a complexity of an individual instruction within the instruction stream.4. The validation and testing method of claim 3 , wherein the inserting the one or more intermediary save points comprises:ignoring individual instruction within the instruction stream comprising a higher probability of working.5. The validation and testing method of claim 3 , wherein the inserting the one or more intermediary save points comprises:ignoring individual instruction within the instruction stream comprising a lower probability of working.6. The validation and testing method of claim 1 , wherein the validation and testing method comprises:executing an in-line register comparison at each of the one or more intermediary ...

METHOD AND DEVICE FOR INTRUSION DETECTION IN A COMPUTER NETWORK

A device and method for intrusion detection in a computer network. A data packet is received at an input of a hardware switch unit, an output of the hardware switch unit is selected for sending the data packet or a copy as a function of security layer information from the data packet and of a hardware address, context information for the data packet being determined, an actual value from a field being compared in a comparison by a hardware filter with a setpoint value for values from this field, the field including security layer data or mediation layer data, and an interrupt for a computing device being triggered as a function of a result of the comparison, an analysis for detecting an intrusion pattern in a network traffic in the computer network, triggered by the interrupt, being carried out as a function of the context information for the data packet. 1. A method for intrusion detection in a computer network , the method comprising the following steps:receiving a data packet at an input of a hardware switch unit;selecting an output of the hardware switch unit for sending the data packet or a copy of the data packet as a function of security layer information from the data packet and as a function of a hardware address;determining context information for the data packet;comparing, by a hardware filter, an actual value from a field of the data packet with a setpoint value for values from the field, the field including security layer data or mediation layer data;triggering an interrupt for a microprocessor as a function of a result of the comparison;carrying out by the microprocessor, triggered by the interrupt, an analysis for detecting an intrusion pattern in a network traffic in the computer network as a function of the context information for the data packet.2. The method as recited in claim 1 , wherein the context information for the data packet is stored in a register claim 1 , a register access of the microprocessor to the register taking place for the ...

On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer

A system and method for avoiding write back collisions. The system receives a plurality of instructions at a pipeline queue. Next an issue queue determines a number of cycles for each instruction of the plurality of instructions. The issue queue further determines if a collision will occur between at least two of the instructions. Additionally, the system determines in response to a collision between at least two of the instructions, a number of cycles to delay at least one of the at least two instructions. The instructions are then executed. The system then places the results of the instruction for instructions that had a calculated delay in a result buffer for the determined number of cycles of delay. After the determined number of cycles of delay, the system sends the results to a results mux. Once received at the results mux the results are written back to the register file.

EVENT NOTIFICATION SUPPORT FOR NESTED VIRTUAL MACHINES

Systems and methods for event notification support for nested virtual machines. An example method may comprise running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine. The Level 1 hypervisor may generate a virtual device and an input/output (I/O) translation table comprising an I/O translation table entry associated with the virtual device, and associate the I/O translation table entry with a Level 1 virtual machine context maintained by at least one of the Level 0 hypervisor or Level 1 hypervisor. The method may further responsive to detecting, by the Level 0 hypervisor, an event notification from the Level 2 virtual machine, cause a central processing unit (CPU) to use the I/O translation table to execute access to the Level 1 guest virtual address. 1. A method comprising:running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine,generating, by the Level 1 hypervisor, a virtual device and an input/output (I/O) translation table comprising an I/O translation table entry associated with the virtual device, wherein the I/O translation table entry maps a Level 2 guest virtual address of a Level 2 address space associated with the Level 2 virtual machine to a corresponding Level 1 guest virtual address of a Level 1 address space associated with the Level 1 virtual machine;associating the I/O translation table entry with a Level 1 virtual machine context maintained by at least one of the Level 0 hypervisor or Level 1 hypervisor; andresponsive to detecting, by the Level 0 hypervisor, an event notification from the Level 2 virtual machine, causing a central processing unit (CPU) to use the I/O translation table to execute access to the Level 1 guest virtual address.2. The method of claim 1 , wherein the I/O ...

RISC PROCESSOR HAVING SPECIALIZED DATAPATH FOR SPECIALIZED REGISTERS

A data path block circuit is disclosed. The data path block circuit includes a data path circuit having logic circuits, each configured to perform a data path operation to generate a result based on first and second operands. The data path block circuit also includes a first operand multiplexer, having inputs, each connected to one of a first register file, including a quantity of read and write ports, and a second register file, including a different quantity of read and write ports. The data path block circuit also includes a second operand multiplexer, having inputs, each connected to one of the first register file and the second register file. At least one of the first and second operand multiplexers includes a data input connected to the first register file. At least one of the first and second operand multiplexers includes a data input connected to the second register file. 1. A data path block circuit , comprising:a first data path circuit comprising a plurality of a logic circuits, each configured to receive data to be used as first and second operands, and to perform a data path operation to generate a result based on the first and second operands; a first register file, comprising a first quantity of read ports and a second quantity of write ports, and', 'a second register file, comprising a third quantity of read ports and a fourth quantity of write ports,', 'wherein the first quantity of read ports is different from the third quantity of read ports, and wherein the second quantity of write ports is different from the fourth quantity of write ports; and, 'a first plurality of data inputs, each connected to one of, 'a first operand multiplexer, comprising the first register file, and', 'the second register file,, 'a second plurality of data inputs, each connected to one of, 'a second operand multiplexer, comprisingwherein at least one of the first operand multiplexer and the second operand multiplexer comprises a data input connected to the first register ...

Method For Enlarging Data Memory In An Existing Microprocessor Architecture With Limited Memory Addressing

A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2 n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.

SEMICONDUCTOR DEVICE

A semiconductor device includes a central processing unit capable of executing a vector instruction. The vector instruction is an instruction to calculate a vector register for every element, combine the additional information based on the calculated result for every element, shift the contents of a register different from the vector register to right or left, insert the combined additional information in an empty portion resulting from the shift, and accumulate the additional information in the register. 1. A semiconductor device comprising a data processor capable of executing a vector instruction ,wherein the data processor includes a first and a second vector registers, and a general register or an exclusive register,wherein the vector instruction is an instruction to calculate contents of the first vector register and contents of the second vector register for every element, combine additional information based on the calculated result for every element, shift contents of the general register or the exclusive register to right or left, insert the combined additional information in an empty portion resulting from the shift, and accumulate the additional information in the general register or the exclusive register.2. The device according to claim 1 ,wherein each of the first and second vector registers is capable of storing N pieces of elements, andwherein the data processor is capable of executing an operation for the N pieces of the elements in parallel and generates N pieces of additional information.3. The device according to claim 2 ,wherein the vector instruction is an instruction to compare the contents of the first vector register and the contents of the second vector register with each other, andwherein the additional information is a flag based on the comparison result; in case of agreement with a comparison condition, 1 or 0, while in case of disagreement with the comparison condition, 0 or 1.4. The device according to claim 3 ,wherein the vector ...

HONORING HARDWARE ENTITLEMENT OF A HARDWARE THREAD

A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition. 1. A method comprising:associating a logical partition in a set of logical partitions to an entitlement special purpose register in a set of entitlement special purpose registers, wherein the logical partition does not time-share the entitlement special purpose register;determining an entitlement processor resource percentage for the logical partition; andsetting an entitlement special purpose register percentage for the entitlement special purpose register equal to the entitlement processor resource percentage; 'at least determining the entitlement processor resource percentage for the logical partition is performed by computer software running on computer hardware.', 'wherein2. The method of claim 1 , wherein the entitlement processor resource percentage is a percentage of an execution capacity of the set of logical partitions.3. The method of claim 1 , wherein the entitlement processor resource percentage is pre-defined.4. The method of claim 1 , wherein setting the entitlement special purpose register percentage for the entitlement special purpose register equal to the entitlement processor resource percentage includes:linking the entitlement processor resource percentage with the entitlement special purpose register percentage to dedicate the logical partition to the register.5. The method of ...

Method and Apparatus for Data Communication in Virtualized Environment, and Processor

A method for data communication in a virtualized environment is disclosed as follows. A write function of a graphics driver is called by a graphics processing program using a graphics processing interface, where a function in a call process is recorded in a function stack; an entry address of a write function of the graphics processing interface is determined according to an entry address of the write function of the graphics driver and a quantity of layers of the function stack, and an offset and a length that are of a vertex buffer of the graphics processing program are read from the entry address of the write function of the graphics processing interface, so as to determine a data area that is modified by the graphics processing program and is in the vertex buffer, where the modified data area is data necessary for graphics rendering.

Predication Methods for Vector Processors

A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.

SEMICONDUCTOR DEVICE

A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor. 1. A semiconductor device , comprising:a first processor comprising a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; anda second processor comprising a second register, the second processor configured to perform arithmetic calculations using the second register, wherein the first register is shared with the second processor, and the second register is shared with the first processor.2. The semiconductor device of claim 1 , wherein the first processor and the second processor share a same instruction set architecture (ISA).3. The semiconductor device of claim 1 , wherein the first register comprises at least one of an image register (IR) claim 1 , a coefficient register (CR) and an output register (OR).4. The semiconductor device of claim 1 , wherein the second register comprises at least one of a scalar register (SR) and a vector register (VR).5. The semiconductor device of claim 1 , wherein the first processor and the second processor are driven by respective independent power supplies.6. The semiconductor device of claim 5 , wherein a power supply from among the respective independent power supplies of an unused one of the first and second processors is cut off.7. The semiconductor device of claim 1 , wherein the first processor is configured to perform at least one of one-dimensional filter calculations claim 1 , two-dimensional filter calculations claim 1 , census transform calculations claim 1 , min/max filter calculations claim 1 , sum of absolute ...

TECHNIQUES TO ENFORCE POLICIES FOR COMPUTING PLATFORM RESOURCES

Various embodiments are generally directed to techniques to enforce policies for computing platform resources, such as to prevent denial of service (DoS) attacks on the computing platform resources. Some embodiments are particularly directed to ISA instructions that allow trusted software/applications to securely enforce policies on a platform resource/device while allowing untrusted software to control allocation of the platform resource. In many embodiments, the ISA instructions may enable secure communication between a trusted application and a platform resource. In several embodiments, a first ISA instruction implemented by microcode may enable a trusted application to wrap policy information for secure transmission through an untrusted stack. In several such embodiments, a second ISA instruction implemented by microcode may enable untrusted software to verify the validity of the wrapped blobs and program registers associated with the platform resource with policy information provided via the wrapped blobs. 1. An apparatus , comprising:a processor; and receive a plurality of wrapped policy blobs; and', 'send a configuration command to a trusted computing base, the command to cause the trusted computing base to program, based in part on the wrapped policy blobs, one or more policy registers to allow access to platform resources by the untrusted system instructions., 'a memory comprising untrusted system instructions, which when executed by the processor cause the processor to2. The apparatus of claim 1 , wherein the command to further cause the trusted computing base to set a lock bit associated with the platform resource to allow access to the platform resources by the untrusted system instructions.3. The apparatus of claim 2 , the untrusted system instructions claim 2 , when executed by the processor cause the processor to:store at least one of the wrapped policy blobs in a general purpose register accessible by the trusted computing base; andadd an indication ...

Programmable State Machine Controller in a Parallel Processing System

Method and system are disclosed for a programmable state machine controller in a parallel processing system. The programmable state machine controller includes a set of control registers configured to serve a set of application specific engines; a set of task engines configured to access a plurality of application resources in parallel; one or more processors configured to: receive multiple requests from the set of application specific engines, determine availability of the set of task engines and the plurality of application resources being requested, assign the set of task engines to serve the set of application specific engines based on the availability of the set of task engines and the availability of the plurality of application resources being requested, and serve the multiple requests from the set of application specific engines in parallel. 1. A programmable state machine controller in a parallel processing system , comprising:a set of control registers, wherein each register in the set of control registers is configured to serve a corresponding application specific engine in a set of application specific engines;a set of task engines, wherein the set of task engines are configured to access a plurality of application resources in parallel;one or more processors configured to:receive multiple requests from the set of application specific engines for accessing the plurality of application resources;determine availability of the set of task engines;determine availability of the plurality of application resources being requested;assign the set of task engines to serve the set of application specific engines based on the availability of the set of task engines and the availability of the plurality of application resources being requested; andserve the multiple requests from the set of application specific engines in parallel using the set of task engines and the set of control registers that correspond to the multiple requests of the set of application specific ...

Reset and replay of memory sub-system controller in a memory sub-system

In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component.

RANDOM TAG SETTING INSTRUCTION FOR A TAG-GUARDED MEMORY SYSTEM

An apparatus has processing circuitry (); memory access circuitry () to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and an instruction decoder () responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry () to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values. 1. An apparatus comprising:processing circuitry;memory access circuitry to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; andan instruction decoder responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values.2. The apparatus according to claim 1 , in which claim 1 , in response to the random tag setting instruction claim 1 , the instruction decoder is configured to control the processing circuitry to prevent at least one excluded value of the set of candidate tag values from being selected as the random tag value claim 1 , and to randomly select the random tag value from a remaining subset of the candidate tag values.3. The apparatus according to claim 2 , in which the at least one excluded tag value includes one or more excluded tag values identified by at least one register specified by the random tag ...

THROTTLING OF COMPONENTS USING PRIORITY ORDERING

An apparatus is provided, where the apparatus includes a plurality of components, wherein an individual component has a corresponding throttling priority of a plurality of throttling priorities. The apparatus further includes logic to selectively throttle one or more of the plurality of components. In an example, an order in which the one or more of the plurality of components are to be throttled may be based on the plurality of throttling priorities. 1. (canceled)2. An apparatus comprising:a plurality of components;a first logic to assign, based on an input provided by an operating system (OS) of the apparatus, respective throttling priorities of a plurality of throttling priorities to respective ones of the plurality of components; andsecond logic to throttle, based on a throttling priority of a component of the plurality of components, the component.3. The apparatus of claim 2 , wherein an order in which the component is to be throttled with respect to a second component of the plurality of components is based on a throttling priority of the component and a throttling priority of the second component.4. The apparatus of claim 3 , wherein the throttling priority of the second component is lower than the throttling priority of the component; andwherein the second logic is to throttle, based on the throttling priorities of the component and the second component, the component prior to throttling of the second component.5. The apparatus of claim 2 , wherein the input is provided to the first priority by a register of the OS.6. The apparatus of claim 5 , wherein the input is related to a 3-bit value of the register.7. The apparatus of claim 5 , wherein the register is to store respective indications of respective throttling priorities of the plurality of throttling priorities as respective 3-bit values.8. The apparatus of claim 2 , wherein the second logic is to throttle the component through reduction of a frequency or voltage of the component.9. One or more non- ...

Techniques For Metadata Processing

Techniques are described for metadata processing that can be used to encode an arbitrary number of security policies for code running on a processor. Metadata may be added to every word in the system and a metadata processing unit may be used that works in parallel with data flow to enforce an arbitrary set of policies. In one aspect, the metadata may be characterized as unbounded and software programmable to be applicable to a wide range of metadata processing policies. Techniques and policies have a wide range of uses including, for example, safety, security, and synchronization. Additionally, described are aspects and techniques in connection with metadata processing in an embodiment based on the RISC-V architecture. 1. A method of processing instructions comprising:establishing a metadata processing domain that is separated and isolated from an associated instruction processing domain;establishing at least one control/status register (CSR) configured to facilitate an exchange of information between the metadata processing domain and the instruction processing domain;receiving from the instruction processing domain, for metadata processing, a current instruction with an associated metadata tag, the metadata processing being performed in the metadata processing domain;determining, in the metadata processing domain and in accordance with the current instruction and metadata tags associated with the current instruction, whether a rule exists in a rule cache for the current instruction, the rule cache including rules on metadata used by said metadata processing to define allowed operations; andresponsive to determining that no rule exists in the rule cache for the current instruction, performing rule cache miss processing in the metadata processing domain, wherein the rule cache miss processing includes performing first rule cache miss processing for a first set of one or more rules using a rule cache miss handler, the rule cache miss handler generating at least one ...

HISTOGRAM OPERATION

A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram. 1. A processor comprising:a cache configured to store a set of tables; and receive an instruction that specifies the first register and the set of tables; and', 'based on the instruction, for each index in the set of indices, increment the respective value stored in the respective table of the set of tables., 'a set of registers that includes a first register configured to store a set of indices each corresponding to a respective value stored in a respective table of the set of tables, wherein the processor is configured to2. The processor of claim 1 , wherein the set of indices includes a first index corresponding to a first value stored in a first table of the set of tables and a second index corresponding to a second value stored in a second table of the set of tables that is different from the first table.3. The processor of claim 1 , wherein:the set of tables includes a plurality of tables;the set of indices includes a plurality of indices; andthe processor is configured to, based on the instruction, increment a plurality of values stored in the plurality of tables associated with the plurality of indices.4. The processor of ...

PERFORMING AN OPERATION ABSENT HOST INTERVENTION

Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. 1. A computer-implemented method of executing an instruction in a computing environment , the computer-implemented method comprising:obtaining a perform frame management function (PFMF) instruction; and 'performing, absent host intervention, a frame management operation on a guest frame, the guest frame being non-resident in host memory, and the frame management operation being determined based on a control of a plurality of controls associated with the PFMF instruction to be used in frame management.', 'executing, by a pageable guest of the computing environment, the obtained PFMF instruction, the executing comprising2. The computer-implemented method of claim 1 , wherein the frame management operation is indicated using a field of the PFMF instruction.3. The computer-implemented method of claim 2 , wherein the field of the PFMF instruction specifies a register claim 2 , and the register includes the control specifying the frame management operation.4. The computer-implemented method of claim 1 , wherein an address of the guest frame is indicated using a field of the PFMF instruction.5. The computer-implemented method of claim 4 , wherein the field of the PFMF instruction specifies a register claim 4 , and the register includes the address of the guest frame.6. The computer-implemented method of claim 1 , wherein the PFMF instruction has further associated therewith a usage indicator to be used with at least one control of the plurality of controls.7. The computer-implemented method of claim 6 , wherein the usage indicator is specified using a field of the PFMF instruction.8. The computer-implemented method of claim 7 , wherein the field of ...

MEMORY DEVICE TEST MODE ACCESS

A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation. 1. A system , comprising:a memory device;a processing device coupled to the memory device and configured to switch an operating mode of the memory device between a test mode and a non-test mode; anda test mode access component, the test mode access component configured to access the memory device while the memory device is in the test mode to perform a test mode operation.2. The system of claim 1 , wherein the system comprises an interface through which the processing device is configured to communicate with the memory device via signaling in accordance with a particular protocol claim 1 , and through which the test mode access component is configured to communicate with the memory device.3. The system of claim 2 , wherein the system comprises a storage subsystem claim 2 , and wherein the storage subsystem includes a controller comprising the processing device and the test mode access component.4. The system of claim 2 , wherein the test mode operation is a fuse identification (FID) read operation.5. The system of claim 2 , wherein signaling between the test mode access component and the interface is non-compliant with the particular protocol.6. The system of claim 5 , wherein the particular protocol is a double data rate (DDR) JEDEC standard protocol.7. The system of claim 1 , wherein the test mode access component is configured to cause claim 1 , via the signal claim 1 , the memory device to program a register of the memory device to access the memory device.8. The system of claim 7 , wherein the register comprises a mode register.9. A method claim 7 , comprising:performing, ...

DIGITAL FINGERPRINT GENERATION CIRCUIT, GENERATION METHOD AND ELECTRONIC DEVICE

Embodiments of the present disclosure provide a circuit and a method for digital fingerprint generation, and an electronic device. The digital fingerprint generation method includes inputting an input signal from outside; generating a frequency relationship indication signal between an input signal and a feedback signal; generating a frequency control signal based on the frequency relationship indication signal; generating an intermediate signal based on a frequency control signal and pulse signals; dividing the intermediate signal in frequency to generate the feedback signal; and generating a digital fingerprint based on the input signal and the feedback signal. 1. A digital fingerprint generation circuit , comprising:a pulse generation sub-circuit configured to generate a plurality of pulse signals;a digital control oscillator sub-circuit configured to generate an intermediate signal based on a frequency control signal and the plurality of pulse signals;a frequency dividing sub-circuit configured to divide the intermediate signal in frequency to generate a feedback signal;a frequency and phase detection sub-circuit configured to generate a digital fingerprint based on an input signal and the feedback signal, and further configured to generate a frequency relationship indication signal between the input signal and the feedback signal; anda control sub-circuit configured to generate the frequency control signal based on the frequency relationship indication signal.2. The digital fingerprint generation circuit according to claim 1 , wherein the frequency and phase detection sub-circuit is further configured to generate the frequency relationship indication signal by generating a phase relationship indication signal between the input signal and the feedback signal.3. The digital fingerprint generation circuit according to claim 1 , wherein the pulse generation sub-circuit is a ring oscillator comprising a NAND gate.4. The digital fingerprint generation circuit ...

CIRCUITRY AND METHOD

Circuitry comprises an instruction decoder to decode a gather load instruction having a vector operand comprising a plurality of vector entries, in which each vector entry defines, at least in part, a respective address from which data is to be loaded; the instruction decoder being configured to generate a set of load operations relating to respective individual addresses in dependence upon the vector operand, each of the set of load operations having a respective identifier which is unique with respect to other load operations in the set, and control circuitry to maintain a data item for the gather load instruction, the data item including a count value representing a number of load operations in the set of load operations awaiting issue for execution; and execution circuitry to execute the set of load operations; the control circuitry being configured, in response to a detection from the count value of the data item associated with a given gather load instruction that the set of load operations generated for the given gather load instruction has reached a predetermined stage relative to execution of all of that set of load operations, to control handling of a consumer instruction, being an instruction which depends upon the completion of the given gather load instruction. 1. Circuitry comprising:an instruction decoder to decode a gather load instruction having a vector operand comprising a plurality of vector entries, in which each vector entry defines, at least in part, a respective address from which data is to be loaded;the instruction decoder being configured to generate a set of load operations relating to respective individual addresses in dependence upon the vector operand, each of the set of load operations having a respective identifier which is unique with respect to other load operations in the set,control circuitry to maintain a data item for the gather load instruction, the data item including a count value representing a number of load operations in ...

METHOD OF CONSTRUCTING A UEFI BOOTLOADER HANDOFF ADDRESS SPACE FOR A PHYSICAL MACHINE HOSTING VIRTUAL MACHINES

A method of creating a new page table structure after first stage boot operations has completed but before handoff to a hypervisor occurs. Firmware page tables are reused and copied to a region of memory by a first-stage bootloader while the firmware is running, processed to have an expected multi-stage page table structure and desired access rights, and copied again to another region of memory by the first-stage bootloader after the first-stage bootloader has completed its booting operations and after the firmware has been quiesced. 1. A method for booting a machine , the method comprising:executing boot firmware, which hands off control to a first-stage bootloader;executing first-stage bootloader operations using page tables set up by the boot firmware;after completion of the first-stage bootloader operations but prior to handing off control of the machine to a second-stage bootloader, moving the firmware page tables from a first address region in memory to a second address region in the memory;creating an updated set of page tables in the second region of the memory by modifying a hierarchical structure of the firmware page tables to have an expected number of page table levels; andmodifying page table entries in each page table of the updated set of page tables such that each page table entry is accessible by a system software kernel when control of the machine is handed off from the second stage bootloader to the system software kernel.2. The method of claim 1 , further comprising:allocating a third region in the memory for storing the updated set of pages tables by the first-stage bootloader.3. The method of claim 2 , further comprising:after completion of the boot operations by the first-stage bootloader, handing off control of from the second-stage bootloader to the system software kernel.4. The method of claim 3 , wherein handing off control of the machine by the first-stage bootloader to the UFI second-stage bootloader comprises ceasing any executable ...

VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED PERFORMANCE

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request. 1. An integrated circuit device comprising:a set of processor interfaces;a data path configured to couple the set of processor interfaces to a shared resource; receive a set of requests via the set of processor interfaces;', 'select a first request from among the set of requests for service over the data path;', 'receive a subsequent request after the set of requests is received;', 'select a second request from among the first request and the subsequent request for service over the data path; and', 'cause the data path to service the second request., 'an arbiter circuit coupled to the set of processor interfaces and the data path and configured to2. The integrated circuit device of claim 1 , wherein the arbiter circuit is configured to select the first request based on a first set of criteria and select the second request based on a second set of criteria that is different from the first set of criteria.3. The integrated circuit device of claim 2 , wherein the arbiter circuit is configured to select the first request based on the first set of criteria by:determining a respective credit cost for each ...

Data processing system and operating method thereof

A data processing system may include a memory apparatus and a controller configured to control the memory apparatus. The memory apparatus includes a plurality of pages and is accessible in units of the pages. The controller may include a mode control component configured to generate an activation mode control signal for setting the memory apparatus in a partial page activation mode based on a type of a processing task requested by a host and address information requested to be accessed, and wherein less than all of a page of the memory apparatus being accessed is activated when the memory apparatus is in the partial page activation mode.

HYPERVISOR-BASED REDIRECTION OF SYSTEM CALLS AND INTERRUPT-BASED TASK OFFLOADING

A security agent configured to initiate a security agent component as a hypervisor for a computing device is described herein. The security agent component may change a value of a processor configuration register, such as a Model Specific Register (MSR), in order to cause system calls to be redirected to the security agent, and may set an intercept for instructions for performing read operations on the processor configuration register so that a process, thread, or component different from the processor of the computing device may receive the original value of the processor configuration register instead of an updated value of the processor configuration register. The security agent component may also be configured to generate interrupts to offload task execution from the hypervisor to a security agent executing as a kernel-level component. 1. A computer-implemented method comprising:changing, by a security agent component executing in a hypervisor of a computing device, a value of a processor configuration register of a processor of the computing device from an original value to an updated value that causes system calls to be received by a security agent executing in kernel mode of the computing device; andreceiving a system call by the security agent after the changing of the value of the processor configuration register.2. The computer-implemented method of claim 1 , further comprising:setting, by the security agent component, an intercept for instructions for performing read operations on the processor configuration register;noting, by the security agent component and after the setting of the intercept, a read operation from a process, a thread, or a component that is different from the processor and is attempting to read the value of the processor configuration register; andin response to the noting of the read operation, returning, by the security agent component, the original value to the process, the thread, or the component that is different from the ...

MEMORY DEVICE AND A METHOD OF OPERATING THE SAME

A memory device in accordance with a described method of operation includes a read only memory (ROM) address controller and a suspend signal generator. The ROM address controller is configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and to suspend output of the plurality of operation ROM addresses in response to a suspend signal. The suspend signal generator is configured to generate the suspend signal that is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output. The suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored. 1. A memory device , comprising:a read only memory (ROM) address controller configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and configured to suspend output of the plurality of operation ROM addresses in response to a suspend signal; and wherein the suspend signal is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output, and', 'wherein the suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored., 'a suspend signal generator configured to generate the suspend signal,'}2. The memory device according to claim 1 , further comprising:a register configured to, in response to a test command, store a time code indicating the preset period and store a ROM address code indicating the suspend ROM address; anda ROM address decoder configured to provide the suspend ROM address obtained by decoding the ROM address code to the suspend signal generator.3. ...

APPARATUS WITH REDUCED HARDWARE REGISTER SET

An apparatus comprises processing circuitry for processing program instructions according to a predetermined architecture defining a number of architectural registers accessible in response to the program instructions. A set of hardware registers is provided in hardware. A storage capacity of the set of hardware registers is insufficient for storing all the data associated with the architectural registers of the pre-determined architecture. Control circuitry is responsive to the program instructions to transfer data between the hardware registers and at least one register emulating memory location in memory for storing data corresponding to the architectural registers of the architecture. 1. An apparatus comprising:processing circuitry to process program instructions in accordance with a predetermined architecture defining a plurality of architectural registers accessible in response to the program instructions; anda set of hardware registers, wherein a storage capacity of the set of hardware registers is insufficient for storing data associated with all of the plurality of architectural registers of the predetermined architecture; andcontrol circuitry responsive to the program instructions to transfer data between the set of hardware registers and at least one register emulating memory location in memory for storing data corresponding to at least one of the plurality of architectural registers of the predetermined architecture.2. The apparatus according to claim 1 , wherein in response to a program instruction specifying at least one source architectural register for storing at least one operand value to be processed in response to the program instruction claim 1 , the control circuitry is configured to trigger a read operation to read the at least one operand value from a register emulating memory location corresponding to said at least one source architectural register and to store the at least one operand value in at least one register of said set of hardware ...

APPARATUS AND METHOD FOR TRANSFERRING A PLURALITY OF DATA STRUCTURES BETWEEN MEMORY AND A PLURALITY OF VECTOR REGISTERS

An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory. Decode circuitry is responsive to a single access instruction identifying a plurality of vector registers and a plurality of data structures that are located discontiguously with respect to each other in the memory, to generate control signals to control the access circuitry to perform a sequence of access operations to move the plurality of data structures between the memory and the plurality of vector registers such that the vector operand in each vector register holds a corresponding data element from each of the plurality of data structures. This provides a very efficient mechanism for performing complex access operations, resulting in an increase in execution speed, and potential reductions in power consumption. 1. An apparatus comprising:a set of vector registers, each vector register arranged to store a vector operand comprising a plurality of data elements;access circuitry to perform access operations to move data elements of vector operands between data structures in memory and said set of vector registers, each data structure comprising multiple data elements stored at contiguous addresses in said memory;decode circuitry, responsive to a single access instruction identifying a plurality of vector registers from said set and a plurality of data structures that are located discontiguously with respect to each other in said memory, to generate control signals to control the access circuitry to perform a sequence of said access operations to move said plurality of ...

TRANSACTIONAL REGISTER FILE FOR A PROCESSOR

Technology related to register files for block-based processor architectures is disclosed. In one example of the disclosed technology, a processor core including a transactional register file and an execution unit can be used to execute an instruction block. The transactional register file can include a plurality of registers, where each register includes a previous value field and a next value field. The previous value field can be updated when a register-write message is received and the processor core is in a first state. The next value field can be updated when a register-write message is received and the processor core is in a second state. The execution unit can execute instructions of the instruction block. The execution unit can be configured to read register values from the previous value field and to cause register-write messages to be transmitted from the processor core when executing instructions that write to the registers. 1. A block-based processor core for executing an instruction block , the processor core comprising:a transactional register file comprising a plurality of registers, each register including a previous value field and a next value field, the previous value field for storing a value corresponding to a state before execution of the instruction block on the processor core, the next value field for storing a value corresponding to a state after execution of the instruction block on the processor core, the next value field being updated when a register-write message is received and the processor core is executing non-speculatively, and the previous value field being updated when a register-write message is received and the processor core is executing speculatively; andan execution unit configured to execute instructions of the instruction block, the execution unit configured to read register values from the previous value field of the transactional register file and to cause register-write messages to be transmitted from the processor core ...

Predicting a table of contents pointer value responsive to branching to a subroutine

Predicting a Table of Contents (TOC) pointer value responsive to branching to a subroutine. A subroutine is called from a calling module executing on a processor. Based on calling the subroutine, a value of a pointer to a reference data structure, such as a TOC, is predicted. The predicting is performed prior to executing a sequence of one or more instructions in the subroutine to compute the value. The value that is predicted is used to access the reference data structure to obtain a variable value for a variable of the subroutine.

PROGRAMMABLE BROADCAST ADDRESS

A method for initializing functional blocks on an electronic chip includes writing a programmable broadcast address to one or more functional blocks in a broadcast group; setting the one or more functional blocks in the broadcast group to a broadcast enable mode; writing one or more transactions to the programmable broadcast address; and disabling the broadcast enable mode. 1. A method for initializing functional blocks on an electronic chip , comprising:writing a programmable broadcast address to one or more functional blocks in a broadcast group;setting the one or more functional blocks in the broadcast group to a broadcast enable mode; andwriting one or more transactions to the programmable broadcast address.2. The method of claim 1 , further comprising identifying two or more functional blocks that share at least a subset of control status register (“CSR”) definitions.3. The method of claim 2 , further comprising placing the two or more functional blocks in the broadcast group.4. The method of claim 1 , further comprising selecting claim 1 , from a memory location claim 1 , the programmable broadcast address for the broadcast group.5. The method of claim 1 , further comprising generating the programmable broadcast address for the broadcast group.6. The method of claim 1 , wherein setting the functional blocks in the broadcast group to the broadcast enable mode comprises writing a broadcast mode bit to each functional block in the broadcast group.7. The method of claim 1 , wherein writing a programmable broadcast address to one or more functional blocks in a broadcast group comprises writing the programmable broadcast address to the unique address for at least one of the functional blocks in the broadcast group.8. The method of claim 1 , further comprising disabling the broadcast enable mode claim 1 , wherein disabling the broadcast enable mode comprises clearing the broadcast mode bit in each functional block in the broadcast group.9. The method of claim 1 , ...

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM

An information processing device according to the present invention includes: a storage unit that stores a first unique value calculated for each portion of a program in advance; and an inspection unit that inspects whether or not there is a tampering in the portion by newly calculating a second unique value for the portion and comparing the first unique value with the second unique value. 1. An information processing device comprising:a storage unit that stores a first unique value calculated for each portion of a program in advance; andan inspection unit that inspects whether or not there is a tampering in the portion by newly calculating a second unique value for the portion and comparing the first unique value with the second unique value.2. The information processing device according to claim 1 ,wherein the storage unit stores a caller of the portion, a memory address of the portion in a storage region of the program, and the first unique value in association with each other for each the portion of the program, andthe information processing device further comprising a specifying unit that specifies the portion inspected by the inspection unit based on the caller.3. The information processing device according to claim 2 , wherein the specifying unit specifies the portion having a call relationship directly and indirectly with the caller.4. The information processing device according to claim 2 ,wherein the caller includes I/O, API that uses the I/O, and a function that realizes a function of the API, andwherein the I/O calls the API, the API calls the function, and the function calls the same or a different function as the portion.5. The information processing device according to claim 4 ,wherein the storage unit stores a combination of an identifier of the I/O and a message input at a time of a call from the I/O in association with an identifier of the API, andwherein the specifying unit references the storage unit based on a combination of an identifier of the ...

PAIRED VALUE COMPARISON FOR REDUNDANT MULTI-THREADING OPERATIONS

Techniques for performing redundant multi-threading (“RMT”) include the use of an RMT compare instruction by two program instances (“work-items”). The RMT compare instruction specifies a value from each work-item to be compared. Upon executing the RMT compare instructions, the work-items transmit the values to a hardware comparator unit. The hardware comparator unit compares the received values and performs an error action if the values do not match. The error action may include sending an error code in a return value back to the work-items that requested the comparison or emitting a trap signal. Optionally, the work-items also send addresses for comparison to the comparator unit. If the addresses and values match, then the comparator stores the value at the specified address. If either or both of the values or the addresses do not match, then the comparator performs an error action. 1. A system for detecting processing discrepancies , the system comprising:a first execution unit configured to execute a first program that includes a first compare instruction specifying a first value to be compared and a first pairing value;a second execution unit configured to execute a second program that includes a second compare instruction specifying a second value to be compared and a second pairing value that is identical to the first pairing value; and responsive to the first pairing value being equal to the second pairing value, compare the first value to the second value, and', 'perform a resulting action in response to the comparison, the resulting action being dependent on whether the first value is identical to the second value and indicating whether a processing discrepancy has occurred., 'a comparator configured to2. The system of claim 1 , wherein:the first instruction specifies the first value by referring to a first register assigned to the first program and the second instruction specifies the second value by referring to a second register assigned to the second ...

Instructions and logic to provide simd sm4 cryptographic block cipher functionality

Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

INDIRECT CHAINING OF COMMAND BUFFERS

Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer. 1. An apparatus comprising:a data structure comprising a plurality of entries that identify a plurality of command buffers to be processed in order; and receive a first packet comprising an address;', identify a location of the data structure using the address in the first packet;', 'process a first command buffer of the plurality of command buffers identified by a first address retrieved from a first entry of the data structure;', 'retrieve a second address from a second entry of the data structure using an address in the first command buffer;', 'process, after the first command buffer has been processed, a second command buffer of the plurality of command buffers identified by the second address; and', 'cause one or more pixels to be driven to a display, wherein the one or more pixels are generated based on processing of the plurality of command buffers., 'responsive to an indirect chaining mode indication], 'a command processor configured to2. The apparatus as recited in claim 1 , wherein at least one command buffer is referenced two or more times by two or more entries of the ...

THROTTLING OF COMPONENTS USING PRIORITY ORDERING

An apparatus is provided, where the apparatus includes a plurality of components, wherein an individual component has a corresponding throttling priority of a plurality of throttling priorities. The apparatus further includes logic to selectively throttle one or more of the plurality of components. In an example, an order in which the one or more of the plurality of components are to be throttled may be based on the plurality of throttling priorities. 1. An apparatus comprising:a plurality of components, wherein an individual component has a corresponding throttling priority of a plurality of throttling priorities; anda logic to receive one or more parameters indicative of the plurality of throttling priorities, and to selectively throttle one or more of the plurality of components,wherein an order in which the one or more of the plurality of components are to be throttled is based on the plurality of throttling priorities.2. The apparatus of claim 1 , wherein:a first component of the plurality of components has a first throttling priority;a second component of the plurality of components has a second throttling priority that is lower than the first throttling priority; andthe logic is to throttle the first component prior to the second component, in response to the second throttling priority being lower than the first throttling priority.3. The apparatus of claim 1 , wherein:the logic is to order the plurality of components in a first order, based on an order of the corresponding plurality of throttling priorities; andthe one or more of the plurality of components are to be throttled in the first order.4. The apparatus of claim 3 , wherein:the first order corresponds to a descending order of the plurality of throttling priorities.5. The apparatus of claim 3 , wherein:the logic is to un-throttle the one or more of the plurality of components in a second order that is opposite of the first order.6. The apparatus of claim 1 , wherein the logic is a first logic claim 1 ...

ENUMERATED PER DEVICE ADDRESSABILITY FOR MEMORY SUBSYSTEMS

A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command. 1. A dynamic random access memory (DRAM) device comprising:a hardware interface to couple to a command bus;a hardware interface to couple to a data bus; anda mode register to store a value to indicate an assigned enumeration identifier (ID), wherein the DRAM device is to receive one or more per-device addressability (PDA) commands via the command bus without a signal via the data bus based on the enumeration ID, wherein the PDA commands include an assigned enumeration ID, and the DRAM device is to process only PDA commands with the assigned enumeration ID to make changes to a configuration setting.2. The DRAM device of claim 1 , wherein the DRAM device is to store a value to indicate whether a PDA enumeration mode of the DRAM device is enabled claim 1 , wherein in the PDA enumeration mode claim 1 , the DRAM device is to receive an enumeration ID command via the command bus in conjunction with a signal via the data bus to assign the enumeration ID.30. The DRAM device of claim 2 , wherein in PDA enumeration mode the DRAM device is to receive the enumeration ID ...

SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS

Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address, and execution circuitry to execute the decoded instruction to store configuration information about usage of storage for two-dimensional data structures at the memory address. 1. An apparatus comprising:decode circuitry to decode an instruction having an opcode and a memory location;execution circuitry to execute the decoded instruction to retrieve configuration information about usage of storage for two-dimensional data structures and store the retrieved configuration information as description data at the memory location.2. The apparatus of claim 1 , wherein the storage is a plurality of packed data registers and the two-dimensional data structures are overlaid on the plurality of packed data registers.3. The apparatus of claim 1 , wherein the storage is a plurality of packed data registers and memory claim 1 , and the two-dimensional data structures are overlaid on the plurality of packed data registers and memory.4. The apparatus of claim 1 , wherein the memory location is stored in a scale-index-base format.5. The apparatus of claim 1 , wherein the description data comprises: 1) an index into a table which is to store a number of bytes in a two-dimensional data structure claim 1 , and bytes per row of the two-dimensional data structure; 2) restart information used in two-dimensional data structure operations; and 3) indications of a number of rows and columns per two-dimensional data structure.6. The apparatus of claim 5 , wherein the description data is to further comprise an indication of pairs two-dimensional data structures.7. The apparatus of claim 1 , wherein the description data is retrieved from at least one register of the apparatus.8. A method comprising:decoding an instruction having an opcode and a memory location;executing the decoded instruction to retrieve configuration ...

APPARATUS AND METHOD FOR A HYBRID CLASSICAL-QUANTUM PROCESSOR

A hybrid classical-quantum processor is described. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate decoded quantum instructions and non-quantum instruction decode circuitry to decode non-quantum instructions to generate decoded non-quantum instructions; execution circuitry including a first plurality of functional units to execute the decoded quantum instructions and a second plurality of functional units to execute the decoded non-quantum instructions; a shared register file shared by the first plurality of functional units and the second plurality of functional units, the shared register file to store operands used for execution of the decoded quantum instructions and decoded non-quantum instructions; and a classical-quantum (C-Q) interface to couple the execution circuitry to a quantum processor, the C-Q interface comprising digital-to-analog circuitry to generate analog signals to manipulate a current state of one or more quantum bits (qubits) of the quantum processor in response to execution of the decoded quantum instructions. 1. A processor comprising:a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate decoded quantum instructions and non-quantum instruction decode circuitry to decode non-quantum instructions to generate decoded non-quantum instructions;execution circuitry including a first plurality of functional units to execute the decoded quantum instructions and a second plurality of functional units to execute the decoded non-quantum instructions;a shared register file shared by the first plurality of functional units and the second plurality of functional units, the shared register file to store operands used for execution of the decoded quantum instructions and decoded non-quantum instructions; anda classical-quantum (C-Q) interface to couple the execution circuitry to a quantum processor, the C-Q ...

Apparatus and method for scalable qubit addressing

An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.

APPARATUS AND METHOD FOR INJECTED SPIN ECHO IN A QUANTUM PROCESSOR

Apparatus and method for injected spin echo sequences in a quantum processor. For example, one embodiment of a processor comprises a decoder to decode quantum instructions to generate quantum microoperations (uops) and non-quantum instructions to generate non-quantum uops; execution circuitry to execute the quantum uops and non-quantum uops; a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions; wherein the decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist and if the one or more corrective uops exist, then to submit the one or more corrective uops for execution by the execution circuitry. 1. A processor comprising:a decoder to decode quantum instructions to generate quantum microoperations (uops) and non-quantum instructions to generate non-quantum uops;execution circuitry to execute the quantum uops and non-quantum uops;a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions;wherein the decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist and if the one or more corrective uops exist, then to submit the one or more corrective uops for execution by the execution circuitry.2. The processor of wherein the corrective sequence data structure comprises a table having a plurality of entries claim 1 , wherein a first entry is to be identified for the first instruction.3. The processor of wherein each entry in the table specifies a set of one or more uops to implement a spin echo operation on an associated one or more qubits.4. The processor of wherein the corrective sequence data structure comprises microcode storage and the one or more corrective uops are encoded in microcode.5. The processor of wherein the first quantum ...

APPARATUS AND METHOD FOR ARBITRARY QUBIT ROTATION

Apparatus and method for arbitrary qubit rotation. For example, one embodiment of a processor comprises: a decoder to decode a quantum rotation instruction specifying an arbitrary rotation value for performing a rotation of a quantum bit (qubit); a storage to store data for a plurality of waveform shapes/pulses; execution circuitry to perform the rotation of the qubit, the execution circuitry to combine a subset of the plurality of waveform shapes/pulses to approximate the arbitrary rotation value; and a classical-quantum (C-Q) interface coupled to the execution circuitry and comprising digital-to-analog circuitry to generate analog signals to rotate the qubit based on the approximation of the rotation value. 1. A processor comprising:a decoder to decode a quantum rotation instruction specifying an arbitrary rotation value for performing a rotation of a quantum bit (qubit);a storage to store data for a plurality of waveform shapes/pulses;execution circuitry to perform the rotation of the qubit, the execution circuitry to combine a subset of the plurality of waveform shapes/pulses to approximate the arbitrary rotation value; anda classical-quantum (C-Q) interface coupled to the execution circuitry and comprising digital-to-analog circuitry to generate analog signals to rotate the qubit based on the approximation of the rotation value.2. The processor of wherein the plurality of waveforms shapes/pulses comprise N waveforms shapes/pulses comprising values π claim 1 , π/2 claim 1 , π/4 claim 1 , π/8 claim 1 , π/16 . . . π/2.3. The processor of wherein the execution circuitry is to perform a binary search operation to combine different subsets of the plurality of waveform shapes/pulses to identify a combination which results in an approximation closest to the arbitrary rotation value.4. The processor of further comprising:a first source register to store a first value uniquely identifying the qubit, the quantum rotation instruction having a first operand to identify the ...

Initializing a data structure for use in predicting table of contents pointer values

Initializing a data structure for use in predicting table of contents (TOC) pointer values. A request to load a module is obtained. Based on the loaded module, a pointer value for a reference data structure is determined. The pointer value is stored in a reference data structure tracking structure, and used to access a variable value for a variable of the module.

Universal floating-point instruction set architecture for computing directly with decimal character sequences and binary formats in any combination

A universal floating-point Instruction Set Architecture (ISA) implemented entirely in hardware. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 “H=20” in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls “gobs” of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware H=20 convertFromDecimalCharacter conversion operators.

PARALLEL UNION CONTROL DEVICE, PARALLEL UNION CONTROL METHOD, AND STORAGE MEDIUM

A parallel union control device includes: at least one memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause each of the plurality of arithmetic units included in an parallel computer including a vector register to: successively compare input elements of a pair of input sets to undergo union processing, the pair being stored in an input operand register in the vector register; select one of the input elements as an output element of an output set, based on a comparison result; and store the output element into an output operand register in the vector register; shift a pointer pointing to the input element; load the input sets into the input operand register from a memory; store the output sets into the memory from the output operand register; and determine whether union processing performed in parallel is ended. 1. A parallel union control device , comprising:at least one memory storing a set of instructions; andat least one processor configured to execute the set of instructions to perform union processing on pairs of input sets in parallel among the pairs, each of the input unit pairs being a sorted set; and', 'output sets each being stored sets, wherein, 'cause a parallel computer including a plurality of arithmetic units and a vector register tothe at least one processor is configured to execute the set of instructions to: successively compare input elements of a pair of input sets to undergo union processing, the pair being stored in an input operand register in the vector register;', 'select one of the input elements as an output element of an output set, based on a comparison result; and', 'store the output element into an output operand register in the vector register;, 'cause each of the plurality of arithmetic units toshift a pointer pointing to the input element;load the input sets into the input operand register from a memory;store the output sets into the memory from the output operand ...

REGISTER ACCESS

An example apparatus can include a memory device and a controller coupled to the memory device configured to receive a command including command information to access a register from a host device. The controller can grant access to the register in response to the controller determining the command is valid and/or deny access to the register in response to the controller determining the command is invalid. The controller can determine the command is valid by calculating an answer using a seed from the command in a formula and verifying the calculated answer matches an answer from the command. The command, once verified as valid, can allow the host device to access configuration registers and/or data registers. 1. An apparatus , comprising:a memory device; and receive a command including command information to access a register from a host device;', 'grant access to the register in response to the controller determining the command is valid; and', 'deny access to the register in response to the controller determining the command is invalid., 'a controller coupled to the memory device configured to2. The apparatus of claim 1 , wherein the controller is configured to determine the command is valid by calculating an answer using a seed from the command information in a formula and verifying the calculated answer matches an answer from the command.3. The apparatus of claim 1 , wherein the controller is configured to determine the command is invalid by calculating an answer using a seed from the command in a formula and determining the calculated answer is different than an answer from the command.4. The apparatus of claim 1 , wherein the controller is configured to write a response to the register indicating access to the register is granted in response to determining the command is valid.5. The apparatus of claim 1 , wherein the controller is configured to discard the command in response to determining the command is invalid.6. The apparatus of claim 1 , wherein the ...

HIGH PERFORMANCE RECOVERY FROM MISSPECULATION OF LOAD LATENCY

A load instruction, for loading a register among a set of registers, is scheduled. Associated with scheduling the load instruction, a register dependency vector, corresponding to the register, is set to a state identifying the load instruction. A consumer instruction is scheduled, having a set of operand register and a target register, the register being in the set of operand registers. A target register dependency vector, corresponding to the target register is set in the memory. Based at least in part on the register being in the set of operand registers, a value of the target register dependency vector identifies the load instruction. Optionally, upon receiving a cache miss notice associated with the load instruction, the target register dependency vector is retrieved. 1. A method for processor load latency misspeculation recovery , comprising:scheduling a consumer instruction which identifies an operand register and a target register; and retrieving from a memory a dependency vector, the dependency vector identifying a load instruction on which the operand register depends, and', 'setting in the memory a target register dependency vector, based on a logical operation on the dependency vector, the target register dependency vector indicating the target register depends on at least the load instruction on which the operand register depends., 'in association with scheduling the consumer instruction,'}2. The method of claim 1 , the operand register being a first operand register claim 1 , the dependency vector being a first dependency vector claim 1 , and the consumer instruction further identifying a second operand register claim 1 , the method further comprising:in association with scheduling the consumer instruction, also retrieving a second dependency vector, the second dependency vector identifying a load instruction on which the second operand register depends, the logical operation being a logical operation on the first dependency vector and on the second ...

TECHNIQUES TO ENFORCE POLICIES FOR COMPUTING PLATFORM RESOURCES

Various embodiments are generally directed to techniques to enforce policies for computing platform resources, such as to prevent denial of service (DoS) attacks on the computing platform resources. Some embodiments are particularly directed to ISA instructions that allow trusted software/applications to securely enforce policies on a platform resource/device while allowing untrusted software to control allocation of the platform resource. In many embodiments, the ISA instructions may enable secure communication between a trusted application and a platform resource. In several embodiments, a first ISA instruction implemented by microcode may enable a trusted application to wrap policy information for secure transmission through an untrusted stack. In several such embodiments, a second ISA instruction implemented by microcode may enable untrusted software to verify the validity of the wrapped blobs and program registers associated with the platform resource with policy information provided via the wrapped blobs. 1. An apparatus , the apparatus comprising:a processor; and generate a wrapped lock policy and a wrapped unlock policy with a first instruction set architecture (ISA) instruction implemented by microcode based on policy data provided by trusted software, wherein the wrapped lock policy includes a policy setting for a platform resource based on the policy data;', 'communicate the wrapped lock policy and the wrapped unlock policy to untrusted system software;', 'verify the wrapped lock policy and the wrapped unlock policy with a second ISA instruction implemented by microcode;', 'determine generation of the wrapped lock policy and the wrapped unlock policy are associated with a common owner identifier; and', 'store the policy setting in a policy register to program the platform resource for use by the trusted software with the second ISA instruction based on verification of the wrapped lock policy and the wrapped lock policy and determination the wrapped lock ...

VECTOR REGISTERS IMPLEMENTED IN MEMORY

Systems and methods related to implementing vector registers in memory. A memory system for implementing vector registers in memory can include an array of memory cells, where a plurality of rows in the array serve as a plurality of vector registers as defined by an instruction set architecture. The memory system for implementing vector registers in memory can also include a processing resource configured to, responsive to receiving a command to perform a particular vector operation on a particular vector register, access a particular row of the array serving as the particular register to perform the vector operation.

OBSOLETING VALUES STORED IN REGISTERS IN A PROCESSOR BASED ON PROCESSING OBSOLESCENT REGISTER-ENCODED INSTRUCTIONS

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

DISAGGREGATED MEMORY POOL ASSIGNMENT

Examples are disclosed that relate to a disaggregated memory pool. One example provides a memory system comprising a memory controller and memory attached to the memory controller and forming at least a portion of a disaggregated memory pool, the disaggregated memory pool including a plurality of slices that are each dynamically assigned to a respective compute node. The memory system is configured to receive a request to adjust an assignment of the memory pool to a requesting compute node, where the portion of the memory pool includes an unassigned slice that can satisfy the request, assign at least part of the unassigned portion to the requesting compute node, and where the portion of the memory pool does not include an unassigned slice that can satisfy the request, cause a request to be directed to another compute node to free at least one slice to the such compute node. 1. A memory system , comprising:a memory controller; andmemory attached to the memory controller and forming at least a portion of a disaggregated memory pool, the disaggregated memory pool including a plurality of slices that are each dynamically assigned to a respective one of two or more compute nodes, receive a request to adjust an assignment of the disaggregated memory pool to a requesting compute node;', 'responsive to determining that the portion of the disaggregated memory pool includes an unassigned slice that can satisfy the request, assign at least part of the unassigned portion to the requesting compute node; and', 'responsive to determining that the portion of the disaggregated memory pool does not include an unassigned slice that can satisfy the request, output a request to another compute node to free at least one slice of the plurality of slices assigned to such compute node., 'where the memory system is configured to2. The memory system of claim 1 , where an address range of the disaggregated memory pool is visible to each of the two or more compute nodes.3. The memory system of ...

METHOD, SYSTEM AND TERMINAL FOR RECORDING ERROR INFORMATION OF BASIC INPUT OUTPUT SYSTEM BASED ON GPNV

The present disclosure provides a method for recording error information of a basic input output system based on general purpose non volatile (GPNV), which is applied to a basic input output system. The method includes the following: obtaining error information and a type of the error information when an error occurs in a system; recording the error information in a GPNV storage space of the basic input output system; setting a value of a serial general-purpose input/output port according to the type of the error information. The method, system and terminal for recording error information of a basic input output system based on GPNV according to the present disclosure record the BIOS error information through GPNV in the BIOS ROM, ensuring the reliable recording of error information and helping to accurately determine the cause of the error.

STATUS REGISTER POWER INTERRUPTION PROTECTION

Techniques are provided for improved restart of a system. In an example, a system can alternate storing a status register value or state to two or more non-volatile memory locations. Upon a power interruption and restart, the value of the status register can be restored to a state very close to or commensurate with a last occurring state even if a write operation to one of the non-volatile memory locations resulted an inaccurate saving of that state of the status register.

SERVICING MEMORY HIGH PRIORITY READ REQUESTS

Various embodiments described herein provide for a memory device that can service a high priority read request during data input without losing the data inputted to the memory device prior to the high priority read request, without re-requesting data from a host, and while leaving one or more internal resources of a memory sub-system available for use by an error correction function of the memory sub-system. 1. A system comprising:a set of memory devices comprising an individual memory device; and processing, by a cache register of the individual memory device, a current write request to write data input to the individual memory device, the data input comprising a series of data units;', 'before completion of the processing the current write request, determining that a first high priority read request, to read from a first page of the individual memory device, exists; and', stopping the processing the current write request;', 'causing a first set of data units of the data input, currently stored on the cache register, to be stored to a second page of the individual memory device;', 'generating first log data that describes an occurrence of the first high priority read request, identifies a first data location in the series of data units where the processing the current write request stopped, and identifies the second page where the first set of data units is stored;', 'servicing the first high priority read request by the cache register; and', 'after completion of the servicing the first high priority read request, resuming, based on the first log data, the processing the current write request from the first data location in the series of data units., 'in response to determining that the first high priority read request exists], 'a processing device, operatively coupled to the set of memory devices, configured to perform operations comprising2. The system of claim 1 , wherein the servicing the first high priority read request by the cache register comprises:causing ...

Processor that mitigates side channel attacks by preventing all dependent instructions from consuming architectural register result produced by instruction that causes a need for an architectural exception

A microprocessor that mitigates side channel attacks includes a front end that processes instructions in program order and a back end that performs speculative execution of instructions out of program order in a superscalar fashion. Producing execution units produce architectural register results during execution of instructions. Consuming execution units consume the produced architectural register results during execution of instructions. The producing and consuming execution units may be the same or different execution units. Control logic detects that, during execution by a producing execution unit, an architectural register result producing instruction causes a need for an architectural exception and consequent flush of all instructions younger in program order than the producing instruction and prevents all instructions within the back end that are dependent upon the producing instruction from consuming the architectural register result produced by the producing instruction.

Method for configuring multiple input-output channels

A system comprises an interposer including multiple conductive interconnects; multiple chiplets arranged on the interposer and interconnected by the interposer; each chiplet including a die-to-die physical layer interface including one or more pads to engage the interconnect of the interposer; and wherein at least one chiplet includes multiple input-output channels organized into at least one column and arranged in an order at a periphery of the chiplet forming a die-to-die physical layer interface to engage the interconnects of the interposer, wherein the order of the channels of the column is programmable.

DEVICE, EVENT AND MESSAGE PARAMETER ASSOCIATION IN A MULTI-DROP BUS

Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. A method performed at a device coupled to a serial bus includes determining that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register that has a first bit width and includes information identifying one or more devices associated with the event register, and exchanging the GPIO state information with the one or more devices over the serial bus. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The configuration information may include an address identifying the one or more devices. The configuration information may include addressing information identifying a target register in the one or more devices. The configuration information may include information identifying a mode of communication for transmitting the GPIO state information. 1. A method performed at a device coupled to a serial bus , comprising:determining that general purpose input/output (GPIO) state information corresponding to a physical GPIO pin or signal is available in an event register, wherein the event register has a first bit width and includes information identifying one or more devices associated with the event register; andexchanging the GPIO state information with the one or more devices over the serial bus, wherein the GPIO state information is transmitted over the serial bus in accordance with configuration information stored in the event register,wherein the configuration information includes an address identifying the one or more devices, addressing information identifying a target register in the one or more devices and information identifying a mode of communication for transmitting the GPIO state information.2. The method of claim 1 , further comprising:storing the GPIO state information in a first device ...

Arithmetic processor

An arithmetic processor of an embodiment comprises program counter, a program memory, registers, and a decoder. Also the arithmetic processor comprises an arithmetic unit that carries out an operation using the operand and operator acquired from the registers based on a decode result by the decoder, a data memory that stores constant data and an address in association with the data, and a load unit that comprises a load data address storing unit that stores a load data address indicating an address where the constant data is stored; and an increment unit that updates the load data address stored in the load data address storing unit. The load unit loads, from the data memory, constant data corresponding to an address specified by an operand of a load instruction from the decoder, and stores the constant data in a specific one of the registers.

SYSTEM POWER MANAGEMENT IN MULTI-PORT I/O HYBRID SYSTEMS

In one embodiment, an apparatus includes a host controller to implement one or more layers of a Universal Serial Bus (USB)-based protocol to provide an interconnect for a plurality of devices. The host controller is to monitor control plane messages on the interconnect, detect, in the control plane messages, a power state change command for a device coupled to the interconnect, wherein the devices utilizes a tunneled protocol on the interconnect, and modify power distribution for one or more other devices of the interconnect based on detecting the power state change command. 1. An apparatus comprising: monitor control plane messages on the interconnect;', 'detect, in the control plane messages, a power state change command for a device coupled to the interconnect, wherein the devices utilizes a tunneled protocol on the interconnect; and', 'modify power distribution for one or more other devices of the interconnect based on detecting the power state change command., 'a host controller to implement one or more layers of a Universal Serial Bus (USB)-based protocol to provide an interconnect for a plurality of devices, wherein the host controller is to2. The apparatus of claim 1 , wherein the host controller is to implement a connection manager (CM) to monitor the control plane messages claim 1 , and the CM is to generate an interrupt based on detecting power state change commands.3. The apparatus of claim 2 , wherein the CM is to generate the interrupt by setting one or more bits of a status register in the host controller.4. The apparatus of claim 2 , wherein host controller is further to implement a device policy manager (DPM) to manage power delivery policies for devices coupled to the interconnect claim 2 , and the CM is to provide an indication of the power state change command to the DPM using an Operating System Power Policy Manager (OSPPM).5. The apparatus of claim 1 , wherein the power state change command is a low power command for a power sink device claim 1 ...

Simd controller and simd predication scheme

In an embodiment, a method for processing data in a single instruction multiple data (SIMD) computer architecture is provided. A processing element (PE) may determine based on a masking instruction, a predication state indicative of one of a conditional predication mode and an absolute predication mode. The PE may receive a predicated instruction and, based on a value of a head bit of the bits of a predication mask and on the value indicative of the predication state whether to commit a computation corresponding to execution of the predicated instruction. In another embodiment, a SIMD controller stores loops and sections of a program as a separate instruction stream record for generating the memory address of the next instruction. For data streams, the SIMD controller records information for each data memory access that references the same register files that are used by the instruction streams.

DELAYED ZERO-OVERHEAD LOOP INSTRUCTION

An apparatus may include a counter circuit and an execution unit. The execution unit may be configured to receive and execute a first instruction. The first instruction may include a first number corresponding to a first number of instructions of a plurality of instructions, a second number corresponding to a number of times to execute a subset of the plurality of instructions, and a third number corresponding to a number of instructions in the subset. The execution unit may be further configured to initialize a first count value in the counter circuit to the second number in response to the execution of the first instruction, to execute the first number of the plurality of instructions, and to execute the subset of the plurality of instructions. The counter circuit may be configured to modify the first count value in response to determining a last instruction of the subset has been retired. 1. An apparatus , comprising:a first counter circuit; and receive and execute a first program instruction of a plurality of program instructions, wherein the first program instruction includes a first number corresponding to a number of program instructions in a first subset of the plurality of program instructions, a second number corresponding to a number of times to execute a second subset of the plurality of program instructions, and a third number corresponding to a number of program instructions in the second subset;', 'initialize a first count value in the first counter circuit to the second number in response to the execution of the first program instruction;', 'execute the first subset of the plurality of program instructions; and', 'execute the second subset of the plurality of program instructions;, 'an execution unit configured towherein the first counter circuit is configured to modify the first count value in response to a determination that a last program instruction of the second subset has been retired.2. The apparatus of claim 1 , wherein the execution unit is ...

RESET AND REPLAY OF MEMORY SUB-SYSTEM CONTROLLER IN A MEMORY SUB-SYSTEM

In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component. 1. A system comprising:a plurality of memory components; and suspending operation of an access management component;', 'determining whether the media management component is operating, and if so then suspending operation of the media management component;', 'resetting the media management component;', 'resuming operation of the media management component; and', 'resuming operation of the access management component., 'responsive to detecting a triggering event for restarting a media management component, performing operations comprising, 'a processing device that is operatively coupled with the plurality of memory components and is configured to perform operations comprising2. The system of claim 1 , wherein the triggering event comprises receipt of a notification from the media management component.3. The system of claim 2 , wherein the notification comprises a notification of an internal error of the media management component.4. The system of claim 2 , wherein the notification comprises a notification of an error related to one or more of the memory components in the plurality of memory components.5. The system of claim 1 , wherein the triggering event comprises receipt of a notification of an error from a firmware of the system.6. The system of ...

PROCESSING-IN-MEMORY AND METHOD AND APPARATUS WITH MEMORY ACCESS

A processing-in-memory includes: a memory; a register configured to store offset information; and an internal processor configured to: receive an instruction and a reference physical address of the memory from a memory controller, determine an offset physical address of the memory based on the offset information, determine a target physical address of the memory based on the reference physical address and the offset physical address, and perform the instruction by accessing the target physical address. 1. A processing-in-memory , comprising:a memory;a register configured to store offset information; and receive an instruction and a reference physical address of the memory from a memory controller,', 'determine an offset physical address of the memory based on the offset information,', 'determine a target physical address of the memory based on the reference physical address and the offset physical address, and', 'perform the instruction by accessing the target physical address., 'an internal processor configured to2. The processing-in-memory of claim 1 , further comprising:a cache configured to store the offset information and the target physical address.3. The processing-in-memory of claim 2 , wherein the internal processor is further configured to:search the cache based on the offset information, andperform the instruction by accessing the target physical address in response to the target physical address corresponding to the offset information being found in the cache by the search.4. The processing-in-memory of claim 3 , wherein claim 3 , for the determining of the target physical address claim 3 , the internal processor is further configured to:determine the target physical address based on the reference physical address and the offset physical address in response to the target physical address corresponding to the offset information not being found in the cache by the search.5. The processing-in-memory of claim 1 , wherein claim 1 , for the performing of the ...

DETECTING THAT A SEQUENCE OF INSTRUCTIONS CREATES AN AFFILIATED RELATIONSHIP

Detecting that a sequence of instructions creates an affiliated relationship. A determination is made that a sequence of instructions creates an affiliated relationship. Based on determining that the sequence of instructions creates the affiliated relationship, a sequence of operations is generated. The sequence of operations provides a predicted target address to be included in a selected register and to be used in branching. 1. A computer program product for facilitating processing within a computing environment , the computer program product comprising: determining that a sequence of instructions creates an affiliated relationship; and', 'generating a sequence of operations, based on determining that the sequence of instructions creates the affiliated relationship, the sequence of operations providing a predicted target address to be included in a selected register and to be used in branching., 'a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising2. The computer program product of claim 1 , wherein the sequence of operations comprises:predicting the predicted target address;loading the predicted target address into a location accessible by instructions for execution; andloading the predicted target address into a first selected location and a second selected location.3. The computer program product of claim 2 , wherein the first selected location comprises a counter register to be used in the branching and the second selected location comprises an affiliated register.4. The computer program product of claim 3 , wherein the method further comprises:allocating a rename register for the affiliated register; andcopying the predicted target address into the rename register.5. The computer program product of claim 4 , wherein the method further comprises marking the rename register as available.6. The computer program product of claim 3 , wherein the method further comprises determining an ...

CONCURRENT PREDICTION OF BRANCH ADDRESSES AND UPDATE OF REGISTER CONTENTS

A value to be used in register-indirect branching is predicted and concurrently stored in a selected location accessible to one or more instructions. The value may be a target address used by an indirect branch and the selected location may be a hardware register, providing concurrent prediction of branch addresses and the update of register contents. 1. A computer program product for facilitating processing within a computing environment , the computer program product comprising: predicting, using a processor of the computing environment, a predicted value to be used in register-indirect branching;', 'storing the predicted value in a selected location accessible to one or more instructions of the computing environment, the storing being performed concurrently to processing of a register-indirect branch, and the selected location being in addition to another location used to store an instruction address; and', 'using the predicted value in speculative processing that includes the register-indirect branch., 'a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising2. The computer program product of claim 1 , wherein the predicted value comprises a target address to be used by an instruction fetch.3. The computer program product of claim 2 , wherein the using comprises redirecting the instruction fetch to the target address.4. The computer program product of claim 1 , wherein the selected location comprises a hardware register.5. The computer program product of claim 1 , wherein the method further comprises:determining whether the predicted value is accurate; andperforming recovery, based on determining the predicted value is inaccurate.6. The computer program product of claim 5 , wherein the recovery comprises:flushing one or more instructions executed subsequent to the using; andreplacing the predicted value with a non-predicted value.7. The computer program product of claim 6 , wherein the ...