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Применить Всего найдено 6. Отображено 6.
11-01-2017 дата публикации

Apparatus and method for executing instruction using range information associated with a pointer

Номер: GB0002540206A
Автор: SIMON JOHN CRASKE [GB], SIMON JOHN CRASKE, Simon John Craske
Принадлежит:

Data processing apparatus 2 comprises bounded pointer storage register 60 storing pointer 62 and associated range information 64. Processing circuitry 4 identifies register 60 and performs predetermined operations for a target range of addresses based on range information 64 in response to a first type of instructions specifying pointer register 60. For example, clean and invalidate operations walk through each entry of caches 20, 24, 36, 52 comparing corresponding tags against the range of addresses 64 and performing cache maintenance if the tags lie within the range. Other examples comprise setting, copying, and searching instructions operating upon the target range of addresses. Second types of instructions use the range to protect against unauthorized access, e.g. in capability-based addressing. They trigger errors if pointer 62 is set or offset outside the allowable range. Restriction information 66 is also used to define capabilities within which pointer 62 can be used.

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Номер записи: 1
26-07-2017 дата публикации

Modal processing of program instructions

Номер: GB0002546465A
Автор: SIMON JOHN CRASKE [GB], SIMON JOHN CRASKE, Simon John Craske
Принадлежит:

Disclosed is a data processing apparatus 2 that has a first set of processing circuitry 8, 12, 18, 20, 22 that processes operations in a first mode of operation and a second set of processing circuitry 8, 12, 14, 18, 20, 22, 24 that processes operations in a second mode of operation. There are within the supported instruction set, a first proper subset of program instructions are processed by the processor selectively using the first mode or the second mode, and a second proper subset of program instructions which are required to be processed by the processor operating in the second mode. The two sets of processing circuitry may have different energy consumption and processing speeds. The second program instruction set may be larger than the first instruction set and the instructions in the second set are longer then in the first set. The second instruction set may include floating point instructions. Processing circuitry which is inactive in a mode of operation may be placed into a low ...

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Номер записи: 2
18-10-2023 дата публикации

Technique for handling ordering constrained access operations

Номер: GB0002617551A
Автор: SIMON JOHN CRASKE [GB], JACOB EAPEN [GB]
Принадлежит:

Processing circuitry is provided to perform operations, along with instruction decoder circuitry to decode instructions to control the processing circuitry to perform the operations specified by the instructions. A set of registers is used to hold data values for access by the processing circuitry. The instruction decoder circuitry is responsive to an ordering constrained access instruction used to access multiple data values, and providing register indication information and memory address information, to control the processing circuitry to perform a sequence of access operations, where each access operation causes a data value from amongst the multiple data values to be moved between an associated register determined from the register indication information and an associated memory address determined from the memory address information. Further, an ordering indication is derived from the ordering constrained access instruction and used to determine an order in which the multiple data ...

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Номер записи: 3
01-06-2016 дата публикации

System error handling in a data processing apparatus

Номер: GB0002532777A
Автор: SIMON JOHN CRASKE [GB], MICHAEL JOHN WILLIAMS [GB], RICHARD ROY GRISENTHWAITE [GB], SIMON JOHN CRASKE, MICHAEL JOHN WILLIAMS, RICHARD ROY GRISENTHWAITE, Simon John Craske, Michael John Williams, Richard Roy Grisenthwaite
Принадлежит:

Apparatus for data processing and a method of data processing where data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists 40 and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set 44 and if an error mask condition is set 46, setting a deferred error exception condition 50 and clearing the error exception condition 52. The system recognises when a system error is reported to processing circuitry that is already performing an exception handing procedure triggered by a previous exception and using an error mask condition enables the processing circuitry to prioritize its response to the error and allows the system to distinguish the source resulting in the system ...

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Номер записи: 4
08-02-2017 дата публикации

Apparatus with reduced hardware register set

Номер: GB0002540948A
Автор: SIMON JOHN CRASKE [GB], SIMON JOHN CRASKE, Simon John Craske
Принадлежит:

An apparatus comprises processing circuitry 4 for processing program instructions according to a predetermined architecture defining a number of architectural registers accessible in response to the program instructions. A set of hardware registers 12 is provided in hardware. A storage capacity of the set of hardware registers 12 is insufficient for storing all the data associated with the architectural registers of the pre-determined architecture. Control circuitry 10 is responsive to the program instructions to transfer data between the hardware registers 12 and at least one register emulating memory location 50- 62 in memory 6 for storing data corresponding to the architectural registers of the architecture. Also provided is an apparatus with at least one operand register and R-bit opcode register, loading an R-bit portion of an S-bit opcode (where S>R) into the opcode register and loading the remainder into one of the operand registers, and an apparatus with a program counter register ...

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Номер записи: 5
01-11-2023 дата публикации

Exception return state lock parameter

Номер: GB0002618116A
Автор: SIMON JOHN CRASKE [GB], JOHN MICHAEL HORLEY [GB]
Принадлежит:

An apparatus comprises exception return state register storage, and processing circuitry. In response to a guarded control stack (GCS) exception return state push instruction, the processing circuitry obtains exception return state information from the exception return state register storage and push the state information to a GCS data structure. In response to a GCS exception return state pop instruction, the processing circuitry obtains GCS-protected exception return state information from the GCS data structure. In at least one operating state, the processing circuitry detects, in response to an attempt to modify the exception return state information stored in the exception return state register storage, whether an exception return state lock parameter is in a locked state or an unlocked state and signals a fault when it is in the locked state.

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Номер записи: 6