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Применить Всего найдено 27599. Отображено 100.
05-01-2012 дата публикации

Carbon-based memory element

Номер: US20120001142A1
Принадлежит: International Business Machines Corp

One embodiment of the disclosure can provide a storage layer of a resistive memory element comprising a resistance changeable material. The resistance changeable material can include carbon. Contact layers can be provided for contacting the storage layer. The storage layer can be disposed between a bottom contact layer and a top contact layer. The resistance changeable material can be annealed at a predetermined temperature over a predetermined annealing time for rearranging an atomic order of the resistance changeable material.

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05-01-2012 дата публикации

Nanoelectronic differential amplifiers and related circuits implemented on a segment of a graphene nanoribbon

Номер: US20120001689A1
Автор: Lester F. Ludwig
Принадлежит: Pike Group LLC

A multiple transistor differential amplifier is implemented on a segment of a single graphene nanoribbon. Differential amplifier field effect transistors are formed on the graphene nanoribbon from a first group of electrical conductors in contact with the graphene nanoribbon and a second group of electrical conductors insulated from, but exerting electric fields on, the graphene nanoribbon thereby forming the gates of the field effect transistors. A transistor in one portion of the graphene nanoribbon and a transistor in another portion of the graphene nanoribbon are responsive to respective incoming electrical signals. A current source, also formed on the graphene nanoribbon, is connected with the differential amplifier, and the current source and the differential amplifier operating together generate an outgoing signal responsive to the incoming electrical signal. In an example application, the resulting circuit can be used to interface with electrical signals of nanoscale sensors and actuators,

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05-01-2012 дата публикации

Methods, structures, and devices for reducing operational energy in phase change memory

Номер: US20120002465A1
Автор: Roy E. Meade
Принадлежит: Micron Technology Inc

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

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10-11-2004 дата публикации

УСТРОЙСТВО ДИСТАНЦИОННОГО УПРАВЛЕНИЯ ПЛАТНЫМИ КАНАЛАМИ ТЕЛЕВИДЕНИЯ

Номер: RU0000041913U1

Устройство дистанционного управления платными каналами телевидения, содержащее 4 кнопки, первый элемент ИЛИ, первый таймер, шифратор и инфракрасный (ИК) передатчик, отличающееся тем, что в него дополнительно введены задающий генератор, первый элемент И, первый вход которого соединен с выходом задающего генератора, счетчик, вход которого является выходом первого элемента И, мультиплексор, первый вход которого соединен с выходом счетчика, 6 кнопок, выходы которых соединены с соответствующими входами мультиплексора, триггер, первый вход которого соединен с выходом мультиплексора, второй вход - с выходом задающего генератора, а выход - со вторым входом первого элемента И, первый регистр сдвига РС1, первый вход которого соединен с выходом первого элемента И, а второй вход - с выходом счетчика, второй регистр сдвига РС2, первый вход которого соединен с выходом первого элемента И, а второй вход - с выходом первого регистра сдвига, первый и второй дешифраторы, входы которых соответственно соединены с выходами первого и второго регистров сдвига, двадцать элементов И, первые входы которых соединены с десятью выходами первого дешифратора, а оставшиеся - с десятью выходами второго дешифратора, второй элемент ИЛИ, входы которого соединены с выходами двадцати элементов И, блок программирования, выходы которого являются вторыми входами двадцати элементов И, второй таймер, вход которого соединен с выходом второго элемента ИЛИ, блок индикации, вход которого соединен с первым выходом второго таймера, блок памяти, первый вход которого соединен с выходом первого таймера, который в свою очередь соединен с выходом второго таймера, а второй вход - с выходом первого элемента ИЛИ, который в свою очередь соединен с выходами первого и второго дешифраторов, а выход блока памяти - со вторым входом ИК передатчика, ИК приемник, первый выход которого соединен с входом блока программирования, а второй вход - со вторым входом шифратора, первый вход которого соединен с выходом счетчика, а выход - с ...

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10-01-2005 дата публикации

УСТРОЙСТВО ОГРАНИЧЕНИЯ ДОСТУПА К ТЕЛЕВИЗИОННЫМ ПРОГРАММАМ

Номер: RU0000043380U1

Устройство ограничения доступа к телевизионным программам, содержащее инфракрасный (ИК) приемник, дешифратор и селектор каналов, отличающееся тем, что в него дополнительно введены первый и второй блоки памяти предустановок селектора каналов, входы которых соединены соответственно с первым и вторым выходами дешифратора, вход которого соединен с выходом ИК приемника, элемент ИЛИ, первый и второй входы которого соединены соответственно с первым и вторым выходами блоков памяти предустановок селектора каналов, элемент И, первый вход которого соединен с выходом элемента ИЛИ, второй вход – с выходом ИК приемника, а выход – с третьим входом селектора каналов, первый и второй входы которого соединены соответственно с первым и вторым выходами дешифратора. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 43 380 (13) U1 (51) МПК G06E 1/04 (2000.01) G11C 13/04 (2000.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ, ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21), (22) Заявка: 2004127413/22 , 17.09.2004 (24) Дата начала отсчета срока действия патента: 17.09.2004 (45) Опубликовано: 10.01.2005 (73) Патентообладатель(и): Людвиг Владимир Алексеевич (RU), Соколова Татьяна Валериевна (RU) U 1 4 3 3 8 0 R U Ñòðàíèöà: 1 U 1 Формула полезной модели Устройство ограничения доступа к телевизионным программам, содержащее инфракрасный (ИК) приемник, дешифратор и селектор каналов, отличающееся тем, что в него дополнительно введены первый и второй блоки памяти предустановок селектора каналов, входы которых соединены соответственно с первым и вторым выходами дешифратора, вход которого соединен с выходом ИК приемника, элемент ИЛИ, первый и второй входы которого соединены соответственно с первым и вторым выходами блоков памяти предустановок селектора каналов, элемент И, первый вход которого соединен с выходом элемента ИЛИ, второй вход – с выходом ИК приемника, а выход – с третьим входом селектора каналов, первый и второй входы которого соединены соответственно с первым и вторым ...

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27-08-2006 дата публикации

СИСТЕМА ДИСТАНЦИОННОГО УПРАВЛЕНИЯ ПЛАТНЫМИ КАНАЛАМИ ТЕЛЕВИДЕНИЯ

Номер: RU0000056016U1

Система дистанционного управления платными каналами телевидения, содержащая k телевизоров, в каждый из которых входит первый инфракрасный (ИК) приемник и селектор каналов, а также k пультов дистанционного управления, содержащих первый ИК передатчик, отличающаяся тем, что в нее дополнительно введены кодер, модулятор, на первый вход которого подключается широкополосный сигнал кабельной сети, а на второй вход-выход кодера; k приставок, в каждой из которых имеется третий ИК приемник и декодер, первый вход которого соединен с выходом модулятора, второй вход соединен с выходом третьего ИК приемника, а выход - с селектором каналов k-го телевизора; в k пультах дистанционного управления: однокристаллическая микроЭВМ, связанная шиной адреса и данных с оперативным запоминающим устройством, постоянным запоминающим устройством, блоком индикации, блоком клавиатуры, дополнительным портом ввода, дополнительным портом вывода, соединенным с первым ИК передатчиком, который оптическим каналом связан с первым ИК приемником k-го телевизора и третьим ИК приемником k-й приставки, второй ИК приемник, выход которого соединен с входом дополнительного порта ввода; в пункт регистрации: ЭВМ с программным обеспечением, второй ИК передатчик, вход которого соединен с выходом ЭВМ, а выход - оптическим каналом с входом второго ИК приемника. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 56 016 (13) U1 (51) МПК G06E 1/04 (2006.01) G11C 13/04 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ, ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21), (22) Заявка: 2006114584/22 , 28.04.2006 (24) Дата начала отсчета срока действия патента: 28.04.2006 (45) Опубликовано: 27.08.2006 (73) Патентообладатель(и): Людвиг Владимир Алексеевич (RU), Соколова Татьяна Валериевна (RU), Кукушкин Андрей Васильевич (RU), Щербина Андрей Дмитриевич (RU) Ñòðàíèöà: 1 U 1 5 6 0 1 6 R U U 1 Формула полезной модели Система дистанционного управления платными каналами телевидения, содержащая k телевизоров, в каждый ...

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10-11-2007 дата публикации

ФОТОННЫЙ ЭХО-ПРОЦЕССОР С ЛАЗЕРНЫМ ОХЛАЖДЕНИЕМ

Номер: RU0000068167U1

1. Фотонный эхо-процессор с лазерным охлаждением, содержащий твердотельный носитель информации, выполненный из материала, содержащего центры возбуждения фотонного эха на ионах редкоземельного элемента, оптически сопряженный через устройство ввода излучения с источником возбуждения импульсов фотонного эха и с источником излучения накачки антистоксового охлаждения, а через устройство вывода излучения с устройством регистрации сигналов фотонного эха, отличающийся тем, что в твердотельный носитель информации дополнительно введены ионы другого редкоземельного элемента в качестве центров антистоксового охлаждения. 2. Фотонный эхо-процессор по п.1, отличающийся тем, что твердотельный носитель информации выполнен в виде активного световода, сердцевина которого изготовлена из материала, содержащего центры возбуждения фотонного эха, а оболочка выполнена из материала, содержащего центры антистоксового охлаждения, при этом источник излучения импульсов фотонного эха и источник излучения накачки антистоксового охлаждения оптически сопряжены с сердцевиной и оболочкой световода соответственно. 3. Фотонный эхо-процессор по п.2, отличающийся тем, что устройство ввода излучения выполнено в виде мультиплексора, а устройство вывода излучения в виде демультиплексора. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 68 167 (13) U1 (51) МПК G11C 13/04 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ, ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21), (22) Заявка: 2007124467/22 , 28.06.2007 (24) Дата начала отсчета срока действия патента: 28.06.2007 (45) Опубликовано: 10.11.2007 6 8 1 6 7 R U Формула полезной модели 1. Фотонный эхо-процессор с лазерным охлаждением, содержащий твердотельный носитель информации, выполненный из материала, содержащего центры возбуждения фотонного эха на ионах редкоземельного элемента, оптически сопряженный через устройство ввода излучения с источником возбуждения импульсов фотонного эха и с источником излучения накачки антистоксового ...

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19-03-2019 дата публикации

Кубит на основе композитного материала РММА+Ag

Номер: RU0000187774U1

Полезная модель относится к компьютерным системам. Техническим результатом полезной модели является система кубитов, при селективном возбуждении одного из которых непрерывным УФ-излучением возможна резонансная передача энергии на большие расстояния. Кубит на основе композитного материала полиметилметакрилата с наночастицами серебра (PMMA+Ag), состоящий из матрицы из полимера PMMA и одной наночастицы серебра, отличающейся тем, что в качестве кубита используется фрагмент композитного материала PMMA+Ag с квазинулевым показателем преломления. Использование полезной модели позволит реализовать резонансную передачу энергии на большие расстояния между двумя кубитами, представляющих собой фрагменты композитного материала PMMA+Ag, при селективном возбуждении одного из кубитов непрерывным УФ-излучением. Использование полезной модели позволит решить задачу резонансной передачи энергии на большие расстояния. Благодаря перепутанности квантовых состояний и когерентности в системе кубитов, обусловленной нулевым показателем преломления системы кубитов, достигается увеличение локального поля в месте кубита-наблюдателя, если индуцирующее поле в месте расположения кубита-индуктора мало. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 187 774 U1 (51) МПК G06N 99/00 (2010.01) G11C 13/02 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК G06N 99/002 (2018.08); G11C 13/02 (2018.08); B82Y 10/00 (2018.08); C08L 33/12 (2018.08) (21)(22) Заявка: 2018135173, 04.10.2018 (24) Дата начала отсчета срока действия патента: 19.03.2019 Приоритет(ы): (22) Дата подачи заявки: 04.10.2018 (56) Список документов, цитированных в отчете о поиске: US 2012/0013052 A1, 11.01.2018. WO (45) Опубликовано: 19.03.2019 Бюл. № 8 1 8 7 7 7 4 R U 2018/125026 A1, 05.07.2018. WO 2018/057024 A1, 29.03.2018. RU 72341 U1, 10.04.2008. (54) Кубит на основе композитного материала РММА+Ag (57) Реферат: Полезная модель относится к компьютерным реализовать резонансную передачу ...

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07-05-2019 дата публикации

ОКСИДНЫЙ МЕМРИСТОР С КОНЦЕНТРАТОРАМИ ЭЛЕКТРИЧЕСКОГО ПОЛЯ

Номер: RU0000189045U1

Полезная модель относится к мемристорам с наноразмерной активной средой. Технический результат: обеспечение сочетания повышенных технологичности изготовления мемристора и стабилизации работы резистивной памяти мемристора, а также высоких временной стабильности параметров резистивной памяти и их устойчивости к многократному переключению. Сущность: мемристор содержит расположенную между первым и вторым электродами наноразмерную активную среду, выполненную на основе обеспечивающего филаментарный механизм переключения слоя диоксида циркония и обладающую резистивной памятью, стабилизированной в результате введения в указанную активную среду наноконцентраторов электрического поля. Первый электрод выполнен из нитрида титана, второй электрод - из тантала. Наноразмерная активная среда выполнена в виде слоя диоксида циркония, стабилизированного иттрием, и расположенного между этим слоем и первым электродом слоя оксида тантала. Наноразмерная среда содержит наноконцентраторы электрического поля, образованные при осаждении на первый электрод оксида тантала в виде нанокристаллических включений тантала в прилежащих к межслойной поверхностной границе раздела участках осажденного слоя оксида тантала и промежуточного интерфейсного слоя диоксида титана, сформированного на поверхности первого электрода при осаждении магнетронным распылением на него оксида тантала, сопровождаемом частичным замещением атомов азота на атомы кислорода. 3 з.п. ф-лы, 3 ил. И 1 189045 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ 7 ВУ‘’” 189 045? 91 ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ИЗВЕЩЕНИЯ К ПАТЕНТУ НА ПОЛЕЗНУЮ МОДЕЛЬ МЕЭК Восстановление действия патента Дата, с которой действие патента восстановлено: 13.12.2021 Дата внесения записи в Государственный реестр: 13.12.2021 Дата публикации и номер бюллетеня: 13.12.2021 Бюл. №35 Стр.: 1 па 9470681 ЕП

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12-01-2012 дата публикации

RESTIVE MEMORY USING SiGe MATERIAL

Номер: US20120008366A1
Автор: Wei Lu
Принадлежит: Crossbar Inc

A resistive memory device includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell.

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12-01-2012 дата публикации

Methods and systems for memristor-based neuron circuits

Номер: US20120011092A1
Принадлежит: Qualcomm Inc

Certain embodiments of the present disclosure support techniques for designing neuron circuits based on memristors. Bulky capacitors as electrical current integrators can be eliminated and nanometer scale memristors can be utilized instead. Using the nanometer feature-sized memristors, the neuron hardware area can be substantially reduced.

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26-01-2012 дата публикации

Non-Volatile Memory Element And Memory Device Including The Same

Номер: US20120018695A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments, relate to a non-volatile memory element and a memory device including the same. The non-volatile memory element may include a memory layer having a multi-layered structure between two electrodes. The memory layer may include first and second material layers and may show a resistance change characteristic due to movement of ionic species therebetween. The first material layer may be an oxygen-supplying layer. The second material layer may be an oxide layer having a multi-trap level.

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02-02-2012 дата публикации

Memory resistor having plural different active materials

Номер: US20120026776A1
Принадлежит: Hewlett Packard Development Co LP

Methods and means related to memory resistors are provided. A memristor includes at least two different active materials disposed between a pair of electrodes. The active materials are selected to exhibit respective and opposite changes in electrical resistance in response to changes in oxygen ion content. The active materials are subject to oxygen ion reconfiguration under the influence of an applied electric field. An electrical resistance of the memristor is thus adjustable by way of applied programming voltages and is non-volatile between programming events.

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09-02-2012 дата публикации

Semiconductor device and method for driving semiconductor device

Номер: US20120033505A1
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.

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16-02-2012 дата публикации

Method and apparatus for optically reading information

Номер: US20120037698A9
Принадлежит: BAYER INNOVATION GMBH

The present invention relates to a novel type of information carrier, on which information is stored in the form of diffraction structures. The information carrier according to the invention can be read by being drawn manually through a reading device. The present invention also relates to a device with which an information carrier according to the invention can be read.

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16-02-2012 дата публикации

Semiconductor memory device

Номер: US20120039110A1
Принадлежит: Toshiba Corp

A memory-cell array that includes a first line, a second line intersecting the first line, and a memory cell including a variable resistive element provided in the intersection of the first and the second lines; a data-write unit configured to apply a voltage pulse to the memory cell through the first and the second lines, the voltage pulse to set and/or reset data; and a detector unit configured to compare a cell current that flows through the memory cell by the voltage pulse at the time of setting and/or resetting the data with a reference current generated from the initial value of the cell current, and to control the data-write unit in accordance with a result of comparison.

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16-02-2012 дата публикации

Destruction of data stored in phase change memory

Номер: US20120039117A1
Автор: Gary Edward Webb
Принадлежит: Individual

A mechanism and means by which the data information pattern stored in Phase Change Memory PCM ( 21 ) can be quickly destroyed and made unreadable upon the receipt of a destruction stimuli( 11 ) by the application of a targeted thermal heat source generated by an internal integrated thermal heater ( 26 ), a heat source mounted under the PCM ( 28 ), on top of the PCM ( 29 ), within the PCB ( 30 ), or an externally generated heat source ( 27 ). Such an operation is non-destructive and while the stored data is rendered unreadable, the physical PCM device is unharmed and can be used again.

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23-02-2012 дата публикации

Memory devices using a plurality of diodes as program selectors for memory cells

Номер: US20120044736A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

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23-02-2012 дата публикации

One-time programmable memories using polysilicon diodes as program selectors

Номер: US20120044738A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).

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23-02-2012 дата публикации

Reversible resistive memory using diodes formed in cmos processes as program selectors

Номер: US20120044747A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistive global wordlines through conductive contact(s) or via(s).

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23-02-2012 дата публикации

Variable resistance nonvolatile storage device and method of forming memory cell

Номер: US20120044749A1
Принадлежит: Panasonic Corp

A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate ( 301 ), (ii) a variable resistance element ( 309 ) having: lower and upper electrodes ( 309 a, 309 c ); and a variable resistance layer ( 309 b ) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes ( 309 a, 309 c ), and (iii) a MOS transistor ( 317 ) formed on the substrate ( 301 ), wherein the variable resistance layer ( 309 b ) includes: oxygen-deficient transition metal oxide layers ( 309 b - 1, 309 b - 2 ) having compositions MO x and MO y (where x<y) and in contact with the electrodes ( 309 a, 309 c ) respectively, and a diffusion layer region ( 302 b ) is connected with the lower electrode ( 309 a ) to form a memory cell ( 300 ), the region ( 302 b ) serving as a drain of the transistor ( 317 ) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer ( 309 b ).

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23-02-2012 дата публикации

Programmably reversible resistive device cells using cmos logic processes

Номер: US20120044753A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

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01-03-2012 дата публикации

Non-volatile memory device

Номер: US20120051170A1
Принадлежит: Hynix Semiconductor Inc

A non-volatile memory device includes a cell array configured to read or write data, a local column switch configured to selectively connect a bit line of the cell array to a global bit line in response to a column selection signal, a global column switch configured to selectively connect the global bit line to a sense-amp in response to an enable signal, and a switching unit configured to selectively connect or sever a current path of the global column switch in response to a control signal corresponding to a bank active operation.

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08-03-2012 дата публикации

Semiconductor memory apparatus and method for controlling programming current pulse

Номер: US20120057417A1
Автор: Yong Bok An
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory apparatus includes a write control code generation unit configured to generate a write control code which is updated at each pulsing timing of an external test pulse signal applied through a pad; and a data write unit configured to output a programming current pulse which has a magnitude corresponding to the code value of the write control code.

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15-03-2012 дата публикации

Multi-level resistance change memory

Номер: US20120063193A1
Автор: Reika Ichihara
Принадлежит: Individual

According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.

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15-03-2012 дата публикации

Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same

Номер: US20120063194A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

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22-03-2012 дата публикации

Reactive metal implated oxide based memory

Номер: US20120069624A1
Принадлежит: Micron Technology Inc

Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.

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22-03-2012 дата публикации

Nonvolatile semiconductor memory device

Номер: US20120069627A1
Принадлежит: Toshiba Corp

A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

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29-03-2012 дата публикации

Resistance Based Memory Having Two-Diode Access Device

Номер: US20120075906A1
Принадлежит: Qualcomm Inc

A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

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29-03-2012 дата публикации

Resistor structure for a non-volatile memory device and method

Номер: US20120075907A1
Автор: Sung Hyun Jo
Принадлежит: Crossbar Inc

A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

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29-03-2012 дата публикации

Resistive Random Access Memory and Verifying Method Thereof

Номер: US20120075908A1

A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

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29-03-2012 дата публикации

Nonvolatile semiconductor memory device

Номер: US20120075912A1
Автор: Koji Hosono
Принадлежит: Toshiba Corp

A nonvolatile semiconductor memory device comprises a three-dimensional cell array block in which a plurality of cell array layers are stacked, each of the cell array layers including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of memory cells disposed at each of intersections of the first and second lines and each including a variable resistance element configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a reading control circuit for reading data from the memory cells under a condition set in respective groups to which one or more cell array layers having a common electric property of the memory cells belong.

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29-03-2012 дата публикации

Phase change memory state determination using threshold edge detection

Номер: US20120075923A1
Автор: Aswin Thiruvengadam
Принадлежит: Numonyx BV Amsterdam Rolle Branch

Subject matter disclosed herein relates to techniques to read a memory cell that involve a threshold edge phenomenon of a reset state of phase change memory.

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05-04-2012 дата публикации

Phase change memory apparatus having row control cell

Номер: US20120081954A1
Автор: Kyoung Wook Park
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes a phase change memory apparatus includes a plurality of row control cells and a plurality of phase change memory cells formed on the row control cells while being electrically connected to the row control cells. The plurality of row control cells and the plurality of phase change memory cells are vertically stacked in a cell array area.

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19-04-2012 дата публикации

Non-volatile memory device and methods for manufacturing the same

Номер: US20120091424A1
Принадлежит: Individual

A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification.

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19-04-2012 дата публикации

Resistive Memory Element and Use Thereof

Номер: US20120092920A1
Автор: Sakyo Hirose
Принадлежит: Murata Manufacturing Co Ltd

A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor which has a composition represented by the general formula: (Ba 1-x Sr x )Ti 1-y M y O 3 (wherein M is at least one from among Mn, Fe, and Co; 0≦x≦1.0; and 0.005≦y≦0.05). The first electrode of the pair of electrodes is made of a material which can form a Schottky barrier which can develop a rectifying property and resistance change characteristics in an interface region between the first electrode and the element body. The second electrode is made of a material which provides a more ohmic junction to the element body as compared with the first electrode.

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19-04-2012 дата публикации

Memory devices and memory systems including discharge lines and methods of forming

Номер: US20120092946A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.

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26-04-2012 дата публикации

Cross point variable resistance nonvolatile memory device

Номер: US20120099367A1
Принадлежит: Panasonic Corp

A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell ( 51 ) is placed at a different one of cross points of bit lines ( 53 ) in an X direction and word lines ( 52 ) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements ( 57, 58 ) switch electrical connection and disconnection between a global bit line ( 56 ) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit ( 92 ) having parallel-connected P-type current limiting element ( 91 ) and N-type current limiting element ( 90 ) is provided between the global bit line and the switch elements.

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03-05-2012 дата публикации

Phase-change memory device

Номер: US20120106244A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

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17-05-2012 дата публикации

Phase change memory device

Номер: US20120120724A1
Автор: Hyuck-Soo Yoon
Принадлежит: Individual

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

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24-05-2012 дата публикации

Memory resistor adjustment using feedback control

Номер: US20120127780A1
Принадлежит: Hewlett Packard Development Co LP

Apparatus and methods related to memory resistors are provided. A feedback controller applies adjustment signals to a memristor. A non-volatile electrical resistance of the memristor is sensed by the feedback controller during the adjustment. The memristor is adjusted to particular values lying between first and second limiting values with minimal overshoot. Increased memristor service life, faster operation, lower power consumption, and higher operational integrity are achieved by the present teachings.

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07-06-2012 дата публикации

Programmable metallization memory cell with planarized silver electrode

Номер: US20120142169A1
Принадлежит: SEAGATE TECHNOLOGY LLC

Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

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14-06-2012 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20120147644A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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14-06-2012 дата публикации

Programming reversible resistance switching elements

Номер: US20120147657A1
Принадлежит: SanDisk 3D LLC

A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption.

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14-06-2012 дата публикации

Three dimensional non-volatile storage with multi block row selection

Номер: US20120147689A1
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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14-06-2012 дата публикации

Schottky diode switch and memory units containing the same

Номер: US20120149183A1
Принадлежит: SEAGATE TECHNOLOGY LLC

A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

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21-06-2012 дата публикации

Multibit magnetic random access memory cell with improved read margin

Номер: US20120155159A1
Автор: Ioan Lucian Prejbeanu
Принадлежит: CROCUS TECHNOLOGY SA

A magnetic random access memory (MRAM) cell including a magnetic tunnel junction including a tunnel barrier layer between a first magnetic layer having a first magnetization direction, and a second magnetic layer having a second adjustable magnetization to vary a junction resistance of the magnetic tunnel junction from a first to a second junction resistance level; said magnetic tunnel junction further including a switching resistant element electrically connected to the magnetic tunnel junction and having a switching resistance switchable from a first to a second switching resistance level when a switching current is passed through the switching resistant element, such that a resistance of the MRAM cell can have at least four different cell resistance levels depending of the resistance level of the junction resistance and the switching resistance. The disclosed MRAM cell achieves improved read margin and allows for writing at least four different cell resistance levels.

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05-07-2012 дата публикации

Memory system with sectional data lines

Номер: US20120170346A1
Автор: Luca Fasoli, Tianhong Yan
Принадлежит: SanDisk 3D LLC

The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

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19-07-2012 дата публикации

Memory unit and method of operating the same

Номер: US20120182785A1
Автор: Wataru Otsuka
Принадлежит: Sony Corp

A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.

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16-08-2012 дата публикации

Organic redox active compounds with reversible storage of charges and substrates and molecular memory devices comprising them

Номер: US20120205605A1

An organic redox active compound with reversible storage of charge is disclosed. The material characterized by a formula R-M-Y-T. According to some aspects, R represents a deconjugating group, M represents an organic redox active fragment, not comprising any metal ion or metal, capable of reversibly storing at least one charge, T represents a tripod group comprising three groups F, capable of being chemically grafted to a surface of a solid substrate, and Y represents a spacer group separating M from T. A substrate on which the compounds are grafted, a molecular memory device including the compound or the substrate, and an electronic apparatus including the molecular memory device are also disclosed.

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23-08-2012 дата публикации

Memory Emulation In An Image Capture Device

Номер: US20120212646A1
Автор: Robert Norman
Принадлежит: Unity Semiconductor Corp

An image capture device using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, a non-volatile memory card, and FLASH memory, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the image capture device. At least one of the memory arrays may be in the form of a removable memory card.

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23-08-2012 дата публикации

Memory apparatus

Номер: US20120212994A1
Принадлежит: Sony Corp

A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.

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30-08-2012 дата публикации

Write bandwidth in a memory characterized by a variable write time

Номер: US20120218814A1
Принадлежит: International Business Machines Corp

A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

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06-09-2012 дата публикации

Methods for increasing bottom electrode performance in carbon-based memory devices

Номер: US20120223414A1
Принадлежит: SanDisk 3D LLC

In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.

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06-09-2012 дата публикации

Three dimensional memory system with intelligent select circuit

Номер: US20120224410A1
Автор: Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

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06-09-2012 дата публикации

High density low power nanowire phase change material memory device

Номер: US20120225527A1
Принадлежит: International Business Machines Corp

A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

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13-09-2012 дата публикации

Semiconductor device

Номер: US20120229197A1
Принадлежит: Renesas Electronics Corp

The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

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20-09-2012 дата публикации

Sensing resistive states

Номер: US20120236623A1
Принадлежит: Hewlett Packard Development Co LP

A memory device capable of being sensed with an oscillating signal includes a first terminal of a memristive element connected to an oscillating signal supply, and a second terminal of the memristive element connected to sensing circuitry, the sensing circuitry to determine an attenuation of an oscillating signal from the oscillating signal supply. A crossbar array includes a first set of parallel lines selectively connected to an oscillating signal supply, a second set of parallel lines intersecting the first set of parallel lines, the second set of parallel lines selectively connected to sensing circuitry, memristive memory elements being disposed at crosspoints between the first set of parallel lines and the second set of parallel lines, in which a memory controller of the crossbar array is to determine a resistive state of one of the memory elements by determining, with the sensing circuitry, an attenuation of an oscillating signal produced by the oscillating signal supply.

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20-09-2012 дата публикации

Program cycle skip

Номер: US20120236663A1
Принадлежит: SanDisk 3D LLC

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

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27-09-2012 дата публикации

Nonvolatile memory device

Номер: US20120241707A1
Автор: Kensuke Takahashi
Принадлежит: Toshiba Corp

According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar includes a current selection film and a plurality of variable resistance films stacked on the current selection film. One variable resistance film includes a metal and either oxygen or nitrogen. Remainder of the variable resistance films include the metal, either oxygen or nitrogen, and a highly electronegative substance having electronegativity higher than electronegativity of the metal. A concentration of highly electronegative substance in the remainder of the variable resistance films is different among the variable resistance films.

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27-09-2012 дата публикации

Memory device

Номер: US20120243292A1
Принадлежит: Individual

According to one embodiment, a memory device includes a first electrode including a crystallized Si x Ge 1-x layer (0≦x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.

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27-09-2012 дата публикации

Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance

Номер: US20120243298A1
Автор: Glen Hush
Принадлежит: Individual

The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.

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27-09-2012 дата публикации

Control Method for Memory Cell

Номер: US20120243346A1

A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

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04-10-2012 дата публикации

Semiconductor memory device and controlling method thereof

Номер: US20120250393A1
Автор: Masanobu Shirakawa
Принадлежит: Individual

According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, a peripheral circuit, a sense amplifier configured to sense the memory cells via the peripheral circuit, and a control circuit configured to control operations of the memory cell array and the sense amplifier. The control circuit is configured to boost a potential of a selected bit line, which is one of a first even bit line and a first odd bit line of a first side, by charge sharing of a second even bit line and a second odd bit line which are nonselected bit lines and physically neighbor the first even bit line or the first odd bit line of the first side, which is connected to a selected one of the memory cells.

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11-10-2012 дата публикации

Semiconductor device

Номер: US20120257437A1
Принадлежит: Elpida Memory Inc

A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element

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18-10-2012 дата публикации

Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells

Номер: US20120262973A1
Автор: Jun Liu
Принадлежит: Individual

An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

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18-10-2012 дата публикации

Semiconductor memory device

Номер: US20120266043A1
Принадлежит: Individual

The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

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25-10-2012 дата публикации

Semiconductor device and its manufacturing method

Номер: US20120268981A1
Принадлежит: Renesas Electronics Corp

In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

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08-11-2012 дата публикации

Nonvolatile latch circuit and nonvolatile flip-flop circuit

Номер: US20120280713A1
Автор: Yoshikazu Katoh
Принадлежит: Panasonic Corp

A nonvolatile latch circuit of the invention includes a variable resistance element which is formed by interposing an oxide layer between electrodes, and changes to a low resistance state by applying a voltage to cause current flow in the direction from the first to the second electrode, and changes to a high resistance state by applying a voltage to cause current flow in the reverse direction, wherein a first terminal of a transistor, a first terminal of other transistor, an output terminal of an inverter circuit, and an output terminal of other inverter circuit are respectively connected to one electrode, the other electrode, a second terminal of the transistor, and a second terminal of the other transistor, and a current flowing through the variable resistance element when changed to a low resistance state is smaller in absolute value than a current therethrough when changed to a high resistance state.

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08-11-2012 дата публикации

Variable resistance nonvolatile storage device

Номер: US20120281453A1

The variable resistance nonvolatile storage device includes a memory cell ( 300 ) that is formed by connecting in series a variable resistance element ( 309 ) including a variable resistance layer ( 309 b ) which reversibly changes based on electrical signals each having a different polarity and a transistor ( 317 ) including a semiconductor substrate ( 301 ) and two N-type diffusion layer regions ( 302 a, 302 b ), wherein the variable resistance layer ( 309 b ) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes ( 309 a, 309 c ) are made of materials of different elements, a standard electrode potential V 1 of the lower electrode ( 309 a ), a standard electrode potential V 2 of the upper electrode ( 309 c ), and a standard electrode potential V t of the transition metal satisfy V t <V 2 and V 1 <V 2 , and the lower electrode ( 309 a ) is connected with the N-type diffusion layer region ( 302 b ), the electrical signals being applied between the lower and upper electrodes ( 309 a, 309 c ).

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22-11-2012 дата публикации

Memory element and memory device

Номер: US20120294063A1
Принадлежит: Sony Corp

There are provided a memory element and a memory device excellently operating at a low current, and having the satisfactory retention characteristics. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer disposed on the first electrode side, and being in a single- or multi-layer structure including a layer containing a highest percentage of tellurium (Te) as an anionic component, and an ion source layer disposed on the second electrode side, and containing a metallic element and one or more chalcogen elements including tellurium (Te), sulfur (S), and selenium (Se) with aluminum (Al) of 27.7 atomic % or more but 47.4 atomic % or less.

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29-11-2012 дата публикации

Memory cell operation

Номер: US20120300530A1
Принадлежит: Micron Technology Inc

Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

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06-12-2012 дата публикации

Nitrogen Doped Aluminum Oxide Resistive Random Access Memory

Номер: US20120305881A1
Принадлежит: Leland Stanford Junior University

A resistive random access memory (RRAM) device is provided that includes a first electrode, a second electrode, and a resistance-change film disposed between the first electrode and the second electrode, where the resistance-change film includes an atomic ratio of aluminum, oxygen and nitrogen.

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06-12-2012 дата публикации

Resistive memory devices and memory systems having the same

Номер: US20120307547A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during a memory cell reset operation. The write driver is further configured to drive the selected bit line in sequence with a first set current pulse, which is responsive to the first external voltage, and a second set current pulse, which is responsive to a second external voltage input through a second terminal/pad of the memory device during a memory cell set operation.

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13-12-2012 дата публикации

Cell-state measurement in resistive memory

Номер: US20120314481A1
Принадлежит: International Business Machines Corp

Apparatus and method for measuring the state of a resistive memory cell. A bias voltage controller applies a bias voltage to the cell and controls the level of the bias voltage. A feedback signal generator senses cell current due to the bias voltage and generates a feedback signal (S FB ) dependent on the difference between the cell current and a predetermined target current. The bias voltage controller controls the bias voltage level in dependence on the feedback signal (S FB ) such that the cell current converges on the target current. An output is provided indicative of the bias voltage level at which the cell current corresponds to the target current, thus providing a voltage-based metric for cell-state.

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13-12-2012 дата публикации

Set pulse for phase change memory programming

Номер: US20120314491A1
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to a memory device, and more particularly to a single pulse algorithm for programming a phase change memory.

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13-12-2012 дата публикации

Non-volatile memory device having phase-change material and method for fabricating the same

Номер: US20120314492A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory cells. In the non-volatile memory device, a circuit of the at least one second memory cell is cut off according to the initial information, and the initial information is defective block information that is information about a defect of the plurality of memory blocks.

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13-12-2012 дата публикации

Synapse for function cell of spike timing dependent plasticity (stdp), function cell of stdp, and neuromorphic circuit using function cell of stdp

Номер: US20120317063A1

A synapse for a spike timing dependent (STDP) function cell includes a memory device having a variable resistance, such as a memristor, and a transistor connected to the memory device. A channel of the memory device is connected in series with a channel of the transistor.

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20-12-2012 дата публикации

Resistance-change memory device and method of operating the same

Номер: US20120320659A1
Автор: Makoto Kitagawa
Принадлежит: Sony Corp

Disclosed herein is a resistance-change memory device including a bit line; a voltage supplying layer; a memory element connected between the bit line and the voltage supplying layer, a resistance value of the memory element being changed in accordance with an applied voltage; and a drive controlling circuit causing a first current to flow through the bit line and causing a second current smaller than the first current to flow through the bit line, thereby controlling a resistance decreasing operation in which the memory element is made to transit from a high resistance state to a low resistance state by using the second current.

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27-12-2012 дата публикации

Programming of phase-change memory cells

Номер: US20120327709A1
Принадлежит: International Business Machines Corp

A method and apparatus for programming a phase-change memory cell. A bias voltage signal (V BL ) is applied to the cell. A measurement portion (m) of this bias voltage signal has a profile which varies with time. A measurement (T M ), which is dependent on a predetermined condition being satisfied, is then made. The predetermined condition is dependent on cell current during the measurement portion (m) of the bias voltage signal. A programming signal is generated in dependence on the measurement (T M ), and the programming signal is applied to program the cell.

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03-01-2013 дата публикации

Magnetoresistive element and method of manufacturing the same

Номер: US20130001652A1
Принадлежит: Individual

According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B 4 C, Al 2 O 3 and AlN.

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03-01-2013 дата публикации

Refresh architecture and algorithm for non-volatile memories

Номер: US20130003451A1
Принадлежит: Micron Technology Inc

Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

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10-01-2013 дата публикации

Memory system with data line switching scheme

Номер: US20130010523A1
Автор: Luca Fasoli, Tianhong Yan
Принадлежит: SanDisk 3D LLC

A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.

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10-01-2013 дата публикации

Descending set verify for phase change memory

Номер: US20130010533A1
Автор: Ferdinando Bedeschi
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

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17-01-2013 дата публикации

Multi-partitioning of memories

Номер: US20130019058A1
Принадлежит: Individual

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

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24-01-2013 дата публикации

Resistive ram, method for fabricating the same, and method for driving the same

Номер: US20130021835A1
Принадлежит: Individual

A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

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24-01-2013 дата публикации

Programming at least one multi-level phase change memory cell

Номер: US20130021845A1
Принадлежит: International Business Machines Corp

A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

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31-01-2013 дата публикации

Nonvolatile semiconductor memory apparatus and manufacturing method thereof

Номер: US20130029469A1
Принадлежит: Takeshi Takagi, Takumi Mikawa

A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

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14-02-2013 дата публикации

Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor device incorporating nonvolatile memory element

Номер: US20130037775A1

A nonvolatile memory element of the present invention comprises a first electrode ( 103 ), a second electrode ( 108 ); a resistance variable layer ( 107 ) which is interposed between the first electrode ( 103 ) and the second electrode ( 107 ) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes ( 103 ) and ( 108 ), and the resistance variable layer ( 107 ) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfO x (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfO y (1.8≦y≦2.0) are stacked together.

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21-02-2013 дата публикации

Programming at least one multi-level phase change memory cell

Номер: US20130044540A1
Принадлежит: International Business Machines Corp

An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

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28-02-2013 дата публикации

Methods, apparatuses, and circuits for programming a memory device

Номер: US20130051136A1
Принадлежит: Micron Technology Inc

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

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07-03-2013 дата публикации

Memory devices, methods of storing and reading data, smm junctions, and methods of preparing alumina substrates

Номер: US20130058149A1
Автор: Lam H. Yu

Various aspects of the invention provide memory devices, methods of storing and reading data, and silver/molecular-layer/metal (SMM) junctions. One aspect of the invention provides a memory device including a plurality of SMM junctions and an electrical structure configured to permit application of electricity across one or more of the plurality of SMM junctions. Another aspect of the invention provides a method of storing data on a memory device including a plurality of SMM junctions. The method includes applying electrical energy across a subset of the SMM junctions to switch the junction to a more conductive state. Another aspect of the invention provides an SMM junction including a silver layer, a copper layer, and a molecular layer positioned between the silver layer and the copper layer.

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07-03-2013 дата публикации

Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact

Номер: US20130058152A1
Принадлежит: Micron Technology Inc

Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

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07-03-2013 дата публикации

Device fabrication

Номер: US20130059436A1
Принадлежит: Individual

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

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21-03-2013 дата публикации

METHOD FOR READING A HOLOGRAPHIC MEMORY ON A DATA MEDIUM

Номер: US20130070510A1
Принадлежит: GEMALTO SA

The embodiments of this invention also describe to a data medium comprising 1. A data medium comprising{'b': '5', 'a holographic memory () carried by the medium and,'}{'b': 1', '11', '5, 'a photonic crystal () configured, firstly, to filter the light received from a broad-spectrum light source () in order to select a frequency band of the said spectrum and secondly, to guide the light corresponding to the said selected frequency band so as to light the said holographic memory () in a predefined direction.'}21. A data medium according to wherein the photonic crystal () comprises a prohibited band wherein the wavelengths located in the said prohibited band are reflected so as to create a waveguide for those wavelengths.315. A data medium according to or claim 1 , wherein the photonic crystal () comprises an optical resonator that makes it possible to light the holographic memory () coherently with the light spectrum corresponding with the selected frequency band.47. A data medium according to or claim 1 , wherein the format of the said medium is a memory card () that allows the easy handling of the said data medium.5791957. A data medium according to claim 4 , wherein the memory card () comprises a window () that makes it possible to transmit the broad-spectrum light received to the photonic crystal () and in which the said window () and the holographic memory () are positioned on the same side of the memory card ().6791957. A data medium according to claim 4 , wherein the memory card () comprises a window () that makes it possible to transmit the broad-spectrum light received to the photonic crystal () and in which the said window () and the holographic memory () are positioned on opposite sides of the memory card ().71351115. Reading equipment () for reading a data medium having a holographic memory () carried by the medium and claim 4 , a photonic crystal () configured claim 4 , firstly claim 4 , to filter the light received from a broad-spectrum light source () in ...

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21-03-2013 дата публикации

Select devices for memory cell applications

Номер: US20130070511A1
Принадлежит: Micron Technology Inc

Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.

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28-03-2013 дата публикации

MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY

Номер: US20130077394A1

A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable to perform in a first programming mode one or more annealing steps to approach the target resistance, wherein the programming scheme is operable to perform in a second programming mode one or more melting steps, wherein the programming scheme is operable to start in the first programming mode and to switch to the second programming mode if the target resistance level of the PCM cell has been undershot in the first programming mode. 1. A programming device for applying one or more programming pulses according to a predefined programming scheme to one or more Phase Change Memory (PCM) cells to achieve a target resistance level of the PCM cells , the programming device comprising:a pulse generator;and a control circuit for controlling the pulse generator according to the predefined programming scheme, wherein the programming scheme is operable to perform in a first mode one or more annealing steps to approach the target resistance level, wherein the programming scheme is operable to perform in a second mode one or more melting steps, and wherein the programming scheme is operable to start in the first mode and to switch to the second mode if the target resistance level of the PCM cell has been undershot in the first programming mode.2. The programming device of claim 1 , wherein by programming pulses of the annealing steps claim 1 , a memory element of the PCM cell that comprises a phase change material is at least partly heated above the glass temperature of the phase change material of the memory element claim 1 , but below the melting temperature of the phase change material of the memory element.3. The programming device of claim 1 , wherein the programming pulses ...

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18-04-2013 дата публикации

Semiconductor device

Номер: US20130094279A1
Автор: Hiroyuki Kobatake
Принадлежит: Renesas Electronics Corp

A semiconductor device is provided with a lower-layer circuit including a transistor formed over a semiconductor substrate, and a memory cell array formed in an interconnection layer above the semiconductor substrate. Respective memory cells of the memory cell array are provided with a variable resistor element formed in the interconnection layer serving as a memory element. The memory cell array includes a first region directly underneath the memory cells, the first region being a region where a via for electrical coupling with the memory cell is not formed. The lower-layer circuit is disposed in such a way as to overlap at least a part of the first region.

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18-04-2013 дата публикации

Device Comprising Deuterated Organic Interlayer

Номер: US20130095327A1

The present invention relates to devices that can be manipulated or controlled with a magnetic field, such as a spin-valve device, an organic light-emitting device, a compass, or a magnetometer. The devices of the invention comprise an organic interlayer comprising a deuterated organic material.

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25-04-2013 дата публикации

Memory array including multi-state memory devices

Номер: US20130103888A1
Принадлежит: Hewlett Packard Development Co LP

A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array.

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