STORAGE SUB-SYSTEM FOR A COMPUTER COMPRISING WRITE-ONCE MEMORY DEVICES AND WRITE-MANY MEMORY DEVICES AND RELATED METHOD

Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-once storage sub-system memory device and a write-many storage sub-system memory device. Numerous other aspects are provided.

Systems for reverse bias trim operations in non-volatile memory

A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Method for programming a three-dimensional memory array incorporating serial chain diode stack

A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N<2 >memory cells, rather than approximately 3N<2 >memory cells as with prior arrays.

METHOD FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY

A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.

System architecture and method for three-dimensional memory

In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.

Temperature compensation of conductive bridge memory arrays

Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME

A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current. 1. A method of programming a memory cell comprising a memory element comprising a first conductive material layer , a first dielectric material layer disposed above the first conductive material layer , a second conductive material layer disposed above the first dielectric material layer , a second dielectric material layer disposed above the second conductive material layer , and a third conductive material layer disposed above the second dielectric material layer , wherein one or both of the first conductive material layer and the second conductive material layer comprises a stack of a metal material layer and a highly doped semiconductor material layer , wherein the memory cell has a first memory state upon fabrication corresponding to a first read current , wherein the method comprises:applying a first programming pulse to the memory cell with a first current limit, wherein the first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first ...

Structure and Method for Biasing Phase Change Memory Array for Reliable Writing

A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Method to program a memory cell comprising a carbon nanotube fabric element and a steering element

A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.

Resistance-switching memory cells adapted for use at low voltage

A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer has a thickness between 20 and 65 angstroms. Other aspects are also provided.

METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE

Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.

METHODS AND APPARATUS FOR INCREASING MEMORY DENSITY USING DIODE LAYER SHARING

A memory is described that includes a shared diode layer and a memory element coupled to the diode layer. The memory element has a pie slice-shape, and includes a sidewall having a carbon film thereon. Numerous other aspects are also disclosed. 1. A memory cell comprising:a shared diode layer; anda memory element coupled to the diode layer,wherein the memory element has a pie slice-shape, and includes a sidewall having a carbon film thereon.2. The memory cell of claim 1 , wherein the memory element has an approximately half of a pie shape.3. The memory cell of claim 1 , wherein the memory element has an approximately quarter of a pie shape.4. The memory cell of claim 1 , wherein the memory element has an approximately eighth of a pie shape.5. The memory cell of claim 1 , wherein the memory element has an approximately sixteenth of a pie shape.6. The memory cell of claim 1 , wherein the memory element comprises a reversible resistance-switching element.7. The memory cell of claim 1 , wherein the memory element comprises a carbon-based material.8. The memory cell of claim 1 , wherein the memory element comprises one of amorphous carbon claim 1 , graphene claim 1 , graphite claim 1 , or carbon nanotubes.9. A plurality of memory cells comprising:a shared diode layer shaped into a circular disk; anda plurality of radially disposed memory elements each coupled to the shared diode layer along a circumference of the shared diode layer,wherein memory elements each have a pie slice-shape, and includes a sidewall having a carbon film thereon.10. The memory cells of claim 9 , wherein the memory elements claim 9 , each coupled to the shared diode layer claim 9 , are shaped in two approximately half pie shapes.11. The memory cells of claim 9 , wherein the memory elements claim 9 , each coupled to the shared diode layer claim 9 , are shaped in four approximately quarter pie shapes.12. The memory cells of claim 9 , wherein the memory elements claim 9 , each coupled to the shared ...

Floating body memory cell system and method of manufacture

A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

Set/Reset Algorithm Which Detects And Repairs Weak Cells In Resistive-Switching Memory Device

A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded. 1. A method for performing an operation to change a resistance state of a memory cell , comprising:performing a first programming phase by applying one or more program voltages to the memory cell until the memory cell passes a program verify test, the memory cell comprises a resistance-switching material;in response to the memory cell passing the program verify test in the first programming phase, performing a stability test phase by applying one or more disturb voltages to the memory cell and performing a stability verify test for the memory cell;determining whether further programming of the memory cell is warranted based on the stability test phase; andif further programming is warranted based on the stability test phase, performing a second programming phase by applying one or more program voltages to the memory cell.2. The method of claim 1 , wherein:during the stability test phase, the stability verify test is not performed until after two or more of the disturb voltages are applied.3. The method of claim 1 , wherein:the one or more disturb voltages have at least one of a reduced magnitude or a reduced duration compared to the one or ...

DUAL DATA-DEPENDENT BUSSES FOR COUPLING READ/WRITE CIRCUITS TO A MEMORY ARRAY

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

Method and apparatus for writing memory arrays using external source of high programming voltage

A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The VPP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip VPP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

Passive element memory array incorporating reversible polarity word line and bit line decoders

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

STORAGE SUB-SYSTEM FOR A COMPUTER COMPRISING WRITE-ONCE MEMORY DEVICES AND WRITE-MANY MEMORY DEVICES AND RELATED METHOD

Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided. 1. A solid state non-volatile storage sub-system of a computer , comprising:a write-many storage sub-system memory device comprising write-many memory cells;a write-once storage sub-system memory device comprising write-once memory cells; anda page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices.2. The storage sub-system of claim 1 , wherein the computer comprises a personal computer.3. The storage sub-system of claim 1 , wherein the write-once storage sub-system memory device comprises a write-once-read-many-times (WORM) memory device.4. The storage sub-system of claim 3 , further comprising a chip associated with the WORM memory device claim 3 , wherein the chip includes an indication whether the WORM memory device has been written to.5. The storage sub-system of claim 4 , wherein the indication whether the WORM memory device has been written to comprises a flag associated with a page of the WORM memory claim 4 , the flag indicating whether the page has been written to.6. The storage sub-system of claim 1 , wherein the write-many storage sub-system memory device comprises at least one file system structure of the group consisting of a master boot record (MBR) claim 1 , a partition boot record (PBR) claim 1 , and a file allocation table (FAT).7. The storage sub-system of claim 1 , wherein the write-once storage sub-system memory device comprises an identifier to identify the write-once storage sub-system memory device as write-once memory.8. The ...

Dynamic sub-array group selection scheme

A method of selecting numbers of sub-array groups for simultaneous operation to optimize bandwidth biases a number of sub-array groups and compares a circuit state value, preferably voltage, to a reference parameter to determine if the operation can successfully be preformed for that number of sub-array groups. The comparison may be repeated with ifferent numbers of sub-array groups biased to find the optimum number of sub-array groups for the operation.

Two terminal nonvolatile memory using gate controlled diode elements

A nonvolatile memory cell includes a gate controlled diode steering element and a resistivity switching element.

THREE DIMENSIONAL NON-VOLATILE STORAGE WITH ASYMMETRICAL VERTICAL SELECT DEVICES

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. 1. A non-volatile storage system , comprising:a substrate;a monolithic three dimensional memory array of memory cells positioned above and not in the substrate;word lines connected to the memory cells;a plurality of vertically oriented bit lines above and not in the substrate, the vertically oriented bit lines are connected to the memory cells;a plurality of global bit lines;a plurality of asymmetrical vertically oriented select devices that are above and not in the substrate, the asymmetrical vertically oriented select devices are connected to the vertically oriented bit lines and the global bit lines, the asymmetrical vertically oriented select devices have a first gate interface and a second gate interface; anda plurality of select lines connected to the select devices, each asymmetrical vertically oriented select device has one of the select lines connected to the first gate interface for the respective asymmetrical vertically oriented select device and another of the select lines connected to the second gate interface for the respective asymmetrical vertically oriented select device.2. The non-volatile storage system of claim 1 , wherein:each asymmetrical vertically oriented select device includes a channel that is asymmetrically doped.3. The non-volatile storage system of claim 1 , wherein:each asymmetrical vertically oriented select device includes an asymmetrical channel.4. The non-volatile storage system of claim 1 , wherein:each asymmetrical vertically oriented select device includes a channel with a first side at the first ...

Digital content kiosk and methods for use therewith

A digital content kiosk and methods for use therewith are disclosed. Various embodiments are disclosed relating to exemplary memory devices, memory architectures, and programming techniques that can be used with a digital content kiosk, exemplary mechanical and electrical components of a digital content kiosk, exemplary security aspects of a digital content kiosk, and exemplary uses of a digital content kiosk. Other embodiments are disclosed, and each of these embodiments can be used alone or in combination with one another.

Flexible multi-pulse set operation for phase-change memories

Methods and apparatus are provided that include reading a plurality of sets of program pulse tuning instructions from a memory page, the memory page including a plurality of memory cells; and creating a plurality of program pulses in accordance with the plurality of sets of program pulses to program the plurality of memory cells. The plurality of sets of program pulse tuning instructions may be different from one another in at least one respect.

Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch

A tree decoder organization particularly useful for a three-dimensional memory array or any array having very small array line pitch is configured to provide a plurality of top-level decode nodes, each of which, when selected, simultaneously selects a block of array lines and couples each array line of a selected block to a respective intermediate node. Each of the top-level decode signals has a range of control which is substantially less than the extent of the intermediate nodes. In some embodiments each selected block includes more than one array line on each of at least two memory layers having array lines which exit to one side of the memory array. As a result, the large layout area requirement to generate each top-level decode node is supported by a contiguous block of array lines of the memory array.

Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements

A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a block erase operation, and is scalable for use with relatively low voltage power supplies. A method for reading such cells reduces read disturb of a selected memory cell by impressing a read bias voltage having a polarity opposite that of a set voltage employed to change the switchable resistor memory element to a low resistance state. Such programming and read methods are well suited for use in a three-dimensional memory array formed on multiple levels above a substrate, particularly those having extremely compact array line drivers on very tight layout pitch.

Three dimensional hexagonal matrix memory array

A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

Single Device Driver Circuit to Control Three-Dimensional Memory Element Array

A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.

Triangle two dimensional complementary patterning of pillars

A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different ...

Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays

The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Reducing programming time of a memory cell

The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.

METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE

Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective. 1. A method of programming an array of memory cells each comprising an antifuse in series with a diode , each antifuse comprising an insulator having a dielectric constant above 5 , each diode comprising a thin film semiconductor material with a band gap smaller than that of silicon , the method comprising:programming a selected one of the memory cells by applying a first voltage in a direction opposite that of natural current flow through the diode of the selected memory cell, the first voltage being sufficient to short the antifuse.2. The method of claim 1 , further comprising:applying a second voltage to word lines contacting unselected ones of the memory cells; andapplying a third voltage to bit lines contacting the unselected ones of the memory cells, wherein the second and third voltages are substantially equal.3. The method of claim 2 , wherein the second and third voltages are approximately half the first voltage applied to the selected one of the memory cells.4. A method of programming a memory cell comprising an antifuse in series with a diode claim 2 , the antifuse comprising an insulator having a dielectric constant above 5 claim 2 , the diode comprising a ...

Method for fabricating high density pillar structures by double patterning using positive photoresist

A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such ...

MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME

In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.

SYSTEMS FOR CONTROLLED PULSE OPERATIONS IN NON-VOLATILE MEMORY

A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to ...

Method for using a hierarchical bit line bias bus for block selectable memory array

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

Programming a memory cell with a diode in series by applying reverse bias

A method of programming a memory cell comprises applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell. The memory cell comprises a diode and a resistivity switching material element in series. The state of the resistivity switching material element changes from a first initial state to a second state different from the first state.

STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING

A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material. 1. A method for programming a plurality of memory cells in a non-volatile memory array , comprising:configuring a first current mirror to supply a first programming current for a first period of time;configuring a second current mirror to supply a second programming current for a second period of time, the second programming current is different from the first programming current;setting a word line connected to the plurality of memory cells to a selected word line voltage, the plurality of memory cells includes a first memory cell and a second memory cell;coupling the first current mirror to the first memory cell and coupling the second current mirror to the second memory cell subsequent to the setting a word line; andsimultaneously programming the first memory cell and the second memory cell, the simultaneously programming includes applying the first programming current to the first memory cell for the first period of time and applying the second programming current to the second memory cell for the second period of time.2. The method of claim 1 , wherein the first programming current is greater than the second programming current.3. The method of claim 2 , wherein the second period of time is greater than the first period of time.4. The method of claim 1 , wherein the first programming current is sufficient to program the first memory cell into a first state and the second programming current is sufficient to ...

SYSTEMS FOR REVERSE BIAS TRIM OPERATIONS IN NON-VOLATILE MEMORY

A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

COOPERATIVE CHARGE PUMP CIRCUIT AND METHOD

A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.

Method and apparatus for biasing selected and unselected array lines when writing a memory array

A passive element memory array preferably biases selected X-lines to an externally received V PP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to V PP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The V PP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip V PP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

Sidewall structured switchable resistor cell

A method of making a memory device includes forming a first conductive electrode, forming an insulating structure over the first conductive electrode, forming a resistivity switching element on a sidewall of the insulating structure, forming a second conductive electrode over the resistivity switching element, and forming a steering element in series with the resistivity switching element between the first conductive electrode and the second conductive electrode, wherein a height of the resistivity switching element in a first direction from the first conductive electrode to the second conductive electrode is greater than a thickness of the resistivity switching element in second direction perpendicular to the first direction.

Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays

The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

METHOD TO PROGRAM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT

A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.

Integrated circuit incorporating dual organization memory array

A memory organization supports a basic page size and an extended page size. A certain portion of its memory cells are dual-addressable memory cells which may be used to provide the additional memory required for the extended pages or alternatively may be used to provide additional memory within a basic page. A memory array is preferably implemented as basic pages and directly addressed to support the basic page size. The received addresses are translated to map each extended page into a portion of a basic page to support the extended pages. In one embodiment, high order row addresses are conveyed for use as high-order column addresses, and the high-order row addresses overridden, to map each extended page into a contiguous block of basic pages.

Systems for high bandwidth one time field-programmable memory

A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial ...

Reversible polarity decoder circuit

A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.

Formation of arrays of microelectronic elements

Arrays of microelectronic elements such as magnetorestive memory elements and FET's, including dual-gate FET's, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.

Reverse set with current limit for non-volatile storage

A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.

REDUCING PROGRAMMING TIME OF A MEMORY CELL

The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.

METHOD OF PROGRAMMING A NONVOLATILE MEMORY CELL BY REVERSE BIASING A DIODE STEERING ELEMENT TO SET A STORAGE ELEMENT

A method of programming a nonvolatile memory cell. The nonvolatile memory cell includes a diode steering element in series with a carbon storage element The method includes providing a first voltage to the nonvolatile memory cell. The first voltage reverse biases the diode steering element. The carbon storage element sets to a lower resistivity state.

Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements

A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a block erase operation, and is scalable for use with relatively low voltage power supplies. A method for reading such cells reduces read disturb of a selected memory cell by impressing a read bias voltage having a polarity opposite that of a set voltage employed to change the switchable resistor memory element to a low resistance state. Such programming and read methods are well suited for use in a three-dimensional memory array formed on multiple levels above a substrate, particularly those having extremely compact array line drivers on very tight layout pitch.

PULSE RESET FOR NON-VOLATILE STORAGE

A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells.

THREE DIMENSIONAL MEMORY SYSTEM WITH PAGE OF DATA ACROSS WORD LINES

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column of bit lines and multiple word lines while maintaining the selection of the one column of bit lines. In one embodiment, programming non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit. 1. A non-volatile storage apparatus , comprising:a monolithic three dimensional array of non-volatile storage elements arranged in blocks of non-volatile storage elements;a plurality of word lines connected to the non-volatile storage elements, each block of non-volatile storage elements includes a set of the word lines;a plurality of bit lines connected to the non-volatile storage elements, the bit lines are grouped into columns, each block has multiple columns of bit lines;row decoders connected to the word lines, the row decoders are positioned underneath the array of non-volatile storage elements;one or more signal sources;selection circuitry for selecting bit lines to be in communication with the one or more signal sources;column decoders in communication with and controlling the selection circuits, the column decoders are arranged outside the array of non-volatile storage elements, each column decoder selects corresponding columns of bit lines for multiple blocks of non-volatile storage elements; anda control circuit in communication with the row decoders and column decoders to store one page of data across multiple word lines and within one column of bit lines for a block by selecting one column of bit lines of the block ...

CONTINUOUS MESH THREE DIMENSIONAL NON-VOLATILE STORAGE WITH VERTICAL SELECT DEVICES

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Three dimensional non-volatile storage with three device driver for row select

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers

An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

Pulse reset for non-volatile storage

A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells.

Structure and method for biasing phase change memory array for reliable writing

A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Resistance-switching memory cells adapted for use at low voltage

A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided.

Method Of Operating FET Low Current 3D Re-Ram

Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY

A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.

Method for using a mixed-use memory array with different data states

A method for using a mixed-use memory array with different data states is disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X≠Y.

Reduced complexity array line drivers for 3D matrix arrays

A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or second plurality of Y lines and one of the plurality of X lines, respectively. Substantially all of the first plurality and second plurality of Y lines are driven to a Y line unselect voltage. At least one selected Y line of the first plurality of Y lines is driven to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage.

Current sensing method and apparatus for a memory array

A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse

A memory cell is described, the memory cell comprising a dielectric rupture antifuse and a layer of a resistivity-switching material arranged electrically in series, wherein the resistivity-switching material is a metal oxide or nitride compound, the compound including exactly one metal. The dielectric rupture antifuse is ruptured in a preconditioning step, forming a rupture region through the antifuse. The rupture region provides a narrow conductive path, serving to limit current to the resistivity-switching material, and improving control when the resistivity-switching layer is switched between higher- and lower-resistivity states.

METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST

A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such ...

Multi-bit resistance-switching memory cell

A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell.

Controlled pulse operations in non-volatile memory

A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.

Temperature compensation of conductive bridge memory arrays

Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

Cross point memory cell with distributed diodes and method of making same

A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.

CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY

A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.

Multiple series passive element matrix cell for three-dimensional arrays

A nonvolatile memory cell including at least two two-terminal non-linear steering elements arranged in series, and a resistivity switching storage element arranged in series with the at least two two-terminal non-linear steering elements. A memory array, comprising a plurality of the nonvolatile memory cells is also described. A method of forming a nonvolatile memory cell is also described.

Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers

An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST

A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such ...

REVERSIBLE-POLARITY DECODER CIRCUIT AND METHOD

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

METHOD FOR USING DUAL DATA-DEPENDENT BUSSES FOR COUPLING READ/WRITE CIRCUITS TO A MEMORY ARRAY

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

Three dimensional hexagonal matrix memory array

A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

Method for fabricating high density pillar structures by double patterning using positive photoresist

A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such ...

Quad memory cell and method of making same

A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.

Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning

The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same

In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

Semiconductor Memory With Improved Memory Block Switching

A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.

Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning

Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof

A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

Method to program a memory cell comprising a carbon nanotube fabric and a steering element

A method to form a rewriteable nonvolatile memory cell is disclosed, the cell comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.

THREE DIMENSIONAL NON-VOLATILE STORAGE WITH INTERLEAVED VERTICAL SELECT DEVICES ABOVE AND BELOW VERTICAL BIT LINES

A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.

Word line arrangement having multi-layer word line segments for three-dimensional memory array

A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and ...

Three dimensional non-volatile storage with multi block row selection

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

CROSS POINT NON-VOLATILE MEMORY CELL

A memory system includes an X line, a first Y line, a second Y line, a semiconductor region of a first type running along the X line, first switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, second switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, and control circuitry. The control circuitry is in communication with the X line, the first Y line and the second Y line. The control circuitry changes the programming state of the first switching material to a first state by causing a first current to flow from the second Y line to the first Y line through the first switching material, the second switching material, the semiconductor region of the first type, the first semiconductor region of the second type and the second semiconductor region of the second type.

Integrated circuit memory array with fast test mode utilizing multiple word line selection and method therefor

In a programmable memory array, multiple memory cells on a single bit line may be tested in parallel for the unprogrammed state by simultaneously selecting multiple word lines associated with a selected bit line within a sub-array. A read current flowing through each selected memory cell is added on the selected bit line, and may be sensed using the same bit line sense circuits used for normal read operations. In the test mode, the sense circuit preferably indicates a pass/fail condition for all N simultaneously selected memory cells, which may be directly conveyed as an output signal, or may be combined with other similar pass/fail signals from other selected bit line sense circuits to generate a combined pass/fail output signal. Multiple bit lines may be simultaneously selected within the same sub-array. In addition, multiple sub-arrays may be simultaneously selected, each having one or more simultaneously selected bit lines, and the respective pass/fail signals conveyed directly or combined ...

Floating Body Memory Cell System and Method of Manufacture

A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL

A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided. 1. A method of programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line , the method comprising:during a first predetermined time interval, switching the word line from a first standby voltage to a first voltage, and switching the bit line from a second standby voltage to a predetermined voltage; andduring a second predetermined time interval, switching the word line from the first voltage to a second voltage, during the first predetermined time interval, a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell, and', 'during the second predetermined time interval, a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell., 'wherein2. The method of claim 1 , wherein a difference between the safe voltage and the programming voltage maximizes programming speed.3. The method of claim 1 , wherein a difference between the safe voltage and the programming voltage distinguishes between programming and not programming the memory cell.4. The method of claim 1 , wherein the bit line is switched to the predetermined voltage without limiting current.5. The method of claim 1 , ...

METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING

Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed. 1. A three-dimensional memory array comprising:a memory array layer including an array and a plurality of memory lines wherein portions of the memory lines extend from the array substantially parallel to each other,wherein a first subset of the memory lines extend from a first side of the array,wherein a second subset of the memory lines extend from a second side of the array,wherein within the first subset of memory lines a first plurality of memory lines terminate proximate an edge of the array,wherein within the first subset of memory lines a second plurality of memory lines extend beyond the edge of the array into a contact region,wherein the contact region includes a plurality of contacts adapted to couple the second plurality of memory lines to support circuitry,wherein the contacts are disposed in two or more rows, the contact rows disposed substantially non-parallel to the memory lines, andwherein adjacent memory lines couple to contacts in different rows.2. The three-dimensional memory array of wherein the contacts are zias.3. The three-dimensional memory array ...

METHODS AND APPARATUS FOR EXTENDING THE EFFECTIVE THERMAL OPERATING RANGE OF A MEMORY

Systems, methods, and apparatus are provided for thermal regulation of a non-volatile memory IC. The systems and apparatus may include a thermal sensor on a memory IC; and a heating element coupled to the thermal sensor and adapted to heat the memory IC in response to a signal from the thermal sensor. The methods may include sensing a temperature of a memory IC using an integrated thermal sensor on the memory IC and heating the memory IC, using an integrated heating element operatively coupled to the thermal sensor, if the sensed temperature is below a threshold temperature.

Redundant memory structure using bad bit pointers

The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

METHOD FOR USING A HIERARCHICAL BIT LINE BIAS BUS FOR BLOCK SELECTABLE MEMORY ARRAY

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

Reverse bias trim operations in non-volatile memory

A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

RESISTANCE-SWITCHING MEMORY CELLS ADAPTED FOR USE AT LOW VOLTAGE

A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided. 1. A memory cell comprising:a diode; and{'sub': v', 'w, 'a resistance-switching material layer coupled in series with the diode, wherein the resistance-switching material layer: (a) comprises a material from the family consisting of XO, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms.'}2. The memory cell of claim 1 , wherein the diode comprises a band gap smaller than 1.12 electron volts.3. The memory cell of claim 1 , wherein the diode comprises one or more of germanium (Ge) and a silicon germanium alloy (SiGe).4. The memory cell of claim 1 , wherein the resistance-switching material layer comprises HfOor ZrO.5. The memory cell of claim 1 , wherein the memory cell is adapted to be programmed with a voltage less than about 5 volts.6. The memory cell of claim 1 , wherein the diode is adapted to be read using a bias voltage less than about 2 volts.7. The memory cell of claim 1 , wherein the memory cell comprises a monolithic 3-dimensional array.8. A memory cell comprising:a diode comprising a semiconductor material with a band gap smaller than that of silicon; and{'sub': v', 'w, 'a resistance-switching material layer coupled in series with the diode, wherein the resistance-switching material layer: (a) comprises a material from the family consisting of XO, wherein X represents an element from the family consisting of Hf and Zr, and wherein the ...

MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE

A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) has a dielectric constant in the range of about 5 to about 27, and (b) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound. Other aspects are also provided.

TFT CHARGE STORAGE MEMORY CELL HAVING HIGH-MOBILITY CORRUGATED CHANNEL

Numerous other aspects are provided a method for making a nonvolatile memory cell. The method includes forming a non-planar dielectric structure, and conformally depositing a semiconductor layer over the dielectric structure. A portion of the semiconductor layer serves as a channel region for a transistor, and the channel region is non-planar in shape. 1. A method for making a nonvolatile memory cell , the method comprising:forming a non-planar dielectric structure; andconformally depositing a semiconductor layer over the dielectric structure,wherein a portion of the semiconductor layer serves as a channel region for a transistor, and wherein the channel region is non-planar in shape.2. The method of claim 1 , wherein the semiconductor layer is germanium or a germanium alloy.3. The method of claim 1 , further comprising crystallizing the semiconductor layer to form a polycrystalline semiconductor layer.4. The method of claim 1 , further comprising forming a charge storage stack on the semiconductor layer.5. The method of claim 4 , wherein the step of forming the charge storage stack comprises:forming a channel blocking dielectric in contact with the channel region;forming a charge storage dielectric above the channel blocking dielectric; andforming a gate blocking dielectric above the charge storage dielectric.6. The method of claim 5 , wherein the charge storage dielectric is adapted to store charge claim 5 , and the channel blocking dielectric and the gate blocking dielectric are adapted to prevent the loss of stored charge.7. The method of claim 5 , further comprising forming a gate electrode above the charge storage stack.8. The method of claim 1 , wherein the nonvolatile memory cell is formed in a monolithic three dimensional memory array.9. The method of claim 1 , wherein the non-planar dielectric structure has a width claim 1 , the channel region has a length claim 1 , and wherein the length of the channel region is at least 25 percent more than the width of ...

MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATRIE POLARITY

A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition. 1. A method for programming a storage system , comprising:changing a reversible resistance-switching memory cell to a first resistance state; andafter changing the reversible resistance-switching memory cell to the first resistance state, changing the reversible resistance-switching memory cell from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions to the reversible resistance-switching memory cell.2. The method of claim 1 , wherein:the one or more pairs of opposite polarity voltage conditions comprise a first voltage condition that operates the reversible resistance-switching memory cell in a first polarity bias mode followed by a second voltage condition that operates the reversible resistance-switching memory cell in a second polarity bias mode.3. The method of claim 2 , wherein:the second voltage condition is a negative voltage pulse with respect to the resistance-switching memory cell; andthe first voltage condition is a positive voltage pulse with respect to the reversible resistance-switching memory cell that immediately ...

MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATRIE POLARITY

A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition. 1. A method for programming a storage system , the storage system includes a set of a first type of control lines and a set of a second type of control lines , the storage system further includes a set of non-volatile storage elements each of which is connected to one of the first type of control lines and one of the second type of control lines , the method comprising:biasing the set of the first type of control lines to a first voltage;biasing the set of the second type of control lines to a second voltage that is lower than the first voltage;raising a selected control line of the second type of control lines to a third voltage that is higher the second voltage;lowering a selected control line of the first type of control lines to a fourth voltage that is lower than the first voltage; andquickly pulling down the selected control line of the second type of control lines to a fifth voltage that is lower than the second voltage.2. The method of claim 1 , wherein:the set of non-volatile storage elements includes a reversible resistance-switching memory cell that is connected to the selected control line of the ...

Re-writable Resistance-Switching Memory With Balanced Series Stack

A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area. 1. A re-writable resistance-switching memory cell , comprising:first and second capacitors arranged in series, the first capacitor comprises a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor comprises a second bipolar resistance switching layer between third and fourth conductive layers, a capacitance per unit area of the first capacitor is a function of a dielectric constant and a thickness of the first bipolar resistance switching layer, and is balanced with of a capacitance per unit area of the second capacitor, the capacitance per unit area of the second capacitor is a function of a dielectric constant and a thickness of the second bipolar resistance switching layer, the first and third conductive layers comprise a common material, and the second and fourth conductive layers comprise a common material.2. The re-writable resistance-switching memory cell of claim 1 , wherein:the capacitance per unit area of the first ...

Multi-Bit Resistance-Switching Memory Cell

A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell. 1. A method of programming a non-volatile storage system , comprising:programming multiple sets of data into different multi-bit memory cells of a plurality of multi-bit memory cells, each set of data includes more than one bit of data, each multi-bit memory cell includes a resistance element in a conductive condition and two or more reversible resistance-switching elements, the resistance element in the conductive condition and the two or more reversible resistance-switching elements are connected to different Y lines, the resistance element in the conductive condition and the two or more reversible resistance-switching elements are connected to a common X line, for at least a subset of the multi-bit memory cells the programming comprises passing a first current between different Y lines.21. The method of , wherein:the passing of the first current between different Y lines includes passing current from a Y line connected to the resistance element in the conductive condition to a Y line connected to one of the reversible resistance-switching elements via the resistance element in the conductive condition ...

Multi-Bit Resistance-Switching Memory Cell

A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell. 1. A non-volatile memory cell , comprising:an X line;a first Y line;a second Y line;a third Y line;a semiconductor region of a first type running along the X line;first resistance-switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, the first semiconductor region of the second type is adjacent to the semiconductor region of the first type;second resistance-switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, the second semiconductor region of the second type is adjacent to the semiconductor region of the first type;first static resistance material and a third semiconductor region of the second type between the third Y line and the semiconductor region of the first type, the third semiconductor region of the second type is adjacent to the semiconductor region of the first type; andcontrol circuitry in communication with the X line, the first Y line, the second Y line and the third Y line;the control circuitry changes the non- ...

Continuous mesh three dimensional non-volatile storage with vertical select devices

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

THREE DIMENSIONAL NON-VOLATILE STORAGE WITH CONNECTED WORD LINES

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. 1. A non-volatile storage system , comprising:a substrate;a monolithic three dimensional memory array of memory cells positioned above and not in the substrate;a plurality of word lines connected together and connected to a set of the memory cells;a word line driver in the substrate, below the set of the memory cells and in communication with all of the word lines connected together;a plurality of global bit lines;a plurality of vertically oriented bit lines connected to the array of memory cells;a plurality of vertically oriented select devices that are above, but not in the substrate, and that are connected to the vertically oriented bit lines and the global bit lines, when the vertically oriented select devices are actuated the vertically oriented bit lines are in communication with the global bit lines.2. The non-volatile storage system of claim 1 , wherein:the set of the memory cells are in a common block; andthe word line driver is positioned underneath the common block.3. The non-volatile storage system of claim 1 , wherein:the monolithic three dimensional memory array of memory cells includes memory cells on multiple levels; andthe word lines connected together are on a common plane and the set of memory cells are on a common level.4. The non-volatile storage system of claim 1 , wherein:the word lines connected together form a comb shape.5. The non-volatile storage system of claim 4 , wherein:the comb shape includes a spine, fingers on a first side and fingers on a second side;a first set of the word lines connected together ...

Three dimensional non-volatile storage with multi block row selection

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING

A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits. 1. A non-volatile storage device , comprising:non-volatile storage elements including a first block of non-volatile storage elements and a second block of non-volatile storage elements adjacent to the first block of non-volatile storage elements;a first set of word lines, each word line of the first set is connected to non-volatile storage elements of the first block and non-volatile storage elements of the second block;word line drivers positioned between the first block of non-volatile storage elements and the second block of non-volatile storage elements, the word line drivers are connected to the first set of word lines;local data lines in selective communication with the non-volatile storage elements;global data lines;one or more first selection ...

Single Device Driver Circuit to Control Three-Dimensional Memory Element Array

A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal. 1. A memory array , comprising:an array of memory cells positioned between a plurality of word lines and a plurality of bit lines; and a bleeder diode having a first terminal coupled to a first word line of the plurality of word lines;', 'a word line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a word line decoder control lead; and', 'at least one first transistor of a first conductivity type having a gate coupled to the word line decoder control lead, at least one of a source or a drain coupled to a word line bias generator circuit, and the other one of the source or the drain coupled to the first word line., 'a circuit comprising2. The array of claim 1 , wherein a path to an unselected bias voltage source from a word line bleeder diode is controlled by a same word line decoder output that controls a path between a selected bias voltage source and the first word ...

CROSS POINT NON-VOLATILE MEMORY CELL

A memory system includes an X line, a first Y line, a second Y line, a semiconductor region of a first type running along the X line, first switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, second switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, and control circuitry. The control circuitry changes the programming state of the first switching material to a first state by causing a first current to flow from the second Y line to the first Y line through the first switching material, the second switching material, the semiconductor region of the first type, the first semiconductor region of the second type and the second semiconductor region of the second type. 1. A non-volatile storage apparatus , comprising:an X line;a first Y line;a second Y line;a semiconductor region of a first type running along the X line;first switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, the first semiconductor region of the second type is adjacent to the semiconductor region of the first type;second switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, the second semiconductor region of the second type is adjacent to the semiconductor region of the first type; andcontrol circuitry in communication with the X line and the first Y line and the second Y line, the control circuitry changes the programming state of the first switching material to a first state by causing a first current to flow from the second Y line to the first Y line through the first switching material and the second switching material.2. The non-volatile storage apparatus of claim 1 , wherein:the control circuitry changes the programming state of the first ...

Antifuse-based memory cells having multiple memory states and methods of forming the same

In some aspects, a memory cell is provided that includes a steering element and a metal-insulator-metal (“MIM”) stack coupled in series with the steering element. The MIM stack includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, without a metal or other conductive layer disposed between the first dielectric material layer and the second dielectric material layer. Numerous other aspects are provided.

METHODS OF PROGRAMMING TWO TERMINAL MEMORY CELLS

Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell. 1. A method comprising:reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions;creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell;locking the first memory cell from further programming pulses;creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell;locking the second memory cell from further programming pulses; andcreating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell.2. The method of claim 1 , wherein the first claim 1 , second claim 1 , and nth program tuning instructions are different from one another in at least one respect.3. The method of claim 1 , wherein the information of a memory page is stored in a memory page sideband area.4. The method of claim 1 , wherein each of the first claim 1 , second claim 1 , and nth program pulse tuning instructions includes a voltage level instruction.5. The method of claim 4 , wherein at least one voltage level instruction includes a ...

LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE

A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode. 1. A non-volatile storage system , comprising:a substrate;a monolithic three dimensional array of non-volatile storage elements positioned above and not in the substrate, the non-volatile storage elements include reversible resistance switching material;word lines connected to the non-volatile storage elements; andbit lines connected to the non-volatile storage elements;wherein the non-volatile storage elements can be set to a low resistance state during operation by biasing the word lines and bit lines to apply a set voltage to the non-volatile storage elements, the non-volatile storage elements can be reset to a high resistance state during operation by biasing the word lines and bit lines to apply a reset voltage to the non-volatile storage elements, prior to operation the non-volatile storage elements undergo a forming process, during the forming process the word lines and bit lines are biased to apply a forming voltage to the non-volatile storage elements with ...

TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS

Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions. 1. A method for operating a non-volatile semiconductor memory array , comprising:acquiring a temperature associated with the semiconductor memory array, the semiconductor memory array includes a first set of control lines arranged in a first direction and a second set of control lines arranged in a second direction, the first set of control lines includes a first particular control line and a plurality of other first control lines, the second set of control lines includes a second particular control line and a plurality of other second control lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first particular control line and the second particular control line;applying a selected first control line voltage to the first particular control line;applying a selected second control line voltage to the second particular control line;applying one or more unselected first control line voltages based on the temperature to the plurality of other first control lines; ...

APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY

A memory layer in a three-dimensional memory array is provided. The memory layer includes a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias, and a plurality of memory cells operatively coupled to the memory lines. Numerous other aspects are disclosed. 1. A memory layer in a three-dimensional memory array , the memory layer comprising:a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias; anda plurality of memory cells operatively coupled to the memory lines.2. The memory layer of claim 1 , wherein the imprint lithography template is formed from at least one of quartz and fused silica.3. The memory layer of claim 1 , wherein the template includes a plurality of rails corresponding to trenches for a plurality of memory lines.4. The memory layer of claim 1 , wherein the template includes a plurality of pillars corresponding to holes for a plurality of vias.5. The memory layer of claim 1 , wherein the template includes a plurality of pillars corresponding to holes for a plurality of vias and a plurality of rails corresponding to trenches for a plurality of memory lines.6. The memory layer of claim 5 , wherein the template includes the pillars disposed on the rails.7. The memory layer of claim 6 , wherein the pillars disposed on the rails are disposed on alternate opposite ends of each adjacent rail.8. The memory layer of claim 6 , wherein the pillars disposed on the rails have a combined height greater than a height of the rails alone.9. The memory layer of claim 1 , wherein the template includes a plurality of landings corresponding to contact pads.10. The memory layer of claim 1 , ...

3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF

A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. 1. A 3D memory having memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x , y and z-directions and with a plurality of parallel planes stacked in the z-direction , said memory having a multi-layer structure on top of a substrate , the multi-layer structure including a multi-plane memory layer , said 3D memory further comprising:a 2-D array in an x-y plane of conductive pillars as bit line pillars elongated in the z-direction through the plurality of planes, the 2-D array of bit line pillars being spaced apart in the x-direction and the y-direction by a spacing Lx and a spacing Ly respectively and a difference between the spacing Ly and the spacing Lx given by a spacing Ls;a 2D array of isolated TFT channels in the x-y plane, each TFT channel being in-line with and having a first end connected to one end of one of the bit line pillars along the z-direction;a layer of gate material surrounding each TFT channel but isolated from the TFT channel by an intermediate oxide layer, said layer of gate material having a thickness that fills a space between adjacent TFT channels in the x-direction to form a select gate line along the y-direction, thereby leaving a select ...

3d memory with vertical bit lines and staircase word lines and vertical switches and methods thereof

A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS

Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions. 1. A method for operating a memory array , comprising:acquiring a temperature associated with the memory array, the memory array comprises a cross-point memory array and includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction perpendicular to the first direction, the plurality of word lines includes a selected word line and a plurality of unselected word lines, the plurality of bit lines includes a selected bit line and a plurality of unselected bit lines, the memory array includes a first storage element disposed between the selected word line and the selected bit line, the memory array includes a plurality of unselected storage elements disposed between the plurality of unselected word lines and the plurality of unselected bit lines;applying a first voltage difference across the plurality of unselected storage elements based on the temperature; andsetting the first storage element into a first state while performing the applying a first voltage ...

CONTINUOUS MESH THREE DIMENSIONAL NON-VOLATILE STORAGE WITH VERTICAL SELECT DEVICES

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. 1. A method for operating a non-volatile storage system , comprising:applying data dependent signals to a plurality of global bit lines;applying address dependent signals to a set of word lines connected to a monolithic three dimensional array of memory elements that form a continuous mesh with the word lines and vertically oriented bit lines, the monolithic three dimensional array of memory elements is positioned above and not in a substrate;applying an enable signal to a first select line to turn on a plurality of vertically oriented select devices that are above and not in the substrate, the vertically oriented select devices are connected to the vertically oriented bit lines and the global bit lines such that turning on the plurality of vertically oriented select devices provides the signals from the global bit lines to the vertically oriented bit lines, the vertically oriented bit lines are above and not in the substrate; andperforming one or more memory operations in response to the applying data dependent signals to the plurality of global bit lines, applying address dependent signals to the set of word lines and applying the enable signal to the first select line,2. The method of claim 1 , further comprising:applying a disable signal to other select lines connected to other vertically oriented select devices that are above and not in the substrate such that the other vertically oriented select devices do not turn on. This application is a divisional application of U.S. patent application Ser. No. 13/323,680, “Continuous Mesh ...

3D Memory Having Vertical Switches with Surround Gates and Method Thereof

A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. 1. A method , comprising: providing in the multi-plane memory layer a 2-D array in an x-y plane of conductive pillars as bit line pillars elongated in the z-direction through the plurality of planes, the 2-D array of bit line pillars being spaced apart in the x-direction and the y-direction by a spacing Lx and a spacing Ly respectively and a difference between Ly and Lx given by a spacing Ls;', 'forming a slab of a vertical switch layer on top of the multi-plane memory layer by forming a 2D array of isolated TFT channels in the x-y plane of the slab, each TFT channel being in-line with and having a first end connected to one end of one of the bit line pillars along the z-direction;', 'depositing a layer of gate oxide on the slab;', 'forming a select gate surrounding and wrapped around each TFT channel in a plane defined by the x-direction and the y-direction by depositing a layer of gate material on top of the layer of gate oxide, said layer of gate material having a thickness that fills a space between adjacent TFT channels in the x-direction to form a select gate line along the x-direction, thereby leaving a select gate with at least half of said thickness surrounding each TFT channel while leaving a space ...

FET LOW CURRENT 3D ReRAM NON-VOLATILE STORAGE

Non-volatile storage devices having reversible resistance storage elements are disclosed herein. In one aspect, a memory cell unit includes one or more memory cells and a transistor (e.g., FET) that is used to control (e.g., limit) current of the memory cells. The drain of the transistor may be connected to a first end of the memory cell. If the memory cell unit has multiple memory cells then the drain may be connected to a node that is common to a first end of each of the memory cells. The source of the transistor is connected to a common source line. The gate of the transistor may be connected to a word line. The same word line may connect to the transistor gate of several (or many) different memory cell units. A second end of the memory cell is connected to a bit line. 1. A memory array comprising: [ a reversible resistance storage element; and', 'a non-linear element in series with the reversible resistance storage element; and, 'a non-volatile memory cell having a first end and a second end, the memory cell comprising, 'a transistor having a drain, a gate, and a source, the drain of the transistor connected to the first end of the memory cell;, 'a plurality of non-volatile memory cell units, each of the memory cell units comprisinga common source line, the source of the transistor connected to the common source line;a plurality of word lines, the gate of the transistor connected to a word line of the plurality of word lines; anda plurality of bit lines, a bit line of the plurality of bit lines connected to the second end of the memory cell.2. The memory array of , wherein the memory cell unit comprises a plurality of memory cells as recited in , each of the memory cells in the same memory cell unit has its first end connected to the transistor in the same memory cell unit , each of the memory cells in the same memory cell unit has its second end connected to a different bit line of the plurality of bit lines.3. The memory array of claim 1 , wherein a first gate ...

METHOD OF OPERATING FET LOW CURRENT 3D RE-RAM

Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states. 1. A method of operating a non-volatile storage device , the method comprising:training a reversible resistance storage element, including applying a first gate-to-source voltage to a transistor that is connected in series to the reversible resistance storage element while applying a training signal to the reversible resistance storage element, wherein the transistor limits a current of the reversible resistance storage element in response to the training signal; andprogramming the reversible resistance storage element between a lower resistance data state and a higher resistance data state after training the reversible resistance storage element, including applying a second gate-to-source voltage to the transistor that is less than the first gate-to-source voltage while applying a programming signal to the reversible resistance storage element, wherein the transistor limits a current of the reversible resistance storage element in response to the programming signal.2. The method of wherein the training a reversible resistance storage element includes:repeatedly cycling the reversible resistance storage element between a first target ...

RESISTANCE-SWITCHING MEMORY CELLS ADAPTED FOR USE AT LOW VOLTAGE

A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer has a thickness between 20 and 65 angstroms. Other aspects are also provided. 1. A memory cell comprising:a diode; anda resistance-switching material layer coupled in series with the diode, wherein the resistance-switching material layer has a thickness between 20 and 65 angstroms.2. The memory cell of claim 1 , wherein the diode comprises a band gap smaller than 1.12 electron volts.3. The memory cell of claim 1 , wherein the diode comprises one or more of germanium (Ge) and a silicon germanium alloy (SiGe).4. The memory cell of claim 1 , wherein the resistance-switching material layer comprises a material from the family consisting of XO claim 1 , wherein X represents an element from the family consisting of Hf and Zr claim 1 , and wherein the subscripts v and w have non-zero values that form a stable compound.5. The memory cell of claim 1 , wherein the memory cell is adapted to be programmed with a voltage less than about 5 volts.6. The memory cell of claim 1 , wherein the diode is adapted to be read using a bias voltage less than about 2 volts.7. The memory cell of claim 1 , wherein the memory cell comprises a monolithic 3-dimensional array.8. A memory cell comprising:a diode comprising a semiconductor material with a band gap smaller than that of silicon; anda resistance-switching material layer coupled in series with the diode, wherein the resistance-switching material layer has a thickness between 20 and 65 angstroms.9. The memory cell of claim 8 , wherein the band gap is smaller than 1.12 electron volts.10. The memory cell of claim 8 , wherein the diode comprises one or more of germanium (Ge) and a silicon germanium alloy (SiGe).11. The memory cell of claim 8 , wherein the resistance-switching material layer comprises a material from the family consisting of XO claim 8 , wherein X represents an ...

NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING

A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits. 1. A method for programming a non-volatile storage device , comprising:selectively connecting selected non-volatile storage elements of two adjacent blocks of non-volatile storage elements to one or more signal sources and connecting unselected non-volatile storage elements to one or more unselected storage element signals using one or more selection circuits, each of the one or more selection circuits can connect a respective signal source to one of two respective connected non-volatile storage elements and connect a respective unselected storage element signal to another of the two respective connected non-volatile storage elements; andconcurrently programming the two adjacent blocks of non-volatile storage elements while performing the selectively ...

LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE

A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes. 1. A method of operating a non-volatile storage element , comprising:applying a forming voltage to a non-volatile storage element with a polarity of voltage such that an electrode with a lower electron injection energy barrier acts as a cathode and an electrode with a higher electron injection energy barrier acts as an anode, and limiting current through the non-volatile storage element to be lower than maximum current for the non-volatile storage element while applying the forming voltage;performing a sensing operation; anddetermining if non-volatile storage element is in low resistance condition based on the sensing operation.2. The method of claim 1 , further comprising:repeating the applying of the forming voltage if, and in response to, determining that the non-volatile storage element is not in the low resistance condition.3. The method of claim 1 , further comprising:performing RESET operations, SET operations, and read operations after performing a forming process comprising the application of the forming voltage.4. The method of claim 1 , wherein:the electrode with the lower electron injection energy barrier is a vertically oriented bit line and the electrode with the higher electron injection energy barrier is a word line; andthe applying the forming voltage includes applying selected voltages to the vertically oriented ...

Temperature compensation of conductive bridge memory arrays

Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME

In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided. 1. A memory cell comprising:a steering element; and a first conductive material layer;', 'a first dielectric material layer disposed above the first conductive material layer;', 'a second conductive material layer disposed above the first dielectric material layer;', 'a second dielectric material layer disposed above the second conductive material layer; and', 'a third conductive material layer disposed above the second dielectric material layer,', 'wherein one or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer., 'a memory element comprising2. The memory cell of claim 1 , wherein the first conductive material layer comprises one or more of titanium claim 1 , titanium nitride claim 1 , tantalum claim 1 , tantalum nitride claim 1 , tungsten claim 1 , tungsten nitride claim 1 , vanadium nitride claim 1 , vanadium silicon nitride claim 1 , zirconium nitride claim 1 , zirconium silicon nitride claim 1 , hafnium nitride claim 1 , hafnium silicon nitride claim 1 , titanium silicon nitride claim 1 , tantalum silicon nitride claim 1 , tungsten silicon nitride claim 1 , tungsten aluminum nitride and carbon.3. The memory cell of ...

THREE DIMENSIONAL NON-VOLATILE STORAGE WITH ASYMMETRICAL VERTICAL SELECT DEVICES

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. 1. A method of fabricating non-volatile storage , comprising:adding one or more devices and signal lines on top of a substrate;adding a select layer above the one or more devices and signal lines, the adding the select layer includes adding select lines and adding asymmetrical vertically oriented select devices; andadding a monolithic three dimensional array above the select layer, the monolithic three dimensional array includes word lines and vertically oriented bit lines connected to memory elements;the vertically oriented select devices are connected to the vertically oriented bit lines, the select lines and global bit lines.2. The method of claim 1 , wherein the adding select lines comprises:depositing a lower oxide layer;depositing gate material on top of the lower oxide layer;depositing an upper oxide layer on top of the gate material; andetching trenches in the lower oxide layer, the gate material and the upper oxide layer to create stacks.3. The method of claim 2 , wherein the adding vertically oriented select devices comprises:depositing thermal oxide material;depositing a sidewall spacer;etching the trenches;performing a high threshold voltage enhancement mode angled implant toward a first angle such that a first side of the stacks receive the high threshold voltage enhancement mode angled implant;performing a depletion mode angled implant angled toward a second angle such that a second side of the stacks receive the depletion mode angled implant;filling the trenches with p− polysilicon;performing a n+ source implant to ...

Erase For 3D Non-Volatile Memory With Sequential Selection Of Word Lines

An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved. 1. A method for performing an erase operation , comprising:pre-charging a channel of an active area of a plurality of selected memory cells, the pre-charging of the channel comprises applying a pre-charge voltage to one end of the active area, the plurality of selected memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory; andsubsequently, for each selected memory cell of the plurality of selected memory cells, erasing the memory cell by applying an erase voltage, higher than the pre-charge voltage, to the one end of the active area to charge the channel higher while configuring a control gate voltage of the selected memory cell to encourage erasing of the selected memory cell in an erase period, a timing of the erase period is based on a position of the selected memory cell in the active area.2. The method of claim 1 , wherein:the timing of the erase period comprises a start time and a duration of the erase period; andfor each selected memory ...

METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL

A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided. 1. A method of programming a memory cell , the method comprising:setting a word line of a memory cell to a first voltage;setting a bit line of the memory to a predetermined voltage wherein a voltage difference between the first voltage and the predetermined voltage is a safe voltage that does not program the memory cell; andswitching the word line from the first voltage to a second voltage,wherein the voltage difference between the second voltage and the predetermined voltage is a programming voltage that is sufficient to program the memory cell.2. The method of claim 1 , wherein a difference between the safe voltage and the programming voltage is selected to maximize programming speed.3. The method of claim 1 , wherein a difference between the safe voltage and the programming voltage is selected to distinguish between programming and not programming the memory cell.4. The method of claim 1 , wherein the bit line is set to the predetermined voltage without limiting current.5. The method of claim 1 , wherein the first voltage is higher than the second voltage.6. The method of claim 1 , wherein switching the word line from the first voltage to a second voltage includes a VT drop.7. An apparatus comprising:a control circuit coupled to a word ...

MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME

In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided. 1. A memory array comprising: a first conductive line;', 'a first bipolar storage element formed above the first conductive line; and', 'a second conductive line formed above the first bipolar storage element; and, 'a first memory cell having a third conductive line;', 'a second bipolar storage element formed above the third conductive line; and', 'a fourth conductive line formed above the second bipolar storage element;, 'a second memory cell formed above the first memory cell, the second memory cell havingwherein the first bipolar storage element has a first storage element polarity orientation within the first memory cell; andwherein the second bipolar storage element has the first storage element polarity orientation within the second memory cell.2. The memory array of claim 1 , further comprising a first steering element formed between the first and second conductive lines and a second steering element formed between the third and fourth conductive lines.3. The memory array of claim 2 , wherein the first steering element ...

THREE DIMENSIONAL NON-VOLATILE STORAGE WITH CONNECTED WORD LINES

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. 117.-. (canceled)18. A method of performing a memory operation on a non-volatile storage system , comprising:applying a common signal to a plurality of word lines and floating vertically oriented bit lines so that the vertically oriented bit lines drift toward the common signal;applying one or more signals to global bit lines;turning on vertically oriented select devices to connect to selected vertically oriented bit lines to corresponding global bit lines; andapplying a new signal to a selected set of the word lines that are connected together and connected to selected memory cells of a monolithic three dimensional array using a common word line driver.19. The method of claim 18 , wherein:the common word line driver is positioned below the selected memory cells.20. The method of claim 18 , wherein:the unselected vertically oriented bit lines remain floating to self bias and avoid a disturb.21. The method of claim 18 , wherein:the common signal is half of a magnitude of a programming voltage.22. The method of claim 18 , further comprising:prior to applying one or more signals to global bit lines, applying an unselected voltage to the global bit lines.23. The method of claim 18 , wherein:selected vertically oriented bit lines move toward the one or more of the data dependent signals.24. The method of claim 18 , wherein:the selected set of the word lines that are connected together form a comb shape;the comb shape includes a spine, fingers on a first side and fingers on a second side;a first set of the selected set of the word lines ...

Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor

An improved charge pump circuit efficiently utilizes multiple charge pump stages to produce output voltages much larger than the power supply voltage by incorporating, in some embodiments, two parallel strings of series-coupled charge pump stages. Each corresponding charge pump stage in one string is controlled at least by a node in the corresponding charge pump stage of the other string.

Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same

A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.

Three-dimensional memory array incorporating serial chain diode stack

A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N 2 memory cells, rather than approximately 3N 2 memory cells as with prior arrays.

Memory array incorporating noise detection line

A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics

A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Method and system for increasing programming bandwidth in a non-volatile memory device

The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Method and apparatus for discharging memory array lines

A passive element memory array preferably biases selected X-lines to an externally received V PP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to V PP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The V PP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip V PP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

Apparatus and method for disturb-free programming of passive element memory cells

In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.

Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

Non-volatile multi-level re-writable memory cell incorporating a diode in series with multiple resistors and method for writing same

A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than “tuning” the resistance of a single resistive element. An exemplary memory cell includes a vertical pillar diode in series with two different bi-stable resistance films. Each bi-stable resistance film has both a high resistance and low resistance state that can be switched with appropriate application of a suitable bias voltage and current. Such a cross-point array is adaptable for two-dimensional rewritable memory arrays, and also particularly well-suited for three-dimensional rewritable (3D R/W) memory arrays.

Cross point memory cell with distributed diodes and method of making same

A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.

Non-volatile memory capable of correcting overwritten cell

A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Method for programming a three-dimensional memory array incorporating serial chain diode stack

A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N 2 memory cells, rather than approximately 3N 2 memory cells as with prior arrays.

Three dimensional non-volatile storage with dual gated vertical select devices

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance

A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.

Three dimensional non-volatile storage with dual gate selection of vertical bit lines

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Transistor layout configuration for tight-pitched memory array lines

A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.

Method of making self-aligned recessed oxide isolation regions

A simple process is provided for making two self-aligned recessed oxide isolation regions of different thicknesses which includes the steps of defining first and second spaced apart regions on the surface of a semiconductor substrate, forming a protective layer over the first region, forming a first insulating layer of a given thickness within the second region while the first region is protected by the protective layer, removing the protective layer from the first region and forming a second insulating layer thinner than that of the first layer within the first region. Field regions may be ion implanted prior to forming the insulating layers.

Apparatus and method for memory operations using address-dependent conditions

An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.

Reverse bias trim operations in non-volatile memory

A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Nonvolatile memory cell comprising switchable resistor and transistor

A rewriteable nonvolatile memory includes a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in a second direction opposite the first. The memory cell is formed in an array, such as a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate. The thin film transistor and a switchable resistor memory element are electrically disposed between a data line and a reference line which are parallel. A select line extending perpendicular to the data line and the reference line controls the transistor.

High bandwidth one time field-programmable memory

A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial resistance state to program the array in accordance with data received from a user or host device.

Multi-use memory cell and memory array and method for use therewith

A multi-use memory cell and memory array and a method for use therewith are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.

Nonvolatile memory cell comprising switchable resistor and transistor

A rewriteable nonvolatile memory cell is taught comprising a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in a second direction opposite the first. In preferred embodiments the memory cell is formed in an array, preferably a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate. In preferred embodiments a thin film transistor and a switchable resistor memory element are electrically disposed between a data line and a reference line which are parallel. Preferably a select line extending perpendicular to the data line and reference line controls the transistor.

Method to program a memory cell comprising a carbon nanotube fabric element and a steering element

A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.

Memory system with reversible resistivity-switching using pulses of alternate polarity

A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.

Method of operating FET low current 3D Re-RAM

Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Methods involving memory with high dielectric constant antifuses adapted for use at low voltage

Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.

Programming non-volatile storage element using current from other element

A non- volatile storage apparatus includes a set of Y lines, a common X line, multiple data storage elements each of which is connected to the common X line, a dummy storage element connected to the common X line and a particular Y line, and control circuitry in communication with the common X line and the set of Y lines. The multiple data storage elements are capable of being in a first state or a second state. The dummy storage element is in a conductive state. The control circuitry provides control signals to the common X line and the set of Y lines to change a first data storage element of the multiple data storage elements from the first state to the second state by passing a current into the first data storage element from the particular Y line through the dummy storage element. The control circuitry provides control signals to the common X line and the set of Y lines to sequentially change additional data storage elements of the multiple data storage elements from the first state to the second state by passing currents into the additional data storage elements from data storage elements of the multiple data storage elements that were previously changed to the second state and their associated different Y lines.

Method for making a write-once memory device read compatible with a write-many file system

The preferred embodiments described herein provide a method for making a write-once memory device read compatible with a write-many file system. In one preferred embodiment, a method for re-writing to a logical address of a write-once memory device is provided. A physical-to-logical address map is built from data stored in the memory device that associates individual physical addresses with individual logical addresses. When a logical address is re-written, data associating that logical address with a new physical address is stored, and data associating that logical address with an old physical address is invalidated. When the logical address is read, the physical-to-logical address map is used to read the new physical address instead of the old physical address. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Multi-use memory cell and memory array and method for use therewith

Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography

Sidewall structured switchable resistor cell

Increasing write voltage pulse operations in non-volatile memory

A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.

Structure and method for biasing phase change memory array for reliable writing

A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Write method of a cross point non-volatile memory cell with diode

A memory system includes an X line, a first Y line, a second Y line, a semiconductor region of a first type running along the X line, first switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, second switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, and control circuitry. The control circuitry is in communication with the X line, the first Y line and the second Y line. The control circuitry changes the programming state of the first switching material to a first state by causing a first current to flow from the second Y line to the first Y line through the first switching material, the second switching material, the semiconductor region of the first type, the first semiconductor region of the second type and the second semiconductor region of the second type.

Reduced complexity array line drivers for 3D matrix arrays

Pulse reset for non-volatile storage

A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells.

Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines

A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.

Low forming voltage non-volatile storage device

A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.

Method for using a mixed-use memory array with different data states

A method for using a mixed-use memory array with different data states is disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X≠Y.

Methods and apparatus for extending the effective thermal operating range of a memory

Systems, methods, and apparatus are provided for thermal regulation of a non-volatile memory IC. The systems and apparatus may include a thermal sensor on a memory IC; and a heating element coupled to the thermal sensor and adapted to heat the memory IC in response to a signal from the thermal sensor. The methods may include sensing a temperature of a memory IC using an integrated thermal sensor on the memory IC and heating the memory IC, using an integrated heating element operatively coupled to the thermal sensor, if the sensed temperature is below a threshold temperature.

Structure and method for biasing phase change memory array for reliable writing

A memory array having memory cells (40, Fig. 5) comprising a diode (42) and a phase change material (23) is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure (70, Fig. 8) controls state switching of the phase change material.

Sidewall structured switchable resistor cell

A method of making a memory device includes forming a first conductive electrode (28), forming an insulating structure (13) over the first conductive electrode, forming a resistivity switching element (14) on a sidewall of the insulating structure, forming a second conductive electrode (26) over the resistivity switching element, and forming a steering element (22) in series with the resistivity switching element between the first conductive electrode and the second conductive electrode, wherein a height of the resistivity switching element in a first direction from the first conductive electrode to the second conductive electrode is greater than a thickness of the resistivity switching element in second direction perpendicular to the first direction.