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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 7968. Отображено 100.
12-01-2012 дата публикации

Anti-fuse circuit and semiconductor integrated circuit including the same

Номер: US20120008448A1
Автор: Hong-Jung Kim, Jin-Hee Cho
Принадлежит: Hynix Semiconductor Inc

An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal.

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Номер записи: 1
23-02-2012 дата публикации

Memory devices using a plurality of diodes as program selectors for memory cells

Номер: US20120044736A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

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Номер записи: 2
23-02-2012 дата публикации

One-time programmable memories using polysilicon diodes as program selectors

Номер: US20120044738A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).

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Номер записи: 3
23-02-2012 дата публикации

Programmably reversible resistive device cells using cmos logic processes

Номер: US20120044753A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

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Номер записи: 4
05-04-2012 дата публикации

Poly Fuse Burning System

Номер: US20120081826A1
Автор: Chieh-Yao Chuang, Jui-Lung Chen, Tien-Hui Huang
Принадлежит: Vanguard International Semiconductor Corp

This invention provides a poly fuse burning system comprising a poly fuse, a controllable power source supplying power for burning the poly fuse, and a monitor circuit monitoring the burning state of the poly fuse, wherein when a targeted burning state is reached, a control signal is output to shut down the controllable power source to stop the burning.

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Номер записи: 5
12-04-2012 дата публикации

Single Polysilicon Non-Volatile Memory

Номер: US20120087170A1
Автор: Ching-Sung Yang, Hau-yan Lu, Hsin-Ming Chen, Shih-Chen Wang
Принадлежит: eMemory Technology Inc

A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

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Номер записи: 6
19-04-2012 дата публикации

Rom memory device

Номер: US20120092917A1
Автор: Perry H. Pelley
Принадлежит: Individual

A memory device includes a plurality of read only memory cells, a precharge circuit, and a sense amplifier. A read only memory (ROM) cell of the plurality of ROM cells is coupled to a word line and a bit line. The ROM cell comprises a transistor having a first current electrode coupled to receive a reference voltage, a second current electrode selectively coupled to the bit line based on the programmed state of the ROM cell, and a control electrode coupled to the word line. The precharge circuit is coupled to the bit line. The precharge circuit precharges the bit line to a precharge voltage, wherein the precharge voltage is less than the reference voltage. The sense amplifier is coupled to the bit line and to a power supply voltage terminal for receiving a power supply voltage, wherein the reference voltage is less than the power supply voltage.

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Номер записи: 7
28-06-2012 дата публикации

Complementary read-only memory (rom) cell and method for manufacturing the same

Номер: US20120163063A1
Автор: Jitendra Dasani
Принадлежит: STMICROELECTRONICS PVT LTD

A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

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Номер записи: 8
05-07-2012 дата публикации

Semiconductor device

Номер: US20120169402A1
Автор: Katsuya Arai, Masanori Shirahama, Toshiaki Kawasaki, Toshihiro Kougami, Yasuhiro Agata
Принадлежит: Panasonic Corp

A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

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Номер записи: 9
23-08-2012 дата публикации

Semiconductor device and operation method thereof

Номер: US20120212991A1
Автор: Matsuo Iwasaki, Shigeru Kanematsu, Yuki Yanagisawa
Принадлежит: Sony Corp

An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.

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Номер записи: 10
23-08-2012 дата публикации

Write control circuit and semiconductor device

Номер: US20120213014A1
Автор: Jun Nagayama, Masahito Isoda, Tomoharu Awaya, Tsuyoshi Koyashiki
Принадлежит: Fujitsu Semiconductor Ltd

In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.

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Номер записи: 11
20-09-2012 дата публикации

Program cycle skip

Номер: US20120236663A1
Автор: Gopinath Balakrishnan, Luca Fasoli, Tz-yi Liu, Yan Li, Yuheng Zhang
Принадлежит: SanDisk 3D LLC

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

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Номер записи: 12
13-12-2012 дата публикации

Non-volatile memory device having phase-change material and method for fabricating the same

Номер: US20120314492A1
Автор: Ji-Won Jung, Yong-Shik Shin
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory cells. In the non-volatile memory device, a circuit of the at least one second memory cell is cut off according to the initial information, and the initial information is defective block information that is information about a defect of the plurality of memory blocks.

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Номер записи: 13
10-01-2013 дата публикации

Storage of an image in an integrated circuit

Номер: US20130011944A1
Автор: Fabrice Marinet, Pascal Fornara
Принадлежит: STMICROELECTRONICS ROUSSET SAS

An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.

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Номер записи: 14
24-01-2013 дата публикации

Anti-fuse circuit

Номер: US20130021854A1
Автор: Ming-Chien Huang
Принадлежит: Elite Semiconductor Memory Technology Inc

An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation.

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Номер записи: 15
21-03-2013 дата публикации

Semiconductor memory device correcting fuse data and method of operating the same

Номер: US20130070548A1
Автор: Byung-Hoon Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.

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Номер записи: 16
28-03-2013 дата публикации

Semiconductor device with otp memory cell

Номер: US20130077377A1
Автор: Tae Hoon Kim
Принадлежит: SK hynix Inc

A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor.

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Номер записи: 17
23-05-2013 дата публикации

Redundant Via Structure For Metal Fuse Applications

Номер: US20130127584A1
Автор: Andrew H. Simon, Griselda Bonilla, Kaushik Chanda, Naftali E. Lustig, Ronald G. Filippi, Samuel S. Choi, Stephan Grunow
Принадлежит: International Business Machines Corp

A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes: a first dielectric layer having a metal feature; a second dielectric layer having a first metal connector embedded therein; and a third dielectric layer having a second metal connector embedded therein. The metal connectors include at least one via and one line, and at least one metal connector has at least two vias.

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Номер записи: 18
13-06-2013 дата публикации

Antifuse-based memory cells having multiple memory states and methods of forming the same

Номер: US20130148404A1
Автор: Abhijit Bandyopadhyay, Peter Rabkin, Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

In some aspects, a memory cell is provided that includes a steering element and a metal-insulator-metal (“MIM”) stack coupled in series with the steering element. The MIM stack includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, without a metal or other conductive layer disposed between the first dielectric material layer and the second dielectric material layer. Numerous other aspects are provided.

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Номер записи: 19
20-06-2013 дата публикации

ELECTRICAL FUSE MEMORY

Номер: US20130155799A1
Автор: HSU Kuoyuan (Peter), HUANG Jiann-Tseng, LIAO Wei-Li, LIN Sung-Chieh, Yen David
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on. 1. A method of reading an eFuse in a column of eFuse memory cells , the method comprising:electrically disconnecting a first end of the eFuse from a first electrical path;activating a second electrical path between a second end of the eFuse and a node to bypass a third electrical path, the third electrical path comprising a diode device between the second end of the eFuse and the node; andturning on a footer coupled with the node.2. The method of claim 1 , wherein the activating the second electrical path comprises turning on a transistor coupled between the second end of the eFuse and the node.3. The method of claim 2 , wherein the transistor is an N-type transistor claim 2 , and the turning on the transistor comprises setting a voltage level at a gate terminal of the N-type transistor at a logic high level.4. The method of claim 1 , wherein the electrically disconnecting the first end of the eFuse from the first electrical path comprises turning off a transistor coupled between the first end of the eFuse and the first electrical path.5. The method of claim 4 , wherein the transistor is a P-type transistor claim 4 , and the turning off the transistor comprises setting a voltage level at a gate terminal of the P-type transistor at a logic high level.6. The method of claim 1 , wherein the footer is an N-type transistor claim 1 , and the turning on the footer comprises setting a voltage level at a gate terminal of the N-type transistor at a logic high level.7. The method of claim 1 , further comprising:turning on a sense amplifier to sense a voltage ...

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Номер записи: 20
11-07-2013 дата публикации

One-time programable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof

Номер: US20130176765A1
Автор: Hiroyuki Furukawa, Isao Naritake
Принадлежит: Renesas Electronics Corp

Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state.

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Номер записи: 21
11-07-2013 дата публикации

METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES

Номер: US20130176805A1
Автор: Chanda Kaushik, Gignac Lynne M., Li Wai-Kin, Wang Ping-Chuan
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. 1. A method for programming and reprogramming an electrically reprogrammable fuse , the method comprising:programming the electrically reprogrammable fuse by inducing an electron current from a first programming wire through an interconnect to a second programming wire operative to effect electromigration in the interconnect, such that a void is formed between the interconnect and a sensing wire; andreprogramming the electrically reprogrammable fuse by inducing an electron current from the second programming wire through the interconnect to the first programming wire operative to effect electromigration in the interconnect, such that the interconnect contacts the sensing wire.2. The method for programming and reprogramming the electrically reprogrammable fuse of claim 1 , wherein the method further comprises determining whether the void exists between the interconnect and the sensing wire by inducing an electron current between the sensing wire and the second programming wire.3. The method for programming and reprogramming the electrically reprogrammable fuse of claim 2 , wherein if the void is determined to not exist claim 2 , repeating the programming step.4. ...

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Номер записи: 22
25-07-2013 дата публикации

Method and apparatus for testing one time programmable (otp) arrays

Номер: US20130188410A1
Автор: Amer Christophe G. Cassier, Anil C. Kota, Gregory A. Uvieghara
Принадлежит: Qualcomm Inc

An array of one time programmable (OTP) devices includes a first set of pre-configurable memory devices appended to one or more columns of me array and a second set of pre-configurable memory devices appended to one or more rows of the array. The pre-configurable memory devices may be additional OTP devices or read only memory (ROM) devices that can be configured to store a predetermined test pattern for the array. Rows, columns and functionalities of the array can be tested based on the stored test pattern. OTP devices in the array may then be programmed after successful testing based on the test pattern stored.

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Номер записи: 23
01-08-2013 дата публикации

Spurious induced charge cleanup for one time programmable (otp) memory

Номер: US20130194885A1
Автор: Jack Z. Peng
Принадлежит: Jack Z. Peng

A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.

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Номер записи: 24
08-08-2013 дата публикации

Circuit and System of a Low Density One-Time Programmable Memory

Номер: US20130201745A1
Автор: Chung Shine C.
Принадлежит:

A low density One-Time Programmable (OTP) memory is disclosed to achieve low gate count and low overhead in the peripheral circuits to save the cost. A maximum-length Linear Feedback Shift Register (LFSR) can be used to generate 2−1 address spaces from an n-bit address. The registers used in the address generator can have two latches. Each latch has two cross-coupled inverters with two outputs coupled to the drains of two MOS input devices, respectively. The inputs of the latch are coupled to the gates of the MOS input devices, respectively. The sources of the MOS input devices are coupled to the drains of at least one MOS device(s), whose gate(s) are coupled to a clock signal and whose source(s) are coupled to a supply voltage. The two latches can be constructed in serial with the outputs of the first latch coupled to the inputs of the second latch. 1. A One-Time Programmable (OTP) memory , comprising: an OTP element fabricated in standard CMOS process;', 'at least one address generator having a plurality of registers constructed as shift registers with the last shift register coupled to the first shift register and operating at each clock cycle; and', 'at least one Exclusive OR (XOR) or equivalent gate being coupled as an input to a shift register and an output from a second shift register, while the other input of the XOR being coupled to a third shift register, and, 'a plurality of OTP cells, at least one of the OTP cells comprisingwherein the output of the shift registers being used as an address to access the OTP memory in each clock cycle.2. An OTP memory as recited in claim 1 , wherein the address generator is a Linear Feedback Shift Register (LFSR) with maximum length to generate 2−1 address spaces from an n-bit address.3. An OTP memory as recited in claim 1 , wherein the address generator is a Linear Feedback Shift Register (LFSR) with maximum length to generate 2−1 address spaces from an n-bit address and has the last state coupled between any states to ...

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Номер записи: 25
08-08-2013 дата публикации

CIRCUIT AND SYSTEM FOR TESTING A ONE-TIME PROGRAMMABLE (OTP) MEMORY

Номер: US20130201746A1
Автор: Chung Shine C.
Принадлежит:

Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array. 1. A One-Time Programmable (OTP) memory , comprising: an OTP element with one end coupled to a program selector and another end coupled to a bitline (BL); and', 'a program selector with an enable signal coupled to a wordline (WL),', 'the OTP cells being organized as a two-dimensional array with the WLs of the OTP cells in the same rows coupled to a WL and the BLs of the OTP cells in the same columns coupled to a BL;, 'a plurality of OTP cells, at least one of the OTP cells comprisingat least one sense amplifiers coupled to at least one BLs to generate a logic state;at least one row or column decoders to select one row or one column from the OTP memory; andat least one control signals coupled to the row or column decoders to turn on or off any adjacent rows or columns,wherein test patterns can be generated with alternative logic 0 and 1 states by setting a combination of the control signals to turn on at least one row or columns through at least one sense amplifiers to read from at least one OTP cells.2. An OTP memory as recited in claim 1 , wherein the control signals are coupled to at least one address buffers claim 1 , which are coupled to a row or column decoder.3. An OTP memory as recited in claim 1 , wherein the sense amplifier has a plurality of reference resistors for select.4. An OTP memory as recited in claim 1 , wherein the sense amplifier has a test device that has a ...

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Номер записи: 26
08-08-2013 дата публикации

PERMANENT SOLID STATE MEMORY USING CARBON-BASED OR METALLIC FUSES

Номер: US20130201747A1
Автор: Davis Robert C., Linford Matthew R., Lunt Barry M., Pearson Anthony
Принадлежит: BRIGHAM YOUNG UNIVERSITY

A permanent solid state memory device is disclosed. Recording data in the permanent solid state memory device forms voids in a data layer between a first wire array and a second wire array. Wires of the first wire array extend transversely to wires in the second wire array. The material is made of a carbon allotrope such that when current is passed through the carbon allotrope, the carbon is quickly oxidized (burned) leaving a complete gap (void) where the fuse once was. One of the advantages of this method is that the fuse material is fully oxidized in the particular “neck region of the bowtie”, such that there is no material left over from which dendrites can grow. In other embodiments, the data layer is a metal or metal oxide selected from the following metals: Tungsten (W), Rhenium (Rh), Osmium (Os), Iridium (Ir), Molybdenum (Mo), Ruthenium (Ru), Rhodium (Rh), Chromium (Cr), and Manganese (Mn). 1. A solid state memory device , comprising:at least one first array of wires in a first layer;at least one second array of wires extending transverse to the first array of wires in a second layer that is generally parallel to the first layer; andat least one data layer disposed between the first layer and the second layer such that a voltage applied to a first wire in the first array and to a second wire in the second array heats the data layer at a location between the first wire and the second wire and forms a data point comprising a void when data is written to the solid state memory device,wherein the data layer is an allotrope of carbon or a metal, a metal alloy, or a metallic oxide comprising one or more of the following metals: Tungsten (W), Rhenium (Rh), Osmium (Os), Iridium (Ir), Molybdenum (Mo), Ruthenium (Ru), Rhodium (Rh), Chromium (Cr), and Manganese (Mn).2. The solid state memory device of claim 1 , wherein the data layer is an allotrope of carbon selected from the group consisting of single-wall nanotubes claim 1 , multi-wall nanotubes claim 1 , graphene ...

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Номер записи: 27
15-08-2013 дата публикации

SOFT BREAKDOWN MODE, LOW VOLTAGE, LOW POWER ANTIFUSE-BASED NON-VOLATILE MEMORY CELL

Номер: US20130208525A1
Автор: FONG David, Peng Jack Z.
Принадлежит:

A non-volatile memory cell uses two transistors only, a bit select and a sense device. Each cell further comprises an antifuse device implemented, for example, with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and under 5-μA is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt. 1. A non-volatile memory (NVM) cell , comprising:an antifuse element configured in series between a word control line WP, the source-drain of a bit-select transistor, and a column bit line BL, wherein the bit select transistor is connected by its gate to a word select control line WS, and wherein the antifuse element will open in its unprogrammed state and present less than 10M ohms in its programmed state;a sensing node at a junction between the antifuse element and the bit select transistor;a sensing transistor connected by its gate to the sensing node and by its source and drain between the column bit line BL and a column bit read line BR;wherein, any current passing through the antifuse element will appear as a voltage drop at the sensing node, and such voltage at the sensing node can act to control the sensing transistor; andwherein, the antifuse and sensing transistor are configured such that less than 5-μA of current is needing for permanent programming.2. The non-volatile memory cell of claim 1 , further comprising:at least one device configured for current limiting.3. The non-volatile memory cell of claim 1 , wherein:the antifuse element is a field effect transistor and any current passing through it on a read cycle is an indication of its programmed logic level, or data content.4. The non-volatile memory cell of claim 1 , further comprising:the antifuse element is a field effect transistor ...

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Номер записи: 28
29-08-2013 дата публикации

VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING AND DRIVING THE SAME

Номер: US20130223124A1
Автор: Do Gap Sok, Park Nam Kyun
Принадлежит: SK HYNIX INC.

Provided are a variable resistive memory device, and methods of fabricating and driving the same. The variable resistive memory device includes a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor. A common wiring is electrically connected to first ends of the plurality of memory cells to apply a common reference voltage. Each wiring line of a plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged n the plurality of rows oriented in the first direction. A plurality of selection lines are respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines. 1. A variable resistive memory device comprising:a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor;a common wiring electrically connected to first ends of the plurality of memory cells to apply a common reference voltage;a plurality of wiring lines, wherein each wiring line of the plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged n the plurality of rows oriented in the first direction; anda plurality of selection lines respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines.2. The variable resistive memory device of claim 1 , wherein the common wiring comprises a plurality of sub-lines electrically connected to one another.3. The variable resistive memory device of claim 1 , wherein the common ...

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Номер записи: 29
29-08-2013 дата публикации

Semiconductor Device Capable of Rescuing Defective Characteristics Occurring After Packaging

Номер: US20130223171A1
Автор: Jeong-Kyoum Kim, Jung-hwan Choi, Seok-Hun Hyun, Seong-Jin Jang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

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Номер записи: 30
12-09-2013 дата публикации

Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same

Номер: US20130234104A1
Автор: Scott Brad Herner
Принадлежит: SanDisk 3D LLC

A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the second stiffness is greater than the first stiffness, and forming a memory element coupled to the steering element pillar. Numerous other aspects are provided.

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Номер записи: 31
12-09-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING A FUSE

Номер: US20130235643A1
Автор: FURUKAWA Hiroyuki
Принадлежит: RENESAS ELECTRONICS CORPORATION

A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region. 1. A semiconductor device comprising:a chip;a SRAM formed on the chip;an active region including a core circuit forming region and a buffer forming region on the chip;a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused; anda pad forming region to be arranged around the buffer forming region,wherein the active region, the fuse element and the pad forming region are arranged on the chip,the fuse element is coupled to the SRAM,the fuse element is coupled to a first pad and a second pad in the pad forming region,the first pad is opened to an external terminal,andthe second pad is bonded to the external terminal by a wire bonding.2. The semiconductor device according to claim 1 ,wherein the first pad and the second pad are formed near the corner of the active region.3. The semiconductor device according to claim 1 ,wherein the first pad is arranged closer to a corner of the chip than the second pad,the corner of the chip is closest corner from the fuse element.4. The semiconductor device according to claim 1 , further comprising:a wire for fusing connected to a fuse element of the fuse element forming region,wherein the wire for fusing being formed in several wire layers arranged in an upper layer of the corner of the chip.5. The semiconductor device according to claim 1 , further comprising:a first group of buffers being arranged to first direction parallel to first side of the chip; anda second group of buffers being arranged to second direction intersect with the first direction and parallel to ...

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Номер записи: 32
12-09-2013 дата публикации

Semiconductor memory device

Номер: US20130235645A1
Автор: Toshihiko Saito
Принадлежит: Semiconductor Energy Laboratory Co Ltd

To provide a semiconductor memory device including an oxide semiconductor that can deal with instability of a threshold characteristic, in which writing is possible by a simple method. The semiconductor memory device functions by utilizing a characteristic that a threshold shifts when a thin film transistor including an oxide semiconductor is irradiated with ultraviolet light. Readout can be performed by setting a readout voltage between the threshold before the ultraviolet light irradiation and the threshold after irradiation. The threshold characteristic of an initial characteristic can be controlled by providing a back gate or by using two thin film transistors.

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Номер записи: 33
26-09-2013 дата публикации

Multi-Time Programmable Memory

Номер: US20130250647A1
Автор: BUER Myron
Принадлежит: BROADCOM CORPORATION

Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip (SoC) products. 1. A method for programming a memory element comprised of a poly diode anti-fuse coupled in parallel with a poly fuse , comprising:applying a first current between a first terminal and a second terminal of the memory element, wherein the first current is configured to open the poly fuse to transition the memory element from an initial programming state to a first programming state, and wherein a first impedance of the memory element in the first programming state is higher than an initial impedance of the memory element in the initial programming state.2. The method of claim 1 , wherein the memory element is equivalent to a short circuit between the first terminal and the second terminal in the initial programming state.3. The method of claim 1 , wherein the first impedance of the memory element is provided by the poly diode anti-fuse in the first programming state.4. The method of claim 1 , further comprising:applying a voltage across the first terminal and the second terminal, wherein the voltage is configured to highly reverse bias the poly diode anti-fuse to transition the memory element from the first programming state to a second programming state.5. The method of claim 4 , wherein a second impedance of the memory element in the second programming state is lower than the first impedance of the memory element in the first programming state.6. The method of claim 5 , wherein the second impedance of the memory element is provided by the poly diode anti-fuse in the second programming state.7. The method of claim 4 , further comprising:applying a second current between the first ...

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Номер записи: 34
03-10-2013 дата публикации

Small-Grain Three-Dimensional Memory

Номер: US20130258740A1
Автор: Guobiao Zhang
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.

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Номер записи: 35
03-10-2013 дата публикации

FUSE DATA READING CIRCUIT HAVING MULTIPLE READING MODES AND RELATED DEVICES, SYSTEMS AND METHODS

Номер: US20130258748A1
Автор: JANG SEONG-JIN, KIM GIL-SU, OH JONG-MIN, RYU JE-MIN, SEO Sung-Min
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit. 1. A fuse data reading circuit comprising:a fuse array including a plurality of fuse cells configured to store fuse data;a sensing circuit configured to sense the fuse data stored in the fuse cells of the fuse array; anda controller configured to control reading of the fuse data stored in the fuse cells, the controller being configured to control reading of the fuse data with a first reading mode having first fuse data sensing conditions and to control reading of the fuse data with a second reading mode having second fuse data sensing conditions different from the first fuse data sensing conditions, the controller being configured to select the first reading mode and second reading mode according to an operation period of the fuse data reading circuit.2. The circuit of claim 1 ,wherein the controller is configured to control reading in the first reading mode during a transition period that occurs directly after the fuse data reading operation is enabled, and controller is configured to control reading in the second reading mode during a stabilized period that comes after the transition period, andwherein the first fuse data sensing conditions cause higher sensitivity for sensing the fuse data during the transition period as compared to sensitivity for sensing the fuse data during the stabilized period ...

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Номер записи: 36
10-10-2013 дата публикации

METHOD OF READING DATA STORED IN FUSE DEVICE AND APPARATUSES USING THE SAME

Номер: US20130265815A1
Автор: Jang Seong Jin, Kim Gil Su, Oh Jong Min, Seo Sung Min
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method for reading data stored in a fuse device included in a memory device including a memory cell array is provided. The method comprises reading trimming data of the fuse device, wherein the trimming data is related to trimming a level of voltage or a level of current used for an operation of the memory device; and after the reading the trimming data, reading defective cell address data of the fuse device, wherein the defective cell address data is related to defective cells in the memory cell array. 1. A method for reading data stored in a fuse device included in a memory device including a memory cell array , the method comprising:reading trimming data, wherein the trimming data is related to trimming of a level of voltage or a level of current used for an operation of the memory device, from the fuse device; andafter the reading the trimming data, reading defective cell address data, wherein the defective cell address data is related to defective cells in the memory cell array, from the fuse device.2. The method of claim 1 , further comprising reading mode register set (MRS) data claim 1 , which is related to setting of a mode register included in the memory device claim 1 , from the fuse device after the reading the trimming data.3. The method of claim 2 , wherein the defective cell address data is read after the MRS data is read.4. The method of claim 1 , further comprising claim 1 , before the reading the defective cell address data claim 1 , reading mode register set (MRS) data from the fuse device claim 1 , wherein the MRS data is related to setting of a mode register included in the memory device.5. The method of claim 4 , wherein reading the MRS data and reading the trimming data are performed in parallel.6. The method of claim 1 , wherein the fuse device includes a plurality of anti-fuse cells.7. A method for reading data stored in a fuse cell array of a memory device comprising a memory cell array claim 1 , the method comprising:reading a first data ...

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Номер записи: 37
17-10-2013 дата публикации

NON-VOLATILE MEMORY, SEMICONDUCTOR DEVICE AND READING METHOD

Номер: US20130272050A1
Автор: OTSUKA Masayuki
Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector. 1. A non-volatile memory circuit comprising:a plurality of storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; andwherein cathodes of respective zener zap devices of the plurality of storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading,wherein the output terminals of the plurality of storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, andwherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector.2. The non-volatile memory circuit of claim 1 , wherein the detector comprises a conversion section that converts a current value claim 1 , that is output when the storage element section that is the target for reading out of the ...

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Номер записи: 38
17-10-2013 дата публикации

NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE

Номер: US20130272051A1
Автор: OTSUKA Masayuki
Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices. 1. A non-volatile memory comprising:a plurality of zener zap devices, each including a cathode region and an anode region formed in a well; anda metal wiring line that is formed above the plurality of zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices.2. The non-volatile memory of claim 1 , wherein the metal wiring line is formed so as to cover at least the cathode region and the anode region formed in the well.3. The non-volatile memory of claim 1 , wherein each of the plurality of zener zap devices is provided with two cathode regions and one anode region formed between the two cathode regions claim 1 , and one of the two cathode regions is commonly shared with an adjacent zener zap device.4. The non-volatile memory of claim 1 , wherein a dual-presence region is provided between the cathode region and the anode region where both a cathode region and an anode region are present.5. The non-volatile memory of claim 4 , wherein the metal wiring line is formed so as to cover at least the dual-presence region.6. The non-volatile memory of claim 1 , wherein the metal wiring line is formed in a layer above a layer of wiring connecting the anode region.7. The non-volatile memory of claim 1 , further comprising a transistor with one end connected to a ground line claim 1 , another end connected to an anode of the zener zap device claim 1 , and the ground line formed adjacent to the metal wiring line.8. The non-volatile memory of claim 1 , further comprising:a first zener zap device group configured by the plurality of zener zap devices ...

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Номер записи: 39
17-10-2013 дата публикации

MEMORY ADDRESS REPAIR WITHOUT ENABLE FUSES

Номер: US20130272075A1
Автор: Blodgett Greg
Принадлежит:

A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims. 1. A circuit for use in a memory device , comprising:a plurality of fuse elements each representing a bit of an address; anda first plurality of logic gates responsive to said plurality of fuse elements for producing sensed states of said fuse elements corresponding to bits of an internal memory address signal and for producing an enable signal from at least one address bit.2. A memory device , comprising:a plurality of fuse elements, a fuse element of the plurality of fuse elements representing a respective bit of an address; anda plurality of logic gates configured to produce sensed states of the plurality of fuse elements corresponding to bits of an internal memory address signal, the plurality of logic gates further configured to produce an enable signal from at least one address bit.3. The memory device of claim 2 , wherein the plurality of logic gates includes gates for comparing a perceived state of the plurality of fuse elements with a corresponding external memory address signal bit to detect a match.4. The memory device of claim 2 , further comprising a circuit for ...

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Номер записи: 40
24-10-2013 дата публикации

E-FUSE ARRAY CIRCUIT

Номер: US20130279282A1
Автор: KIM Kwi-Dong
Принадлежит: SK HYNIX INC.

An e-fuse array circuit includes a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line, a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor, a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line, and a second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor. 1. An e-fuse array circuit comprising:a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line;a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor;a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line; anda second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor.2. The e-fuse array circuit of claim 1 , further comprising:a third select transistor configured to have a gate terminal connected to the first select line and have a first terminal connected to a second bit line;a third e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the third select transistor;a fourth select transistor configured to have a gate terminal connected to the second select line and have a first terminal connected to the ...

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Номер записи: 41
31-10-2013 дата публикации

Redundancy control circuit and memory device including the same

Номер: US20130286758A1
Автор: Byung-Chul Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level. The address fuse circuit is configured to generate a first address using the first fuses based on a cutting operation that depends on the result of comparing. The first circuit is configured to output either the first address or a second address that is an inverted address of the first address as a repair address, wherein a logic level of each of bits of the repair address is the same as that of the defective input address.

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Номер записи: 42
07-11-2013 дата публикации

ANTI-FUSE CIRCUIT IN WHICH ANTI-FUSE CELL DATA IS MONITORED, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20130294140A1
Автор: JANG SEONG-JIN, OH JONG-MIN, Song Ho-Young
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal. 1. An anti-fuse circuit , comprising:an anti-fuse array including one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells, the anti-fuse array configured to store anti-fuse program data;a data storage circuit configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses; anda first selecting circuit configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.2. The anti-fuse circuit according to claim 1 , wherein the first selecting circuit is configured to output selected anti-fuse program data of the selected anti-fuse block through an output pad.3. The anti-fuse circuit according to claim 1 , wherein the anti-fuse program data is configured to be monitored outside of the anti-fuse circuit while the anti-fuse program data is transmitted from the anti-fuse array to the data storage circuit.4. The anti-fuse circuit according to claim 1 , wherein the first selection signal is generated based on a test mode command.5. The anti-fuse circuit according to claim 4 , wherein the anti-fuse ...

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Номер записи: 43
07-11-2013 дата публикации

MEMORY DEVICE INCLUDING ANTIFUSE MEMORY CELL ARRAY AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE

Номер: US20130294141A1
Автор: Kim Joung-Yeal, KIM Soo-Young, KIM Sung-Hoon, Lee Ho-Cheol, Oh Se-Il
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory device includes a memory cell array, a column decoder, and a row decoder. The row decoder includes a first word line driver and a second word line driver. The first word line driver is configured to electrically coupled to a first set of antifuse memory cells coupled to a first word line. The second word line driver is configured to electrically coupled to a second set of antifuse memory cells coupled to a second word line. The first set of antifuse memory cells are arranged in first and third rows of the memory cell array, and the second set of antifuse memory cells are arranged in second and fourth rows of the memory cell array. The second row is arranged between the first and third rows. 1. A memory device including a memory cell array including a plurality of antifuse memory cells electrically coupled to a plurality of bit lines and a plurality of word lines , the memory device comprising:a column decoder configured to select one bit line among the plurality of bit lines; anda row decoder configured to select one word line among the plurality of word lines, a first word line driver configured to output a first word line selection signal to a first word line, the first word line driver electrically coupled to a first set of antifuse memory cells coupled to the first word line; and', 'a second word line driver configured to output a second word line selection signal to a second word line, the second word line driver electrically coupled to a second set of antifuse memory cells coupled to the second word line,, 'wherein the row decoder compriseswherein the first set of antifuse memory cells are arranged in first and third rows of the memory cell array, and the second set of antifuse memory cells are arranged in second and fourth rows of the memory cell array, the second row being arranged between the first and third rows.2. The memory device of claim 1 , wherein the column decoder is arranged at a first side of the memory cell array claim 1 , andwherein ...

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Номер записи: 44
07-11-2013 дата публикации

METHOD FOR CONTROLLING THE BREAKDOWN OF AN ANTIFUSE MEMORY CELL

Номер: US20130294142A1
Автор: Candelier Philippe, Damiens Joel, Leroux Elise
Принадлежит:

A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time. 1. A method , comprising: applying a programming voltage to a terminal of the antifuse memory cell;', 'detecting a breakdown in the antifuse memory cell, the detecting including detecting a current generated in the substrate; and', 'interrupting the applying of the programming voltage after a time period after detecting the breakdown., 'controlling an antifuse memory cell formed on a semiconductor substrate, the controlling including2. The method of wherein the breakdown is associated with a first threshold current and the time period is associated with a second threshold current that is determined by testing a plurality of antifuse memory cells of determined characteristics.3. The method of wherein the second conductivity type is opposite to that of the first conductivity type and wherein the antifuse is formed above a well surrounded with a peripheral insulator claim 1 , the lower surface of the well being laid on a buried layer of a conductivity type opposite to that of the well contacted by a peripheral N-type wall extending from the surface of the component claim 1 , the antifuse being formed above a region adjacent to one or several MOS transistors connected to a reference terminal claim 1 , wherein the detection of the breakdown time is performed by detection of the current generated in the substrate.4. The method of wherein the substrate includes a plurality of MOS transistors claim 3 , the antifuse memory cell being formed above a region that is adjacent to the plurality of MOS transistors claim 3 , at least one of the MOS transistors being electrically coupled to a reference terminal5. The method of wherein detecting the breakdown includes detecting ...

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Номер записи: 45
07-11-2013 дата публикации

Built-In Self Test for One-Time-Programmable Memory

Номер: US20130294143A1
Автор: Kelly Thomas W., Lee James M., Samuels Howard R.
Принадлежит:

An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly. 1. A method of testing one-time-programmable memory , the method comprising:providing one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location, each programming circuitry having a circuit element configured to permanently change state to store the data in the memory;reading each memory location to verify that the memory location is unprogrammed;activating the programming circuitry for each memory location, wherein activating includes applying a test signal to the programming circuitry, the test signal amplitude less than a threshold signal amplitude needed to permanently change the state of the circuit element; anddetermining whether the programming circuitry is functioning properly.2. The method as defined by wherein activating the programming circuitry comprises:limiting the test signal through the one-time-programmable memory to a low amplitude signal, the one-time-programmable memory having the circuit element configured to permanently change state upon receipt of a signal having a threshold amplitude, the low amplitude signal being less than the threshold amplitude;using programming signal assertion circuitry to ...

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Номер записи: 46
21-11-2013 дата публикации

POWER UP DETECTION SYSTEM FOR A MEMORY DEVICE

Номер: US20130308364A1
Автор: Smith Steven
Принадлежит: SIDENSE CORP.

A power up detection method for a memory device and a memory device are disclosed. In a first phase, a test word is read from a read-only memory (ROM) row of a memory array of the memory device, and the test word is compared to predetermined ROM row data. If the test word matches the predetermined ROM row data, a second phase may be performed. In the second phase, first user data is read from a user-programmed row of the memory array at a first time. Second user data is read from the user-programmed row of the memory array at a second time different from the first time. The first user data is compared to the second user data. Successful power up of the memory device is determined when the first user data matches the second user data. 1. A power up detection method for a memory device , the method comprising:a) reading a test word from a read-only memory (ROM) row of a memory array of the memory device;b) comparing the test word to predetermined ROM row data; c.1) reading first user data from a user-programmed row of the memory array at a first time;', 'c.2) reading second user data from the user-programmed row of the memory array at a second time different from the first time; and', 'c.3) comparing the first user data to the second user data,, 'c) if the test word matches the predetermined ROM row datawherein power up of the memory device is detected when the first user data matches the second user data.2. The power up detection method according to further comprising: d.1) waiting a predetermined wait time; and', 'd.2) repeating a) to d)., 'd) if at least one bit of the test word mismatches a corresponding bit of the predetermined ROM row data3. The power up detection method according to further comprising: c.4.1) waiting a predetermined wait time; and', 'c.4.2) repeating a) to c)., 'c.4) if at least one bit of the first user data mismatches a corresponding bit of the second user data4. The power up detection method according to further comprising:c.4) if the first ...

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Номер записи: 47
21-11-2013 дата публикации

CIRCUIT AND METHOD FOR REDUCING WRITE DISTURB IN A NON-VOLATILE MEMORY DEVICE

Номер: US20130308365A1
Автор: Smith Steven
Принадлежит: SIDENSE CORP.

An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to each of the bitlines in a precharge operation and a following programming operation. In the programming operation, a bitline connected to a memory cell to be programmed is driven to a programming level, such as VSS, while the active precharge circuit is enabled to enable programming thereof. Because the other non-selected bitlines are held at the program inhibit voltage level, they will not be inadvertently programmed when the programming voltage is supplied by the word line. 1. A one-time programmable (OTP) memory comprising:OTP memory cells connected to bitlines and wordlines;a precharge circuit for biasing non-selected bitlines at a program inhibit voltage in a programming operation; and,a write circuit configured for driving a selected bitline to a voltage level for enabling programming of an OTP memory cell connected to the selected bitline when a selected wordline is driven to a programming voltage level.2. The OTP memory of claim 1 , wherein the precharge circuit includes an active precharge current source receiving the program inhibit voltage connected to each of the bitlines claim 1 , and configured to operate in a low current mode during a precharge operation prior to the programming operation claim 1 , and to operate in the low current mode during the programming operation.3. The OTP memory of claim 2 , wherein the write circuit includes a sense amplifier for storing write data claim 2 , the sense amplifier including discharge circuitry configured to overwrite the program inhibit voltage of the selected bitline.4. The OTP memory of claim 1 , wherein the precharge circuit is configured to operate in a high current mode during a ...

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Номер записи: 48
21-11-2013 дата публикации

Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices

Номер: US20130308366A1
Автор: Chung Shine C.
Принадлежит:

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact. 1. A One-Time Programmable (OTP) memory , comprising: an OTP element coupled to a first supply voltage line;', 'a diode including at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a second type of dopant, the first active region associated with a first terminal of the diode, the second active region associated with a second terminal of the diode, both the first and second active regions residing in a common well, the first active region coupled to the OTP element and the second active region coupled to a second supply voltage line,, 'a plurality of OTP cells, at least one of the cells comprisingwherein the first and second active regions being fabricated from sources or drains of CMOS devices, and the well is fabricated from wells in CMOS technologies, andwherein the OTP element is configured to be programmable ...

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Номер записи: 49
28-11-2013 дата публикации

PILLAR-SHAPED NONVOLATILE MEMORY AND METHOD OF FABRICATION

Номер: US20130314970A1
Автор: Cleeves James M., Farmwald Paul Michael, Johnson Mark G., Lee Thomas H., Subramanian Vivek
Принадлежит: SanDisk 3D LLC

A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided. 1. A pillar-shaped memory cell comprising:a steering element; anda non-volatile state change element coupled in series with the steering element.2. The pillar-shaped memory cell of claim 1 , wherein the steering element comprises a p-n diode claim 1 , a p-i-n diode or a Schottky diode.3. The pillar-shaped memory cell of claim 1 , wherein the state change element comprises a reversible resistance-switching element.4. The pillar-shaped memory cell of claim 1 , wherein the state change element is capable of having more than two resistance states.5. The pillar-shaped memory cell of claim 1 , wherein the state change element is rewriteable.6. The pillar-shaped memory cell of claim 1 , wherein the state change element comprises a multi-state antifuse.7. A three-dimensional memory array including:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a first memory level comprising a first plurality of the pillar-shaped memory cells of ; and'}{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a second memory level disposed vertically above the first memory level, the second memory level comprising a second plurality of the pillar-shaped memory cells of .'}8. A method of forming a pillar-shaped memory cell claim 1 , the method comprising:forming a steering element; andforming a non-volatile state change element in series with the steering element.9. The method of claim 8 , wherein the steering element comprises a p-n diode claim 8 , a p-i-n diode or a Schottky diode.10. The method of claim 8 , wherein the state change element comprises a reversible resistance-switching element.11. The method of claim 8 , wherein the state change element is capable of having more than two resistance states.12. The method of claim 8 , wherein the state change element is rewriteable.13. The method of claim 8 ...

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Номер записи: 50
05-12-2013 дата публикации

MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE

Номер: US20130322149A1
Автор: CHO YONG-HO, KIM GIL-SU, OH JONG-MIN, RYU JE-MIN, SEO Sung-Min, Song Ho-Young
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively. 1. A memory device including a memory cell array , the memory device comprising:a fuse device including a fuse cell array and a fuse control circuit, a first fuse cell sub-array configured to store first data associated with operation of the fuse control circuit; and', 'a second fuse cell sub-array configured to store second data associated with operation of the memory device,, 'wherein the fuse cell array compriseswherein the fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.2. The memory device of claim 1 , wherein the fuse control circuit comprises a fuse device setting circuit configured to set the operation conditions of the fuse device based on the first data read from the first fuse cell sub-array.3. The memory device of claim 2 , wherein the fuse control circuit further comprises:an access control circuit configured to select the first and second data from the first and second fuse cell array, respectively;a sense amplifier configured to sense and amplify the selected first and second data; anda transmission circuit configured to transmit the amplified first data to the fuse device setting circuit, and to transmit the amplified second data to the memory control circuit.4. The memory device of claim 3 , wherein the first data ...

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Номер записи: 51
02-01-2014 дата публикации

Integrated circuit device featuring an antifuse and method of making same

Номер: US20140001568A1
Автор: John J. Zhu, Xia Li, Zhongze Wang
Принадлежит: Qualcomm Inc

One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage V pp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.

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Номер записи: 52
16-01-2014 дата публикации

Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse

Номер: US20140015096A1
Автор: Eun Sung Lee
Принадлежит: SK hynix Inc

An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. As a result, the fuse can be highly integrated through the above-mentioned structure, and programming of the fuse can be easily achieved.

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Номер записи: 53
16-01-2014 дата публикации

Large Bit-Per-Cell Three-Dimensional Mask-Programmable Read-Only Memory

Номер: US20140015103A1
Автор: Guobiao Zhang
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

A large bit-per-cell three-dimensional mask-programmable read-only memory (3D-MPROM B ) is disclosed. It can achieve large bit-per-cell (e.g. 4-bpc or more). 3D-MPROM B can be realized by adding resistive layer(s) or resistive element(s) to the memory cells.

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Номер записи: 54
16-01-2014 дата публикации

CCIRCUIT AND SYSTEM OF USING JUNCTION DIODE AS PROGRAM SELECTOR FOR METAL FUSES FOR ONE-TIME PROGRAMMABLE DEVICES

Номер: US20140016394A1
Автор: Chung Shine C.
Принадлежит:

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices. An OTP device can have at least one OTP element coupled to at least one diode in a memory cell. With a metal fuse is used by the OTP element, at least one contact and/or a plurality of vias can be built (possibly with use of one or more jumpers) in the program path to generate more Joule heat to assist with programming. The jumpers are conductive and can be formed of metal, metal gate, local interconnect, polymetal, etc. The metal fuse can also have an extended area that is longer than required by design rules for enhanced programmability. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof. 1. A One-Time Programmable (OTP) memory , comprising: an OTP element including at least a metal fuse coupled to a first supply voltage line; and', 'a program selector coupled to the OTP element and to a second supply voltage line,, 'a plurality of OTP cells, at least one of the OTP cells including at leastwherein at least a portion of the metal fuse is coupled through at least one of a contact and/or a plurality of vias to the program selector, andwherein the OTP element is configured to be programmable by applying voltages to the first and second supply voltage lines to generate heat through the at least one of the contact and/or the plurality of vias to thereby change its logic state.2. An OTP memory as recited in claim 1 , wherein the metal fuse is constructed from at least one of a CMOS metal gate claim 1 , a metal interconnect claim 1 , a polymetal claim 1 , a local interconnect or a metal alloy.3. An OTP memory as recited in claim 1 , wherein the at least one of the OTP cells comprises a jumper to couple at least a portion of the at least one contact and/or a plurality of vias to the metal fuse.4. An OTP ...

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Номер записи: 55
23-01-2014 дата публикации

MULTI LEVEL ANTIFUSE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20140022855A1
Автор: JANG MIN-SOO, Lee Chan-Yong, Seo Young-Hun
Принадлежит:

An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison. 1. An antifuse memory device comprising:an antifuse memory cell comprising an antifuse;a reference current generation unit configured to provide a reference current selected from among a plurality of reference currents; anda comparison unit configured to compare an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provide an output signal corresponding to a result of the compare.2. The antifuse memory device of claim 1 , further comprising: a reference current selection unit configured to select the reference current to correspond to a value of a plurality of bits to be programmed to the antifuse from among the plurality of reference currents.3. The antifuse memory device of claim 1 , further comprising:a voltage generation unit configured to apply a destruction voltage to a first terminal of the antifuse memory cell in a program operating mode; anda control unit configured to control the voltage generation unit to prevent the destruction voltage from being applied to the first terminal of the antifuse memory cell when the intensity of the cell current is higher than the intensity of the reference current based on the output signal.4. The antifuse memory device of claim 3 , wherein the control unit controls the voltage generation unit to apply a read voltage to the first terminal of the antifuse memory cell claim 3 , and indicates whether the plurality of bits are programmed to the antifuse memory cell.5. The antifuse memory device ...

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Номер записи: 56
06-02-2014 дата публикации

Otp memory cell and fabricating method thereof

Номер: US20140035014A1
Автор: Seong-Do Jeon
Принадлежит: MagnaChip Semiconductor Ltd

A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region.

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Номер записи: 57
20-02-2014 дата публикации

DIODE-LESS ARRAY FOR ONE-TIME PROGRAMMABLE MEMORY

Номер: US20140050006A1
Автор: Chen Kuan-Fu, Chen Ming-Shang, CHEN YIN-JEN, Han Tzung-Ting
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor. 1. A memory array structure , comprising:a word line;a column conductor connected with the word line and extending through a plurality of elevations;a dielectric material on at least a portion of the column conductor;a plurality of bit lines disposed at the plurality of elevations; anda plurality of memory units, defined at intersections of the column conductor and the bit lines,wherein the dielectric material is continuous between the intersections.2. The memory array structure of claim 1 , wherein a memory element of each memory unit is a fuse.3. The memory array structure of claim 1 , further comprising:a plurality of fuse links, each of which is coupled between the dielectric material on the column conductor and one of the bit lines.4. The memory array structure of claim 3 , wherein the plurality of fuse links is formed of doped or undoped polysilicon.5. The memory array structure of claim 3 , further comprising:an insulator filling voids between the bit lines, the fuse links and the column conductor.6. The memory array structure of claim 3 , wherein a selected fuse link coupled between the dielectric material on the column conductor and a selected bit line is blown by applying a programming voltage on the word line and grounding the selected bit line.7. The memory array structure of claim 3 , wherein a selected fuse link coupled between the dielectric material on the column conductor and a ...

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Номер записи: 58
20-02-2014 дата публикации

FINFET Based One-Time Programmable Device

Номер: US20140050007A1
Автор: Chen Xiangdong, Xia Wei
Принадлежит: BROADCOM CORPORATION

According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET. 120-. (canceled)21. A one-time programmable (OTP) device comprising:a memory FinFET in parallel with a sensing FinFET, wherein said memory FinFET and said sensing FinFET share a common source region, a common drain region, and a common channel region;said memory FinFET being programmed.22. The OTP device of claim 21 , wherein said sensing FinFET has an altered threshold voltage due to said memory FinFET being programmed.23. The OTP device of claim 21 , wherein said sensing FinFET has an altered drain current due to said memory FinFET being programmed.24. The OTP device of claim 21 , wherein said memory FinFET and said sensing FinFET are monolithically integrated silicon FinFETs.25. The OTP device of claim 21 , wherein a gate of said memory FinFET and another gate of said sensing FinFET are coupled to said common channel region of a semiconductor fin of said OTP device claim 21 , said semiconductor fin including said common source region claim 21 , said common drain region claim 21 , and said common channel region.26. The OTP device of claim 21 , wherein a gate of said memory FinFET is ohmically coupled to said common channel region through a ruptured gate dielectric.27. The OTP device of claim 26 , wherein said ruptured ...

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Номер записи: 59
27-02-2014 дата публикации

Semiconductor devices including redundancy cells

Номер: US20140056082A1
Автор: Yeon Hee Park
Принадлежит: SK hynix Inc

Semiconductor devices including redundancy cells are provided. The semiconductor device includes a control signal generator and a comparator. The control signal generator generates a first control signal including a pulse generated in synchronization with a point of time that a row address enable signal is disabled, a second control signal including a pulse generated in synchronization with a point of time that the row address enable signal is enabled, and a fuse control signal which is enabled during a predetermined period from a point of time that the pulse of the first control signal or the pulse of the second control signal occurs. The comparator generates a comparison signal in response to the pulse of the first control signal or in response to the pulse of the second control signal.

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Номер записи: 60
06-03-2014 дата публикации

FUSE CIRCUIT, OPERATING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE FUSE CIRCUIT

Номер: US20140064003A1
Автор: KANG Kyeong-Pil
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a fuse unit including a fuse configured to be programmed with a repair target address, an enable unit configured to enable the fuse unit, an output unit configured to output a signal corresponding to whether the fuse unit is programmed or not, and a control unit configured to control a voltage difference between both ends of the fuse unit in response to a control signal. 1. A semiconductor memory device , comprising:a fuse unit comprising a fuse configured to be programmed with a repair target address;an enable unit configured to activate the fuse unit;an output unit configured to output a signal corresponding to whether the fuse unit is programmed or not; anda control unit configured to control a voltage difference between both ends of the fuse in response to a control signal.2. The semiconductor memory device of claim 1 , wherein the control unit is configured to equalize voltage levels at the both ends of the fuse in response to the control signal claim 1 , andwherein the control signal is an equalization control signal.3. The semiconductor memory device of claim 2 , wherein the control unit is configured to electrically couple the both ends of the fuse in response to the equalization control signal.4. The semiconductor memory device of claim 3 , wherein the control unit comprises a transistor configured to form a path between the both ends of the fuse and receive the equalization control signal through a gate.5. The semiconductor memory device of claim 1 , further comprising a pre-charging unit configured to pre-charge an input terminal of the output unit in response to a pre-charging control signal.6. The semiconductor memory device of claim 2 , wherein the equalization control signal corresponds to a pre-charging control signal for pre-charging an input terminal of the output unit.7. The semiconductor memory device of claim 1 , wherein the fuse unit has a dynamic structure or a static structure.8. The semiconductor memory ...

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Номер записи: 61
13-03-2014 дата публикации

LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD

Номер: US20140071774A1
Автор: Rountree Robert Newton
Принадлежит:

A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier (). The fuse is coupled between the voltage supply terminal and the semiconductor controlled rectifier. A switching circuit () is coupled to the semiconductor controlled rectifier. 1. A fuse circuit , comprising:a voltage supply terminal;a latch circuit comprising a p-channel transistor having a first source terminal and an n-channel transistor having a second source terminal;a semiconductor controlled rectifier having an anode comprising the first source terminal and a cathode comprising the second a source terminal, wherein the anode and cathode are spaced apart without intervening heavily doped regions; anda fuse coupled between the voltage supply terminal and the semiconductor controlled rectifier.2. A circuit as in claim 1 , arranged to receive a control signal and to trigger the semiconductor controlled rectifier in response to a first logic state of the control signal.3. A circuit as in claim 1 , wherein the semiconductor controlled rectifier comprises an NPN transistor having a base-emitter junction claim 1 , and wherein the base of the NPN transistor is floating.4. A circuit as in claim 1 , wherein the fuse is an antifuse.5. A circuit as in claim 1 , comprising:an n-well region formed adjacent the p-channel transistor;an n-well contact electrically connected to the n-well region formed adjacent a drain terminal of the p-channel transistor and opposite the first source terminal; anda trigger transistor having a current path connected to the n-well region adjacent the first source terminal.6. A fuse circuit claim 1 , comprising:a voltage supply terminal;a first transistor of a first conductivity type having a first source terminal;a second transistor of a second conductivity type having a second source terminal;a semiconductor controlled rectifier (SCR) comprising the first source terminal and the second a source terminal ...

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Номер записи: 62
10-04-2014 дата публикации

Antifuse otp memory cell with performance improvement prevention and operating method of memory

Номер: US20140098591A1
Автор: Chin-Yi Chen, Hsin-Ming Chen, Lun-Chun Chen, Meng-Yi Wu, Yueh-Chia Wen
Принадлежит: eMemory Technology Inc

Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.

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Номер записи: 63
10-04-2014 дата публикации

Apparatuses and methods for sensing fuse states

Номер: US20140098623A1
Автор: Marco Sforzin
Принадлежит: Micron Technology Inc

Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of the plurality of sense lines and configured to receive a sense voltage from a cell of the plurality of cells. The sense voltage may be based, at least in part, on a state of a fuse corresponding to the cell of the plurality of cells. The fuse sense circuit may further be configured to compare the sense voltage to a reference voltage to provide a fuse state control signal indicative of the state of the fuse.

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Номер записи: 64
01-01-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND REPAIR METHOD THEREOF

Номер: US20150003141A1
Автор: PARK Chul-woo, SOHN Young-Soo, SON Jong-Pil
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor memory device is provided which includes a memory cell group and a fuse cell group including at least one fuse cell to store a failed address corresponding to a defective memory cell in the memory cell group; a spare cell group including a spare memory cell configured to replace the defective memory cell included in the memory cell group; a data sensing/selection circuit configured to read data stored in the memory cell group and the spare cell group in response to an activation of the word line; a fuse sense amplifier configured to read the failed address in response to the activation of the word line; and a repair logic circuit configured to control the data sensing/selection circuit in response to the failed address such that the defective memory cell in the memory cell group is replaced by the spare memory cell. 1. A semiconductor memory device , comprising:a row decoder;a memory cell group coupled to the row decoder by a word line, the memory cell group including a plurality of memory cells;a fuse cell group coupled to the row decoder by the word line, the fuse cell group including at least one fuse cell configured to store a failed address corresponding to a defective memory cell in the memory cell group;a spare cell group including a spare memory cell configured to replace the defective memory cell in the memory cell group;a data sensing/selection circuit configured to read data stored in the memory cell group and the spare cell group in response to an activation of the word line;a fuse sense amplifier configured to read the failed address in response to the activation of the word line; anda repair logic circuit configured to control the data sensing/selection circuit in response to the failed address such that the defective memory cell in the memory cell group is replaced by the spare memory cell.2. The semiconductor memory device of claim 1 , wherein the at least one fuse cell includes a nonvolatile memory cell.3. The semiconductor memory ...

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Номер записи: 65
01-01-2015 дата публикации

METHOD AND STRUCTURE FOR RELIABLE ELECTRICAL FUSE PROGRAMMING

Номер: US20150003142A1
Автор: Chung Shine C.
Принадлежит:

A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects. 1. A method of programming One-Time Programmable (OTP) memory , comprising: an OTP element including at least one electrical fuse having a first terminal coupled to a first supply voltage line, the at least one electrical fuse having a fuse resistance, and', 'a selector coupled to the OTP element with an enable signal coupled to a second supply voltage line; and, 'providing a plurality of OTP cells, at least one of the OTP cells including at leastone-time programming the at least one OTP cell into a different logic state by applying a plurality of voltage or current pulses to the at least one OTP cell via the first and the second supply voltage lines to turn on the selector and to thereby progressively change the fuse resistance.2. A method of programming OTP memory as recited in claim 1 , wherein the one-time programming of the at least one OTP cell comprises:obtaining a destructive program current that would cause the at least one OTP cell to undergo a drastic resistance change; andlimiting the program current below the destructive program current.3. A ...

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Номер записи: 66
01-01-2015 дата публикации

One-time programmable devices using junction diode as program selector for electrical fuses with extended area

Номер: US20150003143A1
Автор: Shine C. Chung
Принадлежит: Individual

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuses. At least one portion of the electrical fuse can have at least one extended area to accelerate programming. An extended area is an extension of the fuse element beyond contact or via longer than required by design rules. The extended area also has reduced or substantially no current flowing through. The program selector can be at least one MOS. The OTP device can have the at least one OTP element coupled to at least one diode in a memory cell.

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Номер записи: 67
05-01-2017 дата публикации

ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME

Номер: US20170004887A1
Автор: Song Hyun Min
Принадлежит:

An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor. 1. A method of operating an anti-fuse type one-time programmable (OTP) memory cell array including a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns , a plurality of word lines respectively disposed in the plurality of columns , a plurality of well regions respectively disposed in the plurality of rows , wherein each of the well regions is shared by the unit cells in the same row , a plurality of well bias lines respectively connected to the plurality of well regions , a plurality of bit lines respectively connected to drain terminals of the unit cells arrayed in a last column of the plurality of columns , and a plurality of PN diodes coupled between the plurality of well bias lines and the drain terminals of the plurality of unit cells , the method comprising:selecting one of the plurality of rows; andsequentially programming the unit cells which are arrayed in the selected row,wherein each of the plurality of unit cells includes an anti-fuse transistor having a metal-oxide-semiconductor (MOS) transistor structure without a selection transistor.2. The method of claim 1 ...

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Номер записи: 68
05-01-2017 дата публикации

One Time Programmable Memory with a Twin Gate Structure

Номер: US20170005103A1
Автор: ITO Akira, XUE Mei, YANG Wenwei, Zhang Qintao
Принадлежит: BROADCOM CORPORATION

A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL. 1. A one-time programmable (OTP) memory , comprising:a programmable transistor having a first threshold voltage and a first breakdown voltage, the programmable transistor comprising a first source region, a first drain region, and a first gate electrode;a pass transistor having a second threshold voltage and a second breakdown voltage, the pass transistor comprising a second source region, a second drain region, and a second gate electrode; anda combined word line programming line (WL-PL) electrically connected to the first gate electrode and the second gate electrode,wherein the first source region is electrically connected to the second drain region and the second source region is electrically connected to a bit line, andwherein a first work function of the first gate electrode is less than a second work function of the second gate electrode.2. The OTP memory of claim 1 , wherein the first source region of the programmable transistor and the second drain region of the pass transistor are abutting to form a single shared source-drain region.3. The OTP memory of claim 2 , wherein the single shared source-drain region is sized according to a minimum design rule (MDR).4. The OTP memory of claim 1 , wherein the second breakdown voltage is greater than the ...

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Номер записи: 69
07-01-2016 дата публикации

E-FUSE TEST DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20160005494A1
Автор: CHOI Hyun-min, PARK In-gyu, SONG Jung-Hak
Принадлежит:

An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two. 1. An e-fuse test device comprising:a first transistor including a first gate terminal configured to receive a first gate voltage, a first source/drain terminal, and a second source/drain terminal, wherein the e-fuse test device is configured to detect a current passing through the first transistor; anda fuse array including n sets of fuses, each set arranged between a first end line and a second end line,wherein each respective set of fuses of the n sets of fuses includes a first end, a second end, and m first fuse elements connected in series to each other between the first end and the second end,wherein the first ends of the respective sets of fuses of the n sets of fuses are connected to the first end line, and the second ends of the respective sets of fuses of the n sets of fuses are connected to the second end line and the first source/drain terminal of the first transistor,wherein the first end line is configured to receive a first source voltage, andwherein the n and m are natural numbers that are equal to or larger than 2.2. The e-fuse test device of claim 1 , wherein each respective set of fuses of the n sets of fuses comprises (m−1) connection terminals that connect the adjacent first fuse elements to each other claim 1 ,wherein the (m−1) connection terminals of each respective set of fuses of the n sets of fuses includes an 1-th ...

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Номер записи: 70
07-01-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

Номер: US20160005496A1
Автор: Kim Sang-Hee
Принадлежит:

A semiconductor memory device includes a memory cell array including a plurality of word lines; a repair fuse section programmed with one or more repair-target addresses and fuse enable information; an address generation section suitable for generating test addresses during a test operation, corresponding to the word lines based on the repair-target addresses and the fuse enable information; and a word line control section suitable for selectively activating the word lines based on the test addresses. 1. A semiconductor memory device comprising:a memory cell array including a plurality of word lines;a repair fuse section programmed with one or more repair-target addresses and fuse enable information;an address generation section suitable for generating test addresses during a test operation, corresponding to the word lines based on the repair-target addresses and the fuse enable information; anda word line control section suitable for selectively activating the word lines based on the test addresses.2. The semiconductor memory device of claim 1 , wherein the test operation is performed for screening word line disturbance.3. The semiconductor memory device of claim 1 , wherein the memory cell array includes a normal cell array and a redundancy cell array.4. The semiconductor memory device of claim 3 , wherein the word line control section selectively activates normal word lines corresponding to the normal memory cell array and redundancy word lines corresponding to the redundancy memory cell array based on the fuse enable information.5. The semiconductor memory device of claim 4 , wherein the test addresses correspond to the normal word lines and the redundancy word lines during the test operation.6. A method of operating a semiconductor memory device comprising:detecting one or more repair-target addresses;setting test-target normal word lines from a plurality of normal word lines based on the repair-target addresses;detecting fuse enable information;setting one or ...

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Номер записи: 71
05-01-2017 дата публикации

Current balance circuit and the method thereof

Номер: US20170005571A1
Автор: Brent Hughes, Junyong Gong, Xingwei Wang
Принадлежит: Monolithic Power Systems Inc

A current balance circuit for a power management device having a first current channel and a second current channel, having: a first current sense circuit configured to detect a current flowing through the first current channel, and to provide a first current sense signal indicative of the current flowing through the first current channel; wherein the current balance circuit draws current from the second current channel to the first current channel based on the first current sense signal.

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Номер записи: 72
01-01-2015 дата публикации

STRAP-BASED MULTIPLEXING SCHEME FOR MEMORY CONTROL MODULE

Номер: US20150006826A1
Автор: Yong Yean Kee
Принадлежит:

Embodiments include integrated circuits (ICs), system-on-chips (SoCs), and related methods for a strap-based multiplexing scheme for a memory control module. In one embodiment, a memory control module may include a first memory controller coupled to a first bus including a first conductor configured to carry a first signal, and a second memory controller coupled to a second bus including a second conductor configured to carry a second signal. The memory control module may further include a fuse configured to have a fuse setting, and a strap register configured to store a register value. The memory control module may further include a multiplexer configured to selectively pass the first signal or the second signal responsive to the fuse setting and the register value. Other embodiments may be described and claimed. 1. An integrated circuit on a semiconductor die comprising:a first memory controller coupled to a first bus including a first conductor configured to carry a first signal;a second memory controller coupled to a second bus including a second conductor configured to carry a second signal;a fuse configured to have a fuse setting;a strap register configured to store a register value; anda multiplexer coupled to the first conductor, the second conductor, the fuse, and the strap register, and configured to selectively pass either the first signal or the second signal responsive to the fuse setting and the register value.2. The integrated circuit of claim 1 , wherein the first conductor is configured to carry an error correction coding (ECC) signal for ECC of data signals associated with the first memory controller.3. The integrated circuit of claim 2 , wherein the second conductor is configured to carry data signals associated with the second memory controller.4. The integrated circuit of claim 1 , wherein the first conductor is configured to carry a first chip select signal associated with a first rank of the first memory controller claim 1 , and the second ...

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Номер записи: 73
04-01-2018 дата публикации

Otp memory with high data security

Номер: US20180005703A1
Автор: Shine C. Chung
Принадлежит: Attopsemi Technology Co Ltd

A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.

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Номер записи: 74
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180005704A1
Автор: TAKAOKA Hiromichi
Принадлежит: RENESAS ELECTRONICS CORPORATION

There is to provide a semiconductor device capable of improving the reliability. The semiconductor device is provided with an anti-fuse element including a semiconductor substrate, a well region of a first conductivity type formed in the semiconductor substrate, and a gate electrode formed over the semiconductor substrate through a gate insulating film, and source regions of a second conductivity type opposite to the first conductivity type formed within the well region at the both ends of the gate electrode. When writing in the fuse element, a first writing potential is applied to the gate electrode, a first reference potential is applied to the well region, an intermediate potential is supplied to the source regions, and the intermediate potential is lower than the first writing potential and higher than the first reference potential. 1. A semiconductor device comprisingan anti-fuse element including:a semiconductor substrate;a first semiconductor region of a first conductivity type formed in the semiconductor substrate;a gate electrode formed over the semiconductor substrate through a gate insulating film; andsecond and third semiconductor regions of a second conductivity type opposite to the first conductivity type, formed within the first semiconductor region, at both ends of the gate electrode,wherein when writing in the anti-fuse element, a first potential is applied to the gate electrode, a second potential is applied to the first semiconductor region, a third potential is supplied to the second semiconductor region and the third semiconductor region, and the third potential is lower than the first potential and higher than the second potential.2. The device according to claim 1 ,wherein the writing includesa first stage (a) of forming a dielectric breakdown region ranging from the gate electrode to the semiconductor substrate, in a part of the gate insulating film, anda second stage (b) of forming a conductive layer in the dielectric breakdown region.3. The ...

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Номер записи: 75
04-01-2018 дата публикации

FUSE ELEMENT PROGRAMMING CIRCUIT AND METHOD

Номер: US20180005705A1
Автор: Hall Jefferson W.
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element. 1. A circuit for programming a fuse element comprising:a memory cell having the fuse element that includes a first semiconductor material body region and a silicide layer;a programming circuit configured to form a programming current to program the fuse element;a current mirror, of the programming circuit, having a first transistor coupled at a node to a second transistor of the current mirror;a programming element configured to control a value of the programming current, the programming element having a second semiconductor material body region but not a silicide layer;a reference generation circuit coupled in series between the node and the programming element;the programming circuit configured to control the programming current to a first value responsively to a value of the programming element and to subsequently control the programming current to a different value responsively to a value of the fuse element.2. The circuit of wherein a resistivity of the programming element is substantially representative of a resistivity of the first semiconductor material body region of the fuse element.3. The circuit of wherein the programming element includes a doped polysilicon body region that is substantially devoid of a silicide material.4. The circuit of wherein the programming circuit includes a means for forming a value of the programming current to cause electro-migration of silicide material overlying a portion of the first semiconductor material body region of the fuse element and increasing a resistivity of the fuse element.5. The circuit of wherein the reference generation circuit separates the programming element from the first transistor.6. The circuit of wherein the reference generation circuit includes a reference transistor having a first current carrying electrode coupled to the node and a second ...

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Номер записи: 76
04-01-2018 дата публикации

SOFT POST PACKAGE REPAIR OF MEMORY DEVICES

Номер: US20180005710A1
Автор: Wilson Alan J., Wright Jeffrey
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus. 1. A memory device comprising:a memory array;a set of address terminals configured to receive address information;a first volatile storage element configured, responsive to the memory device entering a soft post package repair mode, to store address information received at the set of address terminals as defective address data corresponding to a first address of the memory array that includes at least one defective memory cell; anda second volatile storage element configured, responsive to the memory device exiting from the soft post package repair mode, to store address information received at the set of address terminals as access address data for the memory array.2. The device of claim 1 , further comprising a match logic circuit configured to detect whether the access address data stored in the second volatile storage element matches the defective address data stored in the first volatile storage element.3. The device of claim 2 , further comprising an access circuit configured to:access a second address of the memory array that corresponds to the ...

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Номер записи: 77
03-01-2019 дата публикации

SECURE STORAGE APPARATUS

Номер: US20190006017A1
Автор: FODOR Yair, REINMAN Tzachy, SHAMAY Tsion
Принадлежит:

In one embodiment, an apparatus includes a non-volatile memory, a one-time programmable (OTP) memory, and a processor operative to write data values to the non-volatile memory and then initiate programming of a first bit of the OTP memory, the first bit being associated with locking the non-volatile memory from further data being written thereto, and after the non-volatile memory has been locked from further data being written thereto, initiate programming of the second bit of the OTP memory in order to lock the non-volatile memory from further data being erased therefrom. 1. An apparatus comprising: a non-volatile memory; a one-time programmable (OTP) memory including a plurality of bits; and a processor operatively connected to the non-volatile memory and the OTP memory , wherein the processor is operative to:write a plurality of data values to the non-volatile memory and then initiate programming of a first bit of the plurality of bits of the OTP memory, the programming of the first bit being initiated to lock the non-volatile memory from further data being written thereto but not locking the non-volatile memory from data being erased therefrom; andafter the non-volatile memory has been locked from further data being written thereto, initiate programming of a second bit of the OTP memory in order to lock the non-volatile memory from data being erased therefrom.2. The apparatus according to claim 1 , wherein claim 1 , the processor is operative claim 1 , after the non-volatile memory has been locked from further data being written thereto claim 1 , to: check a programming of the second bit of the plurality of bits of the OTP memory to determine if the non-volatile memory is unlocked for data being erased therefrom claim 1 , the second bit being associated with locking the non-volatile memory from data being erased therefrom; and erase at least one data value of the plurality of data values previously written to the non-volatile memory by the processor;wherein the ...

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Номер записи: 78
03-01-2019 дата публикации

3D SEMICONDUCTOR DEVICE AND SYSTEM

Номер: US20190006240A1
Автор: Cronquist Brian, OR-BACH Zvi, Sekar Deepak C.
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel. 1. A 3D semiconductor device , the device comprising:a first single crystal layer comprising a plurality of first transistors; 'wherein said interconnecting comprises forming memory peripheral circuits;', 'at least one first metal layer interconnecting said plurality of first transistors,'}a plurality of second transistors underlying said first single crystal layer;a second metal layer overlaying said plurality of second transistors;a first memory cell underlying said memory peripheral circuits;a second memory cell underlying said first memory cell;a staircase structure underlying said first single crystal layer; and wherein said first memory cell comprises at least one of said second transistors,', 'wherein said memory peripheral circuits control at least said first memory cell,', 'wherein at least one of said second transistors comprises a source, channel and drain,', 'wherein said source, said channel and said drain have the same dopant type,', 'wherein said non-volatile NAND memory comprises said first memory cell,', 'wherein at ...

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Номер записи: 79
20-01-2022 дата публикации

CIRCUIT FOR DETECTING ANTI-FUSE MEMORY CELL STATE AND MEMORY

Номер: US20220020442A1
Автор: JI Rumin
Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A circuit for detecting an anti-fuse memory cell state includes a current providing module connected to a first node and used to provide constant current; an anti-fuse memory cell array connected to the first node and including at least one bit line, the at least one bit line is connected to a plurality of anti-fuse memory cells and the first node; and a comparator, a first input end of the comparator is connected to the first node and a second input end of the comparator is connected to a first reference voltage, and used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array. 1. A circuit for detecting an anti-fuse memory cell state , comprising:a current providing module connected to a first node and used to provide constant current;an anti-fuse memory cell array connected to the first node and comprising at least one bit line, the at least one bit line being connected to a plurality of anti-fuse memory cells and the first node; anda comparator, wherein a first input end of the comparator is connected to the first node, a second input end of the comparator is connected to a first reference voltage, and the comparator is used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array.2. The circuit for detecting the anti-fuse memory cell state of claim 1 , wherein the current providing module comprises:an amplifier, wherein a first input end of the amplifier is connected to a second reference voltage, a second input end of the amplifier is connected to a second node, and an output end of the amplifier is connected to a third node;a first switching element, wherein a first end of the first switching element is connected to a power voltage, a second end of the first switching element is connected to the second node, and a control end of the first switching element is connected to the third node;a reference resistor, wherein a first end of the reference resistor is connected to ...

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Номер записи: 80
08-01-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED FUSE SENSING RELIABILITY IN SLOW POWER-UP OPERATION AND METHOD FOR READING FUSE BLOCK THEREBY

Номер: US20150009742A1
Автор: Kang Kyu-Chang, Lee Chan-Yong, SHIN Jung-Bum
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided is a semiconductor memory device with improved fuse sensing reliability during a slow power-up operation. The semiconductor memory device may include a memory cell array including a normal memory cell array and a spare memory cell array; an anti-fuse circuit supplied with a first voltage and configured to store fail address information associated with a defective memory cell in the normal memory cell array and configured to sense the fail address information in response to a clock signal applied during a power-up period; and a fuse read circuit including a clock generator supplied with a second voltage, the fuse read circuit configured to detect respective levels of the first and second voltages during the power-up period to generate the clock signal and to read the sensed fail address information from the anti-fuse circuit in response to the clock signal. 1. A semiconductor memory device comprising:a memory cell array including a normal memory cell array and a spare memory cell array;an anti-fuse circuit supplied with a first voltage and configured to store fail address information associated with a defective memory cell in the normal memory cell array and configured to sense the fail address information in response to a clock signal applied during a power-up period; anda fuse read circuit including a clock generator supplied with a second voltage, the fuse read circuit configured to detect respective levels of the first and second voltages during the power-up period, to generate the clock signal, and to read the sensed fail address information from the anti-fuse circuit in response to the clock signal,wherein the clock signal has a period that varies in response to the detected levels of the first and second voltages.2. The semiconductor memory device as set forth in claim 1 , wherein the defective memory cell is a dynamic random access memory (DRAM) cell.3. The semiconductor memory device as set forth in claim 1 , wherein the clock generator is ...

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Номер записи: 81
08-01-2015 дата публикации

Low-Pin-Count Non-Volatile Memory Interface for 3D IC

Номер: US20150009743A1
Автор: Chung Shine C.
Принадлежит:

A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one dies can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each dies in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built. 1. An integrated circuit , comprising:at least one Through Silicon Via (TSV) or interposer being built in the integrated circuit;a plurality of integrated circuit dies arranged in a stack, at least one of the integrated circuit dies having at least one low-pin-count (LPC) One-Time-Programmable (OTP) memory; andinterface pins of the at least one low-pin-count OTP memory in the at least one of the integrated circuit dies being coupled to a set of low-pin-count pins that are accessed externally,wherein the at least one of the integrated circuit dies in the integrated circuit can be selected and configured to be readable or programmable using the set of the low-pin-count external pins.2. An integrated circuit as recited in claim 1 , wherein the integrated circuit has at least one substrate or interposer.3. An integrated circuit as recited in claim 1 , wherein the integrated circuit has at least one Through Silicon Via (TSV) between at least two of the integrated circuit dies or between at least one of the integrated circuit dies and a substrate or interposer.4. An integrated circuit as recited in claim 1 , wherein the at least one integrated circuit die has a unique ID to be selected for ...

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Номер записи: 82
27-01-2022 дата публикации

MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD

Номер: US20220028470A1
Автор: Chang Meng-Sheng, YANG Yao-Jen
Принадлежит:

A memory device includes at least one bit line, at least one source line, at least one program word line, at least one read word line, and at least one memory cell including a program transistor and a read transistor. The program transistor includes a gate terminal coupled to the at least one program word line, a first terminal coupled to the at least one source line, and a second terminal. The read transistor includes a gate terminal coupled to at least one read word line, a first terminal coupled to the at least one bit line, and a second terminal coupled to the second terminal of the program transistor. 1. A memory device , comprising:at least one bit line;at least one source line;at least one program word line;at least one read word line; andat least one memory cell comprising a program transistor and a read transistor,wherein a gate terminal coupled to the at least one program word line,', 'a first terminal coupled to the at least one source line, and', 'a second terminal, and, 'the program transistor comprises a gate terminal coupled to the at least one read word line,', 'a first terminal coupled to the at least one bit line, and', 'a second terminal coupled to the second terminal of the program transistor., 'the read transistor comprises2. The memory device of claim 1 , wherein a first value corresponding to a gate dielectric of the program transistor being broken down under a previous application of a predetermined breakdown voltage or higher, and', 'a second value corresponding to the gate dielectric not yet broken down., 'the at least one memory cell is configured to store a datum having any of'}3. The memory device of claim 1 , whereinthe program transistor and the read transistor are identically configured.4. The memory device of claim 1 , further comprising:a controller coupled to the at least one memory cell via the at least one bit line, the at least one source line, the at least one program word line, and the at least one read word line, apply a ...

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Номер записи: 83
12-01-2017 дата публикации

MEMORY CELL AND CORRESPONDING DEVICE

Номер: US20170011808A1
Автор: Mirabella Ignazio Bruno, Nicolosi Alessandro, Pappalardo Salvatore, Ribellino Calogero
Принадлежит: STMICROELECTRONICS S.R.L.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event. 1. A memory cell , comprising:a plurality of storage elements for redundantly storing an input data logic signal, said plurality of storage elements having output lines for outputting a respective plurality of logic signals having respective logic values,a logic combination network sensitive to said respective logic values of said logic signals on said output lines, said logic combination network configured to generate an output signal of the cell having the same logic value as a majority of said logic signals on said output lines, andan exclusive logic sum circuit sensitive to said respective logic values of said logic signals on said output lines, said exclusive logic sum circuit configured to produce a refresh of said data logic signal as stored in said plurality of storage elements, said exclusive logic sum circuit activated when one of said logic signals on said output lines undergoes a logic value transition.2. The memory cell of claim 1 , wherein said plurality of storage elements includes an odd number of storage elements.3. The memory cell of claim 1 , wherein said plurality of storage elements comprise latch elements.4. The memory cell of claim 1 , wherein said storage elements include at ...

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Номер записи: 84
14-01-2016 дата публикации

E-FUSE ARRAY CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME

Номер: US20160012908A1
Автор: KANG Hyuk Choong
Принадлежит:

An E-fuse array circuit includes a driving block arranged in a predetermined portion of a semiconductor substrate, a normal fuse array configured to one side of the driving block, and an auxiliary circuit part arranged in an other side of the driving block to a direction facing an arrangement direction of the normal fuse array. 1. An electric fuse (E-fuse) array circuit comprising:a driving block arranged in a predetermined region of a semiconductor substrate;a normal fuse array configured to one side of the driving block;an auxiliary circuit part arranged in an other side of the driving block to a direction facing an arrangement direction of the normal fuse array.2. The E-fuse array circuit of claim 1 , wherein the auxiliary circuit part is arranged closed to or spaced from the driving block in the other side of the driving block.3. The E-fuse array circuit of claim 1 , wherein the auxiliary circuit part includes an error check and correction (ECC) circuit unit and a redundancy fuse array.4. The E-fuse array circuit of claim 3 , wherein at least one of the ECC circuit unit and the redundancy fuse array is arranged closed to or space from the driving block in the other side of the driving block.5. The E-fuse array circuit of claim 3 , wherein the ECC circuit unit includes a first ECC unit and a second ECC unit claim 3 ,wherein the first ECC unit is arranged closer to the normal fuse array than the second ECC unit.6. The E-fuse array circuit of claim 1 , wherein the driving block includes a controller claim 1 ,wherein the auxiliary circuit part is configured to be enabled or disabled by the controller.7. A semiconductor memory apparatus comprising:a plurality of banks arranged in a cell region of a semiconductor substrate in which the cell region and a peripheral region are defined; andan electric fuse (E-fuse) array circuit arranged in the peripheral region, and including a driving block arranged in a predetermined region of the semiconductor substrate, a normal ...

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Номер записи: 85
14-01-2016 дата публикации

DATA STORAGE CIRCUIT AND SYSTEM INCLUDING THE SAME

Номер: US20160012909A1
Автор: YUN Dae Ho
Принадлежит:

A data storage circuit includes a first antifuse which is programmed in response to a first access signal, and provide data indicating whether the first antifuse is programmed to a data node, an initialization section which controls a voltage level of the data node in response to an initialization flag, and a second antifuse which is programmed in response to the first access signal, and provide the initialization flag indicating whether the second antifuse is programmed to the initialization section. 1. A data storage circuit , comprising:a first antifuse configured to be programmed in response to a first access signal, and provide data indicating whether the first antifuse is programmed to a data node;an initialization section configured to control a voltage level of the data node in response to an initialization flag; anda second antifuse configured to be programmed in response to the first access signal, and provide the initialization flag indicating whether the second antifuse is programmed to the initialization section.2. The data storage circuit according to claim 1 , further is comprising:a flag control section configured to control a voltage level of a source terminal of the second antifuse in response to an initialization signal.3. The data storage circuit according to claim 2 , wherein the second antifuse is programmed when the first access signal and the initialization signal are enabled.4. The data storage circuit according to claim 1 , further comprising:an access control section configured to electrically connect the data node to an output line in response to a second access signal.5. The data storage circuit according to claim 4 , wherein the first antifuse is programmed when the first access signal and the second access signal are enabled.6. The data storage circuit according to claim 1 , wherein the first access signal is enabled to a high voltage such that the first antifuse or the second antifuse is ruptured by the high voltage.7. A data storage ...

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Номер записи: 86
14-01-2016 дата публикации

STACKED SEMICONDUCTOR DEVICE

Номер: US20160012910A1
Автор: Ware Frederick A.
Принадлежит:

A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies. 1. A packaged semiconductor device comprising:multiple integrated circuit (IC) chips arranged as a stack, each chip including multiple input/output (I/O) pads, each I/O pad selectively coupled to an input/output (I/O ) circuit;wherein the I/O pads for each chip in the stack are vertically aligned with corresponding I/O pads in the other stacked chips to define vertically aligned sets of I/O pads;wherein a given vertically aligned set of I/O pads for the stacked chips is electrically coupled via a conductive path; andwherein less than all of the I/O circuits corresponding to a given vertically aligned set of I/O pads are electrically coupled to the conductive path.2. The packaged semiconductor device according to claim 1 , wherein the multiple IC chips comprise dynamic random access memory (DRAM) devices.3. The packaged semiconductor device according to claim 1 , wherein each path comprises through-silicon-vias formed through each chip.4. The packaged semiconductor device according to claim 1 , wherein each conductive path is coupled to no more than one I/O circuit.5. The packaged semiconductor device according to claim 1 , further comprising a programmable element to ...

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Номер записи: 87
14-01-2016 дата публикации

ONE TIME PROGRAMMING MEMORY CELL, ARRAY STRUCTURE AND OPERATING METHOD THEREOF

Номер: US20160013193A1
Автор: Chen Hsin-Ming, Wu Meng-Yi
Принадлежит:

A one time programming memory cell includes a transistor, a first varactor, and a second varactor. The transistor has a gate terminal, a source terminal and a drain terminal. The gate terminal of the transistor is connected with a word line. The source terminal of the transistor is connected with a bit line. A first end of the first varactor is connected with the drain terminal of the transistor. A second end of the first varactor is connected with a first program line. A first end of the second varactor is connected with the drain terminal of the transistor. A second end of the second varactor is connected with a second program line. 1. A one time programming memory cell , comprising:a P-type substrate;a first gate structure disposed on a surface of the P-type substrate, and connected with a word line;a second gate structure disposed on the surface of the P-type substrate, and connected with a first program line;a third gate structure disposed on the surface of the P-type substrate, and connected with a second program line;a first N-type diffusion region disposed under the surface of the P-type substrate, located near a first side of the first gate structure, and connected with a bit line; anda second N-type diffusion region disposed under the surface of the P-type substrate, wherein the second N-type diffusion region is located near a second side of the first gate structure,wherein a channel region underlying the second gate structure is a first N-type doped channel region, and a channel region underlying the third gate structure is a second N-type doped channel region, wherein a first varactor is defined by the second gate structure, the first N-type doped channel region and the second N-type diffusion region collaboratively, wherein a second varactor is defined by the third gate structure, the second N-type doped channel region and the second N-type diffusion region collaboratively, wherein a transistor is defined by the first gate structure, the P-type ...

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Номер записи: 88
14-01-2021 дата публикации

LAYOUT STRUCTURE OF MEMORY ARRAY

Номер: US20210012846A1
Автор: Chang Meng-Sheng, CHOU Shao-Yu, Wang Yih, YANG Yao-Jen
Принадлежит:

A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line. 1. A layout method , comprising:forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells;disposing a word line between the first row and the second row;disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively;disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes located on a first side of the word line; anddisposing a second cut layer on a second portion of a second control electrode of the plurality of control electrodes located on a second side of the word line;wherein the first side of the word line is opposite to the second side of the word line.2. The layout method of claim 1 , wherein the first cut layer is located between a first storage cell of the first row and the first side of the word line claim 1 , the first control electrode is coupled to the first storage cell claim 1 , the second cut layer is located between a second storage cell of ...

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Номер записи: 89
14-01-2021 дата публикации

Method and Apparatus for enabling Multiple Return Material Authorizations (RMAs) on an Integrated Circuit Device

Номер: US20210012855A1
Автор: Chen Kenneth, Draper Andrew Martyn, Lau Wei Chun, Lu Ting, Menon Sankaran M.
Принадлежит:

An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse. 1. An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) , the IC device comprising:an asset disposed on the IC device; anda return material authorization (RMA) counter fuse comprising a first fuse, a second fuse, and a third fuse, wherein the IC device enters an RMA state that disables access to the asset in response to blowing the first fuse, wherein the IC device enters a second state in response to blowing the second fuse, and wherein the IC device re-enters the RMA state in response to blowing the third fuse.2. The IC device of claim 1 , wherein the asset comprises circuitry claim 1 , nonvolatile code claim 1 , or a field programmable gate array circuit design claim 1 , or a combination thereof.3. The IC device of claim 1 , wherein the IC device blows the second fuse during a time period beginning after the first fuse is blown and wherein the IC device blows the third fuse during a time period beginning after the second fuse is blown.4. The IC device of claim 1 , wherein the IC device enables access to the asset in response to the IC device leaving the RMA state.5. The IC device of claim 1 , wherein the third fuse is blown during a time period beginning after the first fuse is blown.6. The IC device of claim 1 , wherein a status of a fuse on the RMA counter fuse indicates a state of the IC device.7. The IC device of claim 1 , wherein the IC device indicates an amount of times that the IC device has been in the RMA state based on a status of at least one of the first fuse claim 1 , the ...

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Номер записи: 90
10-01-2019 дата публикации

MEMORY ARRAYS

Номер: US20190013415A1
Автор: Bhattacharyya Arup
Принадлежит:

In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack. 1. A memory array , comprising: a gate;', 'a first dielectric stack between a first portion of the gate and the semiconductor pillar, wherein the first dielectric stack is wrapped around at least the portion of the semiconductor pillar and is to store a charge; and', 'a second dielectric stack between a second portion of the gate and the semiconductor pillar, wherein the second dielectric stack is to store a charge and is wrapped around at least the portion of the semiconductor pillar such that the second dielectric stack is separated from the first dielectric stack along the semiconductor pillar., 'a memory cell wrapped around at least a portion of a semiconductor pillar, and comprising2. The memory array of claim 1 , wherein the gate further comprises a third portion contiguous with the first and second portions of the gate and that is between the first and second dielectric stacks.3. The memory array of claim 1 , wherein the memory cell further comprises an interface dielectric between a third portion of the gate and the semiconductor pillar.4. The memory array of claim 3 , wherein the first portion of the gate and the first dielectric stack is a first non-volatile portion of the memory cell claim 3 , the third portion of the gate and the interface dielectric forms a fixed-threshold-voltage portion of the memory cell in series with the first non-volatile portion of the memory cell claim 3 , and the second portion of the gate and the second dielectric stack is a second non-volatile portion of the memory cell in series with the fixed-threshold-voltage ...

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Номер записи: 91
09-01-2020 дата публикации

APPARATUSES AND/OR METHODS FOR OPERATING A MEMORY CELL AS AN ANTI-FUSE

Номер: US20200013472A1
Автор: Redaelli Andrea
Принадлежит:

Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example. 1. (canceled)2. A method comprising:selecting a memory cell for read-only operation, the memory cell operable for storing one of a plurality of reprogrammable states; andapplying a bias to the memory cell based at least in part on the selecting, wherein applying the bias forms a resistance path in the memory cell corresponding to a read-only state of the memory cell that is different than the plurality of reprogrammable states.3. The method of claim 2 , further comprising:determining a logic state for the read-only operation; anddetermining a direction of the bias based at least in part on the determined logic state.4. The method of claim 2 , wherein the bias is greater than biasing associated with programming the plurality of reprogrammable states.5. The method of claim 2 , wherein forming the resistance path comprises operating the memory cell as an anti-fuse.6. The method of claim 2 , wherein forming the resistance path comprises operating the memory cell as a fuse.7. The method of claim 2 , wherein forming the resistance path comprises forming a metallic path in the memory cell.8. The method of claim 2 , wherein forming the resistance path comprises forming a void in the memory cell.9. A memory device claim 2 , comprising:a memory cell operable to store one of a plurality of reprogrammable states; anda selector operable to form a resistance path in the memory cell corresponding to a read-only state of the memory cell that is different than the plurality of reprogrammable states.10. The memory device of claim 9 , wherein claim 9 , to form the resistance path corresponding to the read-only state claim 9 , the selector is operable to form a metallic path in the memory cell.11. The memory device of claim 10 , wherein the selector is operable to form the metallic path based at least in part on ion migration from a metal plug of the ...

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Номер записи: 92
09-01-2020 дата публикации

Semiconductor Device Including a Fuse

Номер: US20200013717A1
Автор: Grivna Gordon M., Hall Jefferson W.
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy. 1. A semiconductor device comprising:a first current source including a terminal;a second current source including a terminal;a first fuse including a first terminal and a second terminal; anda first transistor including a first current-carrying region and a control region, the first transistor is a bipolar junction transistor,', 'the terminals of the first and second current sources and the first terminal of the first fuse are coupled to one another, and', 'the second terminal of the first fuse and the first current-carrying region of the first transistor are coupled to each other., 'wherein2. The semiconductor device of claim 1 , further comprising:a second fuse including a first terminal and a second terminal; anda second transistor including a first current-carrying region and a control region, the first terminals of the first and second fuses are coupled to each other, and', 'the second terminal of the second fuse and the first current-carrying region of the second transistor are coupled to each other., 'wherein3. The semiconductor device of claim 1 , further comprising:a second transistor including a first current-carrying ...

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Номер записи: 93
15-01-2015 дата публикации

INTEGRATED CIRCUITS WITH PROGRAMMABLE ELECTRICAL CONNECTIONS AND METHODS FOR FABRICATING THE SAME

Номер: US20150016174A1
Автор: Chi Min-Hwa, Liu Yanxiang
Принадлежит:

Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and an extending member extends through the interlayer dielectric. The extending member is electrically connected to the programmable layer of the memory line at a point above the inactive area. 1. A method of fabricating an integrated circuit with a programmable electrical connection , the method comprising:providing a memory line comprising a bottom side, a left side, a right side, a metal core, a memory line barrier layer, and a programmable layer, wherein the programmable layer is positioned along the bottom side, the left side and the right side, and the memory line barrier layer is positioned between the programmable layer and the metal core, wherein the memory line extends over an inactive area of the integrated circuit, and wherein sidewall spacers abut the left side and the right side;forming an interlayer dielectric overlying the memory line, the sidewall spacers, and the inactive area;etching a via through the interlayer dielectric to one of the sidewall spacers at a position adjacent to the memory line and over the inactive area;etching one of the sidewall spacers through the via; andforming an extending member within the via such that the extending member is electrically connected to the programmable layer.2. The method of wherein providing the memory line further comprises providing the memory line wherein the programmable layer comprises hafnium oxide.3. The method of wherein providing the memory line further comprises providing the memory line wherein the memory line barrier layer comprises titanium nitride.4. The method of further comprising:providing an access transistor with an access transistor gate, a power inlet, and an ...

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Номер записи: 94
14-01-2021 дата публикации

SEMICONDUCTOR APPARATUS INCLUDING CLOCK PATHS AND SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR APPARATUS

Номер: US20210013875A1
Автор: SEO Young Suk
Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths. 1. A semiconductor apparatus comprising:a first clock path configured to generate a first output clock signal by delaying a first phase clock signal in a normal operation mode and to generate the first output clock signal by delaying a first oscillating signal in a monitoring mode;a second clock path configured to generate a second output clock signal by delaying a second phase clock signal based on a delay compensation signal in the normal operation mode and to generate the second output clock signal by delaying a second oscillating signal in the monitoring mode;an oscillating path generation circuit configured to receive the first output clock signal to generate the first oscillating signal and to feed back the first oscillating signal to the first clock path, and configured to receive the second output clock signal to generate a second oscillating signal and to feed back the second oscillating signal to the second clock path; anda delay information generation circuit configured to generate the delay compensation signal based on the oscillating signal.2. The semiconductor apparatus according to claim 1 , wherein the second phase clock signal has a phase difference corresponding to a unit phase from the first phase clock signal.3. The semiconductor apparatus according to claim 1 , wherein the first clock path comprises:a first oscillating controller configured to receive the first phase clock signal and the first ...

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Номер записи: 95
19-01-2017 дата публикации

Fusible Link Cell with Dual Bit Storage

Номер: US20170018311A1
Автор: Bailey Richard Allen, Ball Michael Allen, Dusa Sunil Kumar, Rodriguez John Anthony, Venugopal Archana
Принадлежит:

A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained. 1. A programmable fusible link circuit in an integrated circuit , comprising:first, second, and third fusible links connected in parallel with one another;a programming circuit for applying a programming voltage across the parallel connected fusible links, the programming voltage selected, responsive to a digital control word of at least two bits, over a range of voltages including a first programming voltage of the first fusible link, a second programming voltage of the second fusible link, and a third programming voltage of the third fusible link; anda sense circuit for outputting a digital output word of at least two bits corresponding to a resistance of the parallel connected fusible links.2. The circuit of claim 1 , wherein the first programming voltage is of a magnitude that opens the first fusible link but not the second and third fusible links;wherein the second programming voltage is of a magnitude that opens the first and second fusible links but not the third fusible link;and wherein the third programming voltage is of a magnitude that opens the first, second, and third fusible links.3. The circuit of claim 2 , wherein the first claim 2 , second claim 2 , and third fusible links are constructed to have different sheet resistances from one another.4. The circuit of claim 3 , wherein each of the first ...

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Номер записи: 96
19-01-2017 дата публикации

SEMICONDUCTOR APPARATUS AND REPAIR METHOD THEREOF

Номер: US20170018316A1
Автор: CHO JIn Hee, KIM Jong Sam
Принадлежит:

A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected. 1. A semiconductor apparatus comprising:a memory region;a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region;a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; anda control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes the fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.2. The semiconductor apparatus according to claim 1 , wherein the memory region comprises:a memory cell array;a plurality of word line groups coupled to the memory cell array;a plurality of redundant word line groups for replacing word line groups that are found to be defective or related to defective memory cells; anda plurality of latch groups corresponding to the plurality of fuse groups.3. The semiconductor apparatus according to claim 1 , wherein the remaining-fuse information indicates a number of available fuse sets among a plurality of fuse sets included in the fuse group that includes the fuse corresponding to the failed address.4. The ...

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Номер записи: 97
19-01-2017 дата публикации

RANDOM NUMBER GENERATION CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

Номер: US20170018317A1
Автор: KIM Kyung Hoon, YOON In Sik
Принадлежит:

A random number generation circuit may include a memory block. The random number generation circuit may include a fuse block configured to store an address of a failed memory cell from a memory cell array of the memory block, as a repair address, and generate a match signal by comparing the repair address with a normal address inputted from an exterior. The random number generation circuit may include a register configured to output a true random number by latching an address corresponding to activation timing of the match signal among normal addresses. 1. A random number generation circuit comprising:a memory block;a fuse block configured to store an address of a failed memory cell from a memory cell array of the memory block, as a repair address, and generate a match signal by comparing the repair address with a normal address inputted from an exterior; anda register configured to output a true random number by latching an address corresponding to activation timing of the match signal among normal addresses.2. The random number generation circuit according to claim 1 , further comprising:a repair processing block configured to replace the failed memory cell in the memory cell array of the memory block, with a redundant memory cell, according to the match signal.3. The random number generation circuit according to claim 1 , further comprising:a data input/output unit configured to process input/output data of the memory block, and output the true random number to an exterior of a semiconductor memory through an input/output terminal,wherein the random number generation circuit is included in a semiconductor memory.4. The random number generation circuit according to claim 1 , further comprising:a data input/output unit configured to perform output data encryption by encoding output data of the memory block and the true random number.5. The random number generation circuit according to claim 1 , further comprising:a data input/output unit configured to decode data ...

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Номер записи: 98
21-01-2016 дата публикации

System and method of a novel redundancy scheme for OTP

Номер: US20160019983A1
Автор: Chung Shine C.
Принадлежит:

A novel redundancy scheme to repair no more than one defect per I/O in a One-Time-Programmable (OTP) memory is disclosed. An OTP memory has a plurality of OTP cells in a plurality of I/Os and at least one auxiliary OTP cell associated with each I/O. At least one volatile cell in each I/O corresponds to the auxiliary OTP cells. At least one Boolean gate to invert the data into and/or out of the main OTP memory in each I/O independently based on the data in the volatile cells. The data in each I/O of the OTP memory can be inverted if no more than one defect per I/O is found. Furthermore, the inversion scheme can be achieved by reading the auxiliary OTP cells and storing into the volatile cells by automatically generating at least one read cycle upon initialization.

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Номер записи: 99
18-01-2018 дата публикации

CMOS Anti-Fuse Cell

Номер: US20180019017A1
Автор: Hsu Fu-Chang
Принадлежит:

A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a drain P+ diffusion deposited in the N− well, a source P+ diffusion deposited in the N− well, and an oxide layer deposited on the N− well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region. 1. A circuit able to perform an anti-fuse function , comprising:a first P+ diffusion layer deposited over an N− well substrate and configured to have a first lip extending underneath of a first portion of a first gate oxide;a second P+ diffusion layer deposited over the N− well substrate and configured to have a first lip extending underneath of a second portion of the first gate oxide and a second lip extending underneath of a first portion of a second gate oxide;a polysilicon select gate (“PSG”) situated over the first gate oxide and configured to receive a voltage; anda polysilicon control gate (“PCG”) situated over the second gate oxide and able to breakdown at least a part of the first portion of second gate oxide near the second lip of the second P+ diffusion layer when a high voltage is applied to the PCG.2. The circuit of claim 1 , wherein the high voltage has a voltage range from 3 volts to 7 volts.3. The circuit of claim 1 , wherein the PCG is able to create a short between the PCG and the first portion of second gate oxide when the second P+ diffusion layer has a low voltage.4. The circuit of claim 3 , wherein the low voltage has a voltage range from negative voltage to zero voltage.5. The circuit of claim 1 , wherein the second P+ diffusion ...

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Номер записи: 100