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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 17637. Отображено 100.
05-01-2012 дата публикации

Nonvolatile memory apparatus

Номер: US20120002480A1
Автор: In Suk YUN
Принадлежит: Hynix Semiconductor Inc

A nonvolatile memory device includes: a data transmission line configured to transmit internal configuration data; a data path control unit configured to control a data transmission path direction of the data transmission line according to control of a test signal; and a configuration data latch unit configured to latch a signal transmitted through the data transmission line or drive a latched signal to the data transmission line, according to control of the test signal.

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Номер записи: 1
09-02-2012 дата публикации

Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device

Номер: US20120033516A1
Автор: Chang-Ho Do
Принадлежит: Individual

A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal.

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Номер записи: 2
16-02-2012 дата публикации

Semiconductor integrated circuit with multi test

Номер: US20120039137A1
Автор: Jong Won Lee, Shin Ho Chu
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

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Номер записи: 3
01-03-2012 дата публикации

System and method for testing integrated circuits

Номер: US20120054565A1
Автор: Chu Pang Huang, Yin-Chin Huang
Принадлежит: Macronix International Co Ltd

A method of testing a semiconductor memory device includes reading previously written test data from the semiconductor memory device simultaneously through at least two data I/O connections, e.g., pins or pads, of the semiconductor memory device. The signals from the two data I/O connections are combined to produce a compound output signal. The compound output signal is received by a single I/O channel of a tester. The tester compares the compound output signal to a predetermined voltage level, and determines whether the semiconductor memory device is operating properly based on the comparison of the compound output signal to the predetermined voltage level

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Номер записи: 4
22-03-2012 дата публикации

On-Chip Memory Testing

Номер: US20120072790A1
Автор: Daniel Robert Burggraf, III, Hari Pendurty
Принадлежит: Texas Instruments Inc

An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

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Номер записи: 5
05-04-2012 дата публикации

Data recovery using outer codewords stored in volatile memory

Номер: US20120084627A1
Автор: Daniel J. Post, Kenneth Herman
Принадлежит: Apple Inc

Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface of an electronic device can program user data to a super block of the NVM. The NVM interface can then determine if a program disturb has occurred in the super block. In response to detecting that a program disturb has occurred in the super block, the NVM interface can perform garbage collection on the super block. The NVM interface can then use outer codewords associated with the super block to recover from any uncorrectable error correction code errors detected in the super block.

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Номер записи: 6
19-04-2012 дата публикации

Apparatus and methods for tuning a memory interface

Номер: US20120096218A1
Автор: Dan Shimizu, Eric Scott, Joe Macri, Sagheer Ahmad
Принадлежит: ATI TECHNOLOGIES ULC

The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

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Номер записи: 7
19-04-2012 дата публикации

Semiconductor package

Номер: US20120096322A1
Автор: Kwi-Dong Kim, Tae-Hyoung HUH
Принадлежит: Hynix Semiconductor Inc

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

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Номер записи: 8
10-05-2012 дата публикации

Test apparatus

Номер: US20120112783A1
Автор: Daisuke Watanabe, Masahiro Ishida, Masayuki Kawabata, Toshiyuki Okayasu
Принадлежит: Advantest Corp

A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer.

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Номер записи: 9
10-05-2012 дата публикации

Memory card

Номер: US20120117430A1
Автор: Kui-Hyun RO, Sung-Eun YUN, Young-Jae Jung, Yun-Bo Yang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory card includes a memory cell, a connector, a controller, and firmware. The memory cell can switch between a plurality of states. The connector can be connected to an external device and exchange signals including commands and data with the external device. The controller exchanges signals with the connector, analyzes a received signal, and accesses the memory cell to record, retrieve or modify data based on the analysis result. The firmware is located within the controller, controls the operation of the controller, and can be set to a test mode or a user mode. When the firmware receives a test command from the external device and the firmware is set to the test mode, the firmware performs a defect test on the memory cell and transmits the result of the defect test to the external device through the connector.

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Номер записи: 10
24-05-2012 дата публикации

Memory controller and information processing system

Номер: US20120131382A1
Автор: Masanori Higeta
Принадлежит: Fujitsu Ltd

A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.

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Номер записи: 11
24-05-2012 дата публикации

Memory device

Номер: US20120131418A1
Автор: Hideki Yoshida, Masaya Tarui, Tatsunori Kanai, Yutaka Yamada
Принадлежит: Toshiba Corp

According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

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Номер записи: 12
31-05-2012 дата публикации

Allocation method and apparatus of moderate memory

Номер: US20120137104A1
Автор: Guoping Li, HE Huang, Qinghua FAN
Принадлежит: Artek Microelectronics Co Ltd

An allocation method comprises: partitioning moderate memory into a plurality of physical memory pages having predetermined page size according to the predetermined page size; scanning the moderate memory using the predetermined page size and recording the physical address and damage degree of each physical memory page; obtaining the allocation information of the physical memory pages when a memory request is received and allocating physical memory to the request based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information. A moderate memory is scanned and the physical address and damage degree of each physical memory page are recorded, then the physical memory is allocated based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information.

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Номер записи: 13
07-06-2012 дата публикации

Semiconductor apparatus

Номер: US20120139508A1
Автор: Tatsuya Matano
Принадлежит: Elpida Memory Inc

A device includes a first internal voltage generation circuit generating a first internal voltage in response to an external power supply voltage, a second internal voltage generation circuit generating a second internal voltage in response to the external power supply voltage, the second internal voltage being different in voltage level from the first internal voltage, and a preset signal generation circuit responding to a power-on of the external power supply voltage to the device and generating, independently of the first internal voltage, first and second preset signals that bring the first and the second internal voltage generation circuits into respective initial states, the preset signal generating circuit stopping generation of the first preset signal when the external power supply voltage reaches a first voltage level and stopping generation of the second preset signal when the external power supply voltage reaches a second voltage level different from the first voltage level.

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Номер записи: 14
14-06-2012 дата публикации

Embedded DRAM having Low Power Self-Correction Capability

Номер: US20120151299A1
Автор: Jungwon Suh
Принадлежит: Qualcomm Inc

Apparatuses and methods for low power combined self-refresh and self-correction of a Dynamic Random Access Memory (DRAM) array. During a self-refresh cycle, a first portion of a first row of the DRAM array is accessed and analyzed for one or more errors, wherein a bit width of the first portion is less than a bit width of the first row. If one or more errors are detected, the one or more errors are corrected to form a corrected first portion. The corrected first portion is selectively written back to the first row. If no errors are detected in the first portion, a write back of the first portion to the first row is prevented.

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Номер записи: 15
28-06-2012 дата публикации

Single check memory devices and methods

Номер: US20120163076A1
Автор: Aaron Yip, Tomoharu Tanaka, Vishal Sarin
Принадлежит: Individual

Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.

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Номер записи: 16
28-06-2012 дата публикации

Data management in flash memory using probability of charge disturbances

Номер: US20120166897A1
Автор: Luiz M. Franca-Neto, Richard Leo Galbraith, Travis Roger Oenning
Принадлежит: Individual

A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.

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Номер записи: 17
19-07-2012 дата публикации

Semiconductor apparatus, method for assigning chip ids therein, and method for setting chip ids thereof

Номер: US20120182042A1
Автор: Chun Seok Jeong, Jae Jin Lee
Принадлежит: Hynix Semiconductor Inc

A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.

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Номер записи: 18
02-08-2012 дата публикации

Cell operation monitoring

Номер: US20120195126A1
Автор: Frankie F. Roohparvar
Принадлежит: Micron Technology Inc

Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation.

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Номер записи: 19
02-08-2012 дата публикации

Locally synchronous shared bist architecture for testing embedded memories with asynchronous interfaces

Номер: US20120198291A1
Автор: Akhil Garg, Prashant Dubey, Sravan Kumar Bhaskarani
Принадлежит: STMICROELECTRONICS PVT LTD

A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

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Номер записи: 20
02-08-2012 дата публикации

Non-volatile semiconductor memory device

Номер: US20120198297A1
Автор: Kenji Sawamura, Takeshi Kamigaichi
Принадлежит: Toshiba Corp

A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

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Номер записи: 21
02-08-2012 дата публикации

Soft decoding systems and methods for flash based memory systems

Номер: US20120198314A1
Автор: Gregory Burd, Xueshi Yang
Принадлежит: MARVELL WORLD TRADE LTD

Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

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Номер записи: 22
16-08-2012 дата публикации

Memory module and video camera

Номер: US20120210049A1
Автор: Isao Ozawa, Yasuyuki NAGAHARA
Принадлежит: Toshiba Corp

According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.

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Номер записи: 23
30-08-2012 дата публикации

Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus

Номер: US20120218846A1
Автор: Yong Gu Kang
Принадлежит: SK hynix Inc

A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

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Номер записи: 24
30-08-2012 дата публикации

Embedded processor

Номер: US20120221911A1
Автор: Joe M. Jeddeloh
Принадлежит: Individual

Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

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Номер записи: 25
20-09-2012 дата публикации

Device for Releasably Receiving a Semiconductor Chip

Номер: US20120238042A1
Автор: Peter Ossimitz
Принадлежит: INFINEON TECHNOLOGIES AG

A device is disclosed for releasably receiving a singulated semiconductor chip having a first main surface and a second main surface opposite the first main surface. The device includes a support structure. At least one elastic element is arranged on the support structure. Electrical contact elements are arranged on the at least one elastic element and adapted to be contacted to the first main surface of the semiconductor chip. A foil is adapted to be arranged over the second main surface of the semiconductor chip.

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Номер записи: 26
18-10-2012 дата публикации

Semiconductor memory device and test method thereof

Номер: US20120266034A1
Автор: Sang-Hoon Shin
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a plurality of memory cells; a data comparison section configured to compare input data to be stored in the memory cells with output data outputted from the memory cells in a test operation, an address storage section configured to store addresses corresponding to defected memory cells of the memory cells in response to a comparison result of the data comparison section, and a comparison period control section configured to generate a period control signal for controlling an activation period of the data comparison section.

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Номер записи: 27
18-10-2012 дата публикации

Semiconductor memory device

Номер: US20120266043A1
Автор: Kazuya Ishihara, Mitsuru Nakura, Nobuyoshi Awaya
Принадлежит: Individual

The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

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Номер записи: 28
01-11-2012 дата публикации

Internal wordline current leakage self-detection method, detection system and computer-readable storage medium for nor-type flash memory device

Номер: US20120275228A1
Автор: Hsiao-Hua Lu
Принадлежит: Eon Silicon Solutions Inc

A wordline internal current leakage self-detection method, system and a computer-readable storage medium thereof employ the originally existed high voltage supply unit and the voltage detector connected to the wordline in the flash memory device, in which the high voltage supply unit applies the test signal to the selected wordline, and the voltage detector detects the voltage signal of the wordline. By comparing the test signal with the voltage signal, the wordline will be indicated as current leakage when the voltage signal is lower than the test signal.

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Номер записи: 29
13-12-2012 дата публикации

Non-volatile memory device having phase-change material and method for fabricating the same

Номер: US20120314492A1
Автор: Ji-Won Jung, Yong-Shik Shin
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory cells. In the non-volatile memory device, a circuit of the at least one second memory cell is cut off according to the initial information, and the initial information is defective block information that is information about a defect of the plurality of memory blocks.

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Номер записи: 30
20-12-2012 дата публикации

Memory device repair apparatus, systems, and methods

Номер: US20120324298A1
Автор: Adrian J. Drexler, Yutaka Ito
Принадлежит: Individual

Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.

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Номер записи: 31
03-01-2013 дата публикации

Stored data reverification management system and method

Номер: US20130006927A1
Автор: Brian Brockway, Jun Lu, Parag Gokhale
Принадлежит: Commvault Systems Inc

A system and method are provided for verifying data copies and reverifying the copies over the life span of media according to a verification policy. Characteristics of media and use of media are tracked to provide metrics which may be used to dynamically reevaluate and reassign verification policies to optimize media usage. Copies that fail verification operations may be repaired by repeating a storage operation for recent copies or by substituting a close temporal copy of the failed copy.

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Номер записи: 32
10-01-2013 дата публикации

Method of Detecting Connection Defects of Memory and Memory Capable of Detecting Connection Defects thereof

Номер: US20130010558A1
Автор: Lien-Sheng Yang, Min-Chih Chang, Shih-Hsing Wang, Te-Yi Yu
Принадлежит: Individual

By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.

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Номер записи: 33
24-01-2013 дата публикации

Mechanisms for built-in self test and repair for memory devices

Номер: US20130021861A1
Автор: Saman M. I. Adham, Volodymyr SHVYDUN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Mechanisms for self-testing and self-repairing memories are efficient in testing and repairing failed memory cells. The self-test-repair mechanisms are based on self-test results of failed bit map (FBM) data of the entire memories and enable early determination of non-repairable memories to prevent and limit wasting time and resources on non-repairable memories. The self-test-repair mechanisms also involve identifying candidates for column and row repairs and allow repeated repair cycles until either the memories are deemed irreparable or are fully repaired.

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Номер записи: 34
07-02-2013 дата публикации

Testing memory subsystem connectivity

Номер: US20130036255A1
Автор: Anthony Fai, Nicholas Seroff, Nir Jacob Wakrat
Принадлежит: Apple Inc

In one implementation, a memory subsystem includes a plurality of non-volatile memory dies, a memory controller that is communicatively connected to each of the non-volatile memory dies over one or more first busses, a host interface through which the memory controller communicates with a host over a second bus, and a joint test action group (JTAG) interface through which the host performs a boundary scan of the memory subsystem including, at least, the non-volatile memory dies and the memory controller. The memory subsystem can be configured to be a subunit of a board-level memory device that includes the host.

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Номер записи: 35
21-02-2013 дата публикации

Error indicator from ecc decoder

Номер: US20130047045A1
Автор: Anthony D. Weathers, Richard D. Barndt, Xinde Hu
Принадлежит: Stec Inc

The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.

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Номер записи: 36
21-02-2013 дата публикации

Dram test architecture for wide i/o dram based 2.5d/3d system chips

Номер: US20130047046A1
Автор: Sandeep Kumar Goel
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.

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Номер записи: 37
28-02-2013 дата публикации

High speed multiple memory interface i/o cell

Номер: US20130049799A1
Автор: Cheng-Gang Kong, Dharmesh Bhakta, Hong-Him Lim, Todd Randazzo
Принадлежит: LSI Corp

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

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Номер записи: 38
14-03-2013 дата публикации

Flash memory storage device and method of judging problem storage regions thereof

Номер: US20130067142A1
Автор: Chiang-Chang Hsien, Chih-Ming Hsu, Kuo-Chung Liao, Yen-Hsin Liu, Young-Joon Choi, Yun-Hui Wang
Принадлежит: A Data Technology Suzhou Co Ltd

A method of judging problem storage regions adapted for a flash memory storage device includes steps of: sending a writing order to a flash memory chip for writing a written data to an appointed storage paging; when the flash memory chip beginning writing the written data to the appointed storage paging, getting the first time; when the flash memory chip finishing writing the written data to the appointed storage paging, getting the second time; calculating a writing time according to the first time and the second time; if the writing time not coincident with a standard value, then labeling the appointed storage paging as a problem storage region and copying the written data to a backup paging; updating a Mapping Table.

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Номер записи: 39
21-03-2013 дата публикации

Semiconductor memory device correcting fuse data and method of operating the same

Номер: US20130070548A1
Автор: Byung-Hoon Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.

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Номер записи: 40
28-03-2013 дата публикации

Integrated solution for identifying malfunctioning components within memory devices

Номер: US20130077422A1
Автор: Carolina Selva, Danilo Rimondi
Принадлежит: STMICROELECTRONICS SRL

A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.

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Номер записи: 41
28-03-2013 дата публикации

Setting data storage for semiconductor devices including memory devices and systems

Номер: US20130080830A1
Автор: Sam-Kyu Won
Принадлежит: SK hynix Inc

A setting data storage circuit includes a setting data storage block configured to store setting data; an access unit configured to access the setting data of the setting data storage block; an error detection unit configured to detect an error in the setting data; and an error recovery unit configured to recover an error in the setting data storage block when the error detection unit detects an error.

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Номер записи: 42
04-04-2013 дата публикации

Apparatus and method to combine pin functionality in an integrated circuit

Номер: US20130082764A1
Автор: Ajat Hukkoo, Kerry Alan THOMPSON, Love Kothari, Mark Fullerton, Paul Penzes, Russell Radke, Veronica Alarcon, Zhongmin Zhang
Принадлежит: Broadcom Corp

An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit.

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Номер записи: 43
09-05-2013 дата публикации

Apparatuses and methods for operating a memory device

Номер: US20130117604A1
Автор: Chang Wan Ha
Принадлежит: Micron Technology Inc

Subject matter described pertains to apparatuses and methods for operating a memory device.

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Номер записи: 44
16-05-2013 дата публикации

Method and apparatus for checking a main memory of a processor

Номер: US20130124925A1
Автор: Christian Hildner
Принадлежит: SIEMENS AG

A method and an apparatus for checking a main memory of a processor, which includes a cache memory and a plurality of registers. Before the memory test is carried out, a boot-up sequence which may be running at that time is interrupted, temporary data required for the memory test is written to at least one register and is held there, and the access from the cache memory to the main memory is activated. The main memory is accessed via the cache memory such that bit patterns are written to the cache memory and from there to the main memory, and are read out again from the main memory via the cache memory and are compared. The area of the main memory to be tested is larger than the size of the cache memory. The interrupted boot-up sequence is then restarted or continued after completion of the memory test.

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Номер записи: 45
23-05-2013 дата публикации

Providing low-latency error correcting code capability for memory

Номер: US20130132799A1
Автор: Joseph Jun Cao, Jun Zhu, Pantas Sutardja, Sheng Lu
Принадлежит: MARVELL WORLD TRADE LTD

A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.

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Номер записи: 46
30-05-2013 дата публикации

Systems and methods for testing and assembling memory modules

Номер: US20130135951A1
Автор: Eric Sin Kwok CHIU, Lawrence Wai Cheung Ho
Принадлежит: Kingtiger Technology Canada Inc

Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises, for each memory device of a plurality of memory devices, based on testing performed on the memory device, determining whether the memory device has any defective memory locations, and if so, identifying the one or more defective memory locations, and generating data that identifies the one or more defective memory locations on the memory device; and assembling a memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises, for each memory device of the memory module having one or more defective memory locations, storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module.

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Номер записи: 47
13-06-2013 дата публикации

Control scheme for 3d memory ic

Номер: US20130148402A1
Автор: Chien-yuan Chen, Meng-Fan Chang, Tsung-Hsien Huang, Wei-Cheng Wu
Принадлежит: National Tsing Hua University NTHU

The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.

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Номер записи: 48
27-06-2013 дата публикации

Semiconductor integrated circuit and method of testing semiconductor integrated circuit

Номер: US20130163356A1
Автор: Hiroyuki Fujimoto, Hitoshi Yamanaka, Masahiro Yanagida
Принадлежит: Fujitsu Ltd

A semiconductor integrated circuit includes a plurality of memory cells, a plurality of receivers, each of the plurality of receivers being provided for a corresponding one of a plurality of units set by dividing the plurality of memory cells in a unit, and each of the plurality of receivers receiving a test result of the corresponding one of the plurality of units, and a controller that reads out a plurality of test results from the plurality of receivers.

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Номер записи: 49
04-07-2013 дата публикации

Electronic device and method for testing endurance of memory

Номер: US20130170307A1
Автор: Min Tan
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

An electronic device for endurance test of a memory includes an interface, a storage unit, an obtaining unit, and a control unit. The interface is for connecting the memory to the electronic device. The storage unit stores a variety of test packages for different storage capacities of memories and at least one test option associated with each test package. The test option defines a predetermined capacity of the associated memory to be tested. The obtaining unit obtains a storage capacity of the memory connected to the electronic device. The control unit selects one of the at least one test option associated with one of the test packages corresponding to the obtained storage capacity, selects a plurality of blocks according to the predetermined capacity of the selected test option, assigns corresponding logical addresses to the selected blocks, and then tests the endurance of the selected blocks.

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Номер записи: 50
11-07-2013 дата публикации

Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit

Номер: US20130176772A1
Автор: Wah Kit Loh, Xiaowei Deng, Yang Yi
Принадлежит: Texas Instruments Inc

A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

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Номер записи: 51
25-07-2013 дата публикации

Method for monitoring a data memory

Номер: US20130191701A1
Автор: Bernd Mueller, Carsten Gebauer, Dieter Thoss
Принадлежит: ROBERT BOSCH GMBH

A method is described for monitoring a data memory in which an error detection method is used to detect and/or correct incorrect data words stored in memory lines of the data memory, an address of the data memory at which a data word evaluated as incorrect by the error detection method is stored being written to an auxiliary memory and being made available to a checking program.

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Номер записи: 52
08-08-2013 дата публикации

Built-in test circuit and method

Номер: US20130201776A1
Автор: Fang Jao, Hung-jen Liao, Tzu-Kuei LIN, Yen-Huei Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.

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Номер записи: 53
15-08-2013 дата публикации

Apparatus And Method For Repairing An Integrated Circuit

Номер: US20130210170A1
Автор: Ding-Ming Kwai, Yung-Fa Chou
Принадлежит: Industrial Technology Research Institute ITRI

A method for repairing an integrated circuit comprises: fabricating a first circuit, the first circuit including a plurality of regular units and a plurality of redundant units, each of the regular units being identified by an address; performing a first test on the first circuit to determine if a defective regular unit is present; activating, if the defective regular unit is present, at least a first redundant unit to replace the defective regular unit, the first redundant unit being identified by an address of the defective regular unit; performing, if the at least first redundant unit is present, a second test on the first circuit to determine if the first redundant unit is defective; and activating at least a second redundant unit to replace the defective first redundant unit, the second redundant unit being identified by the address of the defective regular unit.

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Номер записи: 54
15-08-2013 дата публикации

Method for Data Accessing and Memory Writing for Logic Analyzer

Номер: US20130212346A1
Автор: Chiu-Hao Cheng
Принадлежит: Zeroplus Technology Co Ltd

A method of fetching digital data and writing the digital data into a memory of a logic analyzer, which comprises the steps: designate at least a first region and a second region in a memory; set a first triggering condition and a second triggering condition; fetch digital data continuously and write it into the memory while analyzing; and then write first test data which have an identification to satisfy the first triggering condition into the first region, and write second test data which have an identification to satisfy the second triggering condition into the second region. And once the first test data or the second test data are found, stop writing the digital data into the corresponding regions.

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Номер записи: 55
22-08-2013 дата публикации

Spin-transfer torque memory self-reference read method

Номер: US20130215674A1
Автор: Dimitar V. Dimitrov, Hai Li, Henry F. Huang, Hongyue Liu, Kang Yong Kim, Yiran Chen
Принадлежит: SEAGATE TECHNOLOGY LLC

A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

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Номер записи: 56
22-08-2013 дата публикации

Tracking capacitive loads

Номер: US20130215693A1
Автор: Annie-Li-Keow Lum, Bing Wang, Derek C. Tao, Kuoyuan (Peter) Hsu, Young Seog Kim
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.

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Номер записи: 57
22-08-2013 дата публикации

Circuit for driving word line

Номер: US20130215697A1
Автор: Byeong Chan CHOI, Gyung Tae Kim
Принадлежит: SK hynix Inc

A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.

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Номер записи: 58
22-08-2013 дата публикации

Semiconductor memory device changing refresh interval depending on temperature

Номер: US20130215700A1
Автор: Akinobu Shirota, Kuninori Kawabata
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

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Номер записи: 59
29-08-2013 дата публикации

Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability

Номер: US20130222071A1
Автор: Ching-Te Chuang, Hao-I Yang, Kuen-Di Lee, Ming-Chien Tsai, Ming-Hsien Tu, Nan-Chun Lien, Shyh-Jye Jou, Wei Hwang, Wei-Chiang Shih, Yi-Wei Lin
Принадлежит: National Chiao Tung University NCTU

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

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Номер записи: 60
29-08-2013 дата публикации

Deeply pipelined integrated memory built-in self-test (bist) system and method

Номер: US20130223168A1
Автор: Gary L. Taylor, Rosalee D. Gunderson
Принадлежит: Avago Technologies Enterprise IP Singapore Pte Ltd

A memory system with integrated memory built-in self-test (BIST) circuitry has one or more pipeline registers interposed between combinational logic elements. These combinational logic elements can include write data decoding logic, memory control signal decoding logic, address counter logic, address comparison logic, data comparison logic, and next state decoding logic. Features can be included that compensate for the delay inherent in the pipeline registers.

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Номер записи: 61
29-08-2013 дата публикации

Semiconductor Device Capable of Rescuing Defective Characteristics Occurring After Packaging

Номер: US20130223171A1
Автор: Jeong-Kyoum Kim, Jung-hwan Choi, Seok-Hun Hyun, Seong-Jin Jang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

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Номер записи: 62
19-09-2013 дата публикации

Method and Apparatus for Shortened Erase Operation

Номер: US20130242665A1
Автор: Chang-Ting Chen, Chin-Hung Chang, Chun-Hsiung Hung, Ken-Hui Chen, Kuen-Long Chang, Nai-Ping Kuo
Принадлежит: Macronix International Co Ltd

A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

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Номер записи: 63
19-09-2013 дата публикации

Test circuit, memory system, and test method of memory system

Номер: US20130246867A1
Автор: Hong-Sik Kim, Hyung-Dong Lee, Hyung-Gyun YANG, Yong-Kee KWON, Young-Suk Moon
Принадлежит: Individual

This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.

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Номер записи: 64
26-09-2013 дата публикации

Selected word line dependent programming voltage

Номер: US20130250688A1
Автор: Bo Lei, Guirong Liang, Lanlan Gu, Wenzhou Chen
Принадлежит: SanDisk Technologies LLC

Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines.

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Номер записи: 65
26-09-2013 дата публикации

Selected word line dependent select gate diffusion region voltage during programming

Номер: US20130250689A1
Автор: Chun-Hung Lai, Gerrit Jan Hemink, Shih-Chung Lee, Shinji Sato
Принадлежит: SanDisk Technologies LLC

Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.

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Номер записи: 66
10-10-2013 дата публикации

Semiconductor device having plural data input/output terminals

Номер: US20130265831A1
Автор: Teppei MIYAJI, Yoshinori Matsui
Принадлежит: Elpida Memory Inc

Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

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Номер записи: 67
24-10-2013 дата публикации

Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System

Номер: US20130283002A1
Автор: Abhijeet A. Chachad, Raguram Damodaran, Ramakrishnan Venkatasubramanian
Принадлежит: Texas Instruments Inc

In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

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Номер записи: 68
24-10-2013 дата публикации

Data integrity in memory controllers and methods

Номер: US20130283124A1
Автор: Jui-Yao Yang, Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie
Принадлежит: Micron Technology Inc

The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

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Номер записи: 69
31-10-2013 дата публикации

Method and System For Error Correction in Flash Memory

Номер: US20130290813A1
Автор: Aditya Ramamoorthy, Pantas Sutardja, Zining Wu
Принадлежит: MARVELL WORLD TRADE LTD

A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

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Номер записи: 70
14-11-2013 дата публикации

Switchable on-die memory error correcting engine

Номер: US20130305123A1
Автор: Gurkirat Billing, Mark Leinwander, Samuel David Post, Stephen Bowers
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.

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Номер записи: 71
28-11-2013 дата публикации

Programming rate identification and control in a solid state memory

Номер: US20130314993A1
Автор: Frankie F. Roohparvar
Принадлежит: Micron Technology Inc

Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate.

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Номер записи: 72
28-11-2013 дата публикации

Adaptive error correction for phase change memory

Номер: US20130318418A1
Автор: Alessandro Tomasoni, Christophe Laurent, Ferdinando Bedeschi, Paolo Amato, Roberto Gastaldi, Sandro Bellini
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to memory operations regarding error correction or error detection.

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Номер записи: 73
05-12-2013 дата публикации

Memory device to correct defect cell generated after packaging

Номер: US20130322160A1
Автор: Cheol Kim, Jung-Sik Kim, Sang-Ho Shin
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device to correct a defect cell generated after packing is performed includes a memory cell array in which a plurality of memory cells are arranged, a repair circuit unit including a first storage unit to store defect cell information in the memory cell array, and a fuse circuit unit including a second storage unit that is programmed according to the defect cell information stored in the first storage unit. The first storage unit includes a volatile memory device, and the second storage unit includes a non-volatile memory device.

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Номер записи: 74
05-12-2013 дата публикации

On-chip memory testing

Номер: US20130322176A1
Автор: Daniel R. Burggraf, III, Hari Pendurty
Принадлежит: Texas Instruments Inc

An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

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Номер записи: 75
05-12-2013 дата публикации

Data processing device, microcontroller, and self-diagnosis method of data processing device

Номер: US20130325206A1
Автор: Akira HOSOTANI
Принадлежит: Renesas Electronics Corp

A data processing device according to the present invention includes a memory, an arithmetic circuit that accesses the memory by outputting an access control signal CTRL that controls access to the memory, a first data storage unit that stores first data used when a self-diagnosis is performed, a read-modify-write circuit that generates second data by replacing a part of the first data stored in the first data storage unit with modify data outputted from the arithmetic circuit, and a determination unit that diagnoses a failure of the read-modify-write circuit by comparing the second data with an expected value.

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Номер записи: 76
05-12-2013 дата публикации

Apparatus, system, and method for managing solid-state storage reliability

Номер: US20130326284A1
Автор: James G. Peterson, Warner Losh
Принадлежит: Fusion IO LLC

A storage controller may be configured to assess the reliability of a solid-state storage medium. The storage controller may be further configured to project, forecast, and/or estimate storage reliability at a future time. The projection may be based on a currently reliability metric of the storage and a reliability model. The portions or sections of the solid-state storage media may be retired in response the projected reliability metric failing to satisfy a reliability threshold. The reliability threshold may be based on data correction and/or reconstruction characteristics. The projected reliability metrics of a plurality of erase blocks of a storage division may be combined, and one or more of the erase blocks may be retired in response to determining that the combined reliability metric projection fails to satisfy the reliability threshold.

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Номер записи: 77
05-12-2013 дата публикации

Memory error test routine

Номер: US20130326293A1
Автор: Andrew C. Walton, Melvin K. Benedict, Naveen Muralimanohar, Norman Paul Jouppi
Принадлежит: Hewlett Packard Development Co LP

An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure is to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.

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Номер записи: 78
12-12-2013 дата публикации

Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel

Номер: US20130332680A1
Автор: Kyu-Hyoun Kim, Paul W. Coteus
Принадлежит: International Business Machines Corp

A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.

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Номер записи: 79
26-12-2013 дата публикации

Device and method for storing encoded and/or decoded codes by re-using encoder

Номер: US20130346828A1
Автор: Yiqi Wang, Zhengsheng Han
Принадлежит: Institute of Microelectronics of CAS

The present disclosure provides a device and method for storing encoded and/or decoded codes by re-using an encoder. The device and method for storing the encoded and/or decoded codes according to the present disclosure enables re-use of the encoder during a decoding process, which makes it unnecessary to use additional hardware and thereby reduces an area consumed by an EDAC (error detection and correction) decoder.

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Номер записи: 80
30-01-2014 дата публикации

Memory module and a memory test system for testing the same

Номер: US20140032984A1
Автор: Hyun-Soo Kim, Jung-Kuk Lee, Sang-Seok Kang, Woo-seop Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

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Номер записи: 81
06-02-2014 дата публикации

Error prediction in logic and memory devices

Номер: US20140040692A1
Автор: Dharin N. Shah, SHARAD Gupta, Vinod Joseph Menezes, Vish Visvanathan
Принадлежит: Texas Instruments Inc

Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.

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Номер записи: 82
13-02-2014 дата публикации

Semiconductor device failure analysis system and semiconductor memory device

Номер: US20140043360A1
Автор: Mami Kodama, Yoshikazu Iizuka
Принадлежит: Toshiba Corp

A semiconductor device failure analysis system according to an embodiment of the present invention includes a memory configured to be capable of retaining an initial display information; and a control unit configured to generate a first image based on a configuration information of the semiconductor device and a plurality of fail bit information of the semiconductor device, the semiconductor device including a three-dimensional memory cell array, and to generate a second image from the first image based on the initial display information, the second image corresponding to part of the plurality of fail bit information. The semiconductor device failure analysis system according to the embodiment further includes a display configured to be capable of initially displaying the second image.

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Номер записи: 83
13-02-2014 дата публикации

Memory system and memory controller

Номер: US20140047281A1
Автор: Hironobu Miyamoto, Yoko Masuo
Принадлежит: Toshiba Corp

According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. The memory controller includes a monitoring module and a determination module. The monitoring module acquires an elapsed time from the start of data erase of a first block in the NAND-type flash memory. The determination module determines whether the elapsed time has exceeded a reference time before completion of the data write in the first block.

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Номер записи: 84
13-02-2014 дата публикации

Solid state drive tester

Номер: US20140047286A1
Автор: Eui Won LEE, Hyo Jin Oh
Принадлежит: UniTest Inc

Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

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Номер записи: 85
13-02-2014 дата публикации

Error generating apparatus for solid state drive tester

Номер: US20140047290A1
Автор: Eui Won LEE, Hyo Jin Oh
Принадлежит: UniTest Inc

Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.

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Номер записи: 86
27-02-2014 дата публикации

Method of identifying damaged bitline address in non-volatile memory device

Номер: US20140056088A1
Автор: Takao Akaogi, Tony Chan
Принадлежит: Eon Silicon Solutions Inc

A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.

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Номер записи: 87
06-03-2014 дата публикации

Memory devices, circuits and, methods that apply different electrical conditions in access operations

Номер: US20140063902A1
Автор: Ishai Naveh, Malcolm Wing, Ravi Sunkavalli
Принадлежит: Adesto Technologies Corp

A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

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Номер записи: 88
06-03-2014 дата публикации

Memory operation upon failure of one of two paired memory devices

Номер: US20140063987A1
Автор: Edgar R. Cordero, Girisankar Paulraj, Saravanan Sethuraman, Timothy J. Dell
Принадлежит: International Business Machines Corp

A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.

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Номер записи: 89
06-03-2014 дата публикации

Semiconductor memory device

Номер: US20140068154A1
Автор: Katsuhiko Hoya
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor memory device includes a first memory circuit and a first controller. The first memory circuit includes a register in which a read page size is stored, and a memory cell array. The first controller is configured to access the first memory circuit by the page size stored in the register, in one of an open page policy and closed page policy.

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Номер записи: 90
13-03-2014 дата публикации

Technique for Determining Performance Characteristics Of Electronic Devices And Systems

Номер: US20140070819A1
Автор: Haw-Jyh Liaw, Mark A. Horowitz, Xingchao Yuan
Принадлежит: RAMBUS INC

A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

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Номер записи: 91
13-03-2014 дата публикации

Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay

Номер: US20140071775A1
Автор: Bijan Kumar Ghosh, Donald Albert Evans, Rasoju Veerabadra Chary, Richard John Stephani, Ronald Brian Steele
Принадлежит: LSI Corp

A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

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Номер записи: 92
13-03-2014 дата публикации

Outputting Information of ECC Corrected Bits

Номер: US20140075265A1
Автор: Chun-Hsiung Hung, Hsin Yi Ho
Принадлежит: Macronix International Co Ltd

The present invention provides a method of operating a memory device storing error correcting codes ECCs for corresponding data and including ECC logic to correct errors using the ECCs. The method includes correcting data using ECCs for the data on the memory device, and producing information on the memory device about the use of the ECCs. The method provides the ECC information on an output port of the device in response to a command received on an input port from a process external to the memory device. The present invention also provides a method of controlling a memory device. The method includes sending a command to the memory device requesting ECC information corresponding to data in the memory device, and receiving the ECC information from the memory device in response to the command. The method includes performing a memory management function using the ECC information.

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Номер записи: 93
27-03-2014 дата публикации

Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method of the same

Номер: US20140089574A1
Автор: Dae-Hyun Kim, Seung-Jun Bae, Tae-Young Oh, Woo-Jin Lee, Young-Soo Sohn
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device storing memory characteristic information, a memory module including the semiconductor memory device, a memory system, and an operating method of the semiconductor memory device. The semiconductor memory device may include a cell array including a plurality of areas; a command decoder configured to decode a command and generate an internal command; and an information storage unit configured to store characteristic information of at least one of the plurality of areas. When a first command and a first row address accompanying the first command are received, characteristic information of an area corresponding to the first row address is provided to an outside.

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Номер записи: 94
27-03-2014 дата публикации

Serial advanced technology attachment dual in-line memory module device having testing circuit for capacitor

Номер: US20140089739A1
Автор: Guo-Yi Chen, Xiao-Gang Yin
Принадлежит: Individual

A serial advanced technology attachment dual in-line memory module device includes a capacitor to be tested, a control chip, a display device, a testing chip, and a selecting chip. Voltage pins of the testing chip and the selecting chip are connected to a power source. A testing pin of the testing chip is connected to the capacitor. A first input output (I/O) pin of the selecting chip is connected to a first I/O pin of the testing chip. A second I/O pin of the selecting chip is connected to a second I/O pin of the testing chip. A third I/O pin of the selecting chip is connected to an input pin of the control chip. A fourth I/O pin of the selecting chip is connected to an output pin of the control chip. A fifth I/O pin of the selecting chip is connected to the display device.

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Номер записи: 95
03-04-2014 дата публикации

Functional memory array testing with a transaction-level test engine

Номер: US20140095947A1
Автор: Christopher P. Mozak, James M. Shehadi, Theodore Z. Schoenborn
Принадлежит: Individual

A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.

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Номер записи: 96
03-04-2014 дата публикации

Method and apparatus for diagnosing a fault of a memory using interim time after execution of an application

Номер: US20140095949A1
Автор: Hiroshi Nakatani, Makoto Toko, Naoya OHNISHI, Satoru Amaki, Yoshito Sameda
Принадлежит: Toshiba Corp

An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.

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Номер записи: 97
03-04-2014 дата публикации

Semiconductor device and operating method thereof

Номер: US20140095962A1
Автор: Hong-Sik Kim, Yong-Kee KWON, Young-Suk Moon
Принадлежит: SK hynix Inc

An operating method of a semiconductor device may comprise monitoring error handling information for a data read from a semiconductor memory device; and generating a refresh request for one or more memory cells of the semiconductor memory device according to the error handling information.

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Номер записи: 98
10-04-2014 дата публикации

Apparatuses and methods for sensing fuse states

Номер: US20140098623A1
Автор: Marco Sforzin
Принадлежит: Micron Technology Inc

Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of the plurality of sense lines and configured to receive a sense voltage from a cell of the plurality of cells. The sense voltage may be based, at least in part, on a state of a fuse corresponding to the cell of the plurality of cells. The fuse sense circuit may further be configured to compare the sense voltage to a reference voltage to provide a fuse state control signal indicative of the state of the fuse.

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Номер записи: 99
10-04-2014 дата публикации

Encoding and Decoding Redundant Bits to Accommodate Memory Cells Having Stuck-At Faults

Номер: US20140101517A1
Автор: Cyril Guyot, Hessam Mahdavifar, Luiz Franca-Neto, Qingbo Wang, Robert Eugeniu Mateescu, Zvonimir Bandic
Принадлежит: HGST NETHERLANDS BV

A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.

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Номер записи: 100