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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 13664. Отображено 100.
05-01-2012 дата публикации

Output enable signal generation circuit of semiconductor memory

Номер: US20120002493A1
Автор: Hee Jin Byun
Принадлежит: Hynix Semiconductor Inc

An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).

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Номер записи: 1
05-01-2012 дата публикации

Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction

Номер: US20120005420A1
Автор: Christopher S. Johnson
Принадлежит: Round Rock Research LLC

One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

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Номер записи: 2
12-01-2012 дата публикации

Semiconductor memory device

Номер: US20120008433A1
Автор: Hyun-Su Yoon, Jong-Chern Lee, Seung-joon Ahn
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.

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Номер записи: 3
26-01-2012 дата публикации

Dynamic impedance control for input/output buffers

Номер: US20120019282A1
Автор: Bruce Millar
Принадлежит: Mosaid Technologies Inc

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

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Номер записи: 4
26-01-2012 дата публикации

Memory system with delay locked loop (dll) bypass control

Номер: US20120020171A1
Автор: Kevin C. Gower, Kyu-Hyoun Kim, Lisa C. Gower, Warren E. Maule
Принадлежит: International Business Machines Corp

A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

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Номер записи: 5
16-02-2012 дата публикации

Memory systems and memory modules

Номер: US20120042204A1
Автор: Michael John Sebastian Smith, Suresh Natarajan Rajan
Принадлежит: Google LLC

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

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Номер записи: 6
08-03-2012 дата публикации

Communication system and its method and communication apparatus and its method

Номер: US20120059497A1
Автор: Akihiro Morohashi
Принадлежит: Sony Corp

This invention relates to a communication system including a first apparatus having a first storage medium, and a second apparatus for transmitting data to the first apparatus, the second apparatus comprising: a second storage medium for storing management information of data to be transferred to the first storage medium; communication means for communicating data with the first apparatus; edit means capable of editing the management information; and control means for making a control to transfer data stored in the second storage medium to the first storage medium by way of the communication means on the basis of the management information edited by the edit means.

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Номер записи: 7
15-03-2012 дата публикации

Semiconductor memory device

Номер: US20120063206A1
Автор: Kazuma Furutani, Yutaka Shionoiri
Принадлежит: Semiconductor Energy Laboratory Co Ltd

An object is to provide a semiconductor memory device capable of copying memory data without using an external circuit. The semiconductor memory device includes a bit line to which first terminals of a plurality of memory cells are connected in common; a pre-charge circuit which is connected to the bit line and pre-charges the bit line with a specific potential in data reading; a data holding circuit comprising a capacitor which temporarily holds data read out from the memory cell or data which is written to the memory cell; and an inverted data output circuit which outputs inverted data of data held in the data holding circuit to the bit line. The inverted data output circuit includes a means for controlling output of inverted data of data held in the data holding circuit.

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Номер записи: 8
15-03-2012 дата публикации

Memory and method for sensing data in a memory using complementary sensing scheme

Номер: US20120063249A1
Автор: Bradford L. Hunter, Shayan Zhang
Принадлежит: FREESCALE SEMICONDUCTOR INC

In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

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Номер записи: 9
15-03-2012 дата публикации

System and method of page buffer operation for memory devices

Номер: US20120066442A1
Автор: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

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Номер записи: 10
26-04-2012 дата публикации

Data output buffer and memory device

Номер: US20120099383A1
Автор: Jin-Il Lee, Kwang-Il Park, Seung-Jun Bae, Si-Hong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

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Номер записи: 11
17-05-2012 дата публикации

Semiconductor memory device and method of controlling the same

Номер: US20120120739A1
Автор: Koichi Nishimura, Kotoku Sato, Shinya Fujioka, Tomohiro Kawakubo
Принадлежит: Fujitsu Semiconductor Ltd

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

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Номер записи: 12
31-05-2012 дата публикации

Memory Modules and Devices Supporting Configurable Core Organizations

Номер: US20120134084A1
Автор: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Frederick A. Ware, Richard E. Perego
Принадлежит: RAMBUS INC

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

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Номер записи: 13
14-06-2012 дата публикации

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Номер: US20120146132A1
Автор: Leonard Forbes
Принадлежит: Micron Technology Inc

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

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Номер записи: 14
12-07-2012 дата публикации

Column address strobe write latency (cwl) calibration in a memory system

Номер: US20120176850A1
Автор: Lydia M. Do, William M. Zevin
Принадлежит: International Business Machines Corp

Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.

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Номер записи: 15
19-07-2012 дата публикации

Memory module cutting off dm pad leakage current

Номер: US20120182777A1
Автор: Seok-Il Kim, Seung-jin Seo, You-Keun Han
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.

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Номер записи: 16
30-08-2012 дата публикации

Utilizing two algorithms to determine a delay value for training ddr3 memory

Номер: US20120218841A1
Автор: Brandon L. Hunt
Принадлежит: LSI Corp

A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

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Номер записи: 17
06-09-2012 дата публикации

Three dimensional memory system with intelligent select circuit

Номер: US20120224410A1
Автор: Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

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Номер записи: 18
13-09-2012 дата публикации

Semiconductor memory device and methods thereof

Номер: US20120230125A1
Автор: Nak-Won Heo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.

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Номер записи: 19
04-10-2012 дата публикации

Semiconductor memory and semiconductor memory control method

Номер: US20120250425A1
Автор: Katsumi Abe, Masahiro Yoshihara
Принадлежит: Individual

According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.

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Номер записи: 20
04-10-2012 дата публикации

Separate Pass Gate Controlled Sense Amplifier

Номер: US20120250441A1
Автор: Dipak K. Sikdar, Richard S. Roy
Принадлежит: Mosys Inc

A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

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Номер записи: 21
22-11-2012 дата публикации

Compensating for jitter during ddr3 memory delay line training

Номер: US20120296598A1
Автор: Carl E. Gygi, Craig R. Chafin, William J. Schmitz
Принадлежит: LSI Corp

A method for compensating for jitter during DDR3 delay line training may include using a computer or processor to perform the steps of executing a plurality of tests for each one of a plurality of delay values for an interconnect delay between a Double-Data-Rate Three (DDR3) memory controller and a DDR3 Synchronous Dynamic Random Access Memory (SDRAM); accumulating a plurality of test results for each plurality of tests for each one of the plurality of delay values; determining a plurality of final test results, where each final test result is associated with an accumulated plurality of test results; and determining a working window edge for the interconnect delay between the DDR3 memory controller and the DDR3 SDRAM utilizing the plurality of final test results.

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Номер записи: 22
29-11-2012 дата публикации

Advanced memory device having improved performance, reduced power and increased reliability

Номер: US20120300563A1
Автор: Charles A. Kilmer, Daniel M. Dreps, George L. Chiu, Hillery C. Hunter, Kevin C. Gower, Kyu-Hyoun Kim, Paul W. Coteus, Warren E. Maule
Принадлежит: International Business Machines Corp

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

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Номер записи: 23
29-11-2012 дата публикации

Sense Amplifier Apparatus and Methods

Номер: US20120300567A1
Автор: Jimmy Fort, Nicolas Zammit, Thierry Soude
Принадлежит: Atmel Corp

Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed.

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Номер записи: 24
13-12-2012 дата публикации

Semiconductor memory device and method of driving semiconductor memory device

Номер: US20120314513A1
Автор: Yoshiyuki Kurokawa
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.

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Номер записи: 25
20-12-2012 дата публикации

Low voltage sensing scheme having reduced active power down standby current

Номер: US20120320687A1
Автор: Tae Kim
Принадлежит: Individual

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

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Номер записи: 26
20-12-2012 дата публикации

Semiconductor memory with sense amplifier

Номер: US20120320696A1
Автор: Hiroyuki Takahashi
Принадлежит: Renesas Electronics Corp

In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

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Номер записи: 27
27-12-2012 дата публикации

Random Access Memory Controller Having Common Column Multiplexer and Sense Amplifier Hardware

Номер: US20120327703A1
Автор: Meny Yanni
Принадлежит: Marvell Israel MISL Ltd

Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry is shared between the column multiplexer and the sense amplifier so that the memory controller includes a single instance of the common circuitry for the column multiplexer and sense amplifier pair. The common circuitry includes a common pre-charge circuit, a common equalizer, or a common keeper circuit.

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Номер записи: 28
03-01-2013 дата публикации

Digit line comparison circuits

Номер: US20130003467A1
Автор: Dean A. Klein
Принадлежит: Micron Technology Inc

A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

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Номер записи: 29
10-01-2013 дата публикации

Semiconductor device, adjustment method thereof and data processing system

Номер: US20130010515A1
Автор: Chikara Kondo, Naohisa Nishioka
Принадлежит: Elpida Memory Inc

A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips.

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Номер записи: 30
10-01-2013 дата публикации

Memory circuit and word line control circuit

Номер: US20130010531A1
Автор: Shih-Huang Huang
Принадлежит: MediaTek Inc

The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

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Номер записи: 31
21-02-2013 дата публикации

Processor with memory delayed bit line precharging

Номер: US20130044555A1
Автор: Hong-Yi Chen, Jason Sheu, Jason T. Su, Jensen Tjeng, Sehat Sutardja
Принадлежит: MARVELL WORLD TRADE LTD

A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.

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Номер записи: 32
28-02-2013 дата публикации

Semiconductor device and semiconductor chip

Номер: US20130049223A1
Автор: Keisuke NOMOTO, Toru Ishikawa
Принадлежит: Elpida Memory Inc

The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

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Номер записи: 33
28-02-2013 дата публикации

High speed multiple memory interface i/o cell

Номер: US20130049799A1
Автор: Cheng-Gang Kong, Dharmesh Bhakta, Hong-Him Lim, Todd Randazzo
Принадлежит: LSI Corp

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

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Номер записи: 34
18-04-2013 дата публикации

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Номер: US20130095645A1
Автор: Leonard Forbes
Принадлежит: Micron Technology Inc

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

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Номер записи: 35
02-05-2013 дата публикации

Semiconductor system including semiconductor device

Номер: US20130107641A1
Автор: Jeong Hun Lee
Принадлежит: Hynix Semiconductor Inc

A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the code signals, to compare the reference voltages with the data to generate new data, to store the new data as internal data, and to process the stored internal data to output as the output data.

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Номер записи: 36
02-05-2013 дата публикации

Semiconductor memory device and operating method thereof

Номер: US20130111101A1
Автор: Seok-Cheol Yoon
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address, an address providing unit configured to provide a memory address to the path control unit in response to an active signal, and a plurality of memory banks each configured to receive the memory address provided through the corresponding address transmission path of the path control unit, wherein the bank address corresponds to a memory bank of the plurality of memory banks.

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Номер записи: 37
18-07-2013 дата публикации

Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device

Номер: US20130182513A1
Автор: Yong-Cheol Bae, Yoon-Joo EOM, Young-Chul Cho, Young-Jin Jeon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

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Номер записи: 38
25-07-2013 дата публикации

Memory having isolation units for isolating storage arrays from a shared i/o during retention mode operation

Номер: US20130188435A1
Автор: Alexander E. Runas, Daniel C. Chow, Edward M. McCombs, Kenneth W. Jones
Принадлежит: Apple Inc

A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

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Номер записи: 39
29-08-2013 дата публикации

Refresh request queuing circuitry

Номер: US20130227212A1
Автор: Robert J. Proebsting
Принадлежит: Intellectual Ventures I LLC

An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.

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Номер записи: 40
12-09-2013 дата публикации

Data write training method

Номер: US20130235683A1
Автор: Kwang-Il Park, Seung-Jun Bae, Tae-Young Oh, Young-Soo Sohn
Принадлежит: Individual

Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.

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Номер записи: 41
12-09-2013 дата публикации

Bipolar primary sense amplifier

Номер: US20130235686A1
Автор: Perry H. Pelley
Принадлежит: Individual

A sense amplifier for a memory includes two bipolar transistors and isolation switches for selectively coupling and decoupling the base of the bipolar transistors to bit lines during portions of a read cycle. The sense amplifier has a feedback circuit that couples the collector of one of the bi polar transistors to the base of the other bipolar transistor and vice versa.

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Номер записи: 42
19-09-2013 дата публикации

Signal tracking in write operations of memory cells

Номер: US20130242678A1
Автор: Bing Wang, Kuoyuan (Peter) Hsu, Young Suk Kim
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal.

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Номер записи: 43
10-10-2013 дата публикации

Semiconductor memory device with sense amplifier and bitline isolation

Номер: US20130265839A1
Автор: Byoung Jin Choi
Принадлежит: Mosaid Technologies Inc

A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.

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Номер записи: 44
31-10-2013 дата публикации

Compression and decompression of data at high speed in solid state storage

Номер: US20130290615A1
Автор: Monish Shah
Принадлежит: Indra Networks Inc

Compression and decompression of data at high speed in solid state storage is described, including accessing a compressed data comprising a plurality of blocks of the compressed data, decompressing each of the plurality of blocks in a first stage of decompression to produce a plurality of partially decompressed blocks, and reconstructing an original data from the partially decompressed blocks in a second stage of decompression.

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Номер записи: 45
31-10-2013 дата публикации

Method and System For Error Correction in Flash Memory

Номер: US20130290813A1
Автор: Aditya Ramamoorthy, Pantas Sutardja, Zining Wu
Принадлежит: MARVELL WORLD TRADE LTD

A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

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Номер записи: 46
05-12-2013 дата публикации

Sense amplifier circuitry for resistive type memory

Номер: US20130322154A1
Автор: Adrian E. Ong, Chan-kyung Kim, Sooho Cha, YongSik Youn
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

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Номер записи: 47
05-12-2013 дата публикации

Semiconductor memory device, and method of controlling the same

Номер: US20130326247A1
Автор: Koichi Nishimura, Kotoku Sato, Shinya Fujioka, Tomohiro Kawakubo
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

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Номер записи: 48
26-12-2013 дата публикации

Bitline for Memory

Номер: US20130343140A1
Автор: Raed Sabbah
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.

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Номер записи: 49
09-01-2014 дата публикации

Apparatuses and methods for adjusting a path delay of a command path

Номер: US20140010025A1
Автор: Venkat Bringivijayaraghavan
Принадлежит: Micron Technology Inc

Apparatuses and method for adjusting a path delay of a command path are disclosed. In an example apparatus, a command path configured to provide a command from an input to an output includes an adjustable delay. The adjustable delay is configured to add delay to the command path delay, wherein the delay of the adjustable delay is based at least in part on a phase relationship between a feedback signal responsive to the command propagating through the command path and a clock signal. An example method includes configuring a command path to add delay to a command path delay to provide an internal write command signal to perform a write operation on write data corresponding to the internal write command, and propagating the write data corresponding to the internal write command through a data path without further delaying the write data to match the command path delay.

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Номер записи: 50
09-01-2014 дата публикации

Dynamic memory performance throttling

Номер: US20140013070A1
Автор: Brian Toronyi, Kenneth Shoemaker
Принадлежит: Intel Corp

Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.

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Номер записи: 51
30-01-2014 дата публикации

Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration

Номер: US20140032830A1
Автор: Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Richard S. Perego, Stefanos Sidiropoulos
Принадлежит: RAMBUS INC

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

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Номер записи: 52
06-02-2014 дата публикации

Sense amplifier

Номер: US20140036579A1
Автор: Hai Tao Cao, Huan Shi, Qing QL LI, Xiao Li Hu
Принадлежит: International Business Machines Corp

Embodiments of the invention provide a sense amplifier, a SRAM chip comprising the sense amplifier and a method of performing read operation on the SRAM chip. The sense amplifier according to embodiments of the invention comprises an additional driving assist portion, which further takes a global data bus as input, the driving assist portion is configured to enable the sense amplifier to provide assisted driving for other sense amplifiers. With the solution according to embodiments of the invention, driving capability of a sense amplifier on global data bus can be enhanced.

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Номер записи: 53
13-02-2014 дата публикации

Sense Amplifier Circuit for Nonvolatile Memory

Номер: US20140043928A1
Автор: Yong Seop Lee
Принадлежит: Dongbu HitekCo Ltd

A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal.

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Номер записи: 54
20-02-2014 дата публикации

Cas latency setting circuit and semiconductor memory apparatus including the same

Номер: US20140050034A1
Автор: Seong Jun Lee
Принадлежит: SK hynix Inc

A semiconductor memory apparatus includes a CAS latency setting circuit configured to change an initially-set CAS latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.

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Номер записи: 55
20-02-2014 дата публикации

Memory device with a logical-to-physical bank mapping cache

Номер: US20140052912A1
Автор: Chien-Hsien Wu, Mohammad Issa, Weihuang Wang
Принадлежит: Broadcom Corp

A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

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Номер записи: 56
20-02-2014 дата публикации

Multi-ported memory with multiple access support

Номер: US20140052913A1
Автор: Chien-Hsien Wu, Weihuang Wang
Принадлежит: Broadcom Corp

A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

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Номер записи: 57
06-03-2014 дата публикации

Integrated circuit

Номер: US20140064013A1
Автор: Jae-Bum Ko, Sang-Jin Byeon
Принадлежит: SK hynix Inc

An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

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Номер записи: 58
02-01-2020 дата публикации

One-die trermination control for memory systems

Номер: US20200004436A1
Автор: Gang Yan, Leechung Yiu, Lizhi Jin, Robert Xi Jin, Yibo Jiang
Принадлежит: Montage Technology Shanghai Co Ltd

A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the CA signal is being received from the memory controller.

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Номер записи: 59
02-01-2020 дата публикации

MEMORY DEVICE WITH DYNAMIC PROGRAM-VERIFY VOLTAGE CALIBRATION

Номер: US20200004440A1
Автор: Koudele Larry J., Liikanen Bruce A.
Принадлежит:

A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for the memory cells, determine a feedback measure based on implementing a processing level for processing data, and dynamically adjust the program-verify target according to the feedback measure. 1. A memory device , comprising:a memory array including a plurality of memory cells; and determine a target profile including distribution targets, wherein each of the distribution targets represents a program-verify target corresponding to a desired pattern of processing levels for a logic value for the memory cells,', 'determine a feedback measure based on implementing a processing level for processing data, and', 'dynamically adjust the program-verify target according to the feedback measure., 'a controller coupled to the memory array, the controller configured to2. The memory device of wherein the controller is further configured to determine the feedback measure based on an error count associated with a read level voltage.3. The memory device of wherein the controller is further configured to dynamically adjust the program-verify target based on adjusting separations between adjacent program-verify targets.4. The memory device of wherein the controller is further configured to dynamically adjust the program-verify target balancing an error measure across multiple page types for the memory cells.5. The memory device of wherein the controller is further configured to dynamically adjust the program-verify target based on a net-zero change for the target profile and across the program-verify target.6. The memory device of wherein:the program-verify target controls resulting distribution of actual processing levels associated with the logic value for the ...

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Номер записи: 60
07-01-2021 дата публикации

DATA REPLICATION

Номер: US20210004161A1
Автор: Willcock Jeremiah J.
Принадлежит:

The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising respective sense amplifiers and compute components and a controller. The controller may be configured to cause replication of a data value stored in a first compute component such that the data value is propagated to a second compute component. 120-. (canceled)21. An apparatus , comprising:a first storage location and a second storage location; and determine that the first storage location has a bit corresponding to a mask associated therewith; and', 'write the data stored in the second storage location to the first storage location based, at least in part on the determination that the first storage location has the bit corresponding to the mask associated therewith., 'a controller coupled to the first storage location and the second storage location, wherein the controller is configured to22. The apparatus of claim 21 , wherein the controller is configured to overwrite data previously stored by the first storage location as part of writing the data stored in the second storage location to the first storage location.23. The apparatus of claim 21 , wherein the first storage location and the second storage location comprise a portion of a first compute component and a portion of a second compute component claim 21 , respectively.24. The apparatus of claim 21 , further comprising a control signal line that is coupled to the first storage location and the second storage location claim 21 , wherein the control signal line is configured to assert signaling to cause the data stored in the second storage location to be written to the first storage location.25. The apparatus of claim 21 , further comprising a multiplexer claim 21 , wherein an input of the multiplexer is coupled to an output of the first storage location and an output of the multiplexer is coupled to an input of the second storage location.26. The apparatus ...

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Номер записи: 61
07-01-2016 дата публикации

Independently addressable memory array address spaces

Номер: US20160005447A1
Автор: Troy A. Manning
Принадлежит: Micron Technology Inc

Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

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Номер записи: 62
03-01-2019 дата публикации

Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features

Номер: US20190004945A1
Автор: Kent D. GLOSSOP, Kermin FLEMING, Samantika S. Sury, Simon C. Steely, Jr.
Принадлежит: Intel Corp

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In an embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an atomic operation when an incoming operand set arrives at the plurality of processing elements.

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Номер записи: 63
07-01-2021 дата публикации

SRAM WITH LOCAL BIT LINE, INPUT/OUTPUT CIRCUIT, AND GLOBAL BIT LINE

Номер: US20210005232A1
Автор: KATOCH Atul, Taghvaei Ali
Принадлежит:

A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line. 1. An SRAM memory device , comprising:a memory array including an SRAM memory cell and a local bit line;a local IO circuit having a sense amplifier coupled to the local bit line and configured to generate a local IO signal based on a data signal received on the local bit line, and output a global bit line signal based on the local IO signal to a global bit line, the local IO including a latch circuit having an input terminal connected to the global bit line, wherein the latch circuit is configured to latch the global bit line signal in response to the local IO signal;a global IO circuit coupled to the global bit line and configured to receive the latched global bit line signal and output a global IO signal.2. The SRAM memory device of claim 1 , wherein the sense amplifier is configured to output the local IO signal to a latch enable terminal of the latch circuit in response to a sense amplifier enable signal.3. The SRAM memory device of claim 1 , wherein the sense amplifier is configured to output first and second complementary local IO signals claim 1 , the first and second complementary local IO signals including the local IO signal.4. The SRAM memory device of claim 3 , wherein the latch circuit includes first and second enable terminals claim 3 , which include the latch enable terminal claim 3 , coupled to receive the first and second complementary local IO signals claim 3 , respectively.5. The SRAM memory device of claim 1 , wherein the local IO circuit includes a first transistor configured to pull the global bit line signal to a first predetermined voltage ...

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Номер записи: 64
07-01-2021 дата публикации

Periodic calibrations during memory device self refresh

Номер: US20210005245A1
Автор: Bill Nale, Christopher E. Cox
Принадлежит: Intel Corp

A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

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Номер записи: 65
04-01-2018 дата публикации

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

Номер: US20180005669A1
Автор: Hush Glen E.
Принадлежит:

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation. 120.-. (canceled)21. An apparatus , comprising:an array of memory cells; and a plurality of sense amplifiers coupled to respective pairs of complementary sense lines; and', 'a plurality of compute components coupled to the sense amplifiers via respective pairs of pass gates coupled to the respective pairs of complementary sense lines; and, 'sensing circuitry coupled to the array, and comprisingwherein the plurality of compute components comprise respective stages of a shift register into which data values on the respective pairs of complementary sense lines are loaded by enabling the respective pairs of pass gates.22. The apparatus of claim 21 , further comprising logical operation selection logic configured to control the respective pairs of pass gates based on a selected logical operation.23. The apparatus of claim 22 , wherein the logical operation selection logic is configured to control the respective pairs of pass gates based on:the selected logical operation; and the compute components; and', 'the sense amplifiers., 'respective data values stored in at least one of24. The apparatus of claim 21 , wherein the shift register is configured to shift data in a first direction and in a second direction.25. The apparatus of claim 21 , further comprising a controller configured to provide control signals to the array and sensing circuitry to cause a logical operation to be performed between data values stored in respective ...

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Номер записи: 66
04-01-2018 дата публикации

Method of programming semiconductor memory device

Номер: US20180005696A1
Автор: Eun Mee KWON, Ji Seon Kim, Sang Tae Ahn
Принадлежит: SK hynix Inc

In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.

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Номер записи: 67
02-01-2020 дата публикации

Sram input/output

Номер: US20200005837A1
Автор: Ali Taghvaei, Atul Katoch
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.

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Номер записи: 68
02-01-2020 дата публикации

DATA STROBE CALIBRATION

Номер: US20200005840A1
Автор: "DAlessandro Ferdinando", Castaldo Andrea, Castellano Cristiano, Di Martino Erminio, Giaccio Claudio, Mastrangelo Raffaele, Pascale Ferdinando
Принадлежит:

Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit. 1. A system comprising:a host device configured to receive read data from an embedded MultiMediaCard (eMMC) device over data lines of a communication interface and a data strobe signal from the eMMC device over a data strobe line of the communication interface,wherein the host device is configured to determine a timing relationship between the data strobe signal and an internal clock signal in a calibration mode to align the read data for sampling, andwherein the host device is configured to receive read data from the eMMC device over the data strobe line in a data mode separate from calibration mode.2. (canceled)3. The system of claim 1 , wherein the host device includes:data pins configured to receive read data from the eMMC device over the data lines of the communication interface; anda data strobe pin configured to receive the data strobe signal from the eMMC device over a data strobe line of the communication interface,wherein the host device is configured to receive read data from the eMMC device over at the data pins in both the calibration mode and the data mode.4. The system of claim 3 , wherein the host device is configured to provide a command to the eMMC device to provide read data over the data strobe line of the communication interface in the data mode.5. The system of claim 3 , wherein the data pins consist of a number (N) of data pins claim 3 , and wherein the host is configured to receive read data from the eMMC device using the N data pins and the data strobe pin claim 3 , collectively N+1 pins claim 3 , in the data mode.6. The system of ...

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Номер записи: 69
02-01-2020 дата публикации

MEMORY SYSTEM AND OPERATING METHOD THEREOF

Номер: US20200005888A1
Автор: KIM Hyungsup, WON Hyung-Sik
Принадлежит:

A memory system includes a memory device and a controller. The memory device includes a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region; a register suitable for generating a first signal indicating existence of the reserved memory cell region; and a fuse unit suitable for activating the reserved memory cell region based on the first signal. The controller assigns an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal. A replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region. 1. A memory system comprising:a plurality of memory devices including first and second memory devices, the first memory device having a memory cell array and a device controller, the memory cell array including a normal memory cell area and a redundancy memory cell area, the device controller being configured to generate a first signal associated with the redundancy memory cell area; anda memory controller provided external to the first memory device and configured to enable accessing of a redundancy memory cell of the redundancy memory cell area of the first memory device based on the first signal.2. The memory system of claim 1 , wherein the memory controller is configured to assign a first address for accessing the redundancy memory cell and control the first memory device to activate the redundancy memory cell based on the first address.3. The memory system of claim 2 , wherein the first memory device further comprises a fuse unit configured to activate the redundancy memory cell based on the first address.4. The memory system of claim 3 , wherein the first signal is provided to ...

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Номер записи: 70
03-01-2019 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20190005998A1
Автор: MATSUOKA Fumiyoshi
Принадлежит: Toshiba Memory Corporation

A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period. 1a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command;a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command; anda delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.. A semiconductor storage device comprising: This application is a Continuation application of U.S. application Ser. No. 15/264,545, filed Sep. 13, 2016, which claims the benefit of U.S. Provisional Application No. 62/309,837, filed Mar. 17, 2016. The entire contents of both the above-identified applications are incorporated herein by reference.Embodiments described herein relate generally to a semiconductor storage device.A magnetic random access memory (MRAM) is a memory device employing a magnetic element having a magnetoresistive effect as a memory cell for storing information, and is receiving attention as a next-generation memory device characterized by its high-speed operation, large storage capacity, and non-volatility. Research and development have been advanced to use the MRAM as a replacement for a volatile memory, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). In order to lower the development cost and enable smooth replacement, it is desirable ...

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Номер записи: 71
20-01-2022 дата публикации

Write broadcast operations associated with a memory device

Номер: US20220020424A1
Автор: Dmitri A. Yudanov, Shanky Kumar Jain
Принадлежит: Micron Technology Inc

Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable write broadcast operations. A write broadcast may occur from one or more signal development components or from one or more multiplexers to multiple locations of the memory array.

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Номер записи: 72
08-01-2015 дата публикации

Apparatuses and methods for comparing a current representative of a number of failing memory cells

Номер: US20150009766A1
Автор: Jae-Kwan Park
Принадлежит: Micron Technology Inc

Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current butler configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

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Номер записи: 73
12-01-2017 дата публикации

Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus

Номер: US20170010999A1
Автор: Benjamin A. Fox, George R. Zettles, IV, Layne A. Berge, Wesley D. Martin
Принадлежит: International Business Machines Corp

The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

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Номер записи: 74
27-01-2022 дата публикации

TSV Check Circuit With Replica Path

Номер: US20220028749A1
Автор: Harutaka Makabe
Принадлежит: Micron Technology Inc

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

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Номер записи: 75
11-01-2018 дата публикации

Memory controller that uses a specific timing reference signal in connection with a data brust following a specified idle period

Номер: US20180011805A1
Автор: Giovannini Thomas J., Shaeffer Ian
Принадлежит:

Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device. 1. A method of operation in a memory controller , the method comprising:transmitting a read command which specifies that a memory device output data accessed from a memory core via a data bus, the data to be output by the memory device as a burst of data words;provided that the burst of data words follows a period of specified duration during which the memory device was not exchanging data with the memory controller, transmitting information to the memory device which specifies whether the memory device is to commence outputting of a specified timing reference signal prior to commencing outputting of the burst of data words; andreceiving the timing reference signal if the information specified that the memory device output the timing reference signal.2. The method of claim 1 , wherein transmitting the information to the memory device comprises programming a register of the memory device to cause the outputting of the specified timing reference signal prior to commencing outputting of the burst of data words.3. The method of claim 1 , wherein the timing reference signal comprises a toggling pattern having at least four bits.4. The method of claim 3 , wherein the method further comprises receiving the toggling pattern at the memory ...

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Номер записи: 76
10-01-2019 дата публикации

INJECT DELAY TO SIMULATE LATENCY

Номер: US20190012095A1
Автор: Cherkasova Ludmila, MagaIhaes Guilherme de Campos, Volos Haris
Принадлежит:

Techniques for injecting a delay to simulate latency are provided. In one aspect, it may be determined that a current epoch should end. A delay may be injected. The delay may simulate the latency of non-volatile memory access during the current epoch. The current epoch may then end. A new epoch may then begin. 1. A non-transitory processor readable medium containing instructions thereon which when executed by a processor cause the processor to:determine that a current epoch should end;inject a delay, the delay simulating latency of non-volatile memory access during the current epoch;end the current epoch; andbegin a new epoch.2. The medium of claim 1 , wherein determining that the current epoch should end further comprises instructions to:periodically determine how long the current epoch has lasted; anddetermine the current epoch should end when the current epoch has exceeded a maximum epoch length threshold.3. The medium of claim 1 , wherein determining that the current epoch should end further comprises instructions to;determine that a synchronization primitive has been invoked; andinjecting the delay prior to completion of the synchronization primitive.4. The medium of claim 3 , wherein determining that the current epoch should end further comprises instructions to:determine that a synchronization primitive has been invoked;determine if the current epoch has exceeded a minimum epoch length threshold; andinjecting the delay prior to completion of the synchronization primitive when the minimum epoch length threshold has been exceeded.5. The medium of claim 1 , wherein injecting a delay further comprises instructions to;determine a number of processor stall cycles attributable to memory access; andcompute the delay based on the number of processor stall cycles and the latency of the simulated non-volatile memory.6. The medium of wherein determining the number of processor stall cycles comprises instructions to:retrieve at least one processor performance counter ...

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Номер записи: 77
10-01-2019 дата публикации

APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES

Номер: US20190012173A1
Автор: Kindworth Andre, Lemarie Sebastien, Mirichigni Graziano, Porzio Luca, Tan Chee Weng, Villa Corrado
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received. 1. An apparatus comprising: providing information indicative of a duration of a variable latency period; and', 'waiting a programmable bus turnaround time after the duration of the variable latency period, wherein the programmable bus turnaround time is programmed in the memory., 'a memory configured to receive a memory instruction from a memory controller and perform a memory operation responsive thereto, wherein performing the memory operation comprises the memory2. The apparatus of claim 1 , wherein the memory is configured to provide information indicative of the duration of the variable latency period on one or more input/output signal lines.3. The apparatus of claim 1 , wherein the memory is configured to provide an acknowledgment on an input/output signal line indicative of an end of the variable latency period represented by a change in logic level from a first logic level to a second logic level.4. The apparatus of claim 1 , wherein the memory is configured to provide information indicative of the duration of the variable latency period including a wait state.5. The apparatus of claim 4 , wherein the memory is ...

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Номер записи: 78
09-01-2020 дата публикации

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

Номер: US20200012332A1
Автор: Fuller Andrew M., Palmer Robert E., Poulton John W., Ware Frederick A.
Принадлежит:

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices. 120-. (canceled)21. A memory controller component comprising:a clock transmitter to transmit a first clock signal to a dynamic random access memory device (DRAM), the DRAM having (i) command/address receive circuitry to receive read commands and write commands, (ii) read-data transmit circuitry to transmit, in response to the read commands, read data using the first clock signal, and (iii) write-data receive circuitry to sample, in response to the write commands, write data using the first clock signal;a command/address transmitter to transmit the read commands and the write commands to the DRAM in response to a second clock signal;a write-data transmitter to transmit the write data to the DRAM in response to a third clock signal;a read-data receiver to sample the read data transmitted by the DRAM in response to a fourth clock signal; and phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal and', 'circuitry to generate the second clock signal at a lower frequency than the third and fourth clock signals; and', 'clock-pause circuitry to halt transmission of the first clock signal to the DRAM during a first interval to conserve power and to re- ...

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Номер записи: 79
15-01-2015 дата публикации

Switchable readout device

Номер: US20150014534A1
Автор: Ming-Sheng Yang, Tai-Ping Sun, Tse-Hsin CHEN, Yi-Chuan Lu
Принадлежит: National Chi Nan Univ

A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

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Номер записи: 80
11-01-2018 дата публикации

MEMORY DEVICE HAVING COMMAND WINDOW GENERATOR

Номер: US20180012638A1
Автор: CHOI Hun-Dae, KANG SUKYONG
Принадлежит:

A memory device including a command window generator is provided. The command window generator is configured to generate a delay signal by converting a delay time between a clock signal input to a write path circuit and a clock signal output to a write path replica circuit into a number of cycles of an internal clock signal, by using the write path circuit and the write path replica circuit, and generate a command window to correspond to a data window using the delay signal. The delay window may correspond to a burst length of write data. 1. A command window generator configured to generate a command window for processing data associated with a command after a certain latency from receipt of the command , the command window generator comprising:a clock freezer circuit configured to receive a first clock signal divided from an input clock signal and generate a second clock signal from the first clock signal, where the second clock signal has a freezing section corresponding to a logic low section of a clock freezing signal;a first circuit configured to receive the second clock signal as an input, and output the second clock signal after a first delay time;a second circuit having the same structure as the first circuit and configured to receive an output of the first circuit as an input, and output a third clock signal after the first delay time; anda delay measure circuit configured to receive the second clock signal and the third clock signal as inputs, generate a delay signal by converting a delay time between the second clock signal and the third clock signal into a number of cycles of the input clock signal, and generate the command window to correspond to a data window of the data using the delay signal.2. The command window generator of claim 1 , wherein the delay measure circuit generates a latency control signal generated at a point in which the delay signal is subtracted from the latency claim 1 , andthe first circuit receives the latency control signal as ...

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Номер записи: 81
11-01-2018 дата публикации

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

Номер: US20180012643A1
Автор: Hampel Craig E., Perego Richard E., Sidiropoulos Stefanos, Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. 1. (canceled)2. A controller to control operations of a memory component , the controller comprising: a first command that specifies a first data pattern to be stored in a first register of the memory component;', 'a second command that specifies a second data pattern to be stored in a second register of the memory component; and,', 'a third command to select one of the first data pattern or the second data pattern to be output by the memory component;, 'a first circuit to transmit commands to the memory component, the commands includinga second circuit to receive, from the memory component as a received data pattern, the one of the first data pattern or the second data pattern output by the memory component, as selected by the third command; and,calibration circuitry to based on the received data pattern, adjust a timing of a timing reference signal for sampling data at the second circuit.3. The controller of claim 2 , wherein the commands transmitted by the first circuit include a fourth command that specifies data to be accessed from a memory core of the memory component claim 2 , ...

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Номер записи: 82
10-01-2019 дата публикации

CURRENT-SENSING CIRCUIT FOR MEMORY AND SENSING METHOD THEREOF

Номер: US20190013053A1
Автор: LIN Hung-Hsueh
Принадлежит: WINBOND ELECTRONICS CORP.

A current-sensing circuit for a memory and a sensing method thereof are provided. The current-sensing circuit includes a pre-charge circuit, a sensing current-to-voltage generator, an auxiliary current-to-voltage generator, a reference current-to-voltage generator, and a detection circuit. The pre-charge circuit provides a pre-charge signal to a selected bit line during a pre-charge time period. The sensing current-to-voltage generator generates a sensing voltage to a memory cell current of the selected bit line via a first load. The auxiliary current-to-voltage generator provides a detection voltage to a portion of the memory cell current of the selected bit line via a second load. The reference current-to-voltage generator provides a reference voltage during a data-sensing time period. The detection circuit determines an end time point of the pre-charge time period by comparing a detected voltage generated by the second load with a reference voltage. 1. A sensing circuit for a memory , comprising:a pre-charge circuit coupled to a selected bit line of a read memory cell via a current-to-voltage generator and providing a pre-charge current to the selected bit line during a pre-charge time period;a sensing current-to-voltage generator and switch coupled to the selected bit line during a data-sensing time period to provide a sensing current to generate a sensing voltage via a first load;a reference current-to-voltage generator and switch coupled to the reference memory cell during the data-sensing time period to provide a reference current to generate a reference voltage via a reference load;an auxiliary current-to-voltage generator and switch coupled to the selected bit line during the pre-charge time period to provide an auxiliary sensing current to generate a detected voltage via a second load; anda detection circuit coupled to the second load and determining an end time point of the pre-charge time period by comparing the detected voltage on a coupling point of ...

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Номер записи: 83
10-01-2019 дата публикации

Apparatuses and methods for data movement

Номер: US20190013061A1
Автор: Glen E. Hush
Принадлежит: Micron Technology Inc

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device includes a latch selectably coupled to a column of the memory cells and configured to store a data value moved from the sensing circuitry. The memory device includes a controller configured to direct movement of the data value from the sensing circuitry to the latch.

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Номер записи: 84
10-01-2019 дата публикации

Apparatuses, devices and methods for sensing a snapback event in a circuit

Номер: US20190013067A1
Автор: Hernan A. Castro, Jeremy Miles Hirst, Stephen Tang
Принадлежит: Micron Technology Inc

Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

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Номер записи: 85
10-01-2019 дата публикации

Method and apparatus for multi-level setback read for three dimensional crosspoint memory

Номер: US20190013071A1
Автор: Balaji Srinivasan, Daniel Chu, John Gorman, Kiran Pangal, Lark-Hoon LEEM, Mase Taub, Sandeep Guliani
Принадлежит: Intel Corp

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

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Номер записи: 86
09-01-2020 дата публикации

Semiconductor memory device

Номер: US20200013435A1
Автор: Jumpei Sato
Принадлежит: Toshiba Memory Corp

A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

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Номер записи: 87
09-01-2020 дата публикации

NON-VOLATILE MEMORY DEVICE

Номер: US20200013787A1
Автор: HAHN WOOK-GHEE, LEE YOUN-YEOL
Принадлежит:

A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. 1. A non-volatile memory , comprising:an upper semiconductor layer vertically stacked on a lower semiconductor layer, wherein the upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region,the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.2. The non-volatile memory of claim 1 , further comprising:a control logic that generates a connection control signal, wherein the bypass circuit selectively connects the first bit line with the second bit line in response to the connection control signal.3. The non-volatile memory of claim 1 , wherein the bypass circuit includes a transistor including a first source/drain region and a second source/drain region claim 1 , and a first contact plug extending from the first source/drain region through the separation region to connect the first bit line; and', 'a second contact plug extending from the second source/drain region through the separation region to connect the second bit line., 'the non-volatile memory device further comprises4. (canceled)5. The non-volatile memory of claim 1 , wherein a portion of the lower semiconductor layer underlying the first memory group includes a first portion of a first row decoder claim 1 , a second portion ...

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Номер записи: 88
19-01-2017 дата публикации

Dynamic random access memory with pseudo differential sensing

Номер: US20170018301A1
Автор: Adam J. McPadden, Charles A. Kilmer, Kyu-Hyoun Kim
Принадлежит: International Business Machines Corp

Techniques are disclosed for dynamic random access memory (DRAM) cell. The DRAM cell comprises a first bit line and a first complementary bit line, a storage capacitor having a first node coupled with the first complementary bit line, and a transistor selectable by a word line to couple a second node of the storage capacitor to the first bit line, wherein a voltage potential across the first bit line and the first complementary bit line when the transistor is selected is indicative of a bit of data.

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Номер записи: 89
03-02-2022 дата публикации

Electronic device configured to perform an auto-precharge operation

Номер: US20220036930A1
Автор: Woongrae Kim
Принадлежит: SK hynix Inc

An electronic device may include: an input/output control signal generation circuit configured to generate an input control signal and a first output control signal during a write operation, and generate a second output control signal during a write operation with an auto-precharge operation; and a bank address output circuit configured to latch a bank address based on the input control signal, and output the latched bank address as a write bank address for the write operation or a precharge bank address for the auto-precharge operation, based on the first output control signal and the second output control signal.

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Номер записи: 90
03-02-2022 дата публикации

Monitoring and adjusting access operations at a memory device

Номер: US20220036960A1
Автор: Aaron P. Boehm, Mark D. INGRAM, Scott D. VAN DE GRAAFF, Scott E. Schaefer, Todd Jackson Plum
Принадлежит: Micron Technology Inc

Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

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Номер записи: 91
21-01-2021 дата публикации

APPARATUSES AND METHODS FOR SIMULTANEOUS IN DATA PATH COMPUTE OPERATIONS

Номер: US20210019048A1
Автор: Hush Glen E., Lea Perry V.
Принадлежит:

The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period. 2. The system of claim 1 , wherein the controller is further configured to:direct movement of the result of the first operation from the first logic stripe to the second logic stripe of the first portion of logic stripes in response to completion of the first operation.3. The system of claim 1 , wherein the controller is further configured to direct performance of a second operation on the result of the first operation using a second logic stripe of the first portion of logic stripes.4. The system of claim 3 , wherein the controller is further configured tointerrupt performance of the second operation on the second logic stripe of the first portion of logic stripes and direct the result of the first operation to a third logic stripe of the first portion of logic stripes.5. The system of claim 1 , wherein the controller is further configured to:direct movement of a second portion of data from the array to a first logic stripe of a second portion of logic stripes in the data path via the plurality of I/O lines during the first time period.6. The system of claim 5 , wherein the controller is further configured to:direct ...

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Номер записи: 92
22-01-2015 дата публикации

Memory device and read operation method thereof

Номер: US20150023120A1
Автор: Chia-Jung Chen, Chin-Hung Chang, Ken-Hui Chen, Kuen-Long Chang, Su-Chueh Lo
Принадлежит: Macronix International Co Ltd

A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

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Номер записи: 93
16-01-2020 дата публикации

Memory power management

Номер: US20200020361A1
Автор: Jaspal Singh Shah, Sanjeev Kumar Jain
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

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Номер записи: 94
16-01-2020 дата публикации

Semiconductor storage device

Номер: US20200020379A1
Автор: Fumiyoshi Matsuoka
Принадлежит: Toshiba Memory Corp

A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.

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Номер записи: 95
21-01-2021 дата публикации

BANK TO BANK DATA TRANSFER

Номер: US20210020207A1
Автор: Lea Perry V., Manning Troy A.
Принадлежит:

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks. 1. An apparatus , comprising:a plurality of shared input/output (SIO) lines coupled to logic comprising a plurality of latches;a plurality of memory banks coupled to respective SIO lines among the plurality of SIO lines;a bank-to-bank transfer bus coupled to each SIO line among the plurality of SIO lines; anda controller coupled to the bank-to-bank transfer bus and the plurality of SIO lines and configured to cause data to be transferred to at least one memory bank among the plurality of memory banks via the bank-to-bank transfer bus in a first direction or a second direction based, at least in part, on a transfer time associated with transferring the data to the at least one memory bank.2. The apparatus of claim 1 , further comprising a plurality of control components coupled to respective SIO lines among the plurality of SIO lines claim 1 , wherein the control components are configured to compare a write address value or a read address value claim 1 , or both claim 1 , for designating addresses among the plurality of memory banks prior to the data being transferred between the memory banks.3. The apparatus of claim 1 , wherein the controller is configured to:determine that a processing in memory program is running on a particular memory bank among the plurality of memory banks; andcause the bank-to-bank transfer bus to be bifurcated such that the particular memory bank receives data transferred from other memory banks among the plurality of memory banks directly or in an optimized manner, or both.4. The apparatus of claim 1 , wherein the controller is configured to cause data to be transferred from the plurality of ...

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Номер записи: 96
21-01-2021 дата публикации

Non-volatile memory devices and program methods thereof

Номер: US20210020254A1
Автор: Jinwoo Park, Sang-Wan Nam, Seongjin Kim, Wandong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

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Номер записи: 97
22-01-2015 дата публикации

MOBILE DEVICE AND A METHOD OF CONTROLLING THE MOBILE DEVICE

Номер: US20150026398A1
Автор: Kim Ho-Sung
Принадлежит:

A mobile device including: a storage device; a system-on-chip (SOC) including a central processing unit (CPU) and a memory interface configured to access the storage device in response to a request of the CPU; and a working memory including an input/output (I/O) scheduler and a device driver, the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue, the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue. 1. A mobile device , comprising:a storage device;a system-on-chip (SOC) including a central processing unit (CPU) and a memory interface configured to access the storage device in response to a request of the CPU; anda working memory including an input/output (I/O) scheduler and a device driver,the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue,the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue.2. The mobile device of claim 1 , wherein when the sync queue and the async queue are empty a low power mode of the mobile device is entered.3. The mobile device of claim 1 , wherein the CPU is a heterogeneous multi-core CPU.4. The mobile device of claim 1 , wherein the working memory includes a dynamic random access memory (DRAM).5. The mobile device of claim 1 , wherein the storage device includes a nonvolatile memory device.6. The mobile device of claim 1 , wherein the synch queue includes a plurality of read requests.7. The mobile device of claim 1 , wherein the async queue includes a plurality of write requests.8. The mobile device of claim 1 , wherein the ...

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Номер записи: 98
25-01-2018 дата публикации

Method and apparatus for serial data output in memory device

Номер: US20180025757A1
Автор: Johnny Chan, Tinwai Wong
Принадлежит: Winbond Electronics Corp

A memory device includes a memory array storing data, a sense amplifier configured to read a plurality of data bits from the memory array and output a sense data signal including the data bits read from the memory array, a data multiplexer configured to receive the sense data signal and generate a plurality of group signals, a plurality of local data registers coupled to the data multiplexer, at least one of the local data registers being configured to generate a serial data output signal according to an output mode, and a plurality of output circuits coupled to respective ones of the plurality of local data registers, at least one of the output circuits being configured to receive the serial data output signal output from the at least one of the local data registers and sequentially output the data bits included in the serial data output signal.

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Номер записи: 99
25-01-2018 дата публикации

Apparatuses and methods for reducing off state leakage currents

Номер: US20180026622A1
Автор: Pierguido Garofalo
Принадлежит: Micron Technology Inc

Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

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Номер записи: 100