Routing apparatus and network apparatus

A routing apparatus and a network apparatus that are capable of improving general system performance by compressing/decompressing data and transmitting the result of the compression/decompression, are provided. The routing apparatus may compress and/or decompress input data, and may transmit the compressed and/or decompressed input data.

Apparatus and method for simulating a reconfigurable processor

A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.

LATENCY MANAGEMENT SYSTEM AND METHOD FOR MULTIPROCESSOR SYSTEM

A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal. 1. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory , the shared memory and each of the processors being configured to generate a delayed signal , the apparatus comprising:a delayed signal detector configured to detect the generated delayed signal; andone or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.2. The latency management apparatus of claim 1 , wherein:the plurality of processors include one of the processors that generates the delayed signal and other ones of the processors that do not generate the delayed signal; andthe one or more latency managers are further configured to manage operation latencies of the other ones of the processors based on whether the one of the processors requests access to the shared memory.3. The latency management apparatus of claim 2 , wherein the one or more latency managers are further configured to delay neither operation of the shared memory nor operations of the other ones of the processors if there is no request by the one of the processors to access the shared memory.4. The latency management apparatus of claim 2 , wherein the one or more latency managers are further configured to temporarily stop operations of the other ones of the processors in order to delay the operations of the other ones of the processors if the one of the processors requests access to the shared memory.5. The latency management ...

Multi-port cache memory apparatus and method

Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache.

Apparatus and method for generating code overlay

Provided is an apparatus and method for generating code overlay capable of minimizing the number of memory copies. A static temporal relationship graph (STRG) is generated in which each of functions of a program corresponds to a node of the STRG and a conflict miss value corresponds to an edge of the STRG. The conflict miss value is the maximum number of possible conflict misses between functions. Overlay is generated by selecting at least one function from the STRG, calculating an allocation cost for each region of a memory to be given when the at least one selected function is allocated, and allocating the at least one selected function to a region that has the smallest allocation cost.

Semiconductor memory device and a method for arranging signal lines thereof

The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof. The semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, includes: first IO signal lines for transmitting data between the first memory cell array and the IO control circuit, wherein the first IO signal lines are connected to first data loading locations of the first memory cell array and extend in a straight line to the IO control circuit; and second IO signal lines for transmitting data between the second memory cell array and the IO control circuit, wherein the second IO signal lines are connected to first data loading locations of the second memory cell array and extend to the IO control circuit, wherein lengths of the first IO signal lines starting from the first data loading locations of the first memory cell array to the IO control circuit ...

Power mixing circuit and semiconductor memory device including the same

A power mixing circuit capable of maintaining a stable output voltage in a deep-power-down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.

Semiconductor memory device with a stacked-bank architecture and method for driving word lines of the same

A semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks is disclosed. The semiconductor memory device includes memory bank groups and a decoder unit. Each of the memory bank groups includes a plurality of memory banks arranged in a stacked-bank architecture. The decoder unit generates a decoded row address signal to individually select one of the memory banks in response to an external address signal under the control of an output enable signal. Accordingly, the semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks has lower power consumption and operates stably against noise.

Latency management system and method for multiprocessor system

A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.

MULTIPROCESSOR USING A SHARED VIRTUAL MEMORY AND METHOD OF GENERATING A TRANSLATION TABLE

A multiprocessor using a shared virtual memory (SVM) is provided. The multiprocessor includes a plurality of processing cores and a memory manager configured to transform a virtual address into a physical address to allow a processing core to access a memory region corresponding to the physical address. 1. A multiprocessor using a shared virtual memory (SVM) , the multiprocessor comprising:a plurality of processing cores configured to include a local store; anda memory manager configured to generate a table indicating whether one of a plurality of pages of the SVM allocated to the local store is being used by at least one of the processing cores.2. The multiprocessor of claim 1 , wherein the table includes a first-level descriptor defining a page allocated to the local store.3. The multiprocessor of claim 2 , wherein the table further includes a second-level page descriptor including a field indicating whether the page allocated to the local store is being used by the at least one of the processing cores.4. The multiprocessor of claim 3 , wherein the table further includes a third-level page descriptor indicating a base address of a physical address of the page allocated to the local store.5. The multiprocessor of claim 3 , wherein the second-level page descriptor further includes a field indicating a number of processing cores that have permission to write on the page allocated to the local store and a field indicating whether a twin of the page allocated to the local store has been generated.6. The multiprocessor of claim 4 , wherein the third-level page descriptor includes a field indicating a read right or read and write rights of the at least one of the processing cores on the page allocated to the local store.7. The multiprocessor of claim 1 , wherein the memory manager is further configured to convert a virtual address into a physical address based on the table.8. The multiprocessor of claim 7 , wherein the memory manager is further configured to convert the ...

Semiconductor memory device and power line arrangement method thereof

A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.

COMPUTING APPARATUS AND METHOD USING X-Y STACK MEMORY

A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.

Semiconductor memory device and power line arrangement method thereof

A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.

Simulation device and distribution simulation system

A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus.

Memory controller, method of controlling unaligned memory access, and computing apparatus incorporating memory controller

A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer.

Apparatus to access multi-bank memory

A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.

MEMORY CONTROLLER, METHOD OF CONTROLLING MEMORY ACCESS, AND COMPUTING APPARATUS INCORPORATING MEMORY CONTROLLER

A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer.

Semiconductor device and semiconductor package including the same

A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector.

Semiconductor memory device with a stacked-bank architecture and method for driving word lines of the same

A semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks is disclosed. The semiconductor memory device includes memory bank groups and a decoder unit. Each of the memory bank groups includes a plurality of memory banks arranged in a stacked-bank architecture. The decoder unit generates a decoded row address signal to individually select one of the memory banks in response to an external address signal under the control of an output enable signal. Accordingly, the semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks has lower power consumption and operates stably against noise.

Computing apparatus and method using X-Y stack memory

A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.

APPARATUS TO ACCESS MULTI-BANK MEMORY

A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.

Apparatus and method for generating test cases for processor verification, and verification device

An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description.

Semiconductor memory device and a method for arranging signal lines thereof

The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof. The semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, includes: first IO signal lines for transmitting data between the first memory cell array and the IO control circuit, wherein the first IO signal lines are connected to first data loading locations of the first memory cell array and extend in a straight line to the IO control circuit; and second IO signal lines for transmitting data between the second memory cell array and the IO control circuit, wherein the second IO signal lines are connected to first data loading locations of the second memory cell array and extend to the IO control circuit, wherein lengths of the first IO signal lines starting from the first data loading locations of the first memory cell array to the IO control circuit ...

MULTI-PORT CACHE MEMORY APPARATUS AND METHOD

Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache. 1. A multi-port cache memory apparatus comprising:multiple cache banks; andan allocation unit configured to divide an address space into a plurality of address regions of a predefined size, and to allocate a first address region to a first cache bank of the multiple cache banks and to allocate a second address region, following the first address region, to a second cache bank of the multiple cache banks.2. The multi-port cache memory apparatus of claim 1 , wherein the allocation unit is configured to allocate the divided address regions sequentially to the multiple cache banks.3. The multi-port cache memory apparatus of claim 2 , wherein the allocation unit is configured to allocate the divided first address region to the first cache bank claim 2 , and allocate the divided second address region claim 2 , following the first address region claim 2 , to the second cache bank that is positioned directly behind the first cache bank.4. The multi-port cache memory apparatus of claim 1 , wherein the allocation unit is configured to allocate the divided address regions non-sequentially to the multiple cache banks.5. The multi-port cache memory apparatus of claim 4 , wherein the allocation unit is configured to allocate the divided first address region to the first cache bank claim 4 , and to allocate the second address region claim 4 , following the first address region claim 4 , to a third cache bank that is not positioned directly behind the first cache bank from among the multiple cache banks.6. The multi-port cache memory apparatus of claim 1 , wherein the predefined size of each divided address region is at least one of a block size of the cache bank and a data ...

APPARATUS AND METHOD FOR MODIFYING INSTRUCTION OPERAND

Provided are an apparatus and method for modifying an instruction operand. The apparatus includes a first selector configured to receive first instruction operands and a second selector configured to receive second instruction operands. The apparatus also includes a modification unit configured to select a first instruction operand and a second instruction operand, and to modify the selected first instruction operand and the selected second instruction operand to reduce the operand instructions that are input to the first selector and the second selector. 1. An apparatus for modifying an instruction operand , the apparatus comprising:a first selector configured to receive first instruction operands;a second selector configured to receive second instruction operands; anda modification unit configured to select at least one instruction operand from the first instruction operands and the second instruction operands, and configured to modify at least one of an input path and a type of the at least one selected instruction operand.2. The apparatus of claim 1 , wherein the at least one selected instruction operand is a selected first instruction operand claim 1 , and the modification unit modifies the selected first instruction operand that is input to the first selector to be the same in type as another first instruction operand that is already input to the first selector to reduce the type of instructions operands that are input to the first selector.3. The apparatus of claim 1 , further comprising a detection unit configured to detect types of the first instruction operands and the second instruction operands claim 1 ,wherein the modification unit selects a first instruction operand and a second instruction operand and modifies the input paths of the selected first instruction operand and the selected second instruction operands based on the detected types, such that the selected first instruction operand is input to the second selector and such that the selected ...

POWER MIXING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal. 1. A power mixing circuit , comprising:an input buffer configured to operate using a first supply voltage having a first voltage level, and to generate a first voltage signal in response to an input signal;a power mixing control circuit configured to generate a power mixing control signal based on a power-up signal and a power-down mode signal, the power-up signal generated when an external supply voltage rises up, and the power-down mode signal generated when a semiconductor device operates in a first mode;a power mixing driver configured to operate using the external supply voltage and a second supply voltage having a second voltage level, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal in response to the first voltage signal and the power mixing control signal; andan output buffer configured to operate using the second supply voltage, and to generate an output signal in response to the second voltage signal.2. The power mixing circuit according to claim 1 , wherein the power mixing circuit is configured to output the output ...

Multiprocessor using a shared virtual memory and method of generating a translation table

A multiprocessor using a shared virtual memory (SVM) is provided. The multiprocessor includes a plurality of processing cores and a memory manager configured to transform a virtual address into a physical address to allow a processing core to access a memory region corresponding to the physical address.

APPARATUS AND METHOD FOR GENERATING CODE OVERLAY

Provided is an apparatus and method for generating code overlay capable of minimizing the number of memory copies. A static temporal relationship graph (STRG) is generated in which each of functions of a program corresponds to a node of the STRG and a conflict miss value corresponds to an edge of the STRG. The conflict miss value is the maximum number of possible conflict misses between functions. Overlay is generated by selecting at least one function from the STRG, calculating an allocation cost for each region of a memory to be given when the at least one selected function is allocated, and allocating the at least one selected function to a region that has the smallest allocation cost.

Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device

Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

Simulation apparatus and method for multicore system

A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules.

Delay circuit and semiconductor device including same

A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays an output signal from an immediately previous delay block and transmits a resulting delayed output signal to a next delay block when a delay operation is enabled based on a corresponding control signal. However, where the delay operation of a delay block is disabled based on the corresponding control signal, the delay block transmits the output signal of the immediately previous delay block to the driving portion.

Input receiver circuit having single-to-differential amplifier, and semiconductor device including the same

An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.

APPARATUS AND METHOD FOR GENERATING TEST CASES FOR PROCESSOR VERIFICATION, AND VERIFICATION DEVICE

An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description. 1. An apparatus for generating a test case , the apparatus comprising:a constraint generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; anda test case generator configured to generate a test case using the constrained description.2. The apparatus of claim 1 , further comprising an architecture generator configured to define the total verification space using an architecture specification claim 1 , and generate an architecture description for the total verification space.3. The apparatus of claim 2 , wherein the architecture specification comprises any one or any combination of any two or more of instruction information claim 2 , operand information claim 2 , instruction sequence information claim 2 , and interrupt information.4. The apparatus of claim 3 , wherein the architecture generator is further configured to define the total verification space in a multidimensional space by combining two or more types of the information contained in the architecture specification.5. The apparatus of claim 1 , wherein the constraint generator is further configured to define the plurality of constrained verification spaces in the total verification space by taking into account any one or any combination of any two or more of a size of the total verification space claim 1 , a test purpose claim 1 , and a test time.6. The apparatus of claim 1 , wherein the constraint generator is further configured to generate the constrained description for each of the ...

APPARATUS AND METHOD FOR SIMULATING A RECONFIGURABLE PROCESSOR

A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.

Delay circuit and semiconductor device including same

Disclosed are a delay circuit and a semiconductor device including the same. The delay circuit comprises a plurality of delay blocks, which are connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays an output signal from an immediately previous delay block and transmits a resulting delayed output signal to a next delay block when delay operation is enabled based on a control signal. However, where the delay operation of a delay block is disabled based on the control signal, the delay block transmits the output signal of the immediately previous delay block to the driving portion.

Verification supporting apparatus and verification supporting method of reconfigurable processor

A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation.

ROUTING APPARATUS AND NETWORK APPARATUS

A routing apparatus and a network apparatus that are capable of improving general system performance by compressing/decompressing data and transmitting the result of the compression/decompression, are provided. The routing apparatus may compress and/or decompress input data, and may transmit the compressed and/or decompressed input data. 1. A routing apparatus comprising:a compression/decompression unit configured to compress or decompress input data within a data processing time, and the data processing time is a period of time between the time when data is received and the time when the data is output; anda transmission unit configured to transmit the compressed input data or decompressed input data.2. The routing apparatus of claim 1 , further comprising:a determination unit configured to determine whether congestion has occurred and/or whether congestion has been resolved,wherein, if congestion occurs, the compression/decompression unit continues to compress the input data until the congestion is resolved.3. The routing apparatus of claim 1 , further comprising:a determination unit configured to determine whether the routing apparatus is a last routing apparatus on a path of the transmission of the input data and whether the input data has been fully decompressed,wherein, if the routing apparatus is the last routing apparatus on the path of the transmission of the input data and the input data has not yet been fully decompressed, the compression/decompression unit decompresses the input data until the input data is fully decompressed.4. The routing apparatus of claim 1 , further comprising a memory unit configured to temporarily store at least one of the input data claim 1 , the compressed input data claim 1 , and the decompressed input data.5. The routing apparatus of claim 1 , wherein the transmission unit comprises:a switching module; anda control module configured to control the switching module to transmit at least one of the compressed input data and the ...

Simulation apparatus and method for multicore system

A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules.

Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device

Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES

A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal. 1. A semiconductor memory device comprising:a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal, the clock input buffer configured to buffer a clock signal in order to output a buffered clock signal; andan internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal, wherein the generation of the internal clock signal is started in response to a second control signal.2. The semiconductor memory device of claim 1 , wherein the first control signal is a clock enable signal claim 1 , the second control signal is a chip selection signal claim 1 , and wherein the internal clock generator generates the internal clock signal by starting a division of the buffered clock signal in response to a first pulse of the chip selection signal being input to the internal clock generator.3. The semiconductor memory device of claim 2 , wherein a pulse width of the first pulse of the chip selection signal is greater than one clock cycle of the clock signal.4. The semiconductor memory device of claim 1 , wherein claim 1 , the internal clock generator is configured to start to generate the internal clock signal by dividing the buffered clock signal in response to the first pulse of the second control signal being input to the internal clock generator while the first control signal is activated.5. The semiconductor memory device of claim 1 , wherein the clock input buffer buffers the clock signal in response ...

OUTPUT DRIVING CIRCUIT CAPABLE OF DECREASING NOISE, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

An output driving circuit includes a first pull-up transistor, a first pull-down transistor and a second pull-down transistor. The first pull-up transistor is configured to generate a first output signal at the output node in response to a first control signal. The first pull-down transistor is configured to generate a second output signal at the output node in response to a second control signal. The second pull-down transistor is configured to connect the output node to the first ground voltage in response to a third control signal. The memory device including the output driving circuit may be insensitive to noise and may have little data transmission error.

VERIFICATION SUPPORTING APPARATUS AND VERIFICATION SUPPORTING METHOD OF RECONFIGURABLE PROCESSOR

A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation. 1. A verification supporting apparatus of a reconfigurable processor , the apparatus comprising:an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code; anda masking hint generator configured to generate a masking hint for the detected invalid operation.2. The verification supporting apparatus of claim 1 , wherein the reconfigurable processor comprises a Coarse-Grained Array (CGA)-based processor.3. The verification supporting apparatus of claim 1 , wherein the detected invalid operation comprises one of operations mapped to a prologue or epilogue of a loop according to modulo-scheduling of a compiler.4. The verification supporting apparatus of claim 3 , wherein the masking hint comprises information about a number of a cycle in the prologue or epilogue of the loop in which the detected invalid operation exists and an identification (ID) of a function unit (FU) to which the detected invalid operation is mapped.5. The verification supporting apparatus of claim 1 , wherein the detected invalid operation is not executed in a function simulator while being executed in a Register Transfer Level (RTL) simulator.6. The verification supporting apparatus of claim 5 , wherein the masking hint is used to generate masking information to prevent comparison of simulation results related to the detected invalid operation among simulation results of the function simulator and the RTL simulator.7. A verification supporting method of a reconfigurable processor claim 5 , the method comprising:detecting an invalid operation from a result of ...

INPUT RECEIVER CIRCUIT HAVING SINGLE-TO-DIFFERENTIAL AMPLIFIER, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal. 1. An input receiver circuit , comprising:a first stage amplifier unit configured to amplify a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage; anda second stage amplifier unit configured to amplify the differential output signal in a differential-to-single mode to generate a single output signal.2. The circuit according to claim 1 , wherein the first stage amplifier unit comprises:a common-source amplifier configured to receive an input voltage signal at a gate terminal, amplify the input voltage signal, and output the amplified voltage signal from a drain terminal; anda common-gate amplifier configured to receive the input voltage signal at a first terminal, amplify the input voltage signal, and output the amplified voltage signal from a second terminal.3. The circuit according to claim 2 , wherein the common-source amplifier includes a PMOS transistor configured to receive the input voltage signal at a gate terminal claim 2 , and output the amplified voltage signal from a drain terminal.4. The circuit according to claim 2 , wherein the common-source amplifier includes an NMOS transistor configured to receive the input voltage signal at a gate terminal claim 2 , and output the amplified voltage signal from a drain terminal.5. The circuit according to claim 2 , wherein the common-gate amplifier includes a PMOS transistor configured ...

SMALL SIGNAL RECEIVER AND INTEGRATED CIRCUIT INCLUDING THE SAME

A small signal receiver includes a first current adjustment circuit connected between a first power supply voltage terminal and a first node to provide current in response to a self-bias signal, a self-biased differential amplifier connected between the first node and a second node to compare an input signal with a reference voltage, provide the self-bias signal to a self-biasing node and output an output signal through an output node, and a second current adjustment circuit connected between the second node and a second power supply voltage terminal to sink current at the second node in response to the self-bias signal. The self-biased differential amplifier includes a swing stabilizing block connected between an input node to which the input signal is applied and the self-biasing node to stabilize the input signal compared with the reference voltage. 1. A small signal receiver comprising:a first current adjustment circuit configured to be connected between a first power supply voltage terminal and a first node and to provide current in response to a self-bias signal;a self-biased differential amplifier configured to be connected between the first node and a second node, to compare an input signal with a reference voltage, to provide the self-bias signal to a self-biasing node, and to output an output signal from an output node; anda second current adjustment circuit configured to be connected between the second node and a second power supply voltage terminal and to sink current at the second node in response to the self-bias signal,wherein the self-biased differential amplifier comprises a swing stabilizing block configured to be connected between an input node to which the input signal is applied and the self-biasing node.2. The small signal receiver of claim 1 , wherein the self-biased differential amplifier further comprises:a first P-type metal oxide semiconductor (PMOS) transistor configured to be connected between the first node and the self-biasing node and ...

SOURCE LEVEL DEBUGGING APPARATUS AND METHOD FOR A RECONFIGURABLE PROCESSOR

Provided are a source level debugging apparatus and method for a coarse grained array (CGA)-based reconfigurable processor. The source level debugging apparatus may determine valid operations for setting a breakpoint in a result of source code scheduling using invalid operation information, and may set the breakpoint at an address corresponding to the determined valid operations. 1. A source level debugging apparatus in a reconfigurable processor , the source level debugging apparatus comprising:a valid operation determiner that is configured to determine valid operations within code that is scheduled for processing; anda breakpoint setter that is configured to set breakpoints at addresses corresponding to the determined valid operations.2. The source level debugging apparatus of claim 1 , wherein the reconfigurable processor comprises a coarse grained array (CGA)-based processor.3. The source level debugging apparatus of claim 1 , wherein the scheduled code is a result of loop-unrolling-based modulo scheduling performed by a compiler.4. The source level debugging apparatus of claim 3 , wherein the valid operation determiner also determines an invalid operation that comprises an operation that is mapped to a prologue or an epilogue of the scheduled code in accordance with the loop-unrolling-based modulo scheduling.5. The source level debugging apparatus of claim 1 , wherein the valid operation determiner determines the valid operations based on invalid operation information.6. The source level debugging apparatus of claim 5 , wherein the invalid operation information comprises a cycle number at which an invalid operation is present claim 5 , and identification (ID) information of a function unit to which the invalid operation is mapped.7. A source level debugging method in a reconfigurable processor claim 5 , the source level debugging method comprising:determining valid operations within code that is scheduled for processing; andsetting breakpoints at addresses ...

APPARATUS AND METHOD FOR GENERATING ASSERTION BASED ON USER PROGRAM CODE, AND APPARATUS AND METHOD FOR VERIFYING PROCESSOR USING ASSERTION

Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive. 1. A method for generating an assertion based on a user program code , the method comprising:receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor; andgenerating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.2. The method of claim 1 , wherein the at least one assertion directive indicates the code requiring verification of the operation of the processor from among a plurality of codes contained in the user program.3. The method of claim 1 , wherein the generating the assertion comprises:determining the code requiring verification of the operation of the processor from among a plurality of codes contained in the user program based on an interpretation of the at least one assertion directive; anddetermining a point in time based on schedule information contained in the compiled result and the architecture information of the processor, at which the determined code of the user program, indicated by each of the at least one assertion directive, is executed, and a functional block which executes the code at the point in time.4. The method of claim 3 , wherein the generating the ...

Operating method of input/output interface

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

MEMORY DEVICE, OPERATING METHOD OF THE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE MEMORY DEVICE

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal. 1. A memory device comprising:a first buffer configured to receive an external clock signal and to generate an internal clock signal on the basis of the external clock signal;a second buffer configured to receive the internal clock signal from the first buffer; anda processing circuitry configured to receive the internal clock signal from the second buffer, to receive the internal clock signal from the second buffer,', 'to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal, each of the first through fourth internal clock signals having different phases, each of the first through fourth internal clock signals generated on the basis of the internal clock signal,', 'to generate a first data signal on the basis of first data and the first internal clock signal,', 'to generate a second data signal on the basis of second data and the second internal clock signal,', 'to generate a third data signal on the basis of third data and the third internal clock signal, and', 'to generate a fourth data signal on the basis of fourth data and the fourth ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector. 1. A semiconductor device , comprising:a substrate including a cell region and a circuit region;an upper wiring layer on the substrate and including a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring, the uppermost wiring including an uppermost chip pad electrically connected to the secondary uppermost wiring, at least a portion of the uppermost chip pad in the cell region; anda redistribution wiring layer on the upper wiring layer and including at least one redistribution wiring electrically connected to the uppermost chip pad, at least a portion of the at least one redistribution wiring serving as a landing pad connected to an external connector.2. The semiconductor device as claimed in claim 1 , further comprising:an insulation interlayer covering circuit pattern on the substrate,wherein the upper wiring layer is on the insulation interlayer.3. The semiconductor device as claimed in claim 1 , wherein:the upper wiring layer includes first to fourth wirings sequentially stacked on one another,the third wiring includes the secondary uppermost wiring, andthe fourth wiring includes the uppermost wiring.4. The semiconductor device as claimed in claim 1 , wherein the at least one redistribution ...

SIMULATION DEVICE AND DISTRIBUTION SIMULATION SYSTEM

A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus. 1. A simulation apparatus of a distributed simulation system in which simulation apparatuses share one storage node , the simulation apparatus comprising:a simulation executer configured to execute simulation tasks;a data storage configured to store data related to the simulation tasks based on a data storing policy that is set in advance of the execution of the simulation tasks; anda data updater configured to compare data stored in the data storage with data stored in another simulation apparatus, and update the data stored in the data storage into most recent data.2. The simulation apparatus of claim 1 , wherein the data related to the simulation tasks comprises at least one of Design Under Test (DUT) data claim 1 , simulation input data claim 1 , data generated in a simulation process claim 1 , or simulation result data.3. The simulation apparatus of claim 1 , wherein prior to executing the simulation tasks claim 1 , the simulation executer receives data used for executing the simulation tasks from the storage node only once claim 1 , stores the data in the data storage claim 1 , and executes the simulation tasks by using the data stored in the data storage depending on simulation requirements.4. The simulation apparatus of claim 3 , wherein the data used for executing the simulation tasks comprises at least one of Design Under Test (DUT) data or simulation input data.5. The simulation apparatus of claim 1 , ...

Operating method of input/output interface

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Vliw interface device and method for controlling the same

A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.

METHOD OF PROVIDING USER SPECIFIC INTERACTION USING DEVICE AND DIGITAL TELEVISION(DTV), THE DTV, AND THE USER DEVICE

An interactive method includes displaying image content received through a television (TV) network, identifying an object of interest of a user among a plurality of regions or a plurality of objects included in the image content, and providing additional information corresponding to the object of interest. 1. A method of providing user-specific interaction , the method comprising:receiving image content through a television (TV) network;displaying the image content;identifying an object of interest of a user among at least one of a plurality of regions and a plurality of objects included in the image content; andproviding additional information corresponding to the object of interest.2. The method of claim 1 , wherein the identifying comprises:tracking a gaze of the user using a photographing device; andidentifying an object tracked by the gaze of the user as the object of interest of the user.3. The method of claim 1 , further comprising:receiving signals from a user device used by the user;wherein the identifying comprises identifying the object of interest using the signals received from the user device.4. The method of claim 3 , wherein the identifying of the object of interest using the signals comprises:analyzing the signals received from the user device;determining a scene in which the signals are changed in the image content as a result of the analysis; andidentifying a region or object included in the scene in which the signals are changed as the object of interest.5. The method of claim 3 , wherein the signals received from the user device comprise at least one of a vital signal of the user detected by the user device and an external force applied to the user device.6. The method of claim 1 , further comprising:searching for additional information corresponding to the object of interest.7. The method of claim 1 , wherein the additional information corresponding to the object of interest comprises at least one of information providing sensory stimulus ...

THREE-DIMENSIONAL (3D) DISPLAY DEVICE FOR PROVIDING INPUT-OUTPUT INTERFACE USING DYNAMIC MAGNETIC FIELD CONTROL AND METHOD THEREOF

A three-dimensional (3D) display device for providing an input-output interface using a dynamic magnetic field control is disclosed, the device including a display unit to display a 3D image, a magnetic field generation unit to generate a magnetic field, and a control unit to dynamically control the magnetic field generation unit to generate a 3D magnetic field associated with the 3D image. 1. A three-dimensional (3D) display device providing an input-output interface , the 3D display device comprising:a display unit to display a 3D image;a magnetic field generation unit to generate a magnetic field; anda control unit to dynamically control the magnetic generation unit to generate a 3D magnetic field associated with the 3D image.2. The 3D display device of claim 1 , wherein the control unit comprises:a magnetic field generation control unit to control the magnetic field generation unit to generate a 3D magnetic field corresponding to the 3D image based on location information of pixels included in the 3D image; anda magnetic change recognition unit to recognize a change of the 3D magnetic field in response to an input from a user.3. The 3D display device of claim 2 , wherein the magnetic field generation unit comprises an electromagnet array claim 2 , andthe magnetic field generation unit comprises a current control unit to control a current input to the electromagnet array in order to generate the 3D magnetic field.4. The 3D display device of claim 3 , wherein the current control unit controls a direction of the current and an amount of the current claim 3 , to control a shape of the 3D magnetic field to correspond to a shape of the 3D image.5. The 3D display device of claim 2 , wherein the magnetic field generation unit comprises an electromagnet array claim 2 , andthe magnetic field change recognition unit comprises a current change detection unit to detect a change of a current flowing through the electromagnet array in order to recognize a change of the 3D ...

METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA

A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data 1. A method of compressing configuration data used in a reconfigurable processor , the method comprising:generating one piece of combined data by combining configuration data used during two or more cycles; andgenerating a bit table indicating valid operations in each of the two or more cycles from among operations comprised in the combined data.2. The method of claim 1 , further comprising claim 1 , when two or more pieces of combined data are generated claim 1 , generating an index configured to identify pieces of combined data used in each cycle from among the two or more pieces of combined data.3. The method of claim 1 , wherein the generating of the one piece of combined data is performed by combining two or more pieces of configuration data having valid operations not assigned to the same function unit.4. The method of claim 1 , wherein the reconfigurable processor is a coarse grained array (CGA)-based processor.5. The method of claim 1 , wherein the reconfigurable processor comprises a plurality of function units claim 1 , andthe configuration data used during each of the two or more cycles comprises operations performed by the function units during each of the two or more cycles.6. An apparatus for compressing configuration data used in a reconfigurable processor comprising:a combined data generator generating one piece of combined data by combining configuration data used in two or more cycles; anda bit table generator generating a bit table indicating valid operations in each of the two or more cycles from among operations comprised in the combined data.7. The apparatus of claim 6 , further comprising an index generator generating an index ...

Method of providing user specific interaction using device and digital television(dtv), the dtv, and the user device

An interactive method includes displaying image content received through a television (TV) network, identifying an object of interest of a user among a plurality of regions or a plurality of objects included in the image content, and providing additional information corresponding to the object of interest.

Input/output interface

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Super-resolution processing method for moving image and image processing apparatus therefor

A super-resolution processing method of a moving image is provided. The super-resolution processing method of a moving image includes sequentially inputting a plurality of input frames included in the video to any one of a recurrent neural network (RNN) for super-resolution processing and a convolutional neural network (CNN) for super-resolution processing, sequentially inputting a frame sequentially output from the any one of the RNN and the CNN to an additional one of the RNN and the CNN, and upscaling a resolution of the output frame by carrying out deconvolution with respect to a frame sequentially output from the additional one of the RNN and the CNN.

METHOD OF PROVIDING USER SPECIFIC INTERACTION USING DEVICE AND DIGITAL TELEVISION (DTV), THE DTV, AND THE USER DEVICE

An interactive method includes displaying image content received through a television (TV) network, identifying an object of interest of a user among a plurality of regions or a plurality of objects included in the image content, and providing additional information corresponding to the object of interest. 1. An electronic device of providing an interaction , the electronic device comprising:a sensor to sense a user-generated event; anda processor to identify an object of interest of the user based on the sensed event, to acquire additional information on the object of interest based on information on the identified object of interest, and to provide the additional information on the object of interest.2. The electronic device of claim 1 , further comprising:a communication interface to transmit the information on the identified object of interest to an external device and to receive the additional information on the object of interest from the external device,wherein the additional information comprises information into which the additional information on the object of interest is converted to be appropriate for the electronic device.3. The electronic device of claim 1 , wherein the processor generates the additional information on the object of interest by analyzing the information on the identified object of interest.4. The electronic device of claim 1 , wherein the processor identifies the object of interest among objects or regions included in an image content displayed on an external device different from the electronic device claim 1 , based on the sensed event.5. The electronic device of claim 1 , wherein the event comprises at least one of a biosignal of the user sensed through the electronic device and an external force applied to the electronic device.6. The electronic device of claim 1 , wherein the processor analyzes the generated event and identifies the object of interest of the user based on a result of the analyzing.7. The electronic device of claim ...

Memory device, operating method of the memory device and memory system comprising the memory device

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Super-resolution processing method for moving image and image processing apparatus therefor

Super-resolution processing method for moving image and image processing apparatus therefor

A super-resolution processing method of a moving image is provided. The super-resolution processing method of a moving image includes sequentially inputting a plurality of frames included in the video to any one of a recurrent neural network (RNN) for super-resolution processing and a convolutional neural network (CNN) for super-resolution processing, sequentially inputting a frame sequentially output from the any one of the RNN and the CNN to an other one of the RNN and the CNN, and upscaling a resolution of the output frame by carrying out deconvolution with respect to a frame sequentially output from the other one of the RNN and the CNN.

アサーション生成装置及び方法並びにプロセッサ検証装置及び方法

【課題】ユーザプログラムコードに基づいたアサーション生成装置及び方法、アサーションを利用したプロセッサ検証装置及び方法を提供する。 【解決手段】ユーザプログラムコードに基づいたアサーション生成方法は、少なくとも１つのアサーション生成構文を含むユーザプログラム、ユーザプログラムのコンパイル結果及びプロセッサのアーキテクチャー情報を受信する段階１１０と、ユーザプログラムのコンパイル結果及びプロセッサのアーキテクチャー情報に基づいて、少なくとも１つのアサーション生成構文によって指定されたユーザプログラムのコードによって、プロセッサが行わなければならない動作を記述するアサーションを生成する段階１３０と、を含みうる。 【選択図】図１

Inverse quantizer for use in MPEG-2 decoder

Inverse quantizer for use in MPEG-2 decoder

Memory device, operating method of the memory device and memory system comprising the memory device

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Memory device, operating method of the memory device and memory system comprising the memory device

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Operating method of input/output interface

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Method of providing user specific interaction using device and digital television (DTV), the DTV, and the user device

An interactive method includes displaying image content received through a television (TV) network, identifying an object of interest of a user among a plurality of regions or a plurality of objects included in the image content, and providing additional information corresponding to the object of interest.

Input/output interface

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Three-dimensional (3D) display device for providing input-output interface using dynamic magnetic field control and method thereof

A three-dimensional (3D) display device for providing an input-output interface using a dynamic magnetic field control is disclosed, the device including a display unit to display a 3D image, a magnetic field generation unit to generate a magnetic field, and a control unit to dynamically control the magnetic field generation unit to generate a 3D magnetic field associated with the 3D image.

Apparatus and method for generating assertion based on user program code, and apparatus and method for verifying processor using assertion

Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.

Method of providing user specific interaction using device and digital television (DTV), the DTV, and the user device

An interactive method includes displaying image content received through a television (TV) network, identifying an object of interest of a user among a plurality of regions or a plurality of objects included in the image content, and providing additional information corresponding to the object of interest.