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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 9870. Отображено 100.
26-01-2012 дата публикации

Non-Volatile Memory Element And Memory Device Including The Same

Номер: US20120018695A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments, relate to a non-volatile memory element and a memory device including the same. The non-volatile memory element may include a memory layer having a multi-layered structure between two electrodes. The memory layer may include first and second material layers and may show a resistance change characteristic due to movement of ionic species therebetween. The first material layer may be an oxygen-supplying layer. The second material layer may be an oxide layer having a multi-trap level.

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09-02-2012 дата публикации

Semiconductor device and method for driving semiconductor device

Номер: US20120033505A1
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.

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23-02-2012 дата публикации

Memory devices using a plurality of diodes as program selectors for memory cells

Номер: US20120044736A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

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23-02-2012 дата публикации

One-time programmable memories using polysilicon diodes as program selectors

Номер: US20120044738A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).

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23-02-2012 дата публикации

Reversible resistive memory using diodes formed in cmos processes as program selectors

Номер: US20120044747A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistive global wordlines through conductive contact(s) or via(s).

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23-02-2012 дата публикации

Variable resistance nonvolatile storage device and method of forming memory cell

Номер: US20120044749A1
Принадлежит: Panasonic Corp

A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate ( 301 ), (ii) a variable resistance element ( 309 ) having: lower and upper electrodes ( 309 a, 309 c ); and a variable resistance layer ( 309 b ) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes ( 309 a, 309 c ), and (iii) a MOS transistor ( 317 ) formed on the substrate ( 301 ), wherein the variable resistance layer ( 309 b ) includes: oxygen-deficient transition metal oxide layers ( 309 b - 1, 309 b - 2 ) having compositions MO x and MO y (where x<y) and in contact with the electrodes ( 309 a, 309 c ) respectively, and a diffusion layer region ( 302 b ) is connected with the lower electrode ( 309 a ) to form a memory cell ( 300 ), the region ( 302 b ) serving as a drain of the transistor ( 317 ) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer ( 309 b ).

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23-02-2012 дата публикации

Programmably reversible resistive device cells using cmos logic processes

Номер: US20120044753A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

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15-03-2012 дата публикации

Multi-level resistance change memory

Номер: US20120063193A1
Автор: Reika Ichihara
Принадлежит: Individual

According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.

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15-03-2012 дата публикации

Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same

Номер: US20120063194A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

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22-03-2012 дата публикации

Nonvolatile semiconductor memory device

Номер: US20120069627A1
Принадлежит: Toshiba Corp

A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

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29-03-2012 дата публикации

Resistance Based Memory Having Two-Diode Access Device

Номер: US20120075906A1
Принадлежит: Qualcomm Inc

A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

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29-03-2012 дата публикации

Resistive Random Access Memory and Verifying Method Thereof

Номер: US20120075908A1

A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

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29-03-2012 дата публикации

Nonvolatile semiconductor memory device

Номер: US20120075912A1
Автор: Koji Hosono
Принадлежит: Toshiba Corp

A nonvolatile semiconductor memory device comprises a three-dimensional cell array block in which a plurality of cell array layers are stacked, each of the cell array layers including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of memory cells disposed at each of intersections of the first and second lines and each including a variable resistance element configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a reading control circuit for reading data from the memory cells under a condition set in respective groups to which one or more cell array layers having a common electric property of the memory cells belong.

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19-04-2012 дата публикации

Resistive Memory Element and Use Thereof

Номер: US20120092920A1
Автор: Sakyo Hirose
Принадлежит: Murata Manufacturing Co Ltd

A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor which has a composition represented by the general formula: (Ba 1-x Sr x )Ti 1-y M y O 3 (wherein M is at least one from among Mn, Fe, and Co; 0≦x≦1.0; and 0.005≦y≦0.05). The first electrode of the pair of electrodes is made of a material which can form a Schottky barrier which can develop a rectifying property and resistance change characteristics in an interface region between the first electrode and the element body. The second electrode is made of a material which provides a more ohmic junction to the element body as compared with the first electrode.

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19-04-2012 дата публикации

Memory devices and memory systems including discharge lines and methods of forming

Номер: US20120092946A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.

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26-04-2012 дата публикации

Cross point variable resistance nonvolatile memory device

Номер: US20120099367A1
Принадлежит: Panasonic Corp

A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell ( 51 ) is placed at a different one of cross points of bit lines ( 53 ) in an X direction and word lines ( 52 ) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements ( 57, 58 ) switch electrical connection and disconnection between a global bit line ( 56 ) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit ( 92 ) having parallel-connected P-type current limiting element ( 91 ) and N-type current limiting element ( 90 ) is provided between the global bit line and the switch elements.

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14-06-2012 дата публикации

Programming reversible resistance switching elements

Номер: US20120147657A1
Принадлежит: SanDisk 3D LLC

A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption.

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19-07-2012 дата публикации

Memory unit and method of operating the same

Номер: US20120182785A1
Автор: Wataru Otsuka
Принадлежит: Sony Corp

A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.

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06-09-2012 дата публикации

Methods for increasing bottom electrode performance in carbon-based memory devices

Номер: US20120223414A1
Принадлежит: SanDisk 3D LLC

In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.

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06-09-2012 дата публикации

Three dimensional memory system with intelligent select circuit

Номер: US20120224410A1
Автор: Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

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06-09-2012 дата публикации

High density low power nanowire phase change material memory device

Номер: US20120225527A1
Принадлежит: International Business Machines Corp

A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

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20-09-2012 дата публикации

Program cycle skip

Номер: US20120236663A1
Принадлежит: SanDisk 3D LLC

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

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27-09-2012 дата публикации

Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance

Номер: US20120243298A1
Автор: Glen Hush
Принадлежит: Individual

The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.

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27-09-2012 дата публикации

Control Method for Memory Cell

Номер: US20120243346A1

A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

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04-10-2012 дата публикации

Semiconductor memory device and controlling method thereof

Номер: US20120250393A1
Автор: Masanobu Shirakawa
Принадлежит: Individual

According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, a peripheral circuit, a sense amplifier configured to sense the memory cells via the peripheral circuit, and a control circuit configured to control operations of the memory cell array and the sense amplifier. The control circuit is configured to boost a potential of a selected bit line, which is one of a first even bit line and a first odd bit line of a first side, by charge sharing of a second even bit line and a second odd bit line which are nonselected bit lines and physically neighbor the first even bit line or the first odd bit line of the first side, which is connected to a selected one of the memory cells.

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04-10-2012 дата публикации

Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack

Номер: US20120250443A1
Принадлежит: Individual

Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

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11-10-2012 дата публикации

Semiconductor device

Номер: US20120257437A1
Принадлежит: Elpida Memory Inc

A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element

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18-10-2012 дата публикации

Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells

Номер: US20120262973A1
Автор: Jun Liu
Принадлежит: Individual

An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

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25-10-2012 дата публикации

Semiconductor device and its manufacturing method

Номер: US20120268981A1
Принадлежит: Renesas Electronics Corp

In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

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08-11-2012 дата публикации

Variable resistance nonvolatile storage device

Номер: US20120281453A1

The variable resistance nonvolatile storage device includes a memory cell ( 300 ) that is formed by connecting in series a variable resistance element ( 309 ) including a variable resistance layer ( 309 b ) which reversibly changes based on electrical signals each having a different polarity and a transistor ( 317 ) including a semiconductor substrate ( 301 ) and two N-type diffusion layer regions ( 302 a, 302 b ), wherein the variable resistance layer ( 309 b ) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes ( 309 a, 309 c ) are made of materials of different elements, a standard electrode potential V 1 of the lower electrode ( 309 a ), a standard electrode potential V 2 of the upper electrode ( 309 c ), and a standard electrode potential V t of the transition metal satisfy V t <V 2 and V 1 <V 2 , and the lower electrode ( 309 a ) is connected with the N-type diffusion layer region ( 302 b ), the electrical signals being applied between the lower and upper electrodes ( 309 a, 309 c ).

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13-12-2012 дата публикации

Non-volatile memory device having phase-change material and method for fabricating the same

Номер: US20120314492A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory cells. In the non-volatile memory device, a circuit of the at least one second memory cell is cut off according to the initial information, and the initial information is defective block information that is information about a defect of the plurality of memory blocks.

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13-12-2012 дата публикации

Synapse for function cell of spike timing dependent plasticity (stdp), function cell of stdp, and neuromorphic circuit using function cell of stdp

Номер: US20120317063A1

A synapse for a spike timing dependent (STDP) function cell includes a memory device having a variable resistance, such as a memristor, and a transistor connected to the memory device. A channel of the memory device is connected in series with a channel of the transistor.

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20-12-2012 дата публикации

Resistance-change memory device and method of operating the same

Номер: US20120320659A1
Автор: Makoto Kitagawa
Принадлежит: Sony Corp

Disclosed herein is a resistance-change memory device including a bit line; a voltage supplying layer; a memory element connected between the bit line and the voltage supplying layer, a resistance value of the memory element being changed in accordance with an applied voltage; and a drive controlling circuit causing a first current to flow through the bit line and causing a second current smaller than the first current to flow through the bit line, thereby controlling a resistance decreasing operation in which the memory element is made to transit from a high resistance state to a low resistance state by using the second current.

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03-01-2013 дата публикации

Semiconductor memory device

Номер: US20130003433A1
Принадлежит: Toshiba Corp

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

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24-01-2013 дата публикации

Resistive ram, method for fabricating the same, and method for driving the same

Номер: US20130021835A1
Принадлежит: Individual

A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

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31-01-2013 дата публикации

Apparatuses and methods including memory array and data line architecture

Номер: US20130028023A1
Автор: Toru Tanzawa
Принадлежит: Individual

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

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31-01-2013 дата публикации

Nonvolatile semiconductor memory apparatus and manufacturing method thereof

Номер: US20130029469A1
Принадлежит: Takeshi Takagi, Takumi Mikawa

A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

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14-02-2013 дата публикации

Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor device incorporating nonvolatile memory element

Номер: US20130037775A1

A nonvolatile memory element of the present invention comprises a first electrode ( 103 ), a second electrode ( 108 ); a resistance variable layer ( 107 ) which is interposed between the first electrode ( 103 ) and the second electrode ( 107 ) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes ( 103 ) and ( 108 ), and the resistance variable layer ( 107 ) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfO x (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfO y (1.8≦y≦2.0) are stacked together.

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28-02-2013 дата публикации

Methods, apparatuses, and circuits for programming a memory device

Номер: US20130051136A1
Принадлежит: Micron Technology Inc

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

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07-03-2013 дата публикации

Device fabrication

Номер: US20130059436A1
Принадлежит: Individual

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

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21-03-2013 дата публикации

Select devices for memory cell applications

Номер: US20130070511A1
Принадлежит: Micron Technology Inc

Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.

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30-05-2013 дата публикации

Selector Device for Memory Applications

Номер: US20130134382A1

The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state.

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27-06-2013 дата публикации

Method of programming variable resistance element, method of initializing variable resistance element, and nonvolatile storage device

Номер: US20130163308A1
Принадлежит: Panasonic Corp

Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw 1 |>|Vw 2 |. Vw 1 represents writing voltage for first to N-th steps, Vw 2 represents writing voltage for (N+1)-th and subsequent steps, where N≧1, |Ve 1 |>|Ve 2 |. Ve 1 represents erasing voltage for first to M-th steps. Vet represents erasing voltage for M+1-th and subsequent steps. tw 1 <te 1 . tw 1 represents writing pulse width for first to N-th steps. te 1 represents erasing pulse width for first to M-th steps. M≧1. The (N+1)-th writing step follows the M-th erasing step.

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27-06-2013 дата публикации

Multi-port non-volatile memory that includes a resistive memory element

Номер: US20130163319A1
Автор: Hari M. Rao, Jung Pill Kim
Принадлежит: Qualcomm Inc

A particular method of accessing a multi-port non-volatile memory device includes executing a first memory operation with respect to a first memory cell while executing a second memory operation with respect to a second memory cell. The first memory operation is via a first port and the second memory operation is via a second port. The first memory cell includes a first non-volatile memory that includes a first resistive memory structure. The second memory cell includes a second non-volatile memory that includes a second resistive memory structure. The first memory cell and the second memory cell are each accessible via the first port and the second port.

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27-06-2013 дата публикации

Parallel programming scheme in multi-bit phase change memory

Номер: US20130163322A1
Автор: Chung H. Lam, Jing Li
Принадлежит: International Business Machines Corp

A system, a method for parallel programming multiple bits of a phase change memory array for high bandwidth. The system and method includes parallel programming scheme wherein a common wordline (WL) is driven with a first pulse of one of: gradually increasing (RESET) or decreasing (SET) amplitudes which control current flow through one or more phase change memory cells associated with the WL. Simultaneously therewith, one or more bitlines (BLs) are driven with one or more second pulses, each second pulse more narrow than that of the first pulse applied to the WL. The starting time of the one or more second pulses may vary with each bitline driven at a time later than, but within the window of the wordline pulse to achieve a programming current suitable for achieving the corresponding memory cell state.

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01-08-2013 дата публикации

High current capable access device for three-dimensional solid-state memory

Номер: US20130194855A1
Автор: Luiz M. Franca-Neto
Принадлежит: Individual

The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

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22-08-2013 дата публикации

Variable resistance memory device having equal resistances between signal paths regardless of location of memory cells within the memory array

Номер: US20130215660A1
Автор: Sang Min Hwang
Принадлежит: SK hynix Inc

A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged to couple first ends of the memory cells to the first signal transmission/reception unit; and a second transmission line configured to couple second ends of the memory cells to the second signal transmission/reception unit, wherein a first resistance of a first signal path coupled between the first and second signal transmission/reception units through a first memory cell of the memory cells is substantially equal to a second electrical resistance of a second signal path coupled between a second memory cell and the first and second signal transmission/reception units through a second memory cell of the memory cells.

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29-08-2013 дата публикации

Memory Device Having An Integrated Two-Terminal Current Limiting Resistor

Номер: US20130221314A1
Принадлежит: Intermolecular Inc

A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

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29-08-2013 дата публикации

Method and circuit for switching a memristive device in an array

Номер: US20130223134A1
Принадлежит: Hewlett Packard Development Co LP

A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.

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05-09-2013 дата публикации

Semiconductor memory device

Номер: US20130229853A1
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.

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12-09-2013 дата публикации

Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same

Номер: US20130234104A1
Автор: Scott Brad Herner
Принадлежит: SanDisk 3D LLC

A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the second stiffness is greater than the first stiffness, and forming a memory element coupled to the steering element pillar. Numerous other aspects are provided.

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19-09-2013 дата публикации

Resistance-change type non-volatile semiconductor memory

Номер: US20130242638A1
Автор: Daisaburo Takashima
Принадлежит: Toshiba Corp

A memory cell is formed with a resistance variable element, which is interposed between first and second electrodes and can store resistance changes representing 2 or more different values, and first and second cell transistors having source terminals thereof connected to the first electrode, and gates thereof to a word line. A drain of the first cell transistor is connected to a bit line, and a drain of the second cell transistor is connected to a data line. The second electrode is connected to a source line. During a read operation, the first and second cell transistors are kept in an ON state, and a current is supplied from the bit line to the source line through the memory cell. Data is read according to the electrical potential difference between the data line and the source line.

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26-09-2013 дата публикации

Nonvolatile memory device and method for manufacturing same

Номер: US20130248796A1
Автор: Hideki Inokuma
Принадлежит: Individual

According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

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26-09-2013 дата публикации

Nonvolatile semiconductor memory device and method of manufacturing the same

Номер: US20130248962A1
Принадлежит: Toshiba Corp

A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; an organic molecular layer formed on the semiconductor layer, the organic molecular layer including a plurality of organic molecules, each of the organic molecules includes a tunnel insulating unit of alkyl chain having one end bonded to the semiconductor layer, a charge storing unit, and a bonding unit configured to bond the other end of the alkyl chain to the charge storing unit; a block insulating film formed on the organic molecular layer; and a gate electrode formed on the block insulating film.

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26-09-2013 дата публикации

Nonvolatile memory element and nonvolatile memory device

Номер: US20130250658A1
Принадлежит: Panasonic Corp

A nonvolatile memory device includes: a first electrode; a second electrode; and a variable resistance layer which includes: a first oxide layer including a first metal oxide; a second oxide layer located between and in contact with the first oxide layer and a second electrode including a second metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxide layer; and a local region located in the first oxide layer and the second oxide layer, having contact with the second electrode and no contact with the first electrode, and having a degree of oxygen deficiency higher than the degree of oxygen deficiency of the second oxide layer and different from the degree of oxygen deficiency of the first oxide layer.

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03-10-2013 дата публикации

Small-Grain Three-Dimensional Memory

Номер: US20130258740A1
Автор: Guobiao Zhang
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.

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07-11-2013 дата публикации

Semiconductor memory device

Номер: US20130292630A1
Принадлежит: HITACHI LTD

The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory. A semiconductor memory device according to a first aspect of the present invention includes a variable resistance material layer and a channel layer that are connected in series between a first diffusion layer and a metal wire, thereby separating the metal wire and a channel semiconductor layer. A semiconductor memory device according to a second aspect of the present invention includes a variable resistance material layer electrically connecting channel semiconductor layers opposed to each other in a first direction and electrically connecting channel semiconductor layers adjacent to each other in a second direction, wherein a plurality of the channel semiconductor layers is disposed in the second direction.

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07-11-2013 дата публикации

Memory Arrays

Номер: US20130294132A1
Автор: Zengtao T. Liu
Принадлежит: Micron Technology Inc

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

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21-11-2013 дата публикации

Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines

Номер: US20130308363A1
Принадлежит: SanDisk 3D LLC

A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.

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21-11-2013 дата публикации

Semiconductor memory device

Номер: US20130308368A1
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

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28-11-2013 дата публикации

Method for programming nonvolatile memory element, method for initializing nonvolatile memory element, and nonvolatile memory device

Номер: US20130314975A1
Принадлежит: Panasonic Corp

A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance element and a MSM diode; applying, after the decreasing, a write voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a second resistance value lower than the first resistance value; and applying, after the decreasing, an erase voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a third resistance value lower than the first resistance value.

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05-12-2013 дата публикации

Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same

Номер: US20130320287A1
Принадлежит: SanDisk 3D LLC

A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

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05-12-2013 дата публикации

Memory apparatus with gated phase-change memory cells

Номер: US20130322168A1
Автор: Daniel Krebs, Gael Close
Принадлежит: International Business Machines Corp

A memory apparatus includes a plurality of gated phase-change memory cells having s≧2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only.

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19-12-2013 дата публикации

3d memory with vertical bit lines and staircase word lines and vertical switches and methods thereof

Номер: US20130339571A1
Принадлежит: SanDisk 3D LLC

A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

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02-01-2014 дата публикации

Semiconductor memory structure and control method thereof

Номер: US20140003122A1
Принадлежит: FUDAN UNIVERSITY

The present invention belongs to the technical field of non-volatile semiconductor memories, and relates to a semiconductor memory structure and a control method thereof. The semiconductor memory structure in the present invention comprises a memory unit for storing information and a tunneling field-effect transistor connected with the memory unit. The tunneling field-effect transistor is used for controlling the semiconductor memory's operations such as erasing, writing, and reading. A plurality of semiconductor memory structures compose a semiconductor memory array. The control method provided by the present invention comprises steps of resetting, setting, and reading. A vertical gate-controlled diode structure in a tunneling field-effect transistor is capable of providing a large current for writing a resistive random access memory and a phase change memory and improving the density of the memory array and therefore is very suitable for use in manufacturing of semiconductor memory chips; besides, the control method and the control circuit thereof are simple.

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16-01-2014 дата публикации

Array operation using a schottky diode as a non-ohmic selection device

Номер: US20140014893A1
Принадлежит: Unity Semiconductor Corp

A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

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23-01-2014 дата публикации

Nonvolatile memory device and method for manufacturing same

Номер: US20140021430A1
Принадлежит: Toshiba Corp

A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer

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30-01-2014 дата публикации

Method for driving nonvolatile memory element, and nonvolatile memory device

Номер: US20140029330A1
Принадлежит: Panasonic Corp

A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR<PWHR.

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30-01-2014 дата публикации

Nonvolatile memory device, programming method thereof and memory system including the same

Номер: US20140029344A1
Принадлежит: Individual

Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.

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06-02-2014 дата публикации

Operating method for memory device and memory array and operating method for the same

Номер: US20140036570A1
Принадлежит: Macronix International Co Ltd

An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

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06-03-2014 дата публикации

Nonvolatile semiconductor memory device

Номер: US20140063906A1
Принадлежит: Individual

A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines; and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.

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06-03-2014 дата публикации

Non-volatile memory device and method for manufacturing the same

Номер: US20140063913A1
Принадлежит: Panasonic Corp

A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.

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06-03-2014 дата публикации

Variable resistance memory devices and erase verifying methods thereof

Номер: US20140063914A1
Автор: Kohji Kanamori
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An erase verifying method includes applying a first voltage to a plurality of word lines connected to a memory cell block, and applying a second voltage less than the first voltage to a plurality of bit lines connected to the memory cell block. The method includes sensing bit line currents flowing through the plurality of bit lines, and comparing the sensed bit line currents with a reference current. The method also includes determining that the memory cell block has been sufficiently erased by a first erase operation if each of the sensed bit line currents is less than the reference current.

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20-03-2014 дата публикации

Apparatuses and methods including memory array and data line architecture

Номер: US20140078827A1
Автор: Toru Tanzawa
Принадлежит: Micron Technology Inc

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

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03-04-2014 дата публикации

Multilayer dielectric memory device

Номер: US20140091429A1
Автор: Kyu S. Min
Принадлежит: Intel Corp

A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship.

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03-04-2014 дата публикации

Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof

Номер: US20140092670A1
Автор: Stefan Cosemans

The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.

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06-01-2022 дата публикации

Memory access techniques in memory devices with multiple partitions

Номер: US20220004329A1
Принадлежит: Micron Technology Inc

Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

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05-01-2017 дата публикации

Method, Apparatus and Device for Operating Logical Operation Array of Resistive Random Access Memory

Номер: US20170004880A1
Принадлежит: Huawei Technologies Co Ltd

A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter. The logical operation array is set for performing logical operation and enable to storage output level signal in one resistive random access memory after the logical operation

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05-01-2017 дата публикации

Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture

Номер: US20170004881A1
Принадлежит:

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. 1. A data memory , comprising:a plurality of non-volatile re-programmable memory elements arranged in a three dimensional pattern defined by rectangular coordinates along x, y and z directions and with a plurality of parallel planes stacked in the z direction on top of a semiconductor substrate;a plurality of first conductive lines elongated in the z direction through the plurality of planes and arranged in a two dimensional rectangular array of rows in the x direction and columns in the y-direction;a plurality of second conductive lines elongated in the x-direction across each of the planes and spaced apart in they-direction between and separated from the first plurality of conductive lines in each of the planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across each of the planes, the plurality of second conductive lines forming pairs of adjacent second conductive lines, wherein each non-volatile re-programmable memory element is connected between a corresponding first conductive line and a corresponding second conductive line crossing each other at an associated location of the plurality of locations; anda plurality of select devices arranged to individually couple a selected row of first conductive lines to respective sensing circuits via a plurality of third conductive lines,wherein, for each of the pairs of adjacent second conductive lines, each second conductive line is connected to only one corresponding row of first conductive line such that both of the ...

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07-01-2016 дата публикации

Sensing a non-volatile memory device utilizing selector device holding characteristics

Номер: US20160005461A1
Принадлежит: Crossbar Inc

Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

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13-01-2022 дата публикации

Resistive memory device

Номер: US20220013171A1
Автор: Masayuki Terai
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A resistive memory device includes a first word line extending in a first horizontal direction, a second word line extending on the first word line in the first horizontal direction, a third word line extending on the second word line in the first horizontal direction, a first bit line extending between the first and second word lines in a second horizontal direction, a second bit line extending between the second and third word lines in the second horizontal direction, and memory cells respectively arranged between the first word line and the first bit line, between the first bit line and the second word line, between the second word line and the second bit line, and between the second bit line and the third word line. A thickness of the second word line is greater than a thickness of each of the first word line and the third word line.

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13-01-2022 дата публикации

APPARATUSES AND METHODS INCLUDING MEMORY AND OPERATION OF SAME

Номер: US20220013173A1
Принадлежит: MICRON TECHNOLOGY, INC.

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses. 1. A method comprising:applying a write pulse having a first polarity or a second polarity to a memory cell comprising a layer configured to act as a selector device and a memory element, wherein a first state is written to the memory cell when the write pulse has the first polarity and a second state is written to the memory cell when the write pulse has the second polarity; andapplying a read pulse having the first polarity to the memory cell, wherein a magnitude of the read pulse is between a first threshold voltage of the memory cell in the first state and a second threshold voltage of the memory cell in the second state.2. The method of claim 1 , further comprising sensing a current through the memory cell.3. The method of claim 2 , further comprising determining that the memory cell is in the first state or the second state based on a magnitude of the current sensed.4. The method of claim 3 , wherein the memory cell is determined to be in the second state if the magnitude is below a threshold current and the memory cell is determined to be in the first logic state when the magnitude through the memory cell is equal to or above the threshold current.5. The method of claim 1 , wherein the read pulse has a magnitude less than a magnitude of the write pulse.6. The method of claim 5 , wherein the magnitudes of the read pulse and the write pulse are voltage magnitudes.7. The ...

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07-01-2021 дата публикации

CROSS POINT DEVICE AND STORAGE APPARATUS

Номер: US20210005252A1

A cross point device according to an embodiment of the present disclosure includes a first electrode, a second electrode that is provided to be opposed to the first electrode, and a memory, a selector, and a resistor that are stacked between the first electrode and the second electrode. Of the resistor, a resistance value obtained through application of a negative voltage is lower than a resistance value obtained through application of a positive voltage. 1. A cross point device , comprising:a first electrode;a second electrode provided to be opposed to the first electrode; anda memory, a selector, and a resistor that are stacked between the first electrode and the second electrode, whereinof the resistor, a resistance value obtained through application of a negative voltage is lower than a resistance value obtained through application of a positive voltage.2. The cross point device according to claim 1 , whereinthe positive voltage is a voltage at which the memory turns into a low-resistance state as a result of the application, and the negative voltage is a voltage at which the memory turns into a high-resistance state as a result of the application.3. The cross point device according to claim 1 , whereinthe resistor has a resistance per unit area of not less than 1E9 Ω/cm and 1E11 Ω/cm.4. The cross point device according to claim 1 , whereinthe resistor has a multilayer structure, the resistor including, in at least one layer of the multilayer structure, at least one of carbon (C), germanium (Ge), boron (B), or silicon (Si).5. The cross point device according to claim 1 , whereinthe memory and the selector are stacked in this order between the first electrode and the second electrode, andthe resistor is provided at least one of between the first electrode and the memory, between the memory and the selector, or between the selector and the second electrode.6. The cross point device according to claim 5 , whereinthe selector includes a switch layer and an n-type ...

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07-01-2021 дата публикации

NONVOLATILE MEMORY DEVICE INCLUDING TEMPERATURE COMPENSATION CIRCUIT

Номер: US20210005253A1
Принадлежит:

A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current. 1. A nonvolatile memory device comprising:a differential current driver configured to receive a first differential signal and a second differential signal, which are based on a temperature, and to generate a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals;a current mirror circuit configured to copy a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and to regulate the reference current depending on a difference value of the second current and the second compensation current; anda trimming circuit configured to generate a program current or a read current based on the regulated reference current.2. The nonvolatile memory device of claim 1 , further comprising a control logic circuit configured to generate a temperature compensation magnitude signal for regulating a maximum compensation current value that is a sum of the first compensation current and the second compensation current.3. The nonvolatile memory device of claim 2 , wherein:in response to the temperature compensation magnitude ...

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07-01-2021 дата публикации

Techniques for programming a memory cell

Номер: US20210005257A1
Принадлежит: Micron Technology Inc

Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.

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07-01-2021 дата публикации

Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices

Номер: US20210005259A1
Автор: Liu Jun
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline. 1. A memory cell comprising:a wordline;a first bitline;a second bitline; anda memory element electrically connected to the wordline and selectively electrically connected to the first bitline and to the second bitline, the memory element storing information via a resistive state of the memory element;wherein the memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.2. The memory cell of wherein:the memory cell further comprises a first diode and a second diode;the memory element comprises a first electrode connected to the first bitline via the first diode and to the second bitline via the second diode and a second electrode connected to the wordline; andthe memory element is electrically connected to the first bitline via the first diode when the first diode is forward biased and is electrically disconnected from the first bitline when the first diode is not forward biased; andthe memory element is electrically connected to the second bitline via the second diode when the second diode is ...

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07-01-2021 дата публикации

Operations on memory cells

Номер: US20210005263A1
Автор: Hernan A. Castro
Принадлежит: Micron Technology Inc

In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.

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04-01-2018 дата публикации

HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

Номер: US20180005694A1
Принадлежит:

A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array. 1. (canceled)2. An integrated circuit comprising:a substrate;a base layer formed on the substrate, the base layer comprising a decoder formed with a plurality of transistors configured to operate within a first voltage range; and a plurality of conductive array lines; and', 'a plurality of re-writable two-terminal memory cells formed at intersections of the plurality of conductive array lines, the plurality of re-writable two-terminal memory cells configured to operate within a second voltage range, wherein the first voltage range is smaller than the second voltage range., 'a cross-point memory array formed above the base layer, the cross-point memory array comprising3. The integrated circuit of claim 2 , wherein the plurality of conductive lines comprises a plurality of X-line conductive array lines and a plurality of Y-line conductive array lines.4. The integrated circuit of claim 3 , wherein each of the plurality of re-writable two-terminal memory cells comprises a first terminal electrically coupled with one of the plurality of X-line conductive array lines and second terminal electrically coupled with one of the plurality of Y-line conductive array lines.5. The integrated circuit of claim 4 , wherein the base layer further comprises:an X-line decoder including a first subset of the plurality of ...

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04-01-2018 дата публикации

Methods for Error Correction with Resistive Change Element Arrays

Номер: US20180005706A1
Автор: Sheyang NING
Принадлежит: Nantero Inc

Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.

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04-01-2018 дата публикации

SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE

Номер: US20180005709A1
Принадлежит: Intel Corporation

Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs. 1. A memory device comprising:a memory stack having one or more memory die elements, including a first memory die element; anda system element coupled with the memory stack; a plurality of through silicon vias (TSVs), the plurality of TSVs including a plurality of data TSVs and one or more spare TSVs, and', 'self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs., 'wherein the first memory die element includes2. The memory device of claim 1 , wherein the self-repair logic includes an error correction code generator to generate an error correction code based on data for the data TSVs claim 1 , the error correction code to be transferred via the one or more spare TSVs.3. The memory device of claim 2 , wherein the self-repair logic further includes error correction logic to generate corrected data for the defective TSV.4. The memory device of claim 1 , wherein the self-repair logic includes a detection element to detect the defective TSV.5. The memory device of claim 4 , wherein the self-repair logic includes a multiplexer element to direct data intended for the defective TSV to a first spare TSV.6. The memory device of claim 5 , wherein the self-repair logic further includes a demultiplexer element to direct data received on the first spare TSV to a connection for the defective TSV.7. The ...

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02-01-2020 дата публикации

Memory devices and operation methods thereof

Номер: US20200005864A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device may include a memory cell array including a plurality of memory cells and a compensation resistor electrically connected to the memory cell array. The compensation resistor may generate a cell current compensating for a voltage drop generated in a parasitic resistor of a signal line connected to at least one memory cell of the plurality of memory cells. The compensation circuit may control a magnitude of resistance of a compensation resistor upon receiving an address corresponding to the memory cell. The compensation circuit may increase a magnitude of the cell current based on adjusting the magnitude of resistance of the compensation resistor to be substantially equal to a resistance value of the parasitic resistor.

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02-01-2020 дата публикации

CONTROLLING AGGREGATE SIGNAL AMPLITUDE FROM DEVICE ARRAYS BY SEGMENTATION AND TIME-GATING

Номер: US20200005865A1
Принадлежит:

High dynamic range resistive arrays are provided. An array of resistive elements provides a vector of current outputs equal to the analog vector-matrix product between (i) a vector of voltage inputs to the array encoding a vector of analog input values and (ii) a matrix of analog resistive weights within the array. First stage current mirrors are electrically coupled to a subset of the resistive elements through a local current accumulation wire. A second stage current mirror is electrically coupled to the first stage current mirrors through a global accumulation wire. Each of the first stage current mirrors includes at least one component having respective scaling factors selectable to scale up or down the current in the local current accumulation wire, thus controlling the aggregate current on the global accumulation wire. 1. An artificial neural network , comprising:at least one layer having a plurality of neurons;an array of resistive elements, the array providing a vector of current outputs equal to the analog vector-matrix product between (i) a vector of voltage inputs to the array encoding a vector of analog input values, corresponding to the plurality of neurons and (ii) a matrix of analog resistive weights within the array, corresponding to synaptic weights of the artificial neural network;first stage current mirrors, each of the first stage current mirrors being electrically coupled to a subset of the resistive elements through a local current accumulation wire; and 'each of the first stage current mirrors includes at least one component having respective scaling factors selectable to scale the current in the local current accumulation wire, thus controlling the aggregate current on the global accumulation wire.', 'a second stage current mirror, the second stage current mirror being electrically coupled to the first stage current mirrors through a global accumulation wire, wherein'}2. The artificial neural network of claim 1 , further comprising:a time- ...

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02-01-2020 дата публикации

APPARATUSES AND METHODS TO CONTROL OPERATIONS PERFORMED ON RESISTIVE MEMORY CELLS

Номер: US20200005866A1
Принадлежит:

Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device. 1. An apparatus comprising:a first conductive line;a second conductive line;a resistive memory cell coupled between the first and second conductive lines; anda control unit to:cause a voltage at the first conductive line during a first time interval and a second time interval of an operation of changing a resistance of the resistive memory cell to have a first voltage value during the first time interval and a second voltage value during the second time interval, the second voltage value being greater than the first voltage value, and to cause a current flowing through the resistive memory cell during the first and second time intervals to remain unchanged at a first current value; andcause a voltage at the first conductive line during a third time interval and a fourth time interval of the operation to have a third voltage value during the third time interval and a fourth voltage value during the fourth time interval, the fourth voltage value being greater than the third voltage value, and to cause a current flowing through the resistive memory cell during the third and fourth time intervals to remain unchanged at a second current value, the second current value being greater than the first current value.2. The apparatus of claim 1 , wherein the resistive memory cell has a first resistance before the first time interval and a second resistance after the ...

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02-01-2020 дата публикации

ARCHITECTURE FOR 3-D NAND MEMORY

Номер: US20200005869A1
Принадлежит:

Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area. 1. An apparatus , comprising:multiple stacked memory arrays, including a first array of memory cell strings and a second array of memory cell strings stacked over the first array, each memory cell string extending vertically, and including multiple memory cells; anda data plate associated with the first array and the second array, the data plate being located between the first array and the second array, and the date plate being shared by memory cell strings of the first array and the second array,wherein the first and second memory arrays are configured in multiple blocks, and wherein the multiple blocks each includes a memory cell string from the first array and a memory cell string from the second array.2. The apparatus of claim 1 , wherein the memory cell strings include NAND memory cell strings.3. The apparatus of claim 1 , wherein each of the memory cell strings includes a memory cell region claim 1 , with a drain select gate disposed between the memory cell region and a data line to which the memory cell string is coupled.4. The apparatus of claim 3 , wherein the drain select gate comprises multiple hierarchical select gates coupled between the memory cell region of the memory cell string and the data line to which the memory cell string is coupled.5. The apparatus of claim 1 , wherein each of the memory cell strings includes a source select gate disposed between a memory cell region and a source to which the memory cell string is coupled.6. The apparatus of claim 1 , further comprising:for each of the memory cell strings associated with the data plate, multiple select gates coupled between a memory cell region of the memory cell string and the data plate.7. The apparatus of claim 1 ...

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04-01-2018 дата публикации

ELECTRONIC COMPONENT

Номер: US20180006253A1
Принадлежит: Merck Patent GmBH

An electronic component () comprising a plurality of switching elements () which comprise, in this sequence, 1101. Electronic component () comprising a plurality of switching elements () which comprise , in this sequence ,{'b': '16', 'a first electrode (),'}{'b': '18', 'a molecular layer () bonded to a substrate, and'}{'b': '20', 'a second electrode (),'}where the molecular layer essentially consists of molecules (M) which contain a connecting group (V) and an end group (E) having a polar or ionic function.2. Electronic component according to claim 1 , where the connecting group (V) is of flexible conformation and the molecules (M) have a conformation-flexible molecular dipole moment.310. Electronic component () according to claim 1 , where the connecting group (V) is a C-C-alkylene group claim 1 , which may contain one or more functional groups and/or one or more 3-6-membered claim 1 , saturated or partially unsaturated claim 1 , alicyclic or heterocyclic rings in the chain and in which one or more H atoms may be replaced by halogen.410. Electronic component () according to claim 3 , where the connecting group (V) is a linear or branched C-C-alkylene group claim 3 , in which one or more non-adjacent CHgroups may each be replaced by —C═C— claim 3 , —CH═CH— claim 3 , —NR′— claim 3 , —O— claim 3 , —S— claim 3 , —CO— claim 3 , —CO—O— claim 3 , —O—CO— claim 3 , —O—CO—O— or a 3-6-membered claim 3 , saturated or partially unsaturated claim 3 , alicyclic or heterocyclic ring claim 3 , where N claim 3 , O and/or S are not bonded directly to one another claim 3 , in which one or more tertiary carbon atoms (CH groups) may be replaced by N and in which one or more hydrogen atoms may be replaced by halogen claim 3 , where R′ in each case claim 3 , independently of one another claim 3 , denotes H or C-C-alkyl.510. Electronic component () according to claim 4 , where the connecting group (V) is a linear or branched C-C-alkylene group claim 4 , in which one or more non-adjacent ...

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07-01-2021 дата публикации

RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE

Номер: US20210005811A1
Принадлежит:

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. 1. An apparatus , comprising:an access device comprising a gate and a drain;a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device;a via extending through the dielectric and through at least a portion of the drain of the access device; anda deposited layer of material positioned within the via.2. The apparatus of claim 1 , further comprising:one or more tungsten contacts positioned in the via and in contact with the deposited layer of material.3. The apparatus of claim 1 , further comprising:one or more platinum contacts positioned in the via and in contact with the deposited layer of material.4. The apparatus of claim 1 , wherein the deposited layer of material comprises titanium silicide claim 1 , titanium nitride claim 1 , or a combination thereof.5. The apparatus of claim 1 , wherein the deposited layer of material comprises platinum claim 1 , or platinum silicide claim 1 , or a combination thereof.6. The apparatus of claim 1 , further comprising:a word line in contact with the gate of the access device and the drain of the access device.7. The apparatus of claim 1 , wherein a bottom of the via is p-doped or n-doped.8. A memory device claim 1 , comprising:a first memory cell;an access device comprising a gate and a drain and operatively coupled with the first memory cell; and a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device;', 'a via extending through the dielectric and through at ...

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03-01-2019 дата публикации

THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME

Номер: US20190006387A1
Принадлежит:

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described. 1. A method comprising:forming conductive regions over a substrate;forming conductive materials and dielectric materials over the conductive regions, the conductive materials being electrically isolated from each other by the dielectric materials;forming holes through the conductive materials and dielectric materials to create initial cavities in each of the conductive materials;enlarging a size of each of the initial cavities to form enlarged cavities;forming memory elements in the enlarged cavities, each of the memory elements formed in a respective enlarged cavity of the enlarged cavities; andforming conductive paths through the memory elements, each of the conductive paths formed to electrically couple to a respective conductive region of the conductive regions.2. The method of claim 1 , wherein forming the holes also create additional cavities in the dielectric materials claim 1 , wherein the additional cavities remain substantially unchanged when the size of the each of the initial cavities is enlarged.3. The method of claim 2 , wherein each of the initial cavities and each of the additional cavities have a substantially same diameter.4. The method of claim 1 , wherein the memory element comprises polysilicon.5. The method of claim 1 , wherein the memory element comprises a dielectric material.6. A method comprising:forming conductive regions over a substrate;forming conductive materials and dielectric materials over the ...

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02-01-2020 дата публикации

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY

Номер: US20200006432A1
Принадлежит: SanDisk Technologies LLC

An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current. 1. Apparatus comprising:a bit line above a substrate;a word line above the substrate; anda non-volatile memory cell between the bit line and the word line, the non-volatile memory cell comprising a reversible resistance-switching memory element coupled in series with an isolation element, the isolation element comprises a first selector element coupled in series with a second selector element; and', 'the first selector element comprises a first snapback current, the second selector element comprises a second snapback current lower than the first snapback current., 'wherein2. The apparatus of claim 1 , wherein the first selector element comprises a first selector leakage current claim 1 , the second selector element comprises a second selector leakage current claim 1 , and the first selector leakage current is less than second selector leakage current.3. The apparatus of claim 1 , wherein the first selector element comprises a first selector leakage current claim 1 , the second selector element comprises a second selector leakage current claim 1 , the reversible resistance-switching memory element comprises a memory element leakage current claim 1 , and one of the first selector leakage current and the second selector leakage current substantially equals the memory element leakage current.4. The apparatus of claim 1 , wherein the first selector element comprises a first threshold voltage claim 1 , ...

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02-01-2020 дата публикации

WORD LINE WITH AIR-GAP FOR NON-VOLATILE MEMORIES

Номер: US20200006433A1
Принадлежит: Intel Corporation

Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical. 1. An integrated circuit , comprising:a plurality of word lines (WLs), wherein said WLs are arranged in a stacked configuration with respect to one another;one or more air-gaps arranged between at least some of said WLs;a plurality of bit lines (BLs), wherein one or more said BLs intersects one or more said WLs; andan array of memory cells, at least some of the memory cells being addressable by corresponding ones of said WLs and BLs.2. The integrated circuit according to claim 1 , wherein the array of memory cells includes an RRAM (“Resistance Random Access Memory) memory configuration.3. The integrated circuit according to claim 1 , wherein the array of memory cells includes a FeFET (“Ferroelectric Field Effect Transistor”) memory configuration.4. The integrated circuit according to claim 1 , wherein said WLs are arranged parallel to an underlying wafer surface or substrate surface.5. The integrated circuit according to claim 1 , wherein said WLs are arranged perpendicular to an underlying wafer surface or substrate surface.6. The integrated circuit according to claim 1 , wherein each memory cell comprises a selector claim 1 , a metal electrode claim 1 , and an RRAM switching layer.7. The integrated circuit according to claim 6 , wherein said RRAM switching layer comprises oxygen and one or more of hafnium claim 6 , tantalum claim 6 , silicon claim 6 , and tungsten.8. The integrated circuit according to claim 1 , wherein said integrated circuit is a processor or a communication chip.9. The integrated circuit according to claim 1 , wherein said integrated circuit is part of a mobile computing device.10. An integrated circuit claim 1 , comprising:a first word line (WL) and a second WL;an air-gap between the first WL and second WL; a switching layer including an oxide material,', 'a selector layer, for ...

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03-01-2019 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190006422A1
Автор: PARK Jong-Chul
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A variable resistance memory device including a first conductive line extending in a first direction on a substrate, a second conductive line on the first conductive line and extending in a second direction crossing the first direction, and a memory cell pillar connected to the first conductive line and the second conductive line at a crossing point therebetween and including a heating electrode layer and a variable resistance layer in contact with the heating electrode layer such that both sidewalls of the heating electrode layer are aligned with both sidewalls of the first conductive line in the first direction. 1. A variable resistance memory device comprising:a first conductive line on a substrate, the first conductive line extending in a first direction;a second conductive line on the first conductive line, the second conductive line extending in a second direction, the second direction being a direction crossing the first direction; anda memory cell pillar connected to the first conductive line and the second conductive line at an intersection point therebetween, the memory cell pillar including a heating electrode layer and a variable resistance layer, the variable resistance layer in contact with the heating electrode layer, two opposite sidewalls of the heating electrode layer aligned with two opposite sidewalls of the first conductive line in the first direction, respectively.2. The variable resistance memory device of claim 1 , wherein the heating electrode layer is in contact with a portion of a bottom surface of the variable resistance layer in the first direction claim 1 , and is in contact with an entirety of the bottom surface of the variable resistance layer in the second direction.3. The variable resistance memory device of claim 1 , wherein the substrate includes a substrate recess portion claim 1 , the substrate recess portion being a recess formed in the substrate in a self-aligned manner with respect to the two opposite sidewalls of the first ...

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