ЭЛЕКТРОМЕХАНИЧЕСКИЙ ЭЛЕМЕНТ ПАМЯТИ

Электромеханический элемент памяти, содержащий опорную плату, изоляционный слой, электромеханический привод с электродами управления, площадки крепления, отличающийся тем, что сформирована единая упругодеформируемая балка, предварительно изогнутая относительно ее нейтрального положения, а на одном из электродов электромеханического привода в верхнем ее слое сформирован эмиттер автоэмиссионного диода. И 1 149608 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ ВУ” 149 608” 4 ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ИЗВЕЩЕНИЯ К ПАТЕНТУ НА ПОЛЕЗНУЮ МОДЕЛЬ ММ9К Досрочное прекращение действия патента из-за неуплаты в установленный срок пошлины за поддержание патента в силе Дата прекращения действия патента: 08.07.2020 Дата внесения записи в Государственный реестр: 11.05.2021 Дата публикации и номер бюллетеня: 11.05.2021 Бюл. №14 Стр.: 1 па 830967 ЕП

Mems device and method of manufacture

A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch.

ELECTROMECHANICAL INTEGRATED MEMORY ELEMENT AND ELECTRONIC MEMORY COMPRISING THE SAME

An electromechanical memory element includes a fixed body and a deformable element attached to the fixed body. An actuator causes a deformation of the deformable element from a first position (associated with a first logic state) to a second position (associated with a second logic state) where a mobile element makes contact with a fixed element. A programming circuit then causes a weld to be formed between the mobile element and the fixed element. The memory element is thus capable of associating the first and second positions with two different logic states. The weld may be selectively dissolved to return the deformable element back to the first position. 1. An apparatus including an electromechanical memory element , comprising:a fixed supporting body;a first mobile device including a first deformable element constrained to said fixed supporting body, said first mobile device defining a first mobile contact element;a fixed contact element fixed with respect to the fixed supporting body;an actuator configured to deform the first deformable element so as to set the first mobile device in a first position, where the first mobile contact element is separate from the fixed contact element, or in a second position, where the first mobile contact element is in contact with the fixed contact element, said first and second positions being associable to two different logic states; anda programming circuit configured to co-operate with the actuator to form, if the first mobile device is in the second position and the first mobile contact element and the fixed contact element are not welded together, a weld between the first mobile contact element and the fixed contact element.2. The apparatus according to claim 1 , wherein the programming circuit is further configured to co-operate with the actuator to remove claim 1 , if the first mobile device is in the second position and a previous weld is present between the first mobile contact element and the fixed contact element ...

QUANTUM TECHNOLOGY

A device for the storage and/or processing of quantum information comprises: a body (), formed from a material having negligible net nuclear or electronic magnetic field; a set of data entities () embedded in said body, each having a plurality of magnetic field states; a set of probes (), offset from the body, arranged to acquire internal phase shifts due to the magnetic fields of said data entities; wherein the probes () are each arranged to move relative to a plurality of data entities () in order that each probe () acquires an internal phase shift from the plurality of data entities (); and means for reading each probe (), thereby establishing a parity of the plurality of data entities (). 1. A device for storage and/or processing of quantum information , the device comprising:a first body, formed from a material having negligible net nuclear or electronic magnetic field;a set of data entities embedded in said first body, each data entity of the set of data entities having a plurality of magnetic field states;a set of probes, offset from the first body, arranged to acquire internal phase shifts due to magnetic fields of said set of data entities; wherein each probe of the set of probes is arranged to move relative to a plurality of data entities of the set of data entities to permit each probe to acquire an internal phase shift from the plurality of data entities; anda probe reader arranged to read each probe, thereby establishing a parity of the plurality of data entities.2. The device as claimed in claim 1 , wherein the set of data entities comprises qudits.3. The device as claimed in claim 1 , comprising two magnetic field states for each data entity.4. The device as claimed in claim 1 , arranged such that a probe acquires an internal phase shift from four data entities.5. The device as claimed in claim 1 , arranged to flip the magnetic fields of the set of data entities and the set of probes after the parity is established for the plurality of data entities ...

RESISTIVE CHANGE ELEMENT ARRAYS WITH IN SITU INITIALIZATION

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration. 1. A resistive change element memory array , comprising:a plurality of word lines;a plurality of bit lines;a plurality of select lines;a plurality of initialization driver circuits; a resistive change element having a first terminal and a second terminal, said first terminal in electrical communication with a select line and an initialization driver circuit, wherein said resistive change element is capable of being switched between at least two non-volatile resistance values with a first resistance value corresponding to a first resistive state and a second resistance value corresponding to a second resistive state;', 'a selection device responsive to a control signal on a word line, said selection device selectively providing a conductive path between a bit line and said second terminal of said ...

CASIMIR EFFECT MEMORY CELL

A digital memory device includes a moveable element that is configured to move between a first stable position and a second stable position, where the moveable element comprises a first conducting area. The digital memory device further includes a second conducting area on the surface of a substrate. At the first stable position of the moveable element, a first gap exists between the first conducting area and the second conducting area. At the second stable position of the moveable element, a second gap that is smaller than the first gap exists between the first conducting area and the second conducting area. In at least the second stable position, an attractive Casimir force between the moveable element and the substrate holds the moveable element in the stable position. 1. A digital memory device , comprising:a moveable element configured to move between a first stable position and a second stable position, wherein the moveable element comprises a first conducting area; anda second conducting area on the surface of a substrate;wherein at the first stable position of the moveable element, a first gap exists between the first conducting area and the second conducting area, andwherein at the second stable position of the moveable element, a second gap that is larger than the first gap exists between the first conducting area and the second conducting area, andwherein in at least the first stable position an attractive Casimir force between the moveable element and the substrate holds the moveable element in the stable position;{'sup': 2', '2, 'wherein an area of the moveable element is between 10 nanometersand 1000 nanometers.'}2. The digital memory device of claim 1 , wherein the first conducting area comprises a surface of a conducting disk claim 1 , and wherein the moveable element is configured to move in a perpendicular manner with respect to the second conducting area.3. The digital memory device of claim 1 , wherein the second gap is 10 nanometers or less.4. ...

MEMORY CELL IN CAPACITIVE LOGIC

A memory cell in capacitive logic, including a bistable system including a fixed element and a mobile element capable of taking one or the other of two stable positions with respect to the fixed element; a read device including a variable-capacitance capacitor including a first fixed electrode and a second mobile electrode rigidly fixed to the mobile element; and an electrically controllable write device for placing the mobile element in one or the other of its two stable positions. 2. The cell according to claim 1 , wherein the write device is an electrostatic device comprising a third fixed electrode claim 1 , a fourth fixed electrode claim 1 , and a fifth mobile electrode rigidly fixed to the mobile element claim 1 , the fifth electrode being disposed between the third and fourth electrodes.3. The cell according to claim 2 , wherein the third claim 2 , fourth and fifth electrodes have the form of inter-engaged combs.4. The cell according to claim 2 , wherein the third claim 2 , fourth and fifth electrodes have the form of flat plates that are parallel to one another.5. The cell according to claim 1 , wherein the first and second electrodes have the form of inter-engaged combs.6. The cell according to claim 1 , wherein the first and second electrodes have the form of flat plates that are parallel to each another.7. The cell according to claim 1 , wherein the bistable system is a system in accordance with the alternative a) of .8. The cell according to claim 7 , wherein the fixed electrode and the mobile electrode of the bistable system have the form of inter-engaged combs.9. The cell according to claim 7 , wherein the fixed electrode and the mobile electrode of the bistable system have the form of flat conductive plates that are parallel to each other.10. The cell according to claim 7 , wherein the bistable system is a system according to the alternative b) of . This application claims priority to French patent application number 1857125, the content of which is ...

Resistance memory device and memory apparatus and data processing system

A resistance memory device and a memory apparatus and data processing apparatus having the same are provided. The resistance memory device includes a pair of electrode layers and a variable resistance layer interposed between the pair of electrode layers. The variable resistance layer includes at least one variable resistance material layer and a piezoelectric material layer coupled to the at least one variable resistance material layer.

Mems device and method of manufacture

A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch.

DATA STORAGE CELL AND MEMORY ARRANGEMENT

A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a second control gate, a first output node against which the first moveable beam can be positioned. The data storage cell also comprises a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and a fourth control gate. The second moveable beam can be positioned against the first output node. Further, the first nano electromechanical switch and the second nano electromechanical switch are configured for selecting a first or a second state of the data storage cell and are configured for having their moveable beam complementary positioned to the first output node. A memory arrangement of such data storage cells is also disclosed, as well as methods for writing data to the data storage cells and for reading data from the data storage cells.

METHODS OF FORMING NANOTUBE FILMS AND ARTICLES

Nanotube films and articles and methods of making the same are disclosed. A conductive article or a substrate comprises at least two unaligned nanotubes extending substantially parallel to the substrate and each contacting end points of the article but each unaligned relative to the other, the nanotubes providing a conductive pathway within a predefined space. 1. A method of forming a lithographically-dimensioned conductive article of nanotubes , the method comprising:depositing a fabric of pre-grown, functionalized nanotubes on a substrate having at least a first conductive pad and a second conductive pad;using a lithographic pattern to remove a portion of the fabric to form a patterned nanotube fabric extending substantially parallel to the substrate,wherein each nanotube in the patterned nanotube fabric is in fixed contact with the first conductive pad and each nanotube in fixed contact with the second conductive pad but each nanotube has an independent orientation relative to the other nanotubes,wherein the nanotubes form a conductive article substantially parallel to the substrate between the first and second conductive pads, andwherein the conductive article has at least two sides that are substantially parallel to each other.2. The method of wherein the nanotubes include single-walled nanotubes.3. The method of wherein the nanotubes include multi-walled nanotubes.4. The method of wherein the nanotubes have different lengths.5. The method of wherein the nanotubes are of a controllable density.6. The method of claim 1 , wherein the patterned nanotube fabric spatially extends to edges of the defined claim 1 , region having selected and controlled dimensions corresponding to a selected pattern.7. The method of wherein the patterned nanotube fabric is a multilayer nanotube fabric. This application is a divisional of U.S. patent application Ser. No. 11/111,582 filed on Apr. 21, 2005, entitled NANOTUBE FILMS AND ARTICLES, which is a continuation of U.S. patent ...

Electromechanical nonvolatile memory

A semiconductor device includes an insulating layer on a semiconductor substrate, a bit line including TiAl and disposed on the insulating layer, a sidewall layer disposed on opposite sides of the bit line, a word line including TiN and disposed on the sidewall layer intersecting the bit line, and an air gap in an intersection region of the bit line and the word line. The thickness of the sidewall layer is larger than the thickness of the bit line. By having the TiAl bit line and TiN word line, the uniformity of the bit line and word line can be easily controlled to improve the performance of the semiconductor device.

Ferroelectric Mechanical Memory Based on Remanent Displacement and Method

A ferroelectric mechanical memory structure comprising a substrate, a MEMS switch element movable between a first position and at least one second position, the MEMS switch element comprising first and second electrodes, a layer of ferroelectric material positioned between the first and second electrodes so that upon application of voltage between the first and second electrodes the MEMS switch element moves between the first position and the second position, and a switch contact which contacts the first electrode only when the MEMS switch element is in the first position, wherein the ferroelectric material is selected so that the remanent strain within the layer of ferroelectric material is controlled by the history of the voltage potential applied to the ferroelectric material by the first and second electrodes, and wherein the remanent strain is sufficient to retain the MEMS switch element in the first or second position upon removal of the voltage.

FERROELECTRIC MECHANICAL MEMORY AND METHOD

A method of making a memory device comprising a base; a capacitor comprising a ferroelectric layer and at least two electrically conductive layers, the ferroelectric layer being located between the at least two electrically conductive layers; each of the at least two conductive layers being operatively connected to a current source; a cantilever attached to the base at first end and movable at a second end, the ferroelectric capacitor being mounted to the cantilever such that the second end of the cantilever moves a predetermined displacement upon application of a current to the ferroelectric layer which induces deformation of the ferroelectric layer thereby causing displacement of the cantilever which is operatively associated with a contact so that an electrical connection is enabled with the contact upon the predetermined displacement of the cantilever. The presence or absence of a connection forms two states of a memory cell. 1. A method of making a memory cell comprising;forming a ferroelectric layer; the ferroelectric layer have at least two sides;forming a capacitor by placing conductive layers on each side of the ferroelectric layer; the conductive layers adapted to be connected to a voltage source; securing at least one end of the capacitor while allowing the capacitor to flex into first and second positions; the capacitor flexing into the second position upon application of a voltage from the voltage source;providing a first contact, the capacitor being in operative electrical connection with the first contact in the second position;the voltage source operative to apply a positive or negative voltage to the ferroelectric capacitor causing the ferroelectric layers resulting in different internal deformation of the ferroelectric material depending upon whether a positive or negative voltage is applied, and wherein the deformation can be used to store either a one or zero binary bit, and wherein a subsequent voltage across the ferroelectric capacitor operates ...

SYSTEMS AND METHODS FOR GENERATING PHYSICALLY UNCLONABLE FUNCTIONS FROM NON-VOLATILE MEMORY CELLS

This disclosure describes techniques for generating physically unclonable functions (PUF) from non-volatile memory cells. The PUFs leverage resistance variations in non-volatile memory cells. Resistance variations in array of non-volatile memory cells may be produce a bitstring during an enrollment process. The bitstring may be stored in the non-volatile memory array. Regeneration may include retrieving the bitstring from the non-volatile memory array. 1. A method for generating a physically unclonable bitstring , the method comprising:programming cells in the memory array to a first state;for each of a plurality of cells in the memory array, determining a value corresponding to a respective analog entropy source;determining an approximate median value corresponding to the respective values;programming cells in the memory array having a value greater than the approximate median value to a second state; andgenerating a bitstring by reading the states of cells in the memory array.2. The method of claim 1 , wherein the first state corresponds to a logical zero state and the second state corresponds to a logical one state.3. The method of claim 1 , wherein the first state corresponds to a logical one state and the second state corresponds to a logical zero state.4. The method of claim 1 , wherein the memory array includes a flash memory array.5. The method of claim 4 , wherein determining a value corresponding to a respective analog entropy source includes measuring a voltage corresponding to a threshold voltage of a memory cell.6. The method of claim 1 , wherein the memory array includes a memristor memory array.7. The method of claim 6 , wherein determining a value corresponding to a respective analog entropy source includes measuring a voltage corresponding to a write operation.8. The method of claim 7 , wherein measuring a voltage corresponding to a write operation includes transmitting the voltage to a voltage-to-digital converter.9. The method of claim 1 , wherein ...

DDR COMPATIBLE OPEN ARRAY ACHITECTURES FOR RESISTIVE CHANGE ELEMENT ARRAYS

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration. 1. A resistive change element memory array , comprising:a plurality of word lines;a plurality of bit lines;a plurality of select lines;at least one reference line; a resistive change element having a first terminal and a second terminal, said first terminal in electrical communication with a select line, wherein said resistive change element is capable of being switched between at least two non-volatile resistance values with a first resistance value corresponding to a first informational state and a second resistance value corresponding to a second informational state;', 'a selection device responsive to a control signal on a word line, said selection device selectively providing a conductive path between a bit line and said second terminal of said resistive change element;, 'a plurality of memory ...

Resistive Change Element Arrays Using a Reference Line

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration. 1. A resistive change element memory array , comprising:a plurality of word lines;a plurality of bit lines;a plurality of select lines;at least one reference line, each of said at least one reference lines in electrical communication with a fixed reference voltage; a resistive change element having a first terminal and a second terminal, said first terminal in electrical communication with a select line, wherein said resistive change element is capable of being switched between at least two non-volatile resistance values with a first resistance value corresponding to a first informational state and a second resistance value corresponding to a second informational state;', 'a selection device responsive to a control signal on a word line, said selection device selectively providing a conductive path ...

METHODS FOR PROGRAMING DDR COMPATIBLE OPEN ARCHITECTURE RESISTIVE CHANGE ELEMENT ARRAYS

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration. 1. A method for programming a resistive change element within a resistive change element array , comprising: a plurality of word lines, a plurality of bit lines, and a plurality of select lines;', a two terminal resistive change element, having a first terminal and a second terminal; and', 'an FET selection device, having a source, drain, and gate;', 'wherein the first terminal of said two terminal resistive change element is in electrical communication with the source of said FET selection device;', 'the second terminal of said two terminal resistive change element is in electrical communication with one of said plurality of select lines;', 'the drain of said FET selection device in electrical communication with one of said plurality of bit lines; and', 'the gate of said FET selection device in ...

Carbon based nonvolatile cross point memory incorporating carbon based diode select devices and MOSFET select devices for memory and logic applications

The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Storage device

The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the first electrode and the second electrode and between the adjacent second electrodes. A stored state is determined utilizing the presence of the particle.

Storage device

The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the first electrode and the second electrode and between the adjacent second electrodes. A stored state is determined utilizing the presence of the particle.

Nonvolatile nanotube programmable logic devices and nonvolatile nanoture field programmable gate arrays using same

Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Bi-stable memory element

A bi-stable memory element (1) comprises a base contact (3), and a bridging contact (8), both made from an electrically conductive material. The bridging contact (8) is dimensioned so as to have two stable positions, in one of which the bridging contact (8) is in contact with the base contact (3), and in the other of which the bridging contact (8) is spaced apart from the base contact (3). Deflection means (4, 5) deflects the bridging contact (8) from one stable position to the other.

Methods of nanotube films and articles

Nanotube films and articles and methods of making the same. A nanotube films produced from a conductive article includes an aggregate of nanotube segments. The nanotube segments contact other nanotube segments to define a plurality of conductive pathways along the article. The nanotube segments may be single walled carbon nanotubes, or multi-walled carbon nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. The articles so formed may be disposed on substrates, and may form an electrical network of nanotubes within the article itself. Conductive articles may be made on a substrate by forming a nanotube fabric on the substrate, and defining a pattern within the fabric in which the pattern corresponds to the conductive article. The nanotube fabric may be formed by growing the nanotube fabric on the substrate using a catalyst, for example, in which the catalyst is a gas phase catalyst, or in which the catalyst is a metallic gas phase catalyst. The nanotube fabric may be formed by depositing a solution of suspended nanotubes on the substrate. The deposited solution may be spun to create a spin-coating of the solution. The solution may be deposited by dipping the substrate into the solution. The nanotube fabric is formed by spraying an aerosol having nanotubes onto a surface of the substrate.

Hybrid circuit having nanotube electromechanical memory

A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

Electromechanical memory array using nanotube ribbons and method for making same

Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes.

Nanotube films and articles

Nanotube films and articles and methods of making the same are disclosed. A conductive article includes an aggregate of nanotube segments in which the nanotube segments contact other nanotube segments to define a plurality of conductive pathways along the article. The nanotube segments may be single walled carbon nanotubes, or multi-walled carbon nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. The articles so formed may be disposed on substrates, and may form an electrical network of nanotubes within the article itself. Conductive articles may be made on a substrate by forming a nanotube fabric on the substrate, and defining a pattern within the fabric in which the pattern corresponds to the conductive article. The nanotube fabric may be formed by growing the nanotube fabric on the substrate using a catalyst, for example, in which the catalyst is a gas phase catalyst, or in which the catalyst is a metallic gas phase catalyst. The nanotube fabric may be formed by depositing a solution of suspended nanotubes on the substrate. The deposited solution may be spun to create a spin-coating of the solution. The solution may be deposited by dipping the substrate into the solution. The nanotube fabric is formed by spraying an aerosol having nanotubes onto a surface of the substrate.

Electromechanical memory having cell selection circuitry constructed with nanotube technology

A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. The decoder circuit is constructed of crossbar junctions at least one element of each junction being a nanotube or a nanotube ribbon.

Methods of making electromechanical three-trace junction devices

Methods of producing an electromechanical circuit element are described. A lower structure having lower support structures and a lower electrically conductive element is provided. A nanotube ribbon (or other electromechanically responsive element) is formed on an upper surface of the lower structure so as to contact the lower support structures. An upper structure is provided over the nanotube ribbon. The upper structure includes upper support structures and an upper electrically conductive element. In some arrangements, the upper and lower electrically conductive elements are in vertical alignment, but in some arrangements they are not.

控制微机械元件的装置与方法

本发明涉及控制微机械元件的装置与方法。本发明具体提供了一种利用非易失存储器装置的方法，该非易失存储器装置具有微机械元件、接触电极和切换电极，该方法包括：向该切换电极加载第一偏压电压；将该微机械元件从与该接触电极隔开的第一状态运动到与该接触电极接触并与该切换电极隔开第一距离的第二状态；向该切换电极加载第二偏压电压；将微机械元件运动到与该切换电极隔开第二距离的位置，该第二距离小于该第一距离；将加载到该切换电极上的该偏压电压转换到第三偏压电压；和将微机械元件运动到该第一状态。为了提高本发明的效力，还提供了一种用于非易失存储器装置的短路电路和一种电路。

Electromechanical memory array using nanotube ribbons and method for making same

본 발명에는 메모리 셀 등과 같은 전자 기계식 회로와 그 제조 방법이 개시되어 있다. 상기 전자 기계식 회로는, 기판의 표면으로부터 연장되는 지지부 및 전기 전도성 트레이스를 구비하는 구조물과, 상기 전기 전도성 트레이스와 교차하는 상기 지지부에 의해 현수되며 각각 하나 이상의 나노튜브를 구비하는 나노튜브 리본을 포함한다. 상기 전자 기계식 회로 요소는 기판의 표면으로부터 연장되는 지지부 및 전기 전도성 트레이스를 구비하는 구조물을 마련함으로써 제조된다. 상기 지지부 위에 나노튜브 층을 마련하고, 이 나노튜브 층의 일부를 선택적으로 제거하여 상기 전기 전도성 트레이스와 교차하는 나노튜브의 리본을 형성한다. 각 리본은 하나 이상의 나노튜브를 포함한다. The present invention discloses an electromechanical circuit such as a memory cell and a method of manufacturing the same. The electromechanical circuit includes a structure having a support extending from the surface of the substrate and an electrically conductive trace, and a nanotube ribbon suspended by the support crossing the electrically conductive trace and each having one or more nanotubes. . The electromechanical circuit element is manufactured by providing a structure having a support extending from the surface of the substrate and an electrically conductive trace. A layer of nanotubes is provided over the support, and a portion of the nanotube layer is selectively removed to form a ribbon of nanotubes that intersect the electrically conductive trace. Each ribbon contains one or more nanotubes.

用于阻变元件阵列的ddr兼容的存储器电路架构

本公开是一种用于阻变元件阵列的高速存储器电路架构。阻变元件阵列分为行和列，每列由一根字线服务，每行由两根位线服务。阻变元件的每行包括一对基准元件和感测放大器。在该阵列中使用的阻变元件中，该基准元件为具有对应于SET条件的电阻和对应于RESET条件的电阻之间的电阻值的电阻组件。高速READ操作通过下列步骤执行：将行的一位线通过字线选择的阻变元件放电，并且同时将行的另一位线通过基准元件放电，并使用行的感测放大器比较两条线上放电的速率。存储状态数据以高速同步的数据脉冲传送到输出数据总线。高速数据从外部同步的数据总线接收，并通过在存储器阵列配置中的阻变元件内的编程操作存储。

Nano-elastic memory device and method of manufacturing the same

나노탄성 메모리 소자 및 그 제조 방법에 관해 개시한다. 개시된 나노코일을 이용한 나노탄성 비휘발성 메모리 소자는, 기판; 상기 기판 상에 일정 간격으로 나란하게 배열된 하부전극; 상기 하부전극을 노출시키는 캐비티을 가지며, 상기 기판상에 소정 두께로 형성된 절연물질의 지지대; 상기 캐비티 내의 상기 하부전극 표면으로부터 수직 연장되며 일정간격으로 배열된 나노 탄성체; 상기 지지대 상에 상기 나노 탄성체 상에서 상기 하부전극과 직교하도록 배치된 상부전극;을 구비하는 것을 특징으로 한다.

Memory having tunnel barrier and method for writing and reading information to and from this memory

A resistive memory comprises a tunnel barrier. The tunnel barrier is in contact with a memory material which has a memory property that can be changed by a write signal. Because of the exponential dependence of the tunnel resistance on the parameters of the tunnel barrier, a change in the memory property has a powerful effect on the tunnel resistance, whereby the information stored in the memory material can be read. A solid electrolyte (ion conductor), for example, is suitable as a memory layer, wherein the ions thereof can be moved relative to the interface with the tunnel barrier by the write signal. The memory layer, however, can also be, for example, a further tunnel barrier, the tunnel resistance of which can be changed by the write signal, for example by displacement of a metal layer present in this tunnel barrier. The invention further provides a method for storing and reading information to and from a memory.

Programmable structure of micro-electronics

公开一种用于存储信息的微电子可编程构件(100)、包括该构件的阵列以及形成和对该构件编程的方法。可编程构件通常包括离子导体(140)和多个电极(120，130)。该构件的电气性质可通过向该构件施加能量而改变，并因此可使用该构件存储信息。

Memory having tunnel barrier and method for writing and reading information to and from this memory

A resistive memory comprises a tunnel barrier. The tunnel barrier is in contact with a memory material which has a memory property that can be changed by a write signal. Because of the exponential dependence of the tunnel resistance on the parameters of the tunnel barrier, a change in the memory property has a powerful effect on the tunnel resistance, whereby the information stored in the memory material can be read. A solid electrolyte (ion conductor), for example, is suitable as a memory layer, wherein the ions thereof can be moved relative to the interface with the tunnel barrier by the write signal. The memory layer, however, can also be, for example, a further tunnel barrier, the tunnel resistance of which can be changed by the write signal, for example by displacement of a metal layer present in this tunnel barrier. The invention further provides a method for storing and reading information to and from a memory.

Multi-bit electromechanical memory device and manufacturing method thereof

본 발명은 메모리 소자의 집적도를 증대 또는 극대화할 수 있는 멀티 비트 전기 기계적 메모리 소자 및 그의 제조방법을 개시한다. 그의 소자는 소정의 평탄면을 갖는 기판; 상기 기판 상에서 제 1 방향으로 형성된 비트 라인; 상기 비트 라인에 절연되고 상기 제 1 방향에 교차되는 제 2 방향으로 형성된 하부 워드 라인; 상기 하부 워드 라인의 측벽에서 절연되고 상기 비트 라인에 연결되도록 형성된 패드 전극; 상기 하부 워드 라인의 상부에서 하부 공극을 갖고 상기 제 1 방향으로 부양되면서 상기 패드 전극에 연결되고, 상기 하부 워드 라인에 인가되는 전하에서 유도되는 전기장에 의해 상기 제 1 및 제 2 방향에 수직하는 제 3 방향으로 굴곡되는 캔틸레버 전극; 상기 캔틸레버 전극의 상부에서 상부 공극을 갖고 부양되면서 상기 제 2 방향으로 형성된 트랩 사이트; 및 상기 트랩 사이트 상에 적층되어 상기 캔틸레버 전극을 상기 트랩 사이트의 방향으로 굴곡시키는 전하가 인가되도록 형성된 상부 워드 라인을 포함하여 이루어진다. The present invention discloses a multi-bit electromechanical memory device capable of increasing or maximizing the degree of integration of a memory device and a method of manufacturing the same. Its element includes a substrate having a predetermined flat surface; A bit line formed in a first direction on the substrate; A lower word line insulated from the bit line and formed in a second direction crossing the first direction; A pad electrode insulated from a sidewall of the lower word line and connected to the bit line; A lower pore at an upper portion of the lower word line and connected to the pad electrode while being lifted in the first direction and perpendicular to the first and second directions by an electric field induced in a charge applied to the lower word line. A cantilever electrode bent in three directions; A trap site formed in the second direction while being supported with an upper void at the top of the cantilever electrode; And an upper word line stacked on the trap site and configured to apply an electric charge to bend the cantilever electrode in the direction of the trap site.

Nonvolatile carbon nanotube memory device using multiwall carbon nanotubes and method of operating the same

A non-volatile carbon nanotube memory using a multi-wall carbon nanotube is provided to improve an operation speed while decreasing an operation voltage by enabling a memory function only by a little movement of a core of a multi-wall carbon nanotube. A first electrode(32) is formed on a substrate(30). First and second vertical walls(36,38) are formed on the first electrode, separated from each other. A multi-wall carbon nanotube(34) is formed on the first electrode between the first and the second vertical walls. Second and third electrodes(36b,38b) are formed on the first and the second vertical walls, respectively. A fourth electrode is formed over the multi-wall carbon nanotube. Caps(36a,38a) having tilted surfaces are formed on the upper surface of the first and second vertical walls, and the second and third electrodes are formed on the tilted surfaces of the caps confronting each other. An upper substrate(40) is formed over the multi-wall carbon nanotube, and a fourth electrode(42) is formed in the upper substrate.

Nano-elastic memory device and manufacture method thereof

本发明公开了一种纳米弹性存储装置及其制造方法。所述纳米弹性存储装置包括：基底；布置在所述基底上的多个下电极；支承单元，在具有暴露所述下电极的空腔的基底上以预定厚度由绝缘材料形成；纳米弹性体，在所述空腔中从所述下电极的表面竖直延伸；和多个上电极，形成于所述支承单元上，并且在所述纳米弹性体上面与所述下电极垂直交叉。使用纳米弹性存储装置可以在比使用多个带型纳米管的传统存储装置低的驱动电压下运行，存储单元不相互影响，可靠性更高，集成度更高。

Method and apparatus for bending electrostatic switch

An electronic circuit is formed by closely spacing metallic gate and drain interconnects to a flexible portion of a source interconnect. A gate voltage results in electrostatic attraction and lateral mechanical movement of the flexible source interconnect portion and causes an electrical short between source and drain. VanderWaals attraction between contacting source and drain can be used to provide volatile switching (springy thicker source portion) and non-volatile switching (limp thinner source portion). In accordance with the invention, an easily fabricated, high speed, low power, radiation hard, temperature independent, integrated reconfigurable electronic circuit with embedded logic and non-volatile memory can be realized. The switch uses patterned interconnect material for its structure and can be incorporated to a 3D layered structure consisting of three dimensional interconnect in which different layers and portions of the circuits are linked through volatile and non-volatile switches.

Moving a free-standing structure between high and low adhesion states

Embodiments disclosed herein generally solve a stiction problem in switching devices by using a series of pulses of force which take the switch from being strongly adhered to a landing electrode to the point where it is only weakly adhered. Once in the low adhesion state, the switch can then be pulled away from contact with a lower force provided by either the spring constant of the switch and/or the electrostatic forces resulting from low voltages applied to nearby electrodes.

Data storage device and a method of reading data in a data storage device

本发明包含一个数据存储设备及一种数据存储设备中的数据读取方法。相应地，本发明的首要方面是一个数据存储设备。数据存储包含固定在悬挂机构[202]上的探针尖[208]，数据存储层[214]，至少一个的导电层[218]，有悬挂机构[202]和至少一个的导电层[218]形成的电容[212]，检测由于数据位[210]的出现使探针尖[208]产生位移引起的电容[212]变化的传感器[204]。

Memory array using mechanical switch, method for controlling thereof, display apparatus using mechanical switch and method for controlling thereof

A memory array using a mechanical switch is provided to easily form a memory array without using a semiconductor transistor by using a mechanical switch having a dimple. A plurality of word lines are prepared. A plurality of bit lines cross the plurality of word lines. A plurality of mechanical switches are disposed in a crossing portion of the word lines and bit lines. A gate electrode(120) is connected to each word line. A drain electrode(140) is connected to a capacitor(160), separated from the gate electrode. The capacitor includes a first electrode, a second electrode and a dielectric layer formed between the first and second electrodes. An attach part is connected to each bit line, separated from the gate electrode. A transfer part is extended from the attach part, separated from the gate electrode. A source electrode(150) is extended from the transfer part, composed of a dimple of a protrusion type.

Bistable molecular switches and associated methods

A bistable molecular switch can have a highly conjugated first state and a less conjugated second state. The bistable molecular switch can be configured such that application of an electric field reversibly switches the molecular switch from the first state to the second state. Additionally, the bistable molecular switch can include a hydrophobic moiety and a hydrophilic moiety. Such molecular switches can be incorporated into a thin film as part of a molecular switch system which can include a layer of molecular switches between a first electrode layer and a second electrode layer. The layer of molecular switches can have substantially all of the molecular switches having their hydrophilic moiety oriented in the same direction. An electric potential can then be induced between the first and second electrode layers sufficient to switch the molecular switches from the first or second state to the second or first state, respectively. The first and second states have differences in resistivity which are suitable for use in electronic applications. Thin films containing these oriented molecular switches can be used to produce a wide variety of electronic components such as ROM memory and the like.

Electro-mechanical non-volatile memory device and method for manufacturing the same

전기적-기계적 비휘발성 메모리 장치 및 그 제조 방법에 개시된다. 언급한 메모리 장치는 적어도 상부 표면이 절연성을 갖는 지지 기판 상에 제1 및 제2 전극 패턴을 포함한다. 또한, 상기 지지 기판 상에는 절연막 패턴이 형성된다. 그리고, 상기 절연막 패턴 상에는 제3 전극 패턴 및 상기 제3 전극 패턴의 저면으로부터 연장되는 제4 전극 패턴이 형성된다. 여기서, 상기 제3 전극 패턴은 상기 절연막 패턴에 의해 지지되어 상기 제1 및 제2 전극 패턴의 상부면과는 제1 간격으로 이격되도록 연장되는 구조를 갖고, 상기 제4 전극 패턴은 상기 제3 전극 패턴의 저면으로부터 상기 개구부 내로 연장되고, 상기 제1 전극 패턴의 측벽, 제2 전극 패턴의 측벽, 절연막 패턴 및 지지 기판 각각과는 이격되고, 상기 지지 기판을 향하는 단부는 양측으로 볼록한 라운딩 구조를 갖는다. An electromechanical nonvolatile memory device and a method of manufacturing the same are disclosed. The memory device mentioned includes first and second electrode patterns on a support substrate having at least an upper surface thereof insulating. In addition, an insulating film pattern is formed on the support substrate. A third electrode pattern and a fourth electrode pattern extending from the bottom of the third electrode pattern are formed on the insulating layer pattern. Here, the third electrode pattern is supported by the insulating film pattern and has a structure extending so as to be spaced apart from the upper surface of the first and second electrode pattern by a first interval, the fourth electrode pattern is the third electrode Extends from the bottom of the pattern into the opening, and is spaced apart from each of the sidewall of the first electrode pattern, the sidewall of the second electrode pattern, the insulating film pattern, and the support substrate, and an end portion facing the support substrate has a rounded convex structure on both sides. .

Memory device for use in integrated circuit, has deformable part that is situated at distance from substrate and is deformable between two stable mechanical positions corresponding to two logic levels of memory cell

The memory device has a memory cell (CM) with a membrane (MB) fixed on a substrate (SB). A deformable part (PDF) is situated at a distance to the substrate and is deformable between two stable mechanical positions corresponding to two logic levels of the memory cell. A deformation unit (MDF) is deforms the membrane. A detection unit (MDT) detects the logic level of the memory cell. Independent claims are also included for the following: (a) an integrated circuit (b) a method of controlling a logic level of a memory cell.

CAPACITIVE LOGIC STORAGE CELL

La présente description concerne une cellule de mémorisation (100) en logique capacitive, comportant : - un système bistable (110) comportant un élément fixe (111) et un élément mobile (113) susceptible de prendre l'une ou l'autre de deux positions stables par rapport à l'élément fixe ; - un dispositif de lecture (120) comportant un condensateur à capacité variable (CR) comprenant une première électrode (121) fixe et une deuxième électrode (123) mobile solidaire mécaniquement de l'élément mobile (113) ; et - un dispositif d'écriture (130) commandable électriquement pour placer l'élément mobile (113) dans l'une ou l'autre de ses deux positions stables. The present description relates to a storage cell (100) in capacitive logic, comprising: - a bistable system (110) comprising a fixed element (111) and a mobile element (113) capable of taking one or the other of two stable positions with respect to the fixed element; - a reading device (120) comprising a variable capacitance capacitor (CR) comprising a first fixed electrode (121) and a second movable electrode (123) mechanically secured to the movable element (113); and - an electrically controllable writing device (130) for placing the movable element (113) in one or the other of its two stable positions.

Theoretical model for a nanorelay and same relay

The present invention relates to a nanotube device ( 100, 600 ), comprising a nanotube with a longitudinal and a lateral extension, a structure for supporting at least a first part of the nanotube, and first means for exerting a force upon the nanotube in a first direction defined by its lateral extension. At least a second part of the nanotube protrudes beyond the support of said structure, so that when said force exceeds a certain level, the second part of the nanotube will flex in the direction of its lateral extension, and thereby close a first electrical circuit. Suitably, the first means for exerting said force upon the nanotube is an electrical means, the force being created by applying a voltage to the means.

Device using nanoscopic wire and arrays, and method of manufacture thereof

【課題】本発明は、電界が存在する際に、ナノスコピックワイヤを成長させるステップを含む方法を提供する。電界は、ワイヤの成長の方向を定めるだけの十分な強さからなる。この方法は、オプションで、自己集合した単分子膜上にナノスコピックワイヤを成長させるステップを含む方法と組み合わせて用いることができる。全ての方法において、ナノスコピックワイヤの成長は、化学気相成長（ＣＶＤ）を用いて実行されることができる。 【解決手段】本方法は、金属ナノチューブと半導体ナノチューブとの混合体を設けるステップと、半導体ナノチューブから金属ナノチューブを分離するステップと、を含む方法。 分離するステップは、前記混合体を、金属ナノチューブの向きを選択的に定めるだけの十分な強さの電界にかけるステップを含む。電界は、半導体ナノチューブが前記電界に対して、その向けられないままであるような強さからなる。 【選択図】図２

NON-VOLATILE SRAM MEMORY CELL HAVING MOBILE GRID TRANSISTORS AND PIEZOELECTRIC ACTUATION.

RECORDING SYSTEM HAVING A MEMORY LAYER AND A MICROPOINT NETWORK

Methods of making electromechanical three-trace junctions devices

Methods of producing an electromechanical circuit element are described. A lower structure (103) having lower support structures and a lower electrically conductive element is provided. A nanotube ribbon (10) (or other electromechanically responsive element) is formed on an upper surface of the lower structure (103) so as to contact the lower support structures. An upper structure (102) is provided over the nanotube ribbon (101). The upper structure (102) includes upper support structures and an upper electrically conductive element. In some arrangements, the upper and lower electrically conductive elements are in vertical alignment, but in some arrangements they are not.

Nonvolatile memory device using nanotubes

Ddr compatible memory circuit architecture for resistive change element arrays

Storage device

Circuit arrays having cells with combinations of transistors and nanotube switching elements

Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, cells are arranged as pairs with the nanotube switching elements of the pair being cross coupled so that the set electrode of one nanotube switching element is coupled to the release electrode of the other and the release electrode of the one nanotube switching element being coupled to the set electrode of the other. The nanotube articles are coupled to the reference line, and the source of one field effect transistor of a pair is coupled to the set electrode to one of the two nanotube switching elements and the source of the other field effect transistor of the pair is coupled to the release electrode to the one of the two nanotube switching elements.

Molecular memory & logic

The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.

Mechanical memory device and fabrication method of the same

A mechanical memory device and a method for fabrication the same are provided to obtain a stable switching characteristic and minimize a leakage current by using a mechanical movement of a nano-wire. A source electrode(14) and a drain electrode(15) are formed on an insulating substrate(12). A nano-wire capacitor is formed on the source electrode. The nano-wire capacitor includes a first nano-wire(17) grown vertically on the source electrode to receive a V1 voltage, a dielectric layer formed on an outer surface of the first nano-wire, and a floating electrode formed on an outer surface of the dielectric layer. A second nano-wire(18) is vertically grown on the drain electrode to receive a V2 voltage having the polarity opposite to the polarity of the V1 voltage. A gate electrode(16) is disposed adjacently to the drain electrode on the insulating substrate to receive a V3 voltage having the same polarity as the polarity of the V2 voltage. The second nano-wire and the nano-wire capacitor are in contact with each other by electrostatic force of the first and the second nano-wires and the gate electrode and restitution force of the second nano-wire.

Nanotube-based switching elements and logic circuits

Nanotube-based switching elements and logic circuits are disclosed. Under one embodiment of the invention, a Boolean logic circuit includes at least one input terminal and an output terminal, and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. The Boolean function transformation includes a Boolean inversion within the function, such as a NOT or NOR function.

Method for manufacturing carbon nanotubes as functional elements of mems devices

A system and method for manufacturing carbon nanotubes as functional elements of MEMS devices is disclosed. The method of the present invention comprises the steps of preparing a MEMS substrate for synthesis of a carbon nanotube. A nonosize hole or catalyst retaining structure is fabricated on the MEMS substrate in which a nanotube catalyst is deposited. A nanotube is then synthesized within the nanosize hole.

Nano-electro-mechanical DRAM cell

A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.

Device and method for storing or switching

A device is disclosed, comprising: a first layer including a first molecular network having a first 2D lattice structure, a second layer including a second molecular network having a second 2D lattice structure, wherein the first layer and the second layer are arranged at a distance from each other such that the first and the second molecular network interact electronically via molecular orbital interactions, and a rotation device implemented to rotate the first layer relative to the second layer by a rotation angle, wherein an electrical resistance between the first molecular network and the second molecular network changes as a function of the rotation angle.

Magnetic switching element and signal processing device using the same

A magnetic switching element according to an example of the present invention includes a magnetic element, first and second electrodes which put the magnetic element therebetween, a current control section which is connected to the first and second electrodes, the current control section controlling a magnetization direction of a magnetization free section in such a manner that a current is made to flow between the magnetization free section and the magnetization fixed section, a movable conductive tube having a fixed end and a free end, and a third electrode connected to the fixed end of the conductive tube. A switching operation is performed in such a manner that a spatial position of the conductive tube is caused to change depending on the magnetization direction of the magnetization free section.

Memory element fabricated using atomic layer deposition

Mechanical digital memory

A data storage device and a method of reading data in a data storage device

Tri-state circuit using nanotube switching elements

Nano-tube based logic circuitry is disclosed. Tri-stating elements (52, 56, 62, 66) add an enable/disable function to the circuitry. Tri- stating elements (52, 56, 62, 66) may be provided by nano-tube based switching devices (52, 56, 62, 66 ). In the disabled state, the outputs present a high impedance ie, are tristated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile (52, 56, 62, 66), the inverter state and the control state are maintained in the absence of power. Such an inverter (20, 30) may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOs, bipolar and other transistor level technologies.

Apparatus and method for controlling micromechanical elements

Method for making an electrode structure

An electronic device such as a sensor or a NEMS. The electronic device comprises at least one substrate; a plurality of electrodes disposed on the substrate; and at least one nano-wire growing from an edge of a first electrode to an edge of a second electrode. A method for making an electrode structure by providing a substrate; forming a plurality of electrodes on the substrate; growing at least one nano-wire from the edge of a first electrode; and connecting the at least one nano-wire to the edge of a second electrode is also disclosed.

Method for processing a MEMS/CMOS cantilever based memory storage device

A Seek and Scan Probe (SSP) memory device is disclosed. The memory device includes a moving part having microelectromechanical (MEMS) structures fabricated on a first wafer and CMOS and memory medium components fabricating on a second wafer bonded to the first wafer.

Methods of using pre-formed nanotubes to make non-woven fabric and articles

미리 형성된 나노튜브를 사용하여 탄소 나노튜브 필름, 층, 직물, 리본, 소자 및 제품을 제조하는 방법이 개시되어 있다. 다양한 제품을 제조하기 위하여, 특정 실시태양에서는 기판(12)을 제공한다. 미리 형성된 나노튜브를 기판의 표면에 도포하여 탄소 나노튜브의 부직포를 생성한다. 소정 패턴에 따라 부직포(54)의 일부를 선택적으로 제거하여 제품을 생성한다. 나노직물을 제조하기 위하여, 기판을 제공한다. 미리 형성된 나노튜브를 기판의 표면에 도포하여 탄소 나노튜브의 부직포를 생성하는데, 이때 부직포는 실질적으로 균일한 밀도를 갖는다. Disclosed are methods for making carbon nanotube films, layers, fabrics, ribbons, devices and articles using preformed nanotubes. In order to manufacture various products, in certain embodiments, a substrate 12 is provided. The preformed nanotubes are applied to the surface of the substrate to produce a nonwoven fabric of carbon nanotubes. A portion of nonwoven fabric 54 is selectively removed according to a predetermined pattern to produce a product. In order to manufacture nanofabrics, a substrate is provided. The preformed nanotubes are applied to the surface of the substrate to produce a nonwoven fabric of carbon nanotubes, wherein the nonwoven fabric has a substantially uniform density. 나노튜브, 나노튜브 필름, 나노튜브 리본, 나노직물, 메모리 셀 Nanotubes, nanotube films, nanotube ribbons, nanofabrics, memory cells

Programmable structure, an array including the structure, and methods of forming the same

A microelectric programmable structure (100) suitable for storing information, and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor (140) and a plurality of electrodes (120, 130). Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Programmable structure, an array including the structure, and methods of forming the same

A microelectronic programmable structure suitable for storing information, and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Nonvolatile programmable switch

A nonvolatile programmable switch includes first and second magnetizable conductors having first and second ends, respectively, each of which is a north or south pole. The ends are mounted for relative movement between a first position in which they are in contact and a second position in which they are insulated from each other. The first conductor is permanently magnetized and the second conductor is switchable in response to a magnetic field applied thereto. Programming means are associated with the second conductor for switchably magnetizing the second conductor so that the second end is alternatively a north or south pole. The first and second ends are held in the first position by magnetic attraction and in the second position by magnetic repulsion.

Information Storage Apparatus

1,193,398. Statistical apparatus. BURROUGHS CORP. 14 Nov., 1968 [4 Dec., 1967], No. 54125/68. Heading G4M. A storage or delay device for actuating a deflector in a sorting machine comprises a rotatable wheel 16 having apertures in which one or more magnetic pins 18 slide, a C-shaped magnet 14 which biases the pins 18 to an inoperative position, a solenoid 20 which, when energized, attracts an aligned pin to an operative position, and a C-shaped magnet 12 which retains any actuated pins in the operative position until they are reset by magnet 14. When a pin in the operative position actuates a switch 40, a solenoid controlling the sorting deflector is energized.

Molecular mechanical devices with a band gap change activated by an electric field for optical switching applications

Molecular systems are provided for electric field activated switches, such as optical switches. The molecular system has an electric field induced band gap change that occurs via one of the following mechanisms: (1) molecular conformation change; (2) change of extended conjugation via chemical bonding change to change the band gap; or (3) molecular folding or stretching. Nanometer-scale reversible optical switches are thus provided that can be assembled easily to make a variety of optical devices, including optical displays.

Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Circuits made from nanotube-based switching elements with multiple controls

Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. The control structure includes a control electrode and a release electrode, disposed on opposite sides of the nanotube channel element. The control and release may be used to form a differential input, or if the device is constructed appropriately to operate the circuit in a non-volatile manner. The switching elements may be arranged into logic circuits and latches having differential inputs and/or non-volatile behavior depending on the construction.

Method of producing an integrated circuit with a carbon nanotube

A method of producing an integrated circuit with a carbon nanotube is disclosed. The integrated circuit includes a source, a drain, and a gate, and the source and the drain are positioned on the gate. A catalytic material is deposited onto the source. The catalytic material is then subjected to chemical vapor deposition. This initiates growth of the carbon nanotube such that the carbon nanotube extends from the source. Next, the carbon nanotube is bent toward the integrated circuit such that the carbon nanotube extends between the source and the drain to render the circuit operable.

Molybdenum-based electrode with carbon nanotube growth

A carbon nanotube is formed on at least one Molybdenum-based electrode. In one embodiment, a carbon-nanotube device includes a pair of Molybdenum-based electrodes over respective terraces. Using a catalyst on the Molybdenum-based material of at least one electrode, a carbon nanotube is grown over a gap that separates the terraces to connect the Molybdenum-based electrodes. Yet other aspects of the present invention employ carbon nanotubes extending (suspended) from respective Molybdenum-based structures for use in electrically addressable devices. The nanotubes can also be formed by patterned growth to bridge such Molybdenum-based electrodes. A particular method for manufacturing this device does not require post-growth processing. Applications include, among many others, scalable nanotube transistors/switches nano-electromechanical systems.

Nanotube-based logic driver circuits

Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.

Information disc binder

Multibit electro-mechanical memory device and method of manufacturing the same

A memory device comprises a cantilever electrode comprising a first portion that is supported by a pad electrode, and that extends from the pad electrode, and further comprising a second portion that arches over an upper part of the lower word line, wherein a lower void is between the second portion of the cantilever electrode and the lower word line, and wherein the second portion of the cantilever electrode, in a first position, is curved, wherein a trap site extends above the cantilever electrode, the trap site separated from the cantilever electrode by an upper void, and wherein an upper word line on the trap site receives a charge that enables the second portion of the cantilever electrode, in a second position, to be curved toward the trap site.

Nanotube device structure and methods of fabrication

Nanotube device structures and methods of fabrication. A method of making a nanotube switching element includes forming a first structure having at a first output electrode; forming second structure having a second output electrode; forming a conductive article having at least one nanotube, the article having first and second ends; positioning the conductive article between said first and second structures such that the first structure clamps the first and second ends of the article to the second structure, and such that the first and second output electrodes are opposite each other with the article positioned therebetween; providing at least one signal electrode in electrical communication with the conductive article; and providing at least one control electrode in spaced relation to the conductive article such that the control electrode may control the conductive article to form a conductive pathway between the signal electrode and the first output electrode.

Nanotube relay device

Nanotube films and articles

본 발명에 따르면, 나노튜브 필름 및 물품과 그 제조 방법이 개시되어 있다. 전도성 물품은 나노튜브 절편의 집합체를 포함하며, 상기 나노튜브 절편은 다른 나노튜브 절편과 접촉하여 물품을 따라 복수 개의 전도 경로를 형성한다. 상기 나노튜브 절편은 단일벽 카본 나노튜브일 수도 있고 다중벽 카본 나노튜브일 수도 있다. 다양한 나노튜브 절편은 그 길이가 서로 다를 수 있고, 물품보다 길이가 짧은 절편을 포함할 수 있다. 이렇게 형성된 물품은 기판 상에 배치될 수 있으며, 물품 자체 내에는 나노튜브의 전기망을 형성할 수 있다. 전도성 물품은 나노튜브 섬유를 기판 상에 형성하는 단계와, 전도성 물품에 상응하는 패턴을 상기 섬유 내에 형성하는 단계에 의해, 기판 상에 제조될 수 있다. 나노튜브 섬유는 촉매를 사용하여 기판 상에 나노튜브 섬유를 성장시키는 단계에 의해 형성될 수 있으며, 예컨대 상기 촉매는 기상 촉매이거나 기상 금속 촉매이다. 나노튜브 섬유는 기판 상에 나노튜브의 현탁액을 침적함으로써 형성될 수 있다. 침적된 용액을 회전시켠 현탁액의 스핀 코팅을 형성할 수 있다. 상기 현탁액은 기판을 현탁액에 침지함으로써 침적될 수 있다. 나노튜브 섬유는 나노튜브를 포함하는 연무질을 기판의 표면 상에 분무함으로써 형성된다. In accordance with the present invention, nanotube films and articles and methods of making the same are disclosed. The conductive article comprises an aggregate of nanotube segments, the nanotube segments contacting other nanotube segments to form a plurality of conductive paths along the article. The nanotube segments may be single-walled carbon nanotubes or multi-walled carbon nanotubes. The various nanotube segments may differ in length and may include segments that are shorter in length than the article. The article thus formed may be disposed on a substrate, and within the article itself may form an electrical network of nanotubes. Conductive articles can be made on a substrate by forming nanotube fibers on a substrate and forming a pattern in the fibers corresponding to the conductive article. Nanotube fibers can be formed by growing nanotube fibers on a substrate using a catalyst, for example the catalyst is a gaseous catalyst or a gaseous metal catalyst. Nanotube fibers can be formed by depositing a suspension of nanotubes on a substrate. Spin coating of the suspension with rotating the deposited solution can be formed. The suspension can be deposited by immersing the substrate in the suspension. Nanotube fibers are formed by spraying an aerosol comprising nanotubes onto the surface of a substrate.

Ddr-compatible memory circuit architecture of resistance change element array

【課題】抵抗変化素子アレイの高速メモリ回路アーキテクチャを提供する。 【解決手段】抵抗変化素子のアレイは、行および列に編成され、各列は、１つのワードラインを提供され、かつ、各行は、２つのビットラインを提供される。抵抗変化素子の各行は、１対の参照素子と、１つのセンス増幅器とを含む。参照素子は、アレイ内で使用される抵抗変化素子におけるＳＥＴ状態に対応する抵抗と、ＲＥＳＥＴ状態に対応する抵抗との間の電気抵抗値を有する抵抗成分である。高速ＲＥＡＤオペレーションは、行のビットラインのうちの一方を、ワードラインにより選択される抵抗変化素子を介して放電し、かつ、同時にこの行のビットラインのうちのもう一方を、参照素子を介して放電し、２つのライン上の放電レートを、この行のセンス増幅器を用いて比較することによって実行される。 【選択図】図４Ｂ

Receiver circuit using nanotube-based switches and transistors

Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical communication with the input links and the output links. Each switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. First and second MOS transistors are each in electrical communication with a reference signal and with the output node of a corresponding one of the first and second switching elements.

E-field-modulated bistable molecular mechanical device

A molecular system is provided for nanometer-scale reversible electronic and optical switches, specifically, electric field-activated molecular switches that have an electric field induced band gap change that occurs via a molecular conformation change or a tautomerization. Changing of extended conjugation via chemical bonding change to change the band gap is accomplished by providing the molecular system with one rotating portion (rotor) and two or more stationary portions (stators), between which the rotor is attached. The molecular system of the present invention has three branches (first, second, and third branches) with one end of each branch connected to a junction unit to form a “Y” configuration. The first and second branches are on one side of the junction unit and the third branch is on the opposite side of the junction unit. The first branch contains a first stator unit in its backbone, the junction unit comprises a second stator unit, and the first branch further contains a rotor unit in its backbone between the first stator unit and the second stator unit. The second branch includes an insulating supporting group in its backbone for providing a length of the second branch substantially equal to that of the first branch, wherein the rotor unit rotates between two states as a function of an externally-applied field.

Memory element, method for structuring a surface, and storage device

The invention is essentially characterized in that in a first step a substrate is provided, which is coated with defined pattern of protrusions of a coating layer of a different material, so that an interface is defined between the substrate and the coating layer. As an example, the patterned coating layer can be applied by first forming an essentially homogeneous coating layer, which is then partially removed by means of photolithographic and etching techniques, leaving nanometer sized protrusions in that layer. As a next step, the surface provided with these structures is modified by selectively removing protrusions by means of a micro-device. Such a micro-device can be formed in a similar way to a scanning probe microscope (SPM) tip. The presence or absence of a protrusion represents a readable data bit information.

Micromachined electromechanical (MEM) random access memory array and method of making same

A micromachined electromechanical random access memory (MEMRAM) array is disclosed which includes a plurality of MEM memory cells, where each MEM memory cell has an MEM switch and a capacitor. The MEM switch includes a contact portion configured for moving from a first position to a second position for reading out a charge stored within the capacitor or for writing the charge to the capacitor. A method is also disclosed for fabricating each MEM memory cell of the MEMRAM array.

DATA RECORDING DEVICE HAVING INCLINED CARBON NANOTUBES AND METHOD FOR MANUFACTURING THE SAME

Le dispositif d'enregistrement de données comporte un réseau de nanotubes (9) de carbone, formés sur un substrat (10) plan et constituant des micro-pointes coopérant avec un support de mémoire (11) sensiblement plan. Les nanotubes (9) de carbone sont initialement inclinés d'un angle prédéterminé, compris entre 5° et 40°, par rapport au plan du substrat (10). Les nanotubes 9 fléchissent lorsqu'ils viennent en contact avec le support de mémoire (11), parallèle au substrat (10). Le substrat (10) comporte, de préférence, une structure en relief, destinée à servir d'appui aux extrémités libres des nanotubes (9). The data recording device comprises an array of carbon nanotubes (9) formed on a plane substrate (10) and constituting microtips cooperating with a substantially plane memory medium (11). The carbon nanotubes (9) are initially inclined at a predetermined angle, between 5 ° and 40 °, relative to the plane of the substrate (10). The nanotubes 9 flex when they come into contact with the storage medium (11), parallel to the substrate (10). The substrate (10) preferably comprises a relief structure intended to serve as support for the free ends of the nanotubes (9).

Method of using pre-formed nanotubes to make carbon nanotube films, layers, ribbons, elements and articles

Methods of using performed nanotubes to make carbon nanotube films, layers, fabrics, ribbons, elements and articles are disclosed. To make various articles, certain embodiments provide a substrate (12). Performed nanotubes are applied to a surface of the substrate to create a non-woven fabric of carbon nanotubes. Portions of the non-woven fabric (54) are selectively removed according to a defined pattern to create the article. To make a nonfabxic, a substrate is provide. Prefromed nanotubea are applied to a surface of the substrate to create a non-woven fabric of carbon nanotubes wherein the non-woven fabric is substantially uniform density.

Bistable molecular mechanical devices with an appended rotor activated by an electric field for electronic switching, gating and memory applications

In accordance with the present invention, nanometer-scale reversible electronic switches are provided that can be assembled to make cross-bar circuits that provide memory, logic, and communications functions. The electronic switches, or crossed-wire devices, comprise a pair of crossed wires that form a junction where one wire crosses another at an angle other than zero degrees and at least one connector species connecting the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, wherein at least one connector species and the pair of crossed wires forms an electrochemical cell. The connector species comprises a bistable molecule having a general formula given by The bistable molecules evidence high switching speed. Such molecules are essentially stable against switching due to thermal fluctuations.

Isolation structure for deflectable nanotube elements

Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node.

Switch Device and Fabrication Method Thereof

나노 튜브 또는 나노 와이어를 포함하는 나노 구조물을 이용하여 신뢰성 있는 온/오프가 이루어지는 스위치 소자를 제공된다. 스위치 소자는 기판 상의 하부 도전막, 하부 도전막 상의 제1 절연막으로서, 제1 하부 도전막의 적어도 일부를 노출하는 제1 홀을 구비하는 제1 절연막, 제1 절연막의 제1 홀 내벽에 형성된 도전막 스페이서, 및 일단이 하부 도전막과 전기적으로 연결되어 있고, 나노 튜브 또는 나노 와이어를 포함하는 나노 구조물로서, 하부 도전막으로부터 제1 홀을 통과하여 수직하게 연장하되, 도전막 스페이서와 워킹갭을 사이에 두고 이격되어 있는 나노 구조물을 포함한다. Provided is a switch device in which reliable on / off is achieved by using a nanostructure including a nanotube or a nanowire. The switch element is a lower conductive film on a substrate, a first insulating film on a lower conductive film, a first insulating film having a first hole exposing at least a portion of the first lower conductive film, and a conductive film formed on an inner wall of the first hole of the first insulating film. A nanostructure comprising a spacer and one end electrically connected to a lower conductive layer, the nanostructure including a nanotube or a nanowire, extending vertically through a first hole from a lower conductive layer, between the conductive layer spacer and a working gap. It includes nanostructures spaced apart from. 도전막 스페이서, 나노 구조물, 워킹갭, 희생 스페이서 Conductive Film Spacer, Nano Structure, Working Gap, Sacrificial Spacer

Nano-elastic memory device and method of manufacturing the same

A nano-elastic memory device and a method of manufacturing the same. The nano-elastic memory device may include a substrate, a plurality of lower electrodes arranged in parallel on the substrate, a support unit formed of an insulating material to a desired or predetermined thickness on the substrate having cavities that expose the lower electrodes, a nano-elastic body extending perpendicular from a surface of the lower electrodes in the cavities, and a plurality of upper electrodes formed on the support unit and perpendicularly crossing the lower electrodes over the nano-elastic bodies.

Aggregate of Semicnductor micro-needles and method of manufacturing the same, and semiconductor apparatus and method of manufacturing the same

On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).

Receiver circuit using nanotube-based switches and transistors

Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical communication with the input links and the output links. Each switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. First and second MOS transistors are each in electrical communication with a reference signal and with the output node of a corresponding one of the first and second switching elements.

Nanotube-based switching elements with multiple controls and circuits made from same

本发明是关于具有多个控件的基于纳米管的开关元件以及由其制成的电路。开关元件包括一输入节点、一输出节点、以及具有至少一个导电纳米管的纳米管通道元件。一控制结构相对于该纳米管通道放置，以可控地在输入节点及输出节点之间形成与解除一导电通道。该输出节点被构建与安排为使该通道的形成实质上不受输出节点的电气状态的影响。该控制结构包括置于该纳米管通道元件的相对两侧的一个控制电极和一个释放电极。该控制与释放可用来形成一差动输入，或者如果该装置被适当构建，则以非易失性方式操作该电路。该开关元件可被安排在具有差动输入和/或取决于该构建的非易失性行为的逻辑电路和闩锁中。