СПОСОБ ЗАПИСИ И ЗАПИСЫВАЮЩИЙ АППАРАТ ДЛЯ ЗАПОМИНАЮЩЕГО УСТРОЙСТВА

Изобретение относится к вычислительной технике. Технический результат заключается в предотвращении ошибки при записи, вызываемой константной неисправностью в импедансном запоминающем устройстве. Способ записи, предназначенный для запоминающего устройства, в котором получают n численных значений, которые должны быть записаны; определяют n битов, соответствующих этим n численным значениям, которые должны быть записаны, и информацию о константных неисправностях, содержащихся в этих n битах; группируют эти n битов в В групп битов способом группирования путем регулирования интервала между двумя смежными битами в одной и той же группе, так, чтобы В групп битов удовлетворяли группировочному условию, и, в случае, когда эти n битов представляют двухмерный массив, состоящий из В строк и А столбцов, любые два бита, которые принадлежат к одной и той же группе, находились в различных строках и столбцах или в одной и той же строке; и соответственно записывают эти n численных значений в соответствии с ...

Method of testing the memory cell contents of a program memory

A method of testing the memory cell contents of a program memory is proposed. A checksum, which corresponds to the sum of all memory cell contents of the program memory, is stored in a separate memory cell. At the start of computer operation, or during it, a test routine, which adds all the memory cell contents to the existing checksum, can be run. When the total value is reached, it is reduced by the value of the checksum, and the resulting final value is compared for agreement with the value of the checksum. If they do not agree, a fault display is triggered. ...

SYSTEM ZUR OPTIMIERUNG VON SPEICHERREPARATURZEIT MIT PRÜFDATEN

Latch-based memory array

Initial diagnosis of a processor

A device for performing initial diagnosis of processors comprises a processor module (12), a storage unit (20), an address allocation unit (19) and a diagnostic execution unit (18). The processor module (12) has a processor (13) and a cache storage unit (14). The storage unit (20) stores an initial diagnostic setting program which is for performing a diagnosis of the processor (13) and the cache storage unit (14). The address allocation unit (19) allocates the addresses of the processor (13) by making the addresses of the processor correspond to the addresses of the cache storage unit (14) so that the cache storage unit is accessed by the processor. The diagnostic execution unit (18) reads the initial diagnostic setting program stored in the storage unit (20) into the addresses of the cache storage unit (14) allocated by the address allocation unit (19) and executes the initial diagnostic setting program.

Method and device for initial diagnosis of a processor

Data processing system with self-test

A data processing system employing firmware for executing a self test routine each time the system goes through the power-up cycle. The self test firmware provides for compilation of a system configuration map during each execution so that configuration and status data is made available for accessing by the system operation firmware and application software. This enables external systems to set appropriate interrupt vectors and levels and to arrange their physical I/O and device handlers so that various devices within the local system can be accessed. The routines performed in the self test operation include a CPU test, a RAM test, a real time clock test, a communication controller loop-back test, a ROM signature calculation, a controller I/O test, a system configuration map compilation, and a status display routine.

System for optimizing memory repair time using test data

Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration

METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY

A method for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a prior checksum. It is determined whether the first memory block is designated read-only. A current checksum is calculated based at least in part on data within the memory block. When the first memory block is designated read-only, and the prior checksum represents expected data within the first memory block, it is determined whether the current checksum is equal to the prior checksum. When the current checksum is not equal to the prior checksum, a verification failure for the first memory block is indicated via a notification interface. A system for verifying memory device integrity is also disclosed.

BIST MEMORY TEST SYSTEM

A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.

Test method for storage device

MEMORY HAVING A CIRCUIT FOR DETECTING A GLITCH ON A LINE MEMORY

L'invention concerne une mémoire (MEM1) comprenant un circuit de commande (CCT, HC), un plan (MA1) de cellules mémoire (MC), chaque cellule mémoire étant couplée à une ligne de bits (BLn) et à au moins une ligne de mémoire (WLm), et un circuit de détection d'impulsion transitoire (DC) couplé à au moins une ligne de mémoire et configuré pour recevoir un signal de commande d'opération (OP) envoyé par le circuit de commande, le signal de commande d'opération indiquant si une opération est activée ou désactivée pour la ligne de mémoire, et pour fournir un signal de détection d'impulsion transitoire (DET, GLT) lorsqu'un signal sur la ligne de mémoire passe à une première valeur logique lorsque le signal d'opération est désactivé.

Circuit of checking of digital storage elements

MEMORY MODULE AND METHOD FOR TEST IT

SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME

MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY AND METHOD FOR OPERATING NONVOLATILE MEMORY

BOOT-UP CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING SAME

A boot-up control circuit may be provided. The boot-up control circuit may include a fuse array including a plurality of normal fuses and a plurality of dummy fuses; and a fuse array controller configured to determine whether or not to start a normal boot-up operation for the normal fuses according to a comparison result between expected data and test fuse data output from the dummy fuses through a test boot-up operation. According to an embodiment of the present invention, reliability of boot-up operation can be improved. COPYRIGHT KIPO 2018 (101) Memory cell array (102) Fuse array storage circuit (103) Fuse array (104) Dummy fuse (105) Normal fuse (106) Power detection circuit (107) Fuse array controller ...

System that prevents reduction in data retention

One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the resistive memory. The back end manufacturing system prevents temperatures in back end processing from reducing data retention time of the configuration data in the resistive memory.

Automated method of burn-in and endurance testing for embedded EEPROM

An on-chip processor is used as a controller for burn-in and endurance testing of embedded non-volatile memory. An automated test machine downloads a test program into the non-volatile memory. The downloaded program contains a test program to be run on the non-volatile memory. When the burn-in or endurance test equipment activates the processor, the processor executes the program and performs a test on the non-volatile memory. The same method can be utilized to perform either the burn-in or endurance tests. Only the clock and reset lines are required to operate the test. Since the clock and reset lines are part of the processor's standard inputs, the method performs burn-in and endurance testing of an embedded non-volatile memory without bringing out the memory's address, data and control lines to the package pins of the integrated circuit. Since the clock and reset lines are part of the standard burn-in and endurance test equipment, the method also performs the testing without the use ...

Manufacturing testing for LDPC codes

An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

APPARATUS, METHODS, AND SYSTEM OF NAND DEFECT MANAGEMENT

Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.

Stacked semiconductor module

The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

NON-VOLATILE-MEMORY (NVM) CONTENTS READ RETURN VALIDATION

A boot read only memory (ROM) chip unit can perform a secure boot routine based on various operations. A processor device comprises a boot ROM chip with processing circuitry on a system board configured to perform a system board power up according to a read operation in a one-time-programmable OTP memory/non-volatile memory (NVM). The OTP memory/NVM includes a spare area in a portion of the OTP/NVM that can receive a first sequence pattern. The processor determines whether a secure boot indication indicates a secure boot routine, and differentiates one or more read return content of the OTP memory/NVM between a wrongly read return content and a trusted read return content, in response to, or concurrent with, the secure boot indication indicating the secure boot routine.

Non-volatile memory device, operating method thereof, and storage device including the non-volatile memory device

A memory device includes multiple word lines. A method of operating the memory device includes: performing a first dummy read operation, with respect to first memory cells connected to a first word line among the word lines, by applying a dummy read voltage, having an offset level of a first level, to the first word line; determining, based on a result of the performing of the first dummy read operation, degradation of a threshold voltage distribution of the first memory cells; adjusting an offset level of the dummy read voltage as a second level, based on a result of the determining of the threshold voltage distribution; and performing a second dummy read operation with respect to second memory cells connected to a second word line among the word lines, by applying a dummy read voltage, having the offset level adjusted as the second level, to the second word line among the word lines.

Programmable read-only memory device provided with test cells

A programmable read-only memory device of a junction destruction type is provided with a test circuit for the purpose of detecting a parasitic thyristor effect which may occur in the data programming operation by the user. The test circuit includes first and second additional row lines, a first diode connected between the first additional row line and one column line, a second diode connected between the second additional row line and another column line adjacent to the one column line, and a transistor of a base-open type connected between the second additional row line and the one column line.

Method for controlling read-out or write in of semiconductor memory device and apparatus for the same

A method for controlling the read-out or write-in of a semiconductor memory device, and an apparatus for the same, comprising, in the selection of memory cells in the memory cell array to read out or write in data, the steps of selecting the memory cells of a specific address in the memory cell array, accessing the memory cells of the specific address, and then and only then accessing the memory cells of the designated address corresponding to address signals input from the outside.

СПОСОБ УПРАВЛЕНИЯ ТЕХНИЧЕСКИМ РЕСУРСОМ ЭНЕРГОНЕЗАВИСИМОЙ ПАМЯТИ

... 1. Способ управления техническим ресурсом системы хранения данных, содержащей набор секторов, обладающих собственным гарантированным техническим ресурсом (G), содержащий следующие этапы:- разбивают упомянутую систему хранения данных на ряд рабочих секторов и ряд резервных секторов, способных сформировать резерв технического ресурса, причем определенные рабочие сектора подлежат замещению резервными секторами в случае износа упомянутых рабочих секторов после определенного количества циклов программирования и/или стирания;- задают зону управления адресами для определения расположения резервных секторов, назначаемых на замещение изношенных рабочих секторов;- определяют, сектор за сектором, изношен ли текущий сектор физически и замещают данный рабочий сектор резервным сектором, только если текущий сектор признан физически изношенным;отличающийся тем, что для оценки износа сектора производят автоматическое считывание качества стирания точек памяти упомянутого сектора и сравнивают с пограничным ...

Techniken zum Speichern von Bits in Speicherzellen mit Hängenbleiben-auf-0-oder-1-Fehlern

Ein Datenspeichersystem enthält eine Speicherschaltung, die Speicherzellen umfasst, und eine Steuerschaltung. Die Steuerschaltung erzeugt in Ansprechen auf eine erste Schreiboperation einen ersten Satz redundanter Bits, die die Bitpositionen der Speicherzellen, die Hängenbleiben-auf-0-oder-1-Fehler aufweisen, angeben, falls eine erste Rate der Hängenbleiben-auf-0-oder-1-Fehler in den Speicherzellen größer als ein erster Schwellenwert ist. Die Steuerschaltung ist betreibbar, um in Ansprechen auf eine zweite Schreiboperation die Datenbits zu codieren, um codierte Datenbits und einen zweiten Satz redundanter Bits, die eine Transformation, die an den Datenbits ausgeführt wird, um die codierten Datenbits zu erzeugen, angeben, zu erzeugen, falls eine zweite Rate der Hängenbleiben-auf-0-oder-1-Fehler in den Speicherzellen größer als ein zweiter Schwellenwert ist. Die codierten Datenbits, die in den Speicherzellen gespeichert sind, die Hängenbleiben-auf-0-oder-1-Fehler aufweisen, entsprechen den ...

Latch-based memory array

System and method for testing a computer memory by copying the data from a portion to be tested into a secondary memory whilst the memory is tested

Disclosed is a method for testing the memory of a computer system whilst the computer is running. The method comprises the steps of copying the data in a portion of the memory into a second memory as a cache. The portion of the memory is then tested. After the test is completed and any bad sectors repaired, the data is copied back into the tested portion. The method is then repeated on the next portion of the memory. The system is implemented on a computer system by a memory controller which comprises a cache and a cache controller. The cache controller copies the data from the area to be tested into the cache and readdresses any data requests from a system processor for data from the area being tested to the cache, such that the testing is invisible to the processor. The cache controller may make the data in the area being tested not available to be read. The controller may write data in the cache memory when write requests to the area under test are received during the testing. The system ...

INTEGRITATSSTEUERUNG FUR IN A NICHTFLUCHTIGEN MEMORY STORED DATA

DATA PROCESSING SYSTEM WITH SELF TESTING AND CONFIGURATION MAPPING CAPABILITY

A data processing system employing firmware for executing a self test routine each time the system goes through the power-up cycle. The self test firmware provides for compilation of a system configuration map during each execution so that configuration and status data is made available for accessing by the system operation firmware and application software. This enables external systems to set appropriate interrupt vectors and levels and to arrange their physical I/O and device handlers so that various devices within the local system can be accessed. The routines performed in the self test operation include a CPU test, a RAM test, a real time clock test, a communication controller loop-back test, a ROM signature calculation, a controller I/O test, a system configuration map compilation, and a status display routine.

Monitor burn-in test device and monitor burn-in test method

The invention provides a monitor burn-in test device and a monitor burn-in test method. In a monitor burn-in test device (11), data is written all at once into a plurality of elements (16) requiring a refresh process. The refresh process is performed in the elements (16) after the write process. The data is held. When performing a read-out process, the refresh process is interrupted in the element (16) from which read-out is to be performed. Data is read out from the interrupted element (16). Thus, the refresh process is interrupted only in the element (16) from which read-out is to be performed. Accordingly, the refresh process can be continued in the element (16) other than the element from which read-out is to be performed. Thus, the data is surely held. The data write-in process may be completed at once. Thus, the monitor burn-in test can be effectively performed.

Integrity control for data stored in a non-volatile memory

NON VOLATILE MEMORY EVALUATING METHOD AND NON VOLATILE MEMORY

MEMORY MODULE AND TEST METHOD THEREOF, ESPECIALLY FOR PREVENTING DELAY OF TEST TIME DUE TO EXCESSIVE NUMBERS OF TESTS

PURPOSE: A memory module and a test method thereof are provided to efficiently select a DQ group in on-the-fly method by using an external output group selection signal, during a test using a transparent mode. CONSTITUTION: A memory module(1000) includes a plurality of memories(200) and a hub(100). The hub applies a test signal applied from the outside through N input channels to the memories, and divides plural output data outputted from the memories into M groups in response to the applied test signal and then outputs at least one of the M groups through K output channels according to an output group selection signal inputted from the outside. © KIPO 2007 ...

DATA VERIFICATION DEVICE

SELECTIVE ERROR CORRECTING CODE AND MEMORY ACCESS GRANULARITY SWITCHING

Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.

Reference selection circuit

A reference selection circuit may be provided. The reference selection circuit may include a plurality of reference drivers configured to respectively output a plurality of reference voltages having different voltage levels, and a plurality of selectors configured to select any one of the plurality of reference voltages based on a selection signal, and output the selected reference voltage to a monitoring pad.

Block management scheme to handle cluster failures in non-volatile memory

In a non-volatile memory system, such as flash memory, when selecting a block for write operation, the system selects blocks from a free block list (FBL). The memory circuits of non-volatile systems often experience cluster failures, where multiple blocks of a physical region are bad. If the free block list is loaded with blocks from a region having a cluster failure, this can result in multiple back to back write errors. To help avoid this situation, the blocks of a memory array are divided into physical zones and, when selecting blocks to replenish the free block list, blocks are chosen cyclically from the zones.

TESTING OF NON-VOLATILE MEMORY ARRAYS

A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for Vtesting for reading at least some memory cells. A second test stage including at least one second stage read uses an adjusted step size less in magnitude than the first step size for reading at least some memory cells. Provided no bit pattern match by the second test stage and/or the adjusted step size does not meet a predetermined minimum resolution (PMR), one or more additional test stages including additional array searching are added using a fixed step size less in magnitude than the adjusted step size including at least one read until a final read determines the predetermined bit pattern is matched and a fixed step size for the final read meets the PMR. 1. A method of testing a non-volatile memory array including a plurality of memory cells , comprising:initializing said plurality of memory cells to a predetermined bit pattern, and{'sub': 'T', 'claim-text': [{'sub': 'T', 'performing a first test stage including first array searching including at least one first stage read using a first step size for setting reference current for said BCC testing and/or voltage for said Vtesting for reading at least some of the plurality of memory cells;'}, {'sub': 'T', 'performing a second test stage including second array searching including at least one second stage read using an adjusted step size that is less in magnitude than (<) said first step size for setting reference current for said BCC testing and/or voltage for said Vtesting for reading at least some of the plurality of memory cells, and'}, {'sub': 'T', 'provided said predetermined bit pattern is not matched by said second test stage and/or said adjusted step size does not meet a predetermined minimum resolution (PMR), adding one or more additional test stages including additional array searching using a fixed step size less in ...

Method of storing data in nonvolatile memory device and method of testing nonvolatile memory device

A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence of determining that the target memory cells are in the program pass state, performing a second verify operation to determine whether the target memory cells exhibit a program error symptom.

Semiconductor device and its quality management method

A semiconductor device capable of easily and properly detecting a defective element unit(s) and a quality management method for the semiconductor device are suggested. A semiconducting device simulating interactions between nodes in an interaction model is equipped with a quality management unit for managing the quality of each element unit provided corresponding to each node, wherein the quality management unit executes a specified quality test of each element unit, compares test results of the quality test with pre-given results to be obtained from the quality test, and detects a defective memory cell(s) and a defective element unit(s) based on the comparison results.

System and method for testing a memory

A computer system comprising a processor, a memory, and a memory controller coupled to the processor and the memory is provided. The memory controller comprises a first cache and a cache control. The cache control is configured to cause a portion of the memory to be copied into the first cache. The cache control is configured to cause first information to be provided from the first cache to the processor in response to receiving a read transaction from the processor that includes an address in the portion of memory during testing of the portion.

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes: an output timing test unit configured to edge-trigger a pad output data applied from an input/output pad at a first timing and output the edge-triggered pad output data as output timing test data, during an output timing test mode, and a test output unit configured to receive the output timing test data and output the received output timing test data to a probe pad.

Methods and apparatus for testing and repairing digital memory circuits

An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.

Semiconductor chip and stack type semiconductor apparatus using the same

A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may include a through via configured for signal transfer with another semiconductor chip. The semiconductor may include an internal information processing circuit configured to transmit internal information selected from the internal information to the through via, or may be configured to output internal information of the other semiconductor chip, which has been transmitted through the through via, to an exterior through a special purpose pin, in response to test signals.

Method of generating a curve to determine an optimal operation of a wafer

The fail bit count data, shmoo data, static noise margins and write margins corresponding to a wafer are measured. Using the above mentioned measurements, variables used to generate the curve are calculated. The variables used to generate the curve include the standard deviation of the fail bit count data, the static noise margins and the write margins. The curve is used to determine optimal operating condition of a fabrication process.

Systems and methods for testing memories

A system for testing a plurality of memories includes a plurality of memory testing devices and a controller. Each of the memory testing devices is coupled to one of the memories. The controller is configured to generate a test vector and send the test vector to the memory testing devices. Each of the memory testing devices tests its coupled memory respectively according to the test vector and sends a test result to the controller.

Check method of temporary storage circuit in electronic control unit

Data in RAM 4 indicated by the top address is read, the read contents are written into the next address, and the operation is repeated to the end address, then the RAM value at the end address is compared with the RAM value at the top address only once and if the RAM values are the same, all the RAM is determined to be normal. The data comparison processing may be only one comparison with the end address data. ROM 201 is checked in a distributed manner in the wait time of main processing Mn rather than checked in initial processing In.

SEMICONDUCTOR STORAGE DEVICE

PURPOSE: To attain a test similar to actual operating state by connecting at least one column selecting line for a test bit to each output terminal in a ROM. CONSTITUTION: At least one column selecting line for a test bit is connected to each output terminal of output circuits 2-1W2-m to which plural column selecting lines 4 in a memory cell array 1 such as a ROM are inputted. Test data are written in memory cells at the intersected points between the column selecting lines 4 and row selecting lines 3. Consequently, the noise state or the like of the power supply lines or ground lines which are generated by switching current from the output circuits be tested at the state similar to the actual operating state by reading out said test data. COPYRIGHT: (C)1985,JPO&Japio ...

ALTERNATE MEMORY CHECK SYSTEM

PURPOSE: To check the alternate operation and alternate memory at a storage device having alternate memory effectively, by inverting control of write-in data for an arbitrary information bit. CONSTITUTION: A write-in information inverting circuit 15 is provided between a write-in information bus 1 and a normal memory 2, and connected to a write-in information inverting bit location storage register 17 with a write-in information inverting control line 18. The control of an alternate memory 7 is made by storing the alternate bit location information to an alternate memory bit location storage register 9 via a control line 20 externally, the write-in information inverting bit location information of the register 17 is given to a circuit 15 with a control line 18 to invert the information of the corresponding write-in information bits. Thus, the inverting control of an arbitrary write-in information bit can be made. COPYRIGHT: (C)1982,JPO&Japio ...

ERROR CHECKING METHOD OF RAM

PURPOSE: To decide easily and accurately an error of totalization of charges, etc., by detecting a change of an error checking specific pattern which is stored in an RAM. CONSTITUTION: An error checking specific pattern is written to a specific region 2 close to a region 3 where the data on charges, etc. of an RAM1 are preserved in response to the storage contents of the region 3. This specific pattern is compared with the same specific pattern stored in an ROM. If no coincidence is obtained from this comparison, it is decided that the storage contents of the RAM1 are changed. In such a case, the storage contents of another similar RAM1 for redundancy which have no change are used. Thus it is possible to decide easily and quickly an error of totalization of charges, etc. At the same time, the reliability is improved for the result of totalization, etc. COPYRIGHT: (C)1984,JPO&Japio ...

СПОСОБ УПРАВЛЕНИЯ ТЕХНИЧЕСКИМ РЕСУРСОМ ЭНЕРГОНЕЗАВИСИМОЙ ПАМЯТИ

Изобретение относится к вычислительной технике. Технический результат заключается в увеличении общего технического ресурса памяти. Способ управления техническим ресурсом системы хранения данных, в котором разбивают систему хранения данных на ряд рабочих секторов и ряд резервных секторов, способных сформировать резерв технического ресурса, причем определенные рабочие сектора подлежат замещению резервными секторами в случае износа упомянутых рабочих секторов после определенного количества циклов программирования и/или стирания; задают зону управления резервными секторами для определения расположения резервных секторов, назначаемых на замещение изношенных рабочих секторов; определяют, сектор за сектором, изношен ли текущий рабочий сектор физически и замещают данный рабочий сектор резервным сектором, только если текущий рабочий сектор признан физически изношенным; причем для оценки износа сектора производят автоматическое считывание качества стирания точек памяти упомянутого сектора и сравнивают ...

Nichtflüchtiges Speicherbauelement, Löschverfahren und Löschtestverfahren

Die Erfindung bezieht sich auf ein Löschverfahren, das ein Löschen von ausgewählten Speicherzellen eines nichtflüchtigen Speicherbauelements umfasst, auf ein korrespondierendes Löschtestverfahren und auf ein nichtflüchtiges Speicherbauelement, in welchem diese Verfahren verwendet werden können. Erfindungsgemäß umfasst das Löschverfahren eine Löschverifikation der gelöschten ausgewählten Speicherzellen unter Verwendung einer Vorspannungsbedingung, welche eine Schwellwertspannung der ausgewählten Speicherzellen erhöht. Verwendung z.B. in Flashspeichern.

DATA PROCESSING SYSTEM WITH SELF-TEST

PARALLEL EXAMINATION OF A CCU CACHE AS WELL AS COMMAND UNIT

TEST CELLS FOR AN UNPROGRAMMED OTP MEMORY ARRAY

Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells are fabricated at the same time as the normal OTP cells, except they are smaller in size along one dimension in order to detect mask misalignment along that dimension. Any fabricated test cell which cannot be programmed indicates a level of fabrication mask misalignment has occurred and the OTP memory array should not be used.

MEMORY ORGANIZATION FOR SECURITY AND RELIABILITY

Safety enhancement for memory controllers

A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured towrite the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memoryat the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of thememory based upon the comparison.

MEMORY HAVING A CIRCUIT FOR DETECTING A GLITCH ON A MEMORY LINE

MEMORY ARRAY LATCH-BASED

METHODS AND APPARATUSES USING A TRANSFER FUNCTION TO PREDICT RESISTANCE SHIFTS AND/OR NOISE OF RESISTANCE-BASED MEMORY

CACHE MEMORY CHECKING METHOD OF MULTIPROCESSING SYSTEM

PURPOSE: The cache memory checking method of a multiprocessing system is provided to check the cache memory in the more effective and multiple way. CONSTITUTION: The cache memory checking method of a multiprocessing system comprises the steps of: dividing the cache memory into the test area(400) for checking the cache memory, and into the code area(410) in which the cache memory checking program is placed; arranging the checking program, saved in a shared memory, for responding to the checking program area of the cache memory; running and saving the checking program in the code area of the cache memory after reading the checking program of the shared memory. COPYRIGHT 2001 KIPO ...

반도체 칩 및 이를 이용한 적층형 반도체 장치

... 본 기술은 데이터 저장/출력 또는 내부 정보들의 출력이 가능하도록 구성된 코어 블록; 다른 반도체 칩과의 신호 전달을 위해 구성된 관통 비아; 및 테스트 신호들에 응답하여 상기 내부 정보들 중에서 선택된 내부 정보를 상기 관통 비아로 전송하거나, 상기 관통 비아를 통해 전송된 상기 다른 반도체 칩의 내부 정보를 특수 목적 핀을 통해 외부로 출력하도록 구성된 내부 정보 처리 회로를 포함할 수 있다.

Memory test method, information recording medium and semiconductor integrated circuit

The purpose of the present invention is to provide a kind of method capable of testing on-chip memory with excellent efficiency. The invented method for testing memory of semiconductor integrated circuit (IC) is provided with the followings: CPU (102), which has command queue; memories (107, 108); and bus (105) for connecting CPU and memory. The test program is stored in the command queue, and the test program is executed in the CPU to access the memory through the bus. After the test program is stored in the command queue, once the test program is fetched, it is conducted repeatedly from the command queue but not from the bus. Since the same test program can be repeatedly executed by using the loop queue action of the command queue, no branching command is required. Only the test program, which is repeatedly executed, is repeatedly fetched from the command queue; and the memory read/write access for testing memory and the memory access for fetching the command do not compete on the bus ...

SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST METHOD, AND MEDIUM

Memory, memory system including the same and method for operating memory

A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines.

TEST CELLS FOR AN UNPROGRAMMED OTP MEMORY ARRAY

Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells are fabricated at the same time as the normal OTP cells, except they are smaller in size along one dimension in order to detect mask misalignment along that dimension. Any fabricated test cell which cannot be programmed indicates a level of fabrication mask misalignment has occurred and the OTP memory array should not be used.

BIST memory test system

A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a selected cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition, the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.

Driver level diagnostics

An apparatus and method are disclosed for testing memory and display adapter components of a multi-tasking computer system. The apparatus obtains a memory block and sends a request to a memory virtual device driver (VxD) to reserve, commit and lock the memory block to a physical memory. In requesting the memory block, the apparatus computes the number of virtual memory pages spanned by the request, reserves the pages of virtual memory, commits the virtual memory to a physical memory, and locks the virtual memory to the physical memory. The apparatus then obtains a physical address for the physical memory and returns the physical address for testing. Next, the apparatus tests the memory block using a number of memory test procedures. After the testing completes, the apparatus decommits and unlocks the physical memory before it traverses to the next entry of the chain. This process is repeated until all entries in the virtual memory chain have been tested. The apparatus also tests the video ...

Integrated circuit devices with mode-selective external signal routing capabilities and methods of operation therefor

An integrated circuit device includes a package and an externally accessible signal lead attached to the package. An integrated circuit chip is mounted in the package and connected to the signal lead. The integrated circuit chip includes a mode-selective signal generating circuit configured to receive a mode control signal and an internal signal and coupled to the externally accessible signal lead. The mode-selective signal generating circuit is operative to produce an output signal responsive to one of the internal signal or an external signal applied to the externally accessible signal lead based on the mode control signal. According to an embodiment, the integrated circuit chip further includes a memory circuit including a sense amplifier that senses a bit line voltage in response to a sense enable signal. The internal signal includes a sense enable control signal having a timing adapted for sensing a bit line voltage in a memory cycle of the memory circuit. The mode-selective signal ...

Method and apparatus for testing memory cells for data retention faults

A method for testing memory cells for data retention faults is disclosed. A first logical value is stored in a first cell, and a second logical value is stored in a second cell of a memory device. The second cell shares the same column with the first cell. The bitlines associated with the first and second cells are prevented from being precharged before the second cell can be read. After the second cell has been read repeatedly, the first cell is read, and the bitlines associated with the first and second cells are precharged. At this point, a data retention fault is determined to have occurred if the first cell does not contain the first logical value.

Buffer memory self-diagnosis method for information signal processing apparatus

In an information processing device such as an optical disc device which is used as an external memory unit of a computer, the increasing of the initial access time can be effectively avoided nevertheless the capacity of the buffer memory is bulked up. Only the partial region of the buffer memory is self-diagnosed and then recording and reproducing of the data is started so as to self-diagnose the residual region in the back ground.

ERROR CORRECTION FOR NON-VOLATILE MEMORY

Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Selective Online Burn-In with Adaptive and Delayed Verification Methods for Memory

A memory is released for use without pre-verification of its memory blocks as being defect free. Some memory blocks are subjected to a verification process when the computer memory is in use in order to verify a minimum number of memory blocks required for high performance program operation as being defect free. The verification process continues as the computer memory is in use in order to maintain the minimum number of memory blocks required for high performance operation in the verified defect free state. A verification mode of either no verification, delayed verification, or immediate verification is applied to memory blocks used for regular performance program operation. Delayed verification is maintained until an ability to recover the stored data is going to be lost. Immediate verification can be performed using bit error rate analysis. Some verification processes are performed using aggressive programming trim and/or multiple word line sensing for faster programming.

System for optimizing anti-fuse repair time using fuse id

A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

Integrated solution for identifying malfunctioning components within memory devices

A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.

TESTING MEMORY DEVICES WITH PARALLEL PROCESSING OPERATIONS

An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Method of testing a memory module and hub of the memory module

Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

Semiconductor apparatus

A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.

Semiconductor memory device

A semiconductor memory device comprises a memory cell group (32), a word line group (WLOm, WLn) connected to the memory cell group, a bit line group (BLn) connected to the memory cell group, and a drive circuit (12, 13, 20, 21, 31) connected to the word line group and capable of, in a test mode, selectively driving all word lines or arbitrary word lines whose number is more than that of word lines driven in a normal operation mode.

READ/WRITE MEMORY CIRCUIT

PURPOSE: To obtain a memory circuit where the diagnosis of access to all addresses and all words is possible, by providing an address switching circuit which uses a write address as a read address during the diagnosis, a data switching circuit which switches data on a shift path to normal input data, and a write controlling circuit which writes an inverted value of input data. CONSTITUTION: A memory circuit 1 is provided with a one-bit fourword read/ write memory circuit 2, a data switching circuit 3 which switches the shift path and the normal path by a shift signal to output data, a read address switching circuit 4 which switches a stored write address and a normal read address to output one of them by a diagnostic signal, and a write controlling circuit 5 which writes the inverted value of input data in words other than the word indicated by the write address or writes input data only in the word indicated by the write address in accordance with the diagnostic signal. Therefore, the ...

INFORMATION INSPECTING DEVICE OF NONVOLATILE STORAGE CIRCUIT

PURPOSE: To simplify the hardware and increase the controllability of an inspection, by carrying out the inspection of information with every desired block but with every unit information. CONSTITUTION: The value obtined by subtracting the value obtained by adding all pieces of information of an information part 1 of a nonvolatile storage circuit from the specifice information of "all 0", "all 1", etc. is set at a switch information part 21. All pieces of information of the part 1 are successively supplied to an arithmetic control circuit 3 via a data bus 7 and by the signals of an address bus 5 and a control bus 6 which are supplied from the circuit 3, and thus added together. After this, the information of the part 21 is supplied to the circuit 3 via the bus 7, and the switch information is added to the added data. If all added data are used as the specific information, it is decided that the information of the part 1 is correctly stored. If not, it is known that an error is caused to ...

Techniken zum Speichern von Bits in Speicherzellen mit Hängenbleiben-auf-0-oder-1-Fehlern

Datenspeichersystem, das Folgendes umfasst:eine Speicherschaltung, die Speicherzellen umfasst; undeine Steuerschaltung, die betreibbar ist, in Ansprechen auf eine erste Schreiboperation einen ersten Satz redundanter Bits zu erzeugen, die die Bitpositionen der Speicherzellen angeben, die Hängenbleiben-auf-0-oder-1-Fehler aufweisen, falls eine erste Rate der Hängenbleiben-auf-0-oder-1-Fehler in den Speicherzellen größer als ein erster Schwellenwert ist, wobei während der ersten Schreiboperation erste Datenbits in den Speicherzellen gespeichert werden,wobei die Steuerschaltung betreibbar ist, in Ansprechen auf eine zweite Schreiboperation zweite Datenbits zu codieren, um erste codierte Datenbits und einen zweiten Satz redundanter Bits zu erzeugen, die eine an den zweiten Datenbits ausgeführte Transformation, um die ersten codierten Datenbits zu erzeugen, angeben, falls eine zweite Rate der Hängenbleiben-auf-0-oder-1-Fehler in den Speicherzellen größer als ein zweiter Schwellenwert ist, wobei ...

Techniques for storing bits in memory cells havingstuck-at faults

System and method for testing a memory using DMA

A computer system 100 comprising one or more processors 110, a first bus 152 coupled to the processors, a memory controller 122 coupled to the first bus, a memory 130 coupled to the memory controller, a first input/output (I/O) controller 124 coupled to the first bus, and a test module 128 coupled to the first I/O controller is provided. The test module is configured to causes tests to be performed on the memory using the first bus. The tests comprise Direct Memory Access (DMA) transactions, e.g. read and write transactions, sent via the I/O controller.

SYSTEM AND PROCEDURE FOR EXAMINING A DATA MEMORY MECHANISM WITHOUT EXPOSURE OF MEMORY CONTENTS

MODULE COMPATIBILITY EXAMINATION

PROCEDURE FOR TESTING THE BUFFER MEMORY OF A MICROPROCESSOR SYSTEM

Control apparatus for testing a random access memory

Semiconductor memory device and its test method

A magnetic random access memory circuit

SEMICONDUCTOR MEMORY DEVICE

METHOD FOR TESTING MEMORY MODULE HAVING HUB WITH LOW SPEED TESTER AND HUB OF MEMORY MODULE FOR PERFORMING THE SAME

PURPOSE: A method for testing a memory module having a hub with a low speed tester and the hub of the memory module for performing the same are provided to solve shortage of the number of memory module taps by doubling/comparing/reading data in the hub of the memory module for a test of a transparent mode and expand a test coverage by enabling the tester to input/output diverse test pattern from memories. CONSTITUTION: A transparent mode switch(310) receives an input signal, and switches a normal mode or the transparent mode according to a transparent mode enable signal. In case that the transparent mode switch is the normal mode, a signal process(320) processes an output signal of the transparent mode switch. In the case that the transparent mode switch is the transfer mode, a data transferring/comparing part(330) receives a data signal from the transfer mode switch and determines a failure of the memory by using the received signal. © KIPO 2006 ...

Programmable logic circuit using three-dimensional stacking techniques

A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.

Detecting random telegraph noise induced failures in an electronic memory

A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

Testing memory subsystem connectivity

In one implementation, a memory subsystem includes a plurality of non-volatile memory dies, a memory controller that is communicatively connected to each of the non-volatile memory dies over one or more first busses, a host interface through which the memory controller communicates with a host over a second bus, and a joint test action group (JTAG) interface through which the host performs a boundary scan of the memory subsystem including, at least, the non-volatile memory dies and the memory controller. The memory subsystem can be configured to be a subunit of a board-level memory device that includes the host.

Flash memory storage device and method of judging problem storage regions thereof

A method of judging problem storage regions adapted for a flash memory storage device includes steps of: sending a writing order to a flash memory chip for writing a written data to an appointed storage paging; when the flash memory chip beginning writing the written data to the appointed storage paging, getting the first time; when the flash memory chip finishing writing the written data to the appointed storage paging, getting the second time; calculating a writing time according to the first time and the second time; if the writing time not coincident with a standard value, then labeling the appointed storage paging as a problem storage region and copying the written data to a backup paging; updating a Mapping Table.

Integrated solution for identifying malfunctioning components within memory devices

A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.

FAST PARALLEL TEST OF SRAM ARRAYS

Systems and methods for performing parallel test operations on Static Random Access Memory (SRAM) cells are disclosed. In general, each parallel test operation is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group. 1. A method of testing a plurality of Static Random Access Memory (SRAM) cells , comprising:performing one or more parallel test operations on the plurality of SRAM cells, wherein each parallel test operation of the one or more parallel test operations is a test operation performed on a block of the plurality of SRAM cells.2. The method of wherein the plurality of SRAM cells are arranged into a plurality of rows and a plurality of columns claim 1 , and claim 1 , for each parallel test operation of the one or more parallel test operations claim 1 , the block of the plurality of SRAM cells for the parallel test operation includes SRAM cells from the plurality of SRAM cells in two or more of the plurality of rows.3. The method of wherein the plurality of SRAM cells are arranged into a plurality of rows and a plurality of columns and the plurality of columns are further arranged into one or more column groups claim 1 , and claim 1 , for each parallel test operation of the one or more parallel test operations claim 1 , the block of the plurality of SRAM cells for the parallel test operation includes SRAM cells from the plurality of SRAM cells in two or more of the plurality of columns in a same one of the one or more column groups.4. The method of wherein the plurality of SRAM cells are arranged into a ...

Apparatuses and methods for operating a memory device

Subject matter described pertains to apparatuses and methods for operating a memory device.

Solid-State Disk Manufacturing Self Test

A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or while coupled to a rack unable to load the tests but enabled to provide power to the SSDs. The rack is optionally cost-reduced to enable cost-efficient parallel testing of relatively larger numbers of SSDs for production. The host writes the tests to an ‘input’ SMART log of each SSD, and each SSD writes results to a respective included ‘output’ SMART log. The commands include write drive, erase drive, SATA PHY burn-in, delay, and stress mode. The SSD MST capability is optionally used in conjunction with an SSD virtual manufacturing model. 1. A method comprising:receiving one or more commands from a host, via a storage interface of a storage device coupled to the host, the commands being directed by the host to be stored in storage space of the storage device that is otherwise dedicated to storage of log information produced by the storage device;receiving an indicator to begin execution of the commands in response to an event; andexecuting the commands in response to the event.2. The method of claim 1 , further comprising.providing a cryptographic key to a business to enable the business to decrypt firmware as one or more images from an encrypted firmware repository, the images being executable by processing elements of a storage device controller included in the storage device, the images enabling execution of the commands, the storage device being constructed in accordance with a storage device reference design;providing access to the encrypted firmware repository to the business;wherein the commands comprise a manufacturing self test of the storage device; andwherein the storage device comprises components selected from a list of components, the list being components that ...

APPARATUS, METHODS, AND SYSTEM OF NAND DEFECT MANAGEMENT

Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address. 1. A method comprising:determining whether each of a plurality of memory blocks is defective, wherein the plurality of memory blocks are from different memory block groups, and wherein one of the memory block groups comprises a base memory block group;if the plurality of memory blocks are determined to be non-defective, forming a grouping of memory blocks that includes the plurality of memory blocks; andif at least one of the plurality of memory blocks other than the memory block from the base memory block group is determined to be defective and the memory block from the base memory block group is determined to be non-defective, determining whether there is at least one non-defective memory block in the memory block group that includes the defective memory block and that is not included in another grouping of memory blocks and, if there is at least one non-defective memory block in the memory block group that includes the defective memory block and that is not included in another grouping of memory blocks, forming a remapped grouping of memory blocks that includes the non-defective memory block from the base memory block group and the at least one non-defective memory block in the memory block group that includes the defective memory block and that is not included in another grouping of memory blocks.2. The method of claim 1 , wherein the plurality of memory blocks comprises a plurality of erase blocks.3. The method of claim 2 , wherein the plurality of erase blocks have a same matching unique erase block ...

Code checking method for a memory of a printed circuit board

The present invention discloses a code checking method for a memory of a printed circuit board, which is to firstly add a check code to a data end of codes, after the codes is written in a memory, then use a timing controller to calculate a checksum of the data of the part of the primary codes and further compare the calculated checksum with the check code, and then output to a probe via a testing pin to display the result of comparison, so as to accomplish an object of checking if the written codes are correct. The present invention enhances work efficiency of checking the codes written in the memory.

STORAGE-MEDIUM DIAGNOSIS DEVICE, STORAGE-MEDIUM DIAGNOSIS METHOD

A storage-medium diagnosis includes a storage unit that stores therein respective diagnosis results of subregions of a storage region of a storage medium; a higher-access executing unit that accesses a region corresponding to access request from a higher-level device, and stores a result of the access as a diagnosis result in the storage unit; a diagnosis-region identifying unit that identifies a diagnosis region to be diagnosed next on the basis of the respective diagnosis results of the subregions stored in the storage unit; and a diagnosis executing unit that accesses and diagnoses the diagnosis region identified by the diagnosis-region identifying unit, and stores a result of the diagnosis in the storage unit. The storage-medium diagnosis can reduce the time used for diagnosis of the storage medium and suppress degradation in performance even during operation. 1. A storage-medium diagnosis device comprising:a storage unit that stores therein respective diagnosis results of subregions of a storage region of a storage medium;a higher-access executing unit that accesses a region corresponding to access request from a higher-level device, and stores a result of the access as a diagnosis result in the storage unit;a diagnosis-region identifying unit that identifies a diagnosis region to be diagnosed next on the basis of the respective diagnosis results of the subregions stored in the storage unit; anda diagnosis executing unit that accesses and diagnoses the diagnosis region identified by the diagnosis-region identifying unit, and stores a result of the diagnosis in the storage unit.2. The storage-medium diagnosis device according to claim 1 , whereinthe higher-access executing unit includes an access-operation determining unit that determines an access operation relating to the access request on the basis of a travel distance of a header from a location of access executed immediately preceding the access request to an access location of the access request, andthe ...

Electronic device and method for testing endurance of memory

An electronic device for endurance test of a memory includes an interface, a storage unit, an obtaining unit, and a control unit. The interface is for connecting the memory to the electronic device. The storage unit stores a variety of test packages for different storage capacities of memories and at least one test option associated with each test package. The test option defines a predetermined capacity of the associated memory to be tested. The obtaining unit obtains a storage capacity of the memory connected to the electronic device. The control unit selects one of the at least one test option associated with one of the test packages corresponding to the obtained storage capacity, selects a plurality of blocks according to the predetermined capacity of the selected test option, assigns corresponding logical addresses to the selected blocks, and then tests the endurance of the selected blocks.

DEVICE

A device includes memory banks, each having a plurality of memory cells with respective error data output circuits. Each of the error data output circuits outputs first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank. A test control circuit has first error data synthesis circuits and second to (M+1)-th error data synthesis circuits, each of which synthesizes the first to M-th error data from a corresponding error data output circuit and outputs the synthesized data as first test data. Each of the error data synthesis circuits synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data. 1. A device comprising:a plurality of memory banks each having a plurality of memory cells;a plurality of error data output circuits provided in correspondence with the respective memory banks, each of the error data output circuits outputting first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank; anda test control circuit having a plurality of first error data synthesis circuits each of which synthesizes the first to M-th error data from the corresponding one of the error data output circuits and outputs the synthesized data as first test data, and second to (M+1)-th error data synthesis circuits each of which synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data.2. The device according to claim 1 , wherein:M is equal to 2;each of the plurality of error data output circuits outputs first and second error data according to the first and second retrieved data retrieved from the first and second selected memory cell groups selected from its ...

Method of testing flash memory

A method of testing a flash memory is applied to retrieve the flash memory available by picking up a defective flash memory. The flash memory includes at least a block, a page, and a cell. The method comprises inputting a test command into the flash memory to execute at least one of write, read, or compare of the flash memory. After the test command is executed, the states of the block, page, and cell in the flash memory may be obtained. The states are marked in a flash memory distribution list to allow a controller to access at least one of the normal block, page, and cell from the list. Thus, in the method, the normal block, page, and cell may be obtained.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF SCREENING THE SAME

A semiconductor memory device may include a voltage comparator, a voltage generator, a counter, and a circuit. The voltage comparator may be configured to generate an enabling signal responsive to a comparison indicating that a first voltage is lower than a reference voltage. The voltage generator may be configured to generate oscillation signals and a boost voltage by boosting the first voltage and to feed the boost voltage back as the first voltage in response to the enabling signal. The counter may be configured to count the number of the oscillation signals, and to generate a count output signal having information corresponding to the number of the oscillation signals. The circuit may be configured to output the count output signal as a quality output signal indicating the counted number relative to a target set value. 1. A semiconductor memory device comprising:a voltage comparator configured to generate an enabling signal responsive to a comparison indicating that a first voltage is lower than a reference voltage;a voltage generator configured to generate oscillation signals and a boost voltage by boosting the first voltage and to feed the boost voltage back as the first voltage in response to the enabling signal;a counter configured to count the number of the oscillation signals, and to generate a count output signal having information corresponding to the number of the oscillation signals; anda circuit configured to output the count output signal as a quality output signal indicating the counted number relative to a target set value.2. The semiconductor memory device of claim 1 , further comprising:an external terminal configured to provide the quality output signal indicating the semiconductor device is bad when the counted number is equal to or exceeds the target set value.3. The semiconductor memory device of claim 1 , wherein the counter includes an enable input configured to receive an input responsive to the oscillation signals.4. The semiconductor ...

Method and system for determining support for a memory card

Embodiments related to methods and systems for determining support for a memory card, where the memory card is accessible to a card reader and the card reader is in communication with an accessing device. One embodiment comprises transmitting a first test command to the memory card, receiving a response to the first test command, and determining that the response to the first test command indicates that a card type is not supported by a plurality of card drivers. In response to said determining, at least one additional test command specific to a card type supported by a selected card driver is automatically transmitted, and if the response is successful, the selected card driver, which was previously determined not to support the card type of the memory card, is indicated to support the card type of the memory card.

PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES

A method of configuring a plurality of configurable integrated circuit dies including receiving a configuration data stream at a die stack. The configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies are located on different substrates. The method also includes, performing for each of the dies in the die stack: receiving the configuration memory data for the die, storing the configuration memory data for the die in a configuration memory on the die, determining whether the configuration data stream includes configuration memory data for an additional die in the die stack, and transmitting the configuration data stream to the additional die in the die stack in response to the configuration data stream including configuration memory data for the additional die in the die stack. 1. A method of configuring a plurality of configurable integrated circuit dies , the method comprising:receiving a configuration data stream at a die stack, the configuration data stream comprising configuration memory data for a plurality of configuration memories and logic devices located on dies in the die stack, at least two of the dies in the die stack located on different substrates; and receiving the configuration memory data for the die;', 'storing the configuration memory data for the die in a configuration memory on the die;, 'performing for each die in the die stackdetermining whether the configuration data stream includes configuration memory data for an additional die in the die stack; andtransmitting the configuration data stream to the additional die in the die stack responsive to the configuration data stream including configuration memory data for the additional die in the die stack.2. The method of claim 1 , further comprising configuring the plurality of logic devices responsive to contents of the plurality of configuration memories.3. The method of claim 1 , wherein the transmitting between ...

PHASE-LOCKED LOOP AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME, AND TEST SYSTEM INCLUDING THE INTEGRATED CIRCUIT CHIP

A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock. 1. A phase-locked loop , comprising:a phase detection unit configured to compare a phase of a feedback clock with a phase of an input clock;a clock generation unit configured to adjust a frequency of a first clock based on a result of the comparison of the phase detection unit;a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode; anda second division unit configured to generate the feedback clock by dividing the output clock.2. The phase-locked loop of claim 1 , wherein the clock generation unit comprises:a charge pump configured to generate a charging discharging current based on a result of the comparison of the phase detection unit;loop filter charged/discharged in response to the charging/discharging current to generate a control voltage; anda voltage-controlled oscillator (VCO) configured to generate the first clock having a frequency controlled in response to the control voltage.3. The phase-locked loop of claim 1 , wherein the first division unit comprises a divider having the first or second division ratio in response to a test mode signal indicative of the test mode.4. The phase-locked loop of claim 1 , ...

Memory error test routine

An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure is to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.

APPARATUS AND METHOD FOR TESTING A MEMORY

An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and records a time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test. The apparatus determines, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a time-period from the time-point to current time, and a second position within the storage device on which the test is being performed at the current time. Then, the apparatus performs the test predetermined times on a range included in the storage device and including the first position, according to a testing procedure that has been used at the time-point. 1. An information processing device , comprising:a storage device configured to include an error correction circuit; and to perform a test of the storage device according to a predetermined testing procedure;', 'to record a first time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test;', 'to determine, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a first time-period from the first time-point to current time, and a second position within the storage device on which the test is being performed at the current time; and', 'to perform the test predetermined times on a first range included in the storage device and including the first position, according to a testing procedure that has been used at the first time-point., 'a processor configured2. The information processing device of claim 1 , whereinwhen the processor performs, in parallel, a plurality of the tests on ...

Memory module and a memory test system for testing the same

A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

MEMORY MANAGER

An embodiment of a manager includes at least one input node configured to receive information regarding a region of an integrated circuit, and a determiner configured to determine, in response to the information, a likelihood that the region will cause an error. For example, the region may include a memory, and contents of the memory may be transferred to another, more reliable memory, if the likelihood that the memory will cause an error in the data that it stores equals or exceeds a likelihood threshold. 120-. (canceled)21. A manager , comprising:an input node configured to receive information regarding a region of an integrated circuit; anda determiner configured to determine, in response to the information, a likelihood that the region will cause an error.22. The manager of wherein the information includes a signal from a sensor configured to sense a parameter of the region.23. The manager of wherein the information includes a temperature of the region.24. The manager of wherein the information includes a supply voltage for circuitry disposed in the region.25. The manager of wherein the information includes a physical attribute of the region.26. The manager of wherein the information includes a manufacturing-process-related attribute of the region.27. The manager of wherein the region includes at least one memory cell.28. The manager of wherein the determiner is configured to determine the likelihood that the region will cause an error by determining the reliability of the region.29. The manager of wherein the determiner is configured to determine the likelihood that the region will cause an error by comparing the received information with stored information.30. The manager of wherein the determiner is configured to determine the likelihood that the region will cause an error by comparing the received information with at least one stored value.31. The manager of claim 21 , further comprising:wherein the region includes a memory array; anda handler configured to ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME

A semiconductor memory device includes a write controller configured to transmit a first input data that is supplied through a first pad, to a first global I/O line and a second global I/O line when a write operation is executed in a test mode. The semiconductor memory device further includes a first write driver configured to store the first input data via the first global I/O line in a first cell block when the write operation is executed in the test mode. The semiconductor memory device further includes a first I/O line driver configured to supply signals to the first global I/O line and a first test I/O line in response to a first output data supplied from the first cell block when a read operation is executed in the test mode. 1. A semiconductor memory device comprising:a write controller configured to transmit a first input data from a first pad to a first global I/O line and a second global I/O line when a write operation is executed during a test mode;a first write driver configured to transfer the first input data from the first global I/O line to a first cell block so as to cause the first input data to be stored in the first cell block when the write operation is executed during the test mode; anda first I/O line driver configured to supply signals to the first global I/O line and to a first test I/O line in response to receiving a first output data from the first cell block when a read operation is executed during the test mode.2. The semiconductor memory device of claim 1 , wherein the signal on the first global I/O line is supplied via the first pad when the read operation is executed during the test mode.3. The semiconductor memory device of claim 1 , further comprising a drive control signal generator configured to enable first and second drive control signals when the write operation or the read operation is executed during the test mode.4. The semiconductor memory device of claim 3 , wherein the first I/O line driver comprises:a first I/O line ...

MEMORY TEST METHOD, MEMORY TEST DEVICE, AND ADAPTER THEREOF

A memory test device used to test performance of at least one memory module on an electronic device, are provided. The memory test device includes at least one adapter and a control unit. The adapter includes a plugging portion, a slot, and a switch circuit. The plugging portion is used to be plugged in a memory module slot of the electronic device. The slot is connected electrically to the plugging portion, is used for the memory module to plug in, and is capable of outputting a work voltage to the memory module when the adapter is plugged in the memory module slot and connected electrically to it. The switch circuit is connected electrically to the plugging portion and the slot. The control unit is connected electrically to the switch circuit of each adapter, where the control unit enables or disables the plugged memory module by controlling the switch circuit. 1. A memory module test device , used to test running performance of at least one memory module on an electronic device to be tested , wherein the electronic device to be tested comprises a circuit board , at least one memory module slot is disposed on the circuit board , and each memory module slot is used for the memory module to plug in , the memory module test device comprising: a plugging portion, used to be plugged in the memory module slot;', 'a slot, connected electrically to the plugging portion, used for the memory module to plug in, and capable of outputting a work voltage to the memory module when the adapter is plugged in the memory module slot and connected electrically to the memory module slot; and', 'a switch circuit, connected electrically to the plugging portion and the slot; and, 'at least one adapter, comprisinga control unit, connected electrically to the switch circuit of the adapter, wherein the control unit enables or disables the plugged memory module by controlling the switch circuit.2. The memory module test device according to claim 1 , wherein the control unit is programmable.3 ...

SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF

A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data. 1. A semiconductor chip comprising:a memory array including a plurality of memory cells;a plurality of terminals including a plurality of test terminals to output a result of a specific test; anda circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data.2. The semiconductor chip according to claim 1 , wherein the chip identification data is supplied from outside of the semiconductor chip.3. The semiconductor chip according to claim 1 , wherein the result includes a result of a test for memory array.4. The semiconductor chip according to claim 1 , wherein the plurality of terminals includes a plurality of through silicon vias.5. The semiconductor chip according to claim 4 , wherein at least one of the plurality of through silicon vias provides current paths between a first terminal formed on a first surface of the semiconductor chip and a second terminal formed on a second surface opposite to the first surface of the semiconductor chip.6. The semiconductor chip according to claim 1 , further comprising a chip identification data generating circuit generating the chip identification data in response to a data supplied from outside of the semiconductor chip. The present application is a Continuation application of U.S. patent application Ser. No. 13/137,969 filed on Sep. 22, 2011, which is based on and claims priority from Japanese Patent Application No. 2010-230332, filed on Oct. 13, 2010, the entire contents of which is incorporated herein by reference.1. Field of the InventionThe present invention relates to a semiconductor device and a test method thereof, and more particularly relates to a ...

TRANSACTION-LEVEL TESTING OF MEMORY I/O AND MEMORY DEVICE

A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device. 1. A method comprising:receiving, by a test engine, a memory test software command indicating a test to perform on a memory device;generating, by the test engine, in response to receiving the software command, a memory access transaction to perform the memory test; andpassing the memory access transaction from the test engine to a memory controller device, bypassing a memory address decoder associated with the memory controller device, to cause the memory controller device to generate and schedule memory device commands for the memory device to carry out the transaction.2. The method of claim 1 , wherein receiving the memory test software command comprises receiving a command from a basic input/output system (BIOS).3. The method of claim 1 , wherein generating the memory access transaction comprises generating a command plus specific memory location address information.4. The method of claim 3 , wherein generating the command comprises generating a read command identifier or a write command identifier.5. The method of claim 1 , wherein generating the memory access transaction further comprises performing a logical-to-physical address mapping.6. The method of claim 5 , wherein performing the logical-to-physical address mapping ...

Functional memory array testing with a transaction-level test engine

A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device. 1. A semiconductor memory device comprising:a pad configured to receive a first write data from outside of the semiconductor memory device; anda write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.2. The semiconductor memory device of claim 1 , wherein the first write data have a predetermined burst length.3. The semiconductor memory device of claim 2 , wherein the second write data are loaded on corresponding global input/output lines.4. The semiconductor memory device of claim 3 , wherein the global input/output lines are disposed in a peripheral region.5. The semiconductor memory device of claim 3 , wherein the write circuit comprises:a first data generation unit configured to generate a plurality of third write data in response to the first write data and the data strobe signals; anda second data generation unit configured to generate the plurality of second write data in response to the third write data, the test mode signal, the data strobe signals, and the write enable signal.6. The semiconductor memory device of claim 5 , wherein the first data generation unit comprises a number of latches corresponding to the burst length of the first write data claim 5 , the latches configured to output the third write data.7. The semiconductor memory device of claim 5 , wherein the second data generation unit comprises a plurality of data array blocks ...

SCALABLE INFIELD SCAN COVERAGE FOR MULTI-CHIP MODULE FOR FUCTIONAL SAFETY MISSION APPLICATION

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode. 2. The apparatus of claim 1 , wherein the indication to configure I3C interface to enable multilane comprises an indication of using four serial data lanes.3. The apparatus of claim 1 , wherein the first chip is further configured to transmit error correction data using multiple lanes after the transmission of the data to the second chip using multiple lanes.4. The apparatus of claim 3 , wherein the transmitted error correction data comprises a word for cyclic redundancy check (CRC WORD) which is transmitted over the first data lane.5. The apparatus of claim 4 , wherein the first chip is further configured to transmit HDR Exit data after the word for cyclic redundancy check (CRC WORD) over the first data lane to conclude the transmission.6. The apparatus of claim 1 , wherein the first chip is further configured to transmit the data to the second chip using multiple lanes with a duration of multiples of 10 serial clocks (SCL).7. The apparatus of claim 1 , wherein the first chip is further configured to transmit the data to the second chip in double data rate (DDR).8. The apparatus of claim 1 , wherein a plurality of data packets is transmitted to the second chip after the transmission of the Clear Command Channel (CCC) command.9. The apparatus of claim 1 , wherein the first chip is a master chip and the ...

RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY, AND OPERATING METHOD OF THE RESISTIVE MEMORY DEVICE

An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal. 1. An operating method for a resistive memory device , the method comprising:applying a bias control voltage to a memory cell array of the resistive memory device;measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result;generating a control signal based on the measuring result; andadjusting a level of the bias control voltage in response to the control signal.2. The method of claim 1 , further comprising:storing control information associated with the adjusting of the level of the bias control voltage.3. The method of claim 1 , further comprising:entering a test mode during a power-up period for the resistive memory device, wherein the applying of the bias control voltage, the measuring of the leakage current, the generating of the control signal, and the adjusting of the level of the bias control voltage are performed during the test mode.4. The method of claim 1 , further comprising:entering a normal mode for the resistive memory device during which normal memory operations may be performed,wherein the applying of the bias control voltage, the measuring of the leakage current, the generating of the control signal, and the adjusting of the level of the bias control voltage are performed during the normal mode.5. The method of claim 1 , wherein the measuring of the leakage current comprises:measuring a forward leakage current using a measuring instrument connected to a wordline of the memory cell array; andmeasuring a reverse leakage current using a ...

FAULT BITS SCRAMBLING MEMORY AND METHOD THEREOF

A fault bits scrambling memory and method thereof relate to a memory including at least one memory bank. The memory bank includes a memory module, a scrambling-logic unit, a self-testing unit and a scrambling code generating unit. The memory module includes a plurality of pages. Each page has a plurality of memory cells, and each memory cell has a physical address. The scrambling logic unit receives a scrambling code and the physical address to generate a mapping address by logical calculation, and outputs the mapping address to the memory module. The self-testing unit detects the faulty memory cells of each page. The scrambling code generating unit is applied to generate the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance. 1. A fault bits scrambling memory , comprising:at least a memory bank, each memory bank comprising a memory module, the memory module comprising a plurality of pages, each page comprising a plurality of memory cells, each memory cell having a physical address;a scrambling logic unit, receiving a scrambling code and the physical address to generate a mapping address by logical computation, and outputting the mapping address to the memory module so that an external module accesses the data of the memory cell corresponding to the mapping address according to the physical address;a self-testing unit, detecting faulty memory cells of each page to generate a faulty information; anda scrambling code generating unit, receiving the faulty information and generating the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.2. The fault bits scrambling memory according to claim 1 , wherein each page stores an error correction code claim 1 , an error correcting algorithm is based on the error correction code to repair the faulty memory cells of the page claim 1 , ...

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

An identification technique for physically damaged blocks of a flash memory of a data storage device. In the data storage device, a controller coupled to the flash memory writes data into the flash memory with at least one time stamp corresponding to the data. The time stamp is taken into consideration by the controller to identify the physically damaged blocks of the flash memory, and thereby it is prevented from erroneously identifying a physically undamaged block as bad. Thus, the flash memory is prevented from being erroneously regarded as a write protected memory. The lifespan of the flash memory is effectively prolonged. 1. A data storage device , comprising:a flash memory, providing a storage space which is divided into a plurality of blocks; anda controller coupled to the flash memory, wherein when storing data into the flash memory, the controller further stores at least one time stamp corresponding to the data into the flash memory,wherein, the controller determines whether one of the plurality of blocks for storage of the data is physically damaged by checking the time stamp corresponding to the data.2. The data storage device as claimed in claim 1 , wherein:the controller further records a time reference in a system block between the plurality of blocks of the flash memory, the time reference being arranged to be compared with the time stamp corresponding to the data to determine whether the block for storage of the data is physically damaged; andwhen storing the data and the corresponding time stamp into the flash memory, the controller sets the value of the time stamp based on the time reference.3. The data storage device as claimed in claim 1 , wherein:when there is a problem during a read operation for data in a space of the flash memory, the controller checks whether the time stamp corresponding to the data contained in the space exceeds a time reference by a threshold value to determine whether the block within the space for storage of the data is ...

Manufacturing testing for ldpc codes

An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

Electronic device and operating method thereof

Disclosed is an operating method of an electronic device which includes a semiconductor memory having a plurality of resistive storage cells. The operating method may include: writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value, and successful when the number of resistive storage cells with failed writing of data is equal to or less than the reference value; strengthening the set condition when the writing of data is determined to be failed; and easing the set condition when the writing of data is determined to be successful.

LATCH-BASED MEMORY ARRAY

The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input. 1. A memory array comprising memory cells arranged in a plurality of columns and in a plurality of rows , the memory cells of each column being coupled to at least one common write line of their column , the memory cells of each row being coupled to a common selection line of their row , wherein each of the memory cells comprises:a latch formed of a pair of inverters cross-coupled between first and second storage nodes;a first transistor coupled between said first storage node and a first test data input; anda second transistor coupled between said second storage node and a second test data input.2. The memory array of claim 1 , wherein each memory cell further comprises a data output claim 1 , each of the data outputs being independently connected to an output port of said memory array.3. The memory array of claim 2 , wherein each of said memory cells comprises a buffer providing said data output claim 2 , said buffer comprising a third transistor coupling said data output to a first supply voltage and a fourth transistor coupling said data output to a second supply voltage claim 2 , the third and fourth transistors having their control nodes coupled to said first or second storage node.4. The memory array of claim 1 , wherein a first of said memory cells has its first and second test data inputs coupled to test sequence input circuitry claim 1 , and wherein a second of said memory cells has ...

Semiconductor device and method of evaluating semiconductor device

A semiconductor device includes a plurality of memory cell array units and a test circuit unit. The test circuit unit includes a test data generating unit configured to generate a test data piece per test cycle including a writing period and a retrieving period; an expected value register configured to output the test data piece as an expected value data piece; a memory cell driving unit configured to supply a writing driving signal during the writing period, and a retrieving driving signal during the retrieving period; a data relay switching unit configured to supply the test data piece during the writing period, and to output retrieved data piece during the retrieving period; and a determining unit configured to determine whether the retrieved data piece output from the data relay switching unit matches the expected value data piece, and to generate a test result signal indicating a determination result.

Semiconductor device

A semiconductor device includes a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.

Internal signal monitoring circuit

Disclosed herein is an apparatus that includes a first circuit configured to measure a first time period from a first active edge of one of plurality of internal signals to a second active edge of one of the plurality of internal signals, and a second circuit configured to compare the first time period with a second time period to generate an alert signal.

MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY AND METHOD OF OPERATING NONVOLATILE MEMORY

A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting failed cells based on the first set of data, storing information about the failed cells in a buffer, and reprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer. 1. An operation method of a nonvolatile memory , comprising:programming a plurality of memory cells using a normal program pulse;reading out a first set of data from the plurality of memory cells;detecting failed cells from among the plurality memory cells based on the first set of data;storing information about the failed cells in a buffer; andreprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer.2. The operation method of a nonvolatile memory of claim 1 , wherein the reading out of the first set of data from the plurality of memory cells is successively performed after the programming of the plurality of memory cells.3. The operation method of a nonvolatile memory of claim 1 , wherein the programming of the plurality memory cells claim 1 , the reading out of the first set of data claim 1 , the detecting of the failed cells and the storing of the information are successively performed in response to one command.4. The operation method of a nonvolatile memory of claim 1 , further comprising:reprogramming the failed cells using the normal program pulse; andreading out a second set of data from the plurality memory cells to detect further failed cells not programmed during the reprogramming of the failed cells, after the detecting of the failed cells and before the storing of the information,wherein the storing of the information includes storing information about the further failed cells in the buffer.5. The operation method of a nonvolatile memory of claim 1 , wherein the ...

MEMORY, MEMORY SYSTEM INCLUDING THE SAME AND METHOD FOR OPERATING MEMORY

A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines. 1. A memory comprising:a plurality of word lines to which one or more memory cells are connected; anda control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode,wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines.2. The memory of claim 1 , wherein the first word line includes one or more word lines adjacent to the high-activated word line.3. The memory of claim 1 , wherein the control unit writes a comparison data claim 1 , which is different from the test data claim 1 , to the memory cells connected to the plurality of word lines before writing the test data to the first memory cells during the target refresh operation in the test mode.4. The memory of claim 1 , wherein the control unit reads data written to the memory cells that are connected to the plurality of word lines after writing the test data to ...

MEMORY SYSTEM WITH ENCODING

In an embodiment, a memory system comprises a memory array having memory cells. A decoder is coupled to the memory array and configured to decode input address signals to generate memory cell selection signals. An encoder is configured to generate encoded selection signals based on the memory cell selection signals. In another embodiment, a method comprises: receiving by the decoder of the memory system input address signals, generating, by the decoder, selection signals for selecting a memory cell in the memory array, and generating, by an encoder, encoded selection signals based on the selection signals. 1. A memory system comprising:a memory array having memory cells and column circuitry;a decoder coupled to the memory array, the decoder configured to decode input address signals to generate memory cell selection signals; andan encoder integrated with the column circuitry and configured to generate encoded selection signals based on the memory cell selection signals.2. The memory system of claim 1 , further comprising:a fault detector configured to detect a fault based on the encoded selection signals.3. (canceled)4. (canceled)5. The memory system of claim 1 , where the encoder is configured to generate compliment selection signals from the selection signals.6. The memory system of claim 5 , further comprising;first logic configured to conduct a comparison between the selection signals and the compliment selection signals; andsecond logic configured to detect a fault based on the comparison.7. The memory system of claim 1 , where the decoder includes logic configured to select one of N memory cells in the memory array claim 1 , where N is a positive integer value claim 1 , where N=2 claim 1 , and where M is a positive integer representing a number of input address signals.8. A method comprising:receiving, by a decoder of a memory system having a memory array of memory cells and column circuitry, input address signals;generating, by the decoder, selection signals ...

GPU-BASED ADVANCED MEMORY DIAGNOSTICS OVER DYNAMIC MEMORY REGIONS FOR FASTER AND EFFICIENT DIAGNOSTICS

An information handling system may include a central processing unit (CPU), a graphics processing unit (GPU) including a plurality of processing cores, a memory coupled to the CPU and to the GPU, and a basic input/output system (BIOS). While the information handling system is in a pre-boot environment and prior to initialization of an operating system of the information handling system, the BIOS may cause the central processing unit to select respective portions of the memory for failure testing; and cause individual ones of the plurality of processing cores of the GPU to carry out the failure testing of the respective portions of the memory. 1. An information handling system comprising:a central processing unit (CPU);a graphics processing unit (GPU) comprising a plurality of processing cores;a memory coupled to the CPU and to the GPU; and cause the central processing unit to select respective portions of the memory for failure testing; and', 'cause individual ones of the plurality of processing cores of the GPU to carry out the failure testing of the respective portions of the memory., 'a basic input/output system (BIOS) configured to, while the information handling system is in a pre-boot environment and prior to initialization of an operating system of the information handling system2. The information handling system of claim 1 , wherein the BIOS is a Unified Extensible Firmware Interface (UEFI) BIOS.3. The information handling system of claim 1 , wherein the BIOS is further configured to:detect a particular portion of the memory that has failed; andmark the particular portion of the memory such that the operating system is configured to initialize without using the particular portion of the memory.4. The information handling system of claim 3 , wherein the initialization of the operating system is configured to occur without an additional reboot of the information handling system.5. The information handling system of claim 1 , wherein the individual ones of the ...

MEMORY ORGANIZATION FOR SECURITY AND RELIABILITY

A method and apparatus for retrieving data from a memory in which data, an associated message authentication code (MAC) and an associated error correction code (ECC) are stored in a memory such that the data, MAC and ECC can be retrieved together in a single read transaction and written in a single write transaction. Additional read transactions may be used to retrieve counters values that enable the retrieved MAC to be compared with a computed MAC. Still further, node value values of an integrity tree may also be retrieved to enable hash values of the integrity tree to be verified. The MAC and ECC may be stored in a metadata region of a memory module, for example. 1. A method for retrieving data from a memory having a plurality of addressable lines , each addressable line containing a data region and a metadata region , the method comprising:reading, in a single transaction, a first addressable line at a first address in the memory, where a metadata region of the first addressable line contains a first stored message authentication code (MAC) and an error correction code (ECC), both associated with data contained in a data region of the first addressable line;reading a plurality of counter values from a second addressable line in the memory, where the first stored MAC is generated from the data, a first counter value of the plurality of counter values and a first secret key;computing, by a data checking engine, a first computed MAC dependent upon the data, the first counter value and the first secret key; anddetermining the data to be reliable when the first stored MAC is equal to the first computed MAC.2. The method of claim 1 , where the ECC relates to the data and the first stored MAC claim 1 , the method further comprising claim 1 ,correcting the first stored MAC, the data, or both the first stored MAC and the data in accordance with the ECC; and re-computing the first computed MAC; and', 'determining the data to be reliable when the first stored MAC is equal ...

SEMICONDUCTOR DEVICE ENABLING REFRESHING OF REDUNDANT MEMORY CELL INSTEAD OF DEFECTIVE MEMORY CELL

A semiconductor device includes memory blocks MB and MB and redundancy determination circuit that can enter a normal operation mode that accesses either memory block MB or memory block MB and a refresh mode that simultaneously accesses both memory block MB and memory block MB. In response to normal memory cell NMC that belongs to at least one of memory blocks MB and MB being replaced by redundant memory cell RMC in the refresh mode, redundancy determination circuit deactivates normal cell area NCA to which normal memory cell NMC that is a source of replacement belongs, and activates redundant cell area RCA to which redundant memory cell RMC that is to be replaced belongs and normal cell area NCA to which normal memory cell NMC that is not being replaced belongs. 1. (canceled)2. A method for accessing a dynamic random access memory having two memory blocks each comprising a normal cell area and a redundant cell area , comprising:receiving a normal operation command including a first row address;activating, if the first row address corresponds to a redundant address, a first redundant wordline in the redundant cell area of a first block among the two memory blocks determined by a first bit in the first row address while not activating the normal cell area of the first block, not activating the redundant cell area of a second block among the two memory blocks, and not activating the normal cell area of the second block;activating, if the first row address does not correspond to the redundant address, a first normal wordline corresponding to a portion of the first row address in the normal cell area of the first block while not activating the redundant cell area of the first block, not activating the redundant cell area of the second block, and not activating the normal cell area of the second block;receiving a refresh operation command including a second row address;activating, if the second row address corresponds to the redundant address, the first redundant wordline ...

Chip with embedded non-volatile memory and testing method therefor

A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit.

FLEXIBLE INTERRUPT GENERATION MECHANISM

In a testing device, a method for implementing efficient interrupt routing. The method includes receiving an interrupt from a plurality of interrupt causes, consulting an interrupt routing table to determine an output interrupt vector, and forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table. 1. In a testing device , a method for implementing efficient interrupt routing , comprising:receiving an interrupt from a plurality of interrupt causes; andconsulting an interrupt routing table to determine an output interrupt vector;forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table.2. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules.3. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules and each of the pin electronics modules includes a plurality of bridge components and a plurality of CPUs.4. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules coupled together via a high-speed bus.5. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules having a plurality of bridge components claim 1 , wherein each bridge component comprises two half bridge components.6. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules claim 1 , and wherein each of the pin electronics modules is configured to couple to a plurality of devices under test.7. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules claim 1 , and wherein the pin electronics modules can be configured to support different combined resource modes of operation.8. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules claim 1 , and wherein the pin ...

Green NAND Device (GND) Driver with DRAM Data Persistence For Enhanced Flash Endurance and Performance

A Green NAND Device (GND) driver application queries AC line and battery status and then stores an image of processor states and caches and a resume routine to DRAM when power failure occurs. A DRAM image is then stored to flash memory for a persistent mode when battery power is available. The image in DRAM may be a partial image that includes entries, flushed caches, processor contexts, ramdisks, write caches, and a resume context. Endurance of flash memory is increased by a Super Enhanced Endurance Device (SEED) SSD. In a power down mode, the GND driver limits DRAM use and only caches in DRAM data that can be deleted on power down. Host accesses to flash are intercepted by the GND driver and categorized by data type. Paging files and temporary files cached in DRAM are optionally written to flash.

ELECTROMAGNET, TESTER AND METHOD OF MANUFACTURING MAGNETIC MEMORY

According to one embodiment, an electromagnet includes a first electromagnet coil having a first portion and a second portion. The first portion of the first electromagnet coil extends in a direction in parallel with a first plane. The second portion of the first electromagnet coil extends in a direction in parallel with a second plane. The first and second planes intersect at a predetermined angle. 1. An electromagnet comprising:a first electromagnet coil having a first portion and a second portion,wherein the first portion of the first electromagnet coil extends in a direction in parallel with a first plane,the second portion of the first electromagnet coil extends in a direction in parallel with a second plane, andthe first and second planes intersect at a predetermined angle.2. The electromagnet of claim 1 , wherein the predetermined angle is 90°.3. The electromagnet of claim 1 , further comprising:a tube-shaped body with a bended ring form,wherein the first electromagnet coil is provided in a hollow portion of the tube-shaped body.4. The electromagnet of claim 3 , whereinthe tube-shaped body has an electrode of the first electromagnet coil.5. The electromagnet of claim 3 , whereinthe tube-shaped body has a cross-sectional surface of one of a square from, circular form, and a polygonal form.6. The electromagnet of claim 3 , whereinthe tube-shaped body has a flat bottom surface in parallel with the first plane.7. The electromagnet of claim 1 , further comprising:a second electromagnet coil having a third portion and a fourth portion and being independent of the first electromagnet coil,wherein the third portion of the second electromagnet coil extends in a direction in parallel with a third plane,the fourth portion of the second electromagnet coil extends in a direction in parallel with a fourth plane,the third and fourth planes intersect at the predetermined angle, andthe second and fourth planes face each other.8. The electromagnet of claim 7 , whereinthe ...

Memory system and operating method for the same

A memory system comprises a memory device including a plurality of memory blocks, the memory device being configured to perform a program operation and a program verify operation to program data to the memory blocks, and a controller configured to detect program error bit information as a result of the program verify operation, select a victim memory block among the memory blocks based on the detected program error bit information, and copy programmed data of the victim memory block.

TEST METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TEST APPARATUS

A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell. 1. A test method of a semiconductor device , the test method comprising:providing a semiconductor device having a substrate including an active region and an isolation region, a volatile device cell including a gate insulation layer and a first gate on the active region, a junction region in the active region, and a capacitor connected to the junction region, and a passing gate on the isolation region;providing a first test voltage to the first gate and a second test voltage greater than the first test voltage to the passing gate; andmeasuring retention characteristics of the volatile device cell.2. The test method of claim 1 , wherein the first test voltage is a negative voltage.3. The test method of claim 2 , wherein the second test voltage is a negative voltage.4. The test method of claim 2 , wherein the absolute value of the first test voltage is greater than the absolute value of the second test voltage.5. The test method of claim 1 , wherein the measuring includes measuring a data retention time (tRET) of the volatile device cell.6. The test method of claim 1 , wherein the measuring includes measuring a leakage current of the volatile device cell.7. The test method of claim 1 , wherein the measuring is performed once for each volatile device cell.8. The test method of claim 1 , further ...

SEMICONDUCTOR MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY

According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period. 1. A semiconductor memory comprising:a memory area;an error detection circuit which detect an error of first data output from the memory area; anda control circuit which control operations of the memory area and the error detection circuit,wherein when the error is detected in the first data, the control circuit starts precharge of a bit line of the memory area at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data, andwhen the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period.2. The memory according to claim 1 , whereinwhen the error is detected in the first data, the control circuit executes, before the precharge, first processing for writing second data obtained by correcting the error in the first data,when the error is not detected in the first data, the control circuit starts the precharge without executing the first processing.3. The memory according to claim 1 , whereinthe first data is output from the memory area based on a first command from an outside device,when the error is detected in the first data, the control circuit receives ...

SEMICONDUCTOR DEVICE AND ITS QUALITY MANAGEMENT METHOD

A semiconductor device capable of easily and properly detecting a defective element unit(s) and a quality management method for the semiconductor device are suggested. A semiconducting device simulating interactions between nodes in an interaction model is equipped with a quality management unit for managing the quality of each element unit provided corresponding to each node, wherein the quality management unit executes a specified quality test of each element unit, compares test results of the quality test with pre-given results to be obtained from the quality test, and detects a defective memory cell(s) and a defective element unit(s) based on the comparison results. 1. A semiconductor device simulating interactions between nodes in an interaction model , the semiconductor device comprising:a plurality of element units, each of which is provided corresponding to each of the nodes constituting the interaction model; anda quality management unit that manages quality of each of the element units;wherein the element unit includes:a first memory cell that retains a value indicating a state of the node associated with the element unit;one or more second memory cells, each of which retains each interaction coefficient with each of the other nodes causing an interaction with the relevant node; anda logical circuit that determines a value indicating a next state of the node associated with the element unit based on the interaction coefficient retained in each of the second memory cells and a value which is given from each of the other corresponding element units and indicates the state of each of the other nodes causing the interaction over the node associated with the element unit;wherein the quality management unit:executes a specified quality test for each of the element units;compares test results of the quality test with pre-given results to be obtained from the quality test; anddetects the first and/or second memory cell which is defective and the element unit which ...

MEMORY TEST SYSTEM AND METHOD OF TESTING MEMORY DEVICE

A memory test system may include a tester and N memory devices, where N is a positive integer greater than 1. The tester may generate test signals. A K-th memory device of the N memory devices includes a plurality of K-th memory banks and a K-th decoder, where K is each positive integer equal to or smaller than N. The K-th memory banks may be configured to operate based on first internal signals and each of the K-th memory banks includes a plurality of unit blocks. The K-th decoder may be configured to convert the test signals corresponding to the first test to the first internal signals based on a K-th conversion relation and update the K-th conversion relation based on a result of the first test with respect to the K-th memory device. 1. A memory test system comprising: N memory devices, wherein a K-th memory device of the N memory devices comprises:', 'a K-th decoder configured to convert the test signals corresponding to a first test to first internal signals based on a K-th conversion relation, configured to update the K-th conversion relation based on a result of the first test with respect to the K-th memory device, and configured to convert the test signals corresponding to a second test to second internal signals based on the updated K-th conversion relation, where N is a positive integer greater than 1 and K is a positive integer equal to or smaller than N; and', 'a plurality of K-th memory banks configured to operate based on the first and second internal signals, each of the K-th memory banks including a plurality of unit blocks., 'a tester configured to generate test signals; and'}2. The memory test system of claim 1 , wherein the first through N-th decoders update the first through N-th conversion relations respectively such that the second test for the N memory devices is performed in parallel claim 1 , based on the first through N-th reset conversion relations claim 1 , with respect to the memory banks that are determined through the first test to ...

QUICK PRECHARGE FOR MEMORY SENSING

Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations. 1. (canceled)2. A method , comprising:determining that precharge commands are to be performed using a first sequence that is associated with a reduced duration relative to a second sequence for executing precharge commands;receiving a precharge command associated with a memory cell based at least in part on determining that the precharge commands are to be performed using the first sequence; andperforming, on the memory cell, a set of operations of the first sequence based at least in part on the precharge command associated with the memory cell.3. The method of claim 2 , further comprising:configuring a testing component to execute precharge commands using the first sequence based at least in part on the determining.4. The method of claim 3 , further comprising:indicating, based at least in part on the configuring, a duration for the testing component to execute precharge commands using the first sequence, wherein the testing component executes precharge commands using the second sequence after an end of the duration.5. The method of claim 2 , further comprising:activating, based at ...

TESTING MEMORY CELLS

A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range 1. A method for managing accesses to a memory , comprising:allocating an access value to a memory access;granting an access credit; andif the access value of the memory access does not exceed the access credit, performing the memory access and reducing the access credit by the access value,wherein the memory access is performed on one memory cell or at bit level on a plurality of memory cells.2. The method as claimed in claim 1 ,wherein the access value is allocated to the memory access on the basis of an information content resulting from the memory access, orwherein the allocation of the access value to the memory access is determined on the basis of a ratio of a number of ones to a number of bit positions which are subjected to the memory access, or on the basis of a ratio of a number of zeros to the number of bit positions which are subjected to the memory access.3. The method as claimed in claim 1 , further comprising:electively making a memory area accessible for the memory access; andblocking the memory against the memory access if the memory access ...

METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS

In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC. 1. A method comprising:receiving a metal isolation test circuit comprising a pseudo static random access memory (SRAM) cell disposed on a semiconductor substrate, wherein the pseudo SRAM cell includes a plurality of transistors and an interconnect structure disposed over the plurality of transistors, the interconnect structure including a plurality of pins that are coupled to a plurality of nodes in the pseudo SRAM cell;applying a first voltage bias across first and second pins of the plurality of pins, and measuring a first leakage current while the first voltage bias is applied;applying a second voltage bias across third and fourth pins, and measuring a second leakage current while the second voltage bias is applied; andcharacterizing a process or a design rule by which the pseudo SRAM cell is made based on the first leakage current and the second leakage current.2. The method of claim 1 , further comprising:modifying the process, the design rule, or an actual SRAM cell design based on the characterization of the process or the design rule.3. The method of claim 2 , wherein the pseudo SRAM cell and the actual SRAM cell design have the ...

Drive strength calibration for multi-level signaling

Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

SCANNABLE MEMORIES WITH ROBUST CLOCKING METHODOLOGY TO PREVENT INADVERTENT READS OR WRITES

An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit. 1. A scannable register file , comprising: produce a read data output by reading data from a memory location selected based on a register file read address input, wherein the reading is triggered by rising edges of a register file read clock input, and', 'write data from a register file write data input to a memory location selected based on a register file write address input, wherein the writing is triggered by edges of a register file write clock input; and, 'a register file module configured to'}a scan logic module configured to receive a scan clock input, a scan enable input, and shift enable input and to supply the register file read address input, the register file write address input, the register file read clock, and the register file write clock to the register file module.2. The scannable register file of claim 1 , wherein the scan logic module comprises an address counter configured to produce a count output that is reset when not in a shift phase of a scan test and that counts on edges of the scan clock input.3. The scannable register file of claim 2 , wherein the scan logic module further comprises a read address selector ...

RECONFIGURABLE CIRCUIT, STORAGE DEVICE, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE

A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit. 1. A CPU comprising: first to k-th logic circuits, where k is an integer of two or more;', 'first to k-th configuration memories;', 'a programmable look-up table;', 'a register; and', 'a multiplexer,, 'at least one programmable logic element, the programmable logic element comprising, 'a storage device, the storage device comprisingwherein the register is configured to store data output from the programmable look-up table, andwherein the multiplexer is configured to select and output data output from the programmable look-up table or data output from the register.2. The CPU according to claim 1 ,wherein the first to k-th logic circuits are each configured to perform an operation of an exclusive-NOR of first to k-th data and first to k-th configuration data output from the first to k-th configuration memories, respectively, and output an operation result as (k+1)th to 2k-th data, andwherein the programmable look-up table is configured to perform a logical operation of the (k+1)th to 2k-th data and (2k+1)th data and output an operation result as (2k+2)th data.3. The CPU according to claim 2 ,wherein in the h programmable logic elements, where h is an integer of two or more, the h programmable look-up tables are cascaded, andwherein the (2k+2)th data output ...

Method and system for testing semiconductor device

A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.

MEMORY OPERATION OF PAIRED MEMORY DEVICES

A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices. 1. A method comprising:receiving by a memory buffer a write operation request to write a data word to a memory module, the memory module having a set of paired memory devices comprising a first memory device and a second memory device;determining whether any failures exist in a word section storage of the first memory device and whether any failures exist in a word section storage of the second memory device;writing a first section of the data word to the first memory device and a second section of the data word to the second memory device when no failures are found; andwriting the first section and second section of the data word to both the first memory device and the second memory device if either memory device has a failure in their respective word section storages so long as no failures are found in equivalent locations of word section storage in the two memory devices.2. The method of claim 1 , further comprising:canceling the write operation request if failures in the word section storage of the first and second memory device are in equivalent locations of word section storage.3. The method of claim 1 , further comprising:receiving by the ...

MEMORY APPARATUS WITH REDUNDANCY ARRAY

Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair. 1. An apparatus comprising:a plurality of data terminals;at least one memory cell array that includes a plurality of memory cells;an ECC/parity redundancy array that includes a plurality of memory cells; anda redundancy circuit configured to communicate data with the data terminals and further configured to provide the data to the at least one memory cell array and the ECC/parity redundancy array and to receive the data from the at least one memory cell array and the ECC/parity redundancy array,wherein the redundancy circuit is configured to provide a portion of the data received from the plurality of data terminals to the ECC/parity redundancy array and further configured to receive the portion of the data from the ECC/parity redundancy array and to provide the portion of the data responsive to a first state of a control signal, andwherein the redundancy circuit is configured to provide error correction information to the ECC/parity redundancy array and further configured to receive the error correction information from the ECC/parity redundancy array responsive to a second state of the control signal that is ...

MEMORY CONTROLLER METHOD AND SYSTEM COMPENSATING FOR MEMORY CELL DATA LOSSES

A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh. 1. An apparatus , comprising:a memory device configured to store a data record identifying information corresponding to memory cells in the memory device having relatively weak data retention characteristics; and an address generating circuit configured to sequentially output addresses;', 'an address comparator configured to stored addresses corresponding to memory cells in the memory device having relatively low retention times, the address comparator coupled to the address generating circuit to receive each of the addresses from the address generating circuit, the address comparator configured to invert at least one of the bits of the address received, from the address generating circuit to provide respective comparison addresses, the address comparator further configured to compare the comparison addresses to the stored addresses and to generate an indicating signal responsive to a match between one of the comparison addresses and one of the stored addresses, and', 'a memory control state machine coupled to receive the indicating signal from the address comparator, the ...

SEMICONDUCTOR MEMORY DEVICE

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip. 1. A semiconductor memory device comprising:a plurality of memory cells;a word line commonly connected to the plurality of memory cells;a plurality of bit lines and a plurality of inverted bit lines respectively connected to the plurality of memory cells; anda memory controller operable to control access to the plurality of memory cells, an inverter loop connected between a first node and a second node;', 'a first access transistor connected between the first node and a bit line, the first access transistor being turned on and off according to a voltage applied to the word line;', 'a second access transistor connected between the second node and an inverted bit line, the second access transistor being turned on and off according to a voltage applied to the word line;', 'a first node capacitor connected to the first node, the first node capacitor having a higher capacitance than a parasitic capacitor of the bit line; and', 'a second node capacitor connected to the second node, the second node capacitor having a higher capacitance than a parasitic capacitor of the inverted bit line, and, 'wherein the plurality of memory cells each includewherein, when accessing a memory cell that is a target of a read/write, the ...

Memory Programming Methods and Memory Systems

Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Block Structure Profiling in Three Dimensional Memory

Memory hole diameter in a three dimensional memory array may be calculated from characteristics that are observed during programming. Suitable operating parameters may be selected for operating a block based on memory hole diameters. Hot counts of blocks may be adjusted according to memory hole size so that blocks that are expected to fail earlier because of small memory holes are more lightly used than blocks with larger memory holes. 1. A method of characterizing a three-dimensional NAND memory die comprising:selecting a plurality of sample blocks from the three-dimensional NAND memory array;writing sample data to a plurality of sample word lines of a plurality of physical levels of the sample blocks to obtain characterization information for the sample word lines; andcalculating a physical dimension of memory cells at each of the plurality of levels from the characterization information.2. The method of wherein the sample data consists of a predetermined test pattern for efficiently obtaining the characterization information.3. The method of wherein the test pattern assigns first logic states to memory cells on a drain side of a NAND string and assigns second logic states that are the inverse of the corresponding first logic states to corresponding memory cells on the source side of the NAND string.4. The method of wherein the physical dimension is a diameter of a vertical memory hole that extends through memory cells in each of the plurality of levels.5. The method of wherein the physical dimension is a thickness of a layer formed in a memory hole that extends through memory cells in each of the plurality of levels.6. The method of wherein the three-dimensional NAND memory die comprises a plurality of planes claim 1 , and wherein selecting the plurality of sample blocks comprises selecting at least one sample block from each of the plurality of planes.7. The method of wherein the plurality of sample word lines of the plurality of physical levels includes at ...

Selection of Data for Redundancy Calculation By Likely Error Rate

Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low. 1. A method of operating a three-dimensional NAND memory comprising:categorizing word lines in a block of the three-dimensional NAND memory into a plurality of categories according to predicted error rates for the word lines;selecting data assigned to a first word line from a first category for an exclusive OR (XOR) operation, the first category having a high predicted error rate;selecting data assigned to a second word line from a second category for the XOR operation, the second category having a low predicted error rate; andperforming the XOR operation on the data assigned to the first and second word lines to generate XOR data.2. The method of wherein the categorizing categorizes word lines according to predicted error rates by their physical levels with respect to a substrate on which the three-dimensional NAND memory is formed claim 1 , all word lines of a particular level assigned to the same category.3. The method of wherein levels are assigned to categories according to estimated memory hole diameters for different levels.4. The method of wherein the estimated memory hole diameters are obtained from testing performed on word lines of the block.5. The method of wherein the estimated memory hole diameters are obtained from testing performed on word lines of at least one other block that is on the same memory die as the block.6. The method of wherein the first category of word lines comprises word lines from levels with small memory hole diameters and the second category of word lines comprises word lines from levels with large memory hole diameters.7. A method of operating a three-dimensional memory array that includes ...

TEST DEVICES, TEST SYSTEMS, AND OPERATING METHODS OF TEST SYSTEMS

A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other. 1. A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation , the test device comprising:a logic generation/determination device configured to generate multiple bits corresponding to a test pattern;a first driver configured to generate a first non return to zero (NRZ) signal according to a logic state of a first bit among the multiple bits and output the generated first NRZ signal via a first channel; anda second driver configured to generate a second NRZ signal according to a logic state of a second bit among the multiple bits and output the generated second NRZ signal via a second channel,wherein the first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit,wherein the first high level is different from the second high level.2. The test device of claim 1 , wherein the first low level is different from the second low level.3. The test device of claim 1 , whereinthe first NRZ signal and the ...

Semiconductor memory device, semiconductor memory module and operation methods thereof

An operation method of a semiconductor memory device including a fuse array for storing one or more repair addresses includes latching additionally a repair address having an address value, which is not stored in the fuse array in response to an active command signal during a repair operation mode, receiving a repair entry control code from an external device in response to a first column command signal during the repair operation mode, performing a rupture operation of the repair address, which is latched, in response to a second column command signal, wherein the rupture operation is determined based on a value of a repair entry control code, and performing exit of the repair operation mode in response to a precharge command signal, which is provided after the second column command signal.

METHOD AND APPARATUS FOR BATCH TESTING DEVICE, RELATED COMPUTER DEVICE AND MEDIUM

The present application relates to a method and apparatus for batch testing device, related a computer device and a medium. The method includes: writing a corresponding test identification into each of the devices to be tested, wherein different devices to be tested have different test identifications; acquiring a device identification of each of the devices to be tested and generating a device identification sequence; sending corresponding test cases to the devices to be tested sequentially according to the device identification sequence, so that each of the devices to be tested executes the corresponding test case; and generating a test result for each of the devices to be tested, the test result corresponding to the corresponding test identification. 1. A method for batch testing device , for batch testing of a plurality of devices to be tested , the method comprising:writing a corresponding test identification into each of the devices to be tested, wherein different the devices to be tested have different test identifications;acquiring a device identification of each of the devices to be tested and generating a device identification sequence;sending corresponding test cases to the devices to be tested sequentially according to the device identification sequence, so that each of the devices to be tested executes the corresponding test case; andgenerating a test result for each of the devices to be tested, the test result corresponding to the corresponding test identification.2. The method according to claim 1 , further comprising: prior to the step of writing a corresponding test identification into each of the devices to be tested claim 1 ,acquiring the test identification of each of the devices to be tested.3. The method according to claim 2 , wherein the test identification is a user-defined test identification.4. The method according to claim 1 , wherein the step of acquiring a device identification of each of the devices to be tested and generating a device ...

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

A semiconductor memory device includes a memory cell array including a plurality of memory cells coupled between a common source line and a bit line, and a voltage generator applying operating voltages to word lines coupled to the memory cells or discharging potential levels of the word lines, wherein during a program verify operation, the voltage generator applies a program verify voltage and a pass voltage as the operating voltages to the word lines, and subsequently applies a set voltage to the common source line during a period in which the memory cells are turned on. 1. A semiconductor memory device , comprising:a memory string including a source selection transistor, a plurality of memory cells, and a drain selection transistor coupled in series between a common source line and a bit line; anda voltage generator applying operating voltages to a source selection line coupled to the source selection transistor, a plurality of word lines coupled to the plurality of memory cells, and a drain selection line coupled to the drain selection transistor during a verify operation,wherein the voltage generator increases a channel potential level of the memory string by applying a set voltage to the common source line or the bit line when applying a constant voltage to the source selection line, the plurality of word lines, and the drain selection line to turn on the source selection transistor, the plurality of memory cells, and the drain selection transistor.2. The semiconductor memory device of claim 1 , wherein the operating voltages include a verify voltage claim 1 , a pass voltage and the constant voltage claim 1 , andwherein during the verify operation, the voltage generator applies the verify voltage and the pass voltage to a selected word line and unselected word lines of the plurality of word lines, and subsequently applies the constant voltage to the source selection line, the plurality of word lines, and the drain selection line.3. The semiconductor memory ...

Offset cancellation

Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

SEAMLESS FAIL ANALYSIS WITH MEMORY EFFICIENT STORAGE OF FAIL LISTS

A method for testing memory devices under test (DUTs) using automated test equipment (ATE) is presented. The method comprises retrieving a portion of raw test data from a memory device under test (DUT). It also comprises comparing the portion of raw test data with expected test data to determine failure information, wherein the failure information comprises information regarding failing bits generated by the memory DUT. Next, the method comprises utilizing paging to transfer data comprising the failure information to a filtering module and filtering out the failure information from transferred data using the filtering module. Further, it comprises updating a fail list using the failure information, wherein the fail list comprises address information for respective failing bits within the memory DUT. Finally, it comprises repeating all the prior steps for the next block of raw test data. 1. A method for testing memory devices under test (DUTs) using automated test equipment (ATE) , said method comprising:a) retrieving a portion of raw test data from a memory device under test (DUT);b) comparing said portion of raw test data with expected test data to determine failure information, wherein said failure information comprises information regarding failing bits generated by said memory DUT;c) utilizing paging to transfer data comprising said failure information to a filtering module;d) filtering out said failure information from transferred data using said filtering module;e) updating a fail list using said failure information, wherein said fail list comprises address information for respective failing bits within said memory DUT; andf) repeating said (a)-(e) for another portion of raw test data.2. The method of claim 1 , further comprising masking out a plurality of failing bits from said failure information prior to said updating claim 1 , wherein said plurality of failing bits is correctable using software during post-processing claim 1 , and further wherein ...

TESTING MEMORY CELLS BY ALLOCATING AN ACCESS VALUE TO A MEMORY ACCESS AND GRANTING AN ACCESS CREDIT

A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range 17-. (canceled)8. A method for testing memory cells under test of an integrated circuit , comprising:allocating an access value to a memory access;granting an access credit;forming a first signature on a data word segment of a first bit sequence;writing the data word segment of the first bit sequence to the memory cells under test;if the access value of the memory access does not exceed the access credit, reading a second bit sequence from the memory cells under test and reducing the access credit by the access value;forming a second signature on the second bit sequence; andsignaling if the second signature differs from the first signature, or signaling if the second signature matches the first signature.9. The method as claimed in claim 8 , wherein the formation of the first signature or the formation of the second signature comprises:determining a checksum on the data word segment,determining a hash on the data word segment,determining an error correction code (ECC) for the data word segment, or determining a checksum for the data word segment.10. The ...

Nonvolatile Logic Array with Built-In Test Result Signal

A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.

Nonvolatile Logic Array with Built-In Test Drivers

A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits. 12-. (canceled)3. A system on chip (SoC) comprising a memory array , wherein the memory array comprises:n rows by m columns of bit cells, wherein each of the bit cells is configured to store a bit of data;m bit lines each coupled to a corresponding one of the m columns of bit cells;m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit, wherein the m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and wherein the m drivers are operable to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits;wherein each of the m drivers further comprise a transfer gate configured to transfer an offset voltage into a sense node of the bitcell during a read access in response to a control signal.4. A system on chip (SoC) comprising a memory array , wherein the memory array comprises:n rows by m columns of bit cells, wherein each of the bit cells is configured to store a bit of data;m bit lines each coupled to a corresponding one of the m columns of bit cells;m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a ...

PROCESS VARIATION SKEW IN AN SRAM COLUMN ARCHITECTURE

Aspects of the invention provide for a structure and method for determining a degree of process variation skew between a plurality of bit cells in a static random-access-memory (SRAM) column architecture. In one embodiment, a structure includes: a plurality of bit cells within a static random access memory (SRAM) column architecture; a digital-to-analog converter (DAC) connected to the bit cells through a pair of multiplexers; and a pre-charge circuit connected to the bit cells through the pair of multiplexers, wherein the DAC and the pre-charge circuit control and test the bit cells to determine a degree of process variation skew between each of the bit cells. 1. A structure , comprising:a plurality of bit cells within a static random access memory (SRAM) column architecture;a digital-to-analog converter (DAC) connected to the bit cells through a pair of multiplexers; anda pre-charge circuit connected to the bit cells through the pair of multiplexers,wherein the DAC and the pre-charge circuit control and test the bit cells to determine a degree of process variation skew between each of the bit cells.2. The structure of claim 1 , wherein the pre-charge circuit includes a field-effect transistor.3. The structure of claim 2 , wherein the pre-charge circuit equalizes a bit line voltage for each of the bit cells.4. The structure of claim 1 , further comprising a selection circuit for selecting a bit cell to test.5. The structure of claim 4 , wherein the DAC adjusts the bit line voltage6. The structure of claim 1 , wherein the SRAM column architecture includes a plurality of columns.7. The structure of claim 1 , further comprising selection signals for selecting one of: a signal from the DAC or a signal from the pre-charge circuit to output from each of the pair of multiplexers to the plurality of bit cells.8. The structure of claim 1 , further comprising a sense amplifier to output a true output and a complement output in testing the bit cells.9. A method for ...

SYSTEMS AND METHODS FOR DETECTING A DIMM SEATING ERROR

DIMM seating errors may be detected. An example detection method includes determining whether a training error has occurred for a number of dynamic random access memories (DRAMs) of a DIMM. The Example method includes identifying a location for each of the DRAMs. The example method includes determining whether a seating error has occurred based on the training error, the number, and the location of the DRAMs. 1. A method for detecting a dual in-line memo module (DIMM) seating error , the method comprising:determining whether a training error has occurred for a number of dynamic random access memories (DRAMs) of a DIMM;identifying a location for each of the DRAMs; anddetermining whether a seating error has occurred based or the training error, the number, and the location of the DRAMs.2. The method recited in claim 1 , wherein the seating error has occurred if the number equals one.3. The method recited in claim 1 , wherein the seating error has occurred if the number is greater than one claim 1 , and the location is disposed approximate to an end of the DIMM.4. The method recited in claim 1 , wherein the seating error has not occurred if the number indicates a universal failure of the DRAMs.5. The method recited in claim 1 , wherein a WRITE LEVELING process comprises determining whether the seating error has occurred6. The method recited in claim 1 , wherein the DIMM comprises DDR3 and DDR4 DRAMS.7. The method recited in claim 1 , comprising generating an error message indicating the seating error and the DIMM.8. The method recited in claim 1 , comprising:removing the DIMM; andre-seating the DIMM.9. The method recited in claim 8 , comprising removing a contaminant from the DIMM.10. The method recited to claim 1 , where the seating error has occurred if:the DIMM that returns valid WRITE LEVELING data; andthe DIMM is not detected.11. A computer system for detecting DIMM seating errors claim 1 , the computer system comprising;a processor that is adapted to, execute ...

RESISTANCE VARIABLE MEMORY APPARATUS, READ CIRCUIT UNIT AND OPERATION METHOD THEREFOR

A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code by repeating a cyclic analog-to-digital conversion (ADC) process a designated number of times, generate read data from the digital code, and output the generated read data during a normal read mode for the memory cell array, and to generate test data corresponding to the cell current and output the generated test data during a test read mode for the memory cell to array. 1. A resistance variable memory apparatus comprising:a memory cell array; anda read circuit unit configured to receive a cell current, generate a digital code by repeating a cyclic analog-to-digital conversion (ADC) process a designated number of times, generate read data from the digital code, and output the generated read data during a normal read mode for the memory cell array, and to generate test data corresponding to the cell current and output the generated test data during a test read mode for the memory cell array.2. The resistance variable memory apparatus according to claim 1 , wherein the read circuit unit comprises:a sense amplifier configured to output a cell current corresponding to a resistance state of a memory cell; anda data output unit configured to receive the cell current and a threshold current, generate the digital code by repeating the cyclic ADC process the designated number of times based on a preset normal reference voltage, and generate the read data from the digital code during the normal read mode, and to generate the test data corresponding to the cell current based on a preset test reference voltage during the test read mode.3. The resistance variable memory apparatus according to claim 2 , wherein the data output unit comprises:a first determination section configured to generate a pre-MSB (most significant bit) code based on a comparison result between the cell current and the threshold current;a second ...

EEPROM ARCHITECTURE WHEREIN EACH BIT IS FORMED BY TWO SERIALLY CONNECTED CELLS

An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors. 1. An integrated circuit , comprising:a first bit line;a second bit line; and a first select transistor;', 'a second select transistor;', 'a first floating gate transistor for storing said single data bit; and', 'a second floating gate transistor for storing said single data bit;, 'a first memory cell configured to store a single data bit, comprisingwherein source-drain paths of the first and second select transistors and the first and second floating gate transistors are coupled in series with each other between the first bit line and the second bit line;wherein gate terminals of the first and second select transistors are connected to a same first word line for the first memory cell.2. The integrated circuit of claim 1 , wherein gate terminals of the first and second floating gate transistors are connected to a same control gate line for the first memory cell.3. The integrated circuit of claim 2 , further comprising a control circuit coupled to the word line claim 2 , the control gate line claim 2 , the first bit line and the second bit line claim 2 , said control circuit configured to perform read claim 2 , erase and program operations on the first memory cell.4. The ...

ELECTRONIC MEMORY DEVICE AND TEST METHOD OF SUCH A DEVICE

The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously. 1. A method for testing an electronic memory device , the electronic memory device comprising:a memory matrix organized in rows and columns, the memory matrix having memory cells, wherein the cells of one row are forming one or more memory words;an address decoder with address input lines for selecting a row according to a particular address given on the address input lines, the address defined by fixed number of bits;read/write lines for reading/writing at least one word of a row selected by the particular address;additional address mask input lines, each address mask input line assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line;the method for testing one particular bit of the address other than the lowest bit of the address comprising the steps of:A) erasing the memory matrix by putting all address mask input lines into an activated state;B) putting all address mask input lines in an activated state except the particular bit of the assigned address mask input line to ignore all bits of the address except the particular bit to be tested;C) setting the particular bit of the address to 0;D) performing a write operation with a same dedicated word for different selected lines;{'b': '0', 'E ...

NON-INTRUSIVE PERFORMANCE MONITOR AND SERVICE ENGINE

A method of monitoring a plurality of storage devices using a storage management system includes receiving and analyzing input/output data related to the storage devices and generating a model in response to the monitoring, including the detected input/output data related to at least a first and a second storage device, and where the input/output data includes at least one measurable storage device aspect. The method also includes determining, in response to the generating, that the first storage device is a control storage device, and that the second storage device is to be compared to the first storage device and comparing the input/output data of the second storage device to the first storage device according to the at least one measurable storage device aspect. The method also includes determining that the second storage device is operating sub-optimally and transmitting a notification that the second storage device is operating sub-optimally. 1. A method , comprising:monitoring a plurality of storage devices using a storage management system, wherein the monitoring includes receiving and analyzing input/output data related to the storage devices;generating a model in response to the monitoring, wherein the model includes the detected input/output data related to at least a first and a second storage device, and wherein the input/output data includes at least one measurable storage device aspect;determining, in response to the generating, that the first storage device is a control storage device, and that the second storage device is to be compared to the first storage device;comparing the input/output data of the second storage device to the first storage device according to the at least one measurable storage device aspect;determining that the second storage device is operating sub-optimally; andtransmitting a notification that the second storage device is operating sub-optimally.2. The method of claim 1 , wherein the monitoring is performed host side using an ...

Voltage trimming circuit

A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

WRITE METHOD AND WRITE APPARATUS FOR STORAGE DEVICE

A write method and a write apparatus for a storage device, where the write method includes: acquiring n numerical values that need to be written; determining n bits corresponding to the n numerical values, and information about a stuck-at fault included in the n bits; grouping the n bits into B groups of bits, so that the B groups of bits meet a grouping condition; and correspondingly writing the n numerical values according to information about a stuck-at fault included in each group of bits in the B groups of bits and a numerical value that needs to be written and that is corresponding to the information about the stuck-at fault included in each group of bits in the B groups of bits. 1. A write method for a storage device , the method comprising:determining n bits in the storage device, wherein the n bits include stuck-at fault bits, wherein the stuck-at fault bits comprise a stuck-at right fault bit and a stuck-at wrong fault bit, wherein a value of the stuck-at right fault bit is the same as a value to be written to the stuck-at right fault bit, and a value of a stuck-at wrong fault bit is opposite to a value to be written to the stuck-at wrong fault bit;grouping the n bits into B groups according to the stuck-at fault bits, wherein each group comprises at most A bits grouped with one type of stuck-at fault, and wherein stuck-at fault bits in each group are of a same type corresponding to the one type of stuck-at fault with the group; andwriting values into bits of the group according to the one type of stuck-at fault with the group, wherein n, A, and B are positive integers, and n≤A×B.2. The write method according to claim 1 , wherein the grouping the n bits into B groups comprises:generating an array of B rows and A columns to represent the n bits, wherein the B groups are obtained based on the array, and wherein any two of the n bits that belong to a same group are represented in different rows and columns, or any two bits that belong to a same group are ...

DYNAMIC HARD ERROR DETECTION

An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition. 1. An apparatus for detecting hard errors , comprising:a storage device having stored therein test data and normal data; anda processing circuit comprising combinational logic in series with at least one set of input latches and at least one set of output latches; anda test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.2. The apparatus of claim 1 , wherein halting the flow of normal data through the processing circuit includes stopping the flow of the normal data into normal data inputs of the at least one set of input latches and storing the normal data from the at least one set of input latches and the at least one set of output latches in the storage prior to running the test data through the processing circuit.3. The apparatus of claim 2 , wherein the processing circuit is further configured to restore the normal data to the at least one set of input latches and the at least one set of output latches based on determining that a number of hard errors in the processing circuit is less than a predetermined threshold.4. The apparatus of claim 2 , wherein both of the normal data and the test data are input through normal data inputs of the at least one set of input latches and read out from normal data outputs of the at ...

HAMMING-DISTANCE ANALYZER

A device is disclosed that includes a memory array, a comparing circuit, and a calculating circuit. The memory array is configured to store a first response of an under-test device. The comparing circuit is configured to compare the first response with a plurality of responses of the under-test device operated in conditions that are different from each other to generate comparing results. The calculating circuit is configured to output a maximum hamming distance between two of the first response and the plurality of responses according to the comparing results. 1. A device , comprising:a memory array configured to store a first response of an under-test device;a comparing circuit configured to compare the first response with a plurality of responses of the under-test device operated in conditions that are different from each other, to generate comparing results; anda calculating circuit configured to output, according to the comparing results, a maximum hamming distance between two of the first response and the plurality of responses.2. The device of claim 1 , further comprising:a register configured to store the comparing results for the calculation of the maximum hamming distance.3. The device of claim 1 , wherein the comparing circuit comprises:an exclusive OR gate configured to perform an exclusive OR operation of the first response and each one of the plurality of responses.4. The device of claim 1 , wherein the comparing circuit comprises:at least one exclusive OR gate configured to perform an exclusive OR operation of bits of the first response and corresponding bits of one response of the plurality of response.5. The device of claim 1 , wherein the memory array is a duplicate of an under-test memory array implemented in or by the under-test device.6. The device of claim 1 , wherein the calculating circuit comprises:a counter configured to generate a value indicating a number of bits, in a corresponding comparing result of the comparing results, having a same ...

REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED DATA BOUNDARIES

Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache. 1. A computer-implemented method executed by at least one processor for testing a computer processor device comprising:providing test data comprising a plurality of segments of test data that together make a slice of test data, wherein each of the plurality of segments are non-naturally aligned where the beginning and ending of each of the plurality of segments when placed end to end in a memory do not line up with a cache line boundary, wherein the plurality of segments comprise an odd number of words where the odd number is chosen from 5, 7, 9, and 11;placing multiple instances of the slice of test data in consecutive locations in a cache memory; andrunning a test code on the consecutive slices of test data with non-naturally aligned boundaries by branching back to rerun the test code on each of the slices of test data.2. The method of wherein the step of running a test code on the consecutive slices of test data with non-naturally aligned boundaries further comprises:executing test code with one or more test cases on a first slice of test data of the plurality of test data slices using a base offset;determining if there are additional slices of test data; andwhere there are additional slices of test data, modifying the base offset to point to a next test data slice and branching back to execute the test code with the modified base offset.3. The method of wherein the plurality ...

NONVOLITILE MEMORY REFRESH

A system and method of refreshing a nonvolatile memory having memory cells. The method includes identifying one or more of the memory cells that do not satisfy a data retention test; remapping the one or more identified memory cells from original memory addresses to spare memory addresses; and refreshing the identified memory cells. 1. A method of refreshing a nonvolatile memory having memory cells , the method comprising:identifying one or more of the memory cells that do not satisfy a data retention test;remapping the one or more identified memory cells from original memory addresses to spare memory addresses; andrefreshing the one or more identified memory cells.2. The method of claim 1 , wherein the spare addresses are located in a mapping table stored in a volatile memory.3. The method of claim 1 , wherein the spare addresses are located in a mapping table stored in a nonvolatile memory.4. The method of claim 1 , further comprising:remapping the one or more identified memory cells from the spare addresses back to the original addresses.5. The method of claim 4 , wherein the remapping of the one or more identified memory cells from the spare addresses to the original addresses is performed after the nonvolatile memory ceases to be at a temperature that is greater than a predetermined temperature.6. The method of claim 1 , wherein the identifying and remapping steps are performed at startup.7. The method of claim 1 , further comprising:identifying, using an error-correcting code algorithm, one or more of the memory cells having an error; andremapping the one or more memory cells identified as having an error from original addresses to spare memory addresses.8. The method of claim 1 , wherein the identifying and remapping steps are performed repeatedly.9. The method of claim 7 , wherein the refreshing step comprises:reading data from the one or more identified memory cells;correcting the read data the error-correcting algorithm; andwriting the corrected data to ...

APPARATUS FOR BOOSTING SOURCE-LINE VOLTAGE TO REDUCE LEAKAGE IN RESISTIVE MEMORIES

Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation. 1. An apparatus comprising:a leakage tracker to track leakage current of a column of resistive memory cells; anda circuit, coupled to the leakage tracker, for adjusting voltage on a Source Line (SL) of the column of resistive memory cells.2. The apparatus of claim 1 , wherein the circuit is to adaptively adjust the voltage on the SL.3. The apparatus of claim 1 , wherein the leakage tracker includes a replica column of resistive memory cells claim 1 , and wherein the replica column includes a Bit Line (BL) and a SL.4. The apparatus of claim 3 , wherein the circuit includes a current mirror.5. The apparatus of claim 4 , wherein the circuit includes a negative feedback path to control a voltage on a gate terminal of a transistor such that leakage current through the replica column is substantially equal to a ratio of current of the current mirror.6. The apparatus of claim 3 , wherein the SL of the replica column is electrically shorted to a SL of a data column.7. The apparatus of claim 3 , wherein at least one of the resistive memory cells includes an access transistor having a gate terminal coupled to ground claim 3 , and wherein the access transistor includes a source/drain terminal coupled to the SL.8. The apparatus of claim 1 , wherein the circuit is operable to turn on during memory read operations.9. The apparatus of claim 1 , wherein the circuit is operable to turn off during non-read ...

MAGNETIC TUNNEL JUNCTION LOADED RING OSCILLATORS FOR MRAM CHARACTERIZATION

Circuits are provided for modeling and characterizing the switching of magnetic tunnel junctions (MTJ) elements. More specifically, ring oscillators loaded with MTJ elements are used to characterize magnetic tunnel junction (MTJ) element performance. The circuits can include a ring oscillator (RO) having an odd number of inverters connected in series with a magnetic tunnel junction (MTJ) element inserted between each inverter. In some embodiments, the magnetic tunnel junction (MTJ) elements are arranged to act as a load to the inverters. The circuits optionally include one or more of a time to amplitude converter, a pulse distribution analyzer and/or PFET(s) and NFET(s). Methods of characterizing the switching characteristics of MTJ elements are also provided herein. Such MTJ elements can be suitable for use in magnetoresistive random access memory (MRAM) devices. Methods of making the ring oscillator are further provided herein. 1. A circuit for characterizing switching characteristics of a magnetic tunnel junction element , the circuit comprising:an odd number of inverters connected in series, wherein each inverter forms a stage; anda plurality of magnetic tunnel junction elements configured such that a magnetic tunnel junction element is electrically connected between each of the inverter stages,wherein the inverter stages and the plurality of the magnetic tunnel junction elements are configured in a ring oscillator (RO), andwherein the number of inverters is (2n+1), wherein n is an integer between 1-100 and wherein the number of magnetic tunnel junction elements is n.2. The circuit of claim 1 , wherein a frequency (f) of the ring oscillator is delayed by R×C claim 1 , wherein Ris the resistance of the magnetic tunnel junction element and Cis the input capacitance of the inverter.3. The circuit of claim 1 , further comprising a source of applied voltage (Vdd) to the ring oscillator.4. The circuit of claim 1 , wherein the plurality of the magnetic tunnel junction ...

MITIGATION OF SOLID STATE MEMORY READ FAILURES WITH A TESTING PROCEDURE

Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability. 1. A method for testing for read failures in a solid-state memory device , the method comprising:initiating a test procedure on a memory region of the solid-state memory device in response to a trigger;modifying an error correction capability of the solid-state memory device from an operational error correction capability to a test error correction capability;detecting an uncorrectable read error on a first memory portion of the memory region, the uncorrectable read error being based on the test error correction capability;tracking a region read fail metric based on the uncorrectable read errors per memory region;comparing the region read fail metric to an error threshold; anddetermining whether to retire the memory region based on the region read fail metric in relation to the error threshold.2. The method of claim 1 , wherein the initiating operation includes cessation of memory read operation from a host device.3. The method of claim 2 , wherein the uncorrectable read error is in response to a test read operation performed on one or more first memory portions of the memory region.4. The ...

Semiconductor memory device and method of testing the same

A semiconductor memory device may include: a memory cell array including first and second word lines coupled to first and second memory cells, respectively; a word line driving unit suitable for selectively driving the first and second word lines; and a test control unit suitable for enabling the first word line to write test data to the first memory cell, and enabling the second word line to write the test data to the second memory cell, during a test operation.

MECHANISM TO SUPPORT RELIABILITY, AVAILABILITY, AND SERVICEABILITY (RAS) FLOWS IN A PEER MONITOR

A mechanism to support reliability, availability, and serviceability (RAS) flows in a peer monitor is disclosed. A method of the disclosure includes receiving, by a processing device, a system management interrupt (SMI) event. The method further includes invoking, in response to the SMI event, a privilege manager to execute from a read-only memory (ROM) entry point to handle the SMI event, the privilege manager comprising a hot plug service module to provide support for memory hot plug functionality and processor hot plug functionality. 125.-. (canceled)26. A method for supporting reliability , availability , and serviceability (RAS) flows in a peer monitor , comprising:receiving, by a processing device, a system management interrupt (SMI) event; andinvoking, by the processing device in response to the SMI event, a privilege manager to execute from a read-only memory (ROM) entry point to handle the SMI event, the privilege manager comprising a hot plug service module to provide support for memory hot plug functionality and processor hot plug functionality.27. The method of claim 26 , wherein the privilege manager is a system management interrupt (SMI) transfer monitor (STM).28. The method of claim 26 , wherein the privilege manager comprises a hypervisor executing system management mode (SMM) code of a basic input/output system (BIOS) as a guest of the privilege manager.29. The method of claim 26 , wherein the privilege manager is to execute an error check on read-access memory (RAM) subsequent to invocation.30. The method of claim 29 , wherein the privilege manager is to access a transition data structure to verify an integrity of the RAM for the error check.31. The method of claim 30 , wherein the transition data structure maintains data comprising at least one of a size of the privilege manager in the ROM claim 30 , a size of the privilege manager in the RAM claim 30 , a cyclic redundancy check (CRC) value claim 30 , a check value claim 30 , a hash claim 30 , or ...

Methods and apparatuses using a transfer function to predict resistance shifts and/or noise of resistance-based memory

Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.

TEST CIRCUIT OF SEMICONDUCTOR APPARATUS

A test circuit of a semiconductor apparatus includes a plurality of memory blocks, and a comparison block configured to compare data of two memory blocks, wherein the two of the plurality of memory blocks do not share word lines. 1. A test circuit of a semiconductor apparatus , comprising:a plurality of memory blocks; anda comparison block configured to compare data of two of the plurality of memory blocks, wherein the two of the plurality of memory blocks do not share word lines.2. The test circuit according to claim 1 , wherein the plurality of memory blocks are configured to share claim 1 , by the unit of a pair of memory blocks claim 1 , one of even-numbered word lines and odd-numbered word lines.3. The test circuit according to claim 1 , wherein the comparison block is configured to perform a parallel test in where pluralities of data of the two memory blocks are compared with each other claim 1 , wherein the two memory blocks do not share word lines.4. The test circuit according to claim 1 , wherein the word lines comprise sub word lines.5. A test circuit of a semiconductor apparatus claim 1 , comprising:a plurality of memory blocks;a first comparison block configured to select a first pair of alternate memory blocks in series of the plurality of memory blocks, and to compare data of the selected first pair of alternate memory blocks; anda second comparison block configured to select a second pair of alternate memory blocks in the series of the plurality of memory blocks, and to compare data of the selected second pair of alternate memory blocks, wherein the memory blocks in the first pair of memory blocks are different from the memory blocks in the second pair of memory blocks.6. The test circuit according to claim 5 , wherein the first pair of alternate memory blocks selected by the first comparison block and second pair of alternate memory blocks selected by the second comparison block are configured to not share word lines.7. The test circuit according to ...

MEMORY CONTROLLER AND MEMORY SYSTEM

A controller according to one embodiment controls a memory, the memory including blocks and configured to erase data in the blocks with each of the blocks as a minimum unit. Each of the blocks includes unit memory areas each specified by an address. The controller is configured to add a code for error correction to received data to generate a data unit, divide the data unit into data unit sections, and write the data unit sections in unit memory areas of respective blocks, the unit memory areas having different addresses. 1. A controller which controls a memory , whereinthe memory comprises blocks and is configured to erase data in the blocks with each of the blocks as a minimum unit,each of the blocks comprises unit memory areas each specified by an address, add a code for error correction to received data to generate a data unit;', 'divide the data unit into data unit sections, and', 'write the data unit sections in unit memory areas of respective blocks, the unit memory areas having different addresses., 'the controller is configured to2. The controller of claim 1 , whereineach of the blocks comprises word lines each having an address unique within that block,each of the word lines specifies a physical unit comprising memory cells coupled to that word line, andeach of the unit memory areas comprises at least a physical unit.3. The controller of claim 2 , whereinthe memory has a substrate,the physical units are formed above the substrate, andphysical units having the same address in respective blocks are located at the same height from the substrate.4. The controller of claim 1 , wherein generate data units in parallel, and', 'write respective data unit sections of the data units in the blocks in parallel., 'the controller is further configured to5. The controller of claim 1 , whereinthe controller is further configured to write data unit sections of a data unit in the blocks in parallel.6. The controller of claim 1 , wherein use blocks having the same address as ...

System For Testing Memory And Method Thereof

A system for testing memory and a method thereof are disclosed. In the system, a physical address range of at least one memory module is converted into a logical address range of the memory, and a read and write test is performed on the memory according to the logical address range of the memory, and an error message corresponding to the memory is detected during the read and write test, and a logical address contained in the error message is converted into a physical address of the memory module corresponding to the logical address, so as to improve test coverage and validity of memory test, and effectively determine the problematic memory module, thereby achieving the technical effect of preventing the test program from being closed by the operating system.

MEMORY APPARATUS FOR IN-CHIP ERROR CORRECTION

A method of performing memory deduplication and single error correction double error detection (SEC-DED) in a computer memory, the method including reading data from an array of memory chips, calculating at least one hash based on the data, checking the one or more hashes against at least one of a physical line ID hash and against a secondary hash, determining whether an error is detected, when an error is detected, correcting the data by changing each bit of the array of the memory chips one at a time until no error is detected, wherein between changing each bit, at least one hash is calculated based on the changed data, and the one or more hash for the new data is compared against one or more of a physical line ID hash and against a secondary hash, and again determining whether an error is detected, and outputting the corrected data when no error is detected. 1. A method of performing memory deduplication and single error correction double error detection (SEC-DED) in a computer memory , the method comprising:reading data from an array of memory chips;calculating at least one hash based on the data;checking the one or more hashes against at least one of a physical line ID hash and against a secondary hash;determining whether an error is detected;when an error is detected, correcting the data to generate new data by changing each bit of the array of the memory chips one at a time until no error is detected;wherein between changing each bit, at least one hash is calculated based on the changed data, and the one or more hash for the new data is compared against one or more of a physical line ID hash and against a secondary hash, and again determining whether an error is detected; andoutputting the corrected data when no error is detected.2. The method of claim 1 , wherein the data comprises eight bytes.3. The method of claim 1 , wherein the array of memory chips comprises 4-bit memory chips.4. The method of claim 1 , wherein the array of memory chips comprises ...

ERROR CORRECTION FOR NON-VOLATILE MEMORY

Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell. 1. A method of error correcting data for writing to a memory comprising:determining whether the memory includes a defective memory cell;receiving a message to be written to the memory;sub-dividing the message into a plurality of sub-messages;generating a first error correction code for the sub-messages, the first error correction code being a first type;generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type;generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes; andwriting the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.2. The method of claim 1 , wherein the memory is a non-volatile memory storage system claim 1 , memory module claim 1 , or CPU cache memory.3. The method of claim 2 , wherein the non-volatile memory storage system is a solid state drive.4. The method of claim 1 , wherein an output of the defective memory ...