Method of self-testing a random access memory (RAM) of a circuit

During operation of a flight-critical or safety-critical circuit, e.g. of an on-board computer, only certain types of error of a RAM can be tested. Since such computers are necessarily of the Neumann type, RAM self-tests by programs take up part of the computer power. The RAM self-test device of the invention uses address and data information which is available to the central processing unit of the computer to generate RAM test area information, so that the RAM self-test device can almost always carry out its RAM tests at the maximum speed of the RAM, and thus carry out the following tests: physical cells which are not adjacent to each other, and maximum speed tests of the read amplifier. The device uses the information listed above to predict whether the cells to be tested will be required for the next cycles or not, and thus whether they will be available for the test.

Verfahren und Vorrichtung zur Erzeugung digitaler Signalmuster

Associative memory circuit device, e.g. content addressable memory

The method involves using a test pattern with zero to the number of rows less 1 (m-1) input signals formed by a test circuit with an input and an output with corresponding flip-flop inputs for each cell of a row, and provided with sensing inputs and outputs. The input-sense-flip-flop is controlled by the same clock pulse. At the start, all the associative cells in an m*n array are initialised after which the test pattern is initialised. The logic value of one of the input signals (j) is then inverted during the time that the test pattern with that row number is actualised. The test pattern is then inscribed in the i-th column of the associative memory cells during the actualisation of te i-th column. The j-th row of the memory array is then compared for each of the columns within which the contents of the j-th input signal is held.

SYSTEM ZUR OPTIMIERUNG VON SPEICHERREPARATURZEIT MIT PRÜFDATEN

Memories and the testing thereof

A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage word. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accessed by an address line failure. The method according to the ...

MEMORIES AND THE TESTING THEREOF

Method and system for fault coverage testing memory

DETECTING A FAULT IN A MEMORY DEVICE

Data processing system with self-test

A data processing system employing firmware for executing a self test routine each time the system goes through the power-up cycle. The self test firmware provides for compilation of a system configuration map during each execution so that configuration and status data is made available for accessing by the system operation firmware and application software. This enables external systems to set appropriate interrupt vectors and levels and to arrange their physical I/O and device handlers so that various devices within the local system can be accessed. The routines performed in the self test operation include a CPU test, a RAM test, a real time clock test, a communication controller loop-back test, a ROM signature calculation, a controller I/O test, a system configuration map compilation, and a status display routine.

DETECTING FAULTS IN A MEMORY DEVICE

System for optimizing memory repair time using test data

DIGITAL SIGNAL SCRAMBLER

A digital signal scrambler for use in testing semiconductor memory circuits such as RAMs. The scrambler is comprised of look-up tables in conjunction with EXCLUSIVE OR logic circuitry, for receiving generated address and data signals and transmitting scrambled signals in response thereto, conforming to the predefined topological scrambling function of the memory circuit being tested. The digital signal scrambler of the present invention is of simple and inexpensive design, is easy to use and typically occupies very little circuit board area.

MEMORY MANAGEMENT METHOD AND APPARATUS

MEMORY MANAGEMENT METHOD AND APPARATUS Apparatus and method for vital memory management of data. Method and apparatus is disclosed for clearing memory on specified conditions and for assuring the clearing is effected. Both random access and stack operation are implemented. Furthermore, an intentional delay may be provided to ensure that data using apparatus properly interprets the signals provided thereto. Included is a word testing method and apparatus which is also arranged to be self-checking.

MEMORY MANAGEMENT METHOD AND APPARATUS

PROCESS AND DEVICE FOR the Control Of a NUMERICAL MEMORY

Apparatus for locating faults in a working storage

METHOD FOR TESTING THE OPERATION OF PUFS

Procédé pour tester le fonctionnement d'un PUF caractérisé en ce qu'il utilise une signature de référence et des signatures mesurées lorsque le PUF est soumis à un ensemble de stimuli.

DETECTION CIRCUIT OF THE DEFECTS OF THE MEMORIES

SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY SWITCHING METHOD

MEMORY DIAGNOSIS APPARATUS

A memory diagnosis apparatus comprises: an in-word test means for testing coupling faults between the bits within a word on a word-by-word basis in a memory; an inter word test means for testing coupling faults between the words within a partial array for each partial array consisting of a plurality of words in the memory; and an inter block test means for testing coupling faults between the partial arrays in the memory. The memory diagnosis apparatus can perform a quick coupling fault diagnosis while maintaining the diagnostic accuracy at a certain level. © KIPO & WIPO 2008 ...

UNIVERSALLY ACCESSIBLE FULLY PROGRAMMABLE MEMORY BUILT-IN SELF-TEST (MBIST) SYSTEM AND METHOD

A universally accessible fully propammable memory built-in self-test (MBIST) system including an MBIST controller (60) having an address generator (64) configured to generate addresses for a memory under test (66), a sequencer circuit (68) configured to deliver test data to selected addresses of the memory under test (66) and reading out that test data, a comparator circuit (72) configured to compare the test data read out of the memory under test (66) to the test data delivered to the memory under test to identify a memory failure, and an externally accessible user programmable a pattern register (70) for providing a pattern of test data to the memory under test (66). The system includes an external pattern programming device (75) configured to supply the pattern of test data to the user programmable data pattern register (70).

Checking data integrity in buffered data transmission

Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values. The method comprising the following stages: combination of the data to be read in with a value generated by a first counter (20) in accordance with an exclusive-OR operation; reading the logically combined data into the memory (50); reading the logically combined data from the memory (50); combination of the logically combined data read out with a value generated by a second counter (80) in accordance with an exclusive-OR operation; checking the ...

Method and apparatus for converting logic test vectors to memory test patterns

Logic test vectors, used for testing logic circuitry on a logic tester, are converted to test patterns having a format that is used by a memory tester. This allows an integrated circuit having both logic circuitry and a memory array to be tested on a memory tester. A software tool, or computer program, is used to convert the logic test vectors to test patterns, and also generates the memory test code for applying the test patterns to, for example, a logic intensive integrated circuit memory. The software tool is encoded using a high-level programming language and is executed on a computer system (60). The program allows the logic intensive integrated circuit memory to be tested on a memory tester, as compared to testing the integrated circuit memory on a logic tester, significantly reducing testing costs associated with manufacturing.

Semiconductor memory testing apparatus

A memory unit for storing failure data of a semiconductor memory under test comprises a plurality of interleaved DRAMs. A buffer memory temporarily stores failure data to be stored into the DRAMs and addresses thereof. The DRAMs are associated respectively with storage controllers which store failure addresses whose row addresses correspond to the DRAMs, among inputted failure addresses, into buffer memories associated respectively with the DRAMs. Write controllers are associated respectively with the DRAMs, for reading the failure data from the buffer memories and writing the failure data into the DRAMs in a high-speed write mode.

Method and apparatus for testing random access memory

A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is modified to produce a set of modified data. The modified data is then written to another address in the memory. The steps of reading, modifying, and writing modified data back to the memory are repeated until all addresses in the memory have been written to. Thereafter, the data values stored in the memory are compared to a reference list of data values to determine whether the memory contains a detect. In phase two, the steps of phase one are repeated except that the first address in the memory is initialized by writing a set of data which is the complement of the initial set of data used in phase one. Phase two, in effect, complements the contents of each address in the memory to ensure that each cell in the memory is written with both ...

Methods and apparatus for testing integrated circuits

In some aspects a method is provided for testing an integrated circuit (IC). The method includes the steps of selecting a bit from each of a plurality of memory arrays formed on an IC chip, selecting one of the plurality of memory arrays, and storing the selected bit from the selected memory array. Numerous other aspects are provided.

Method and apparatus for converting logic test vectors to memory test patterns

Logic test vectors, used for testing logic circuitry on a logic tester, are converted to test patterns having a format that is used by a memory tester. This allows an integrated circuit having both logic circuitry and a memory array to be tested on a memory tester. A software tool, or computer program, is used to convert the logic test vectors to test patterns, and also generates the memory test code for applying the test patterns to, for example, a logic intensive integrated circuit memory. The software tool is encoded using a high-level programming language and is executed on a computer system (60). The program allows the logic intensive integrated circuit memory to be tested on a memory tester, as compared to testing the integrated circuit memory on a logic tester, significantly reducing testing costs associated with manufacturing.

Method and apparatus for testing random access memory

A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is modified to produce a set of modified data. The modified data is then written to another address in the memory. The steps of reading, modifying, and writing modified data back to the memory are repeated until all addresses in the memory have been written to. Thereafter, the data values stored in the memory are compared to a reference list of data values to determine whether the memory contains a defect. In phase two, the steps of phase one are repeated except that the first address in the memory is initialized by writing a set of data which is the complement of the initial set of data used in phase one. Phase two, in effect, complements the contents of each address in the memory to ensure that each cell in the memory is written with both ...

Hardware-assisted high speed memory test apparatus and method

A board-mounted memory array includes a plurality of memory modules, each module N bits wide by M bits long, the memory array including YM addresses of words that are XN bits long, where X and Y are integers. Each word is comprised of N bits from a common address value in each of X modules. The memory array includes memory interface logic mounted on the board which accesses the memory array in response to address signals. The memory interface logic is configured to use a first address procedure to access individually addressed words in the memory array at a first rate and, upon command, to use a second address procedure to sequentially access a span of contiguous addresses at a second, higher rate. A controller is coupled to the memory interface logic and enables application of address signals generated external to the board. Hardware test circuitry is resident on the board and controls the memory interface logic to implement the second address procedure and to apply test signals to a plurality ...

Data invert jump instruction test for built-in self-test

A data invert jump instruction test for a built-in self-test of a memory device is provided. The data invert system comprises a read only memory (72) operable to store a plurality of test algorithms wherein at least one of the test algorithms includes a data invert jump instruction (160). Also included is a data invert circuit (178) coupled to the read only memory (72) and a toggle register (188) within the data invert circuit (178). The toggle register (188) is set to one when the data invert jump instruction (160) occurs for the first time in the test algorithm. This causes the data invert circuit (178) to output the inverse of the data inputted through the data invert circuit (178).

Manufacturing testing for LDPC codes

An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

Circuit and method of testing semiconductor memory devices

A circuit for testing a semiconductor memory device includes a data comparator and a signal aligner. The data comparator compares a first output data and a second output data provided from an output buffer circuit. The data comparator determines whether logical states of the first output data and the second output data are identical to generate a comparison signal. The signal aligner aligns the first output data and the comparison signal, and generates a plurality of test signals in response to a clock signal. The test signals includes an even bit test data, an odd bit test data, an even bit comparison test data and an odd bit comparison test data. The even bit data and the odd bit data are simultaneously tested by using one pattern, and a correct test result is yielded even when test data are all inverted.

TECHNOLOGIES FOR APPLICATION VALIDATION IN PERSISTENT MEMORY SYSTEMS

Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.

MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE

Provided herein is a memory device and a method of operating the memory device. The memory device may include a one or more memory blocks, one or more peripheral circuits configured to perform an erase operation and a threshold voltage distribution scan operation on a selected memory block, and a control logic configured to control the one or more peripheral circuits, and determine the selected memory block to be a normal memory block or a defective memory block based on a result of the threshold voltage distribution scan operation.

MEMORY REPAIR USING OPTIMIZED REDUNDANCY UTILIZATION

A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

TEST OF RAM ADDRESS DECODER FOR RESISTIVE OPEN DEFECTS

Method of and apparatus for diagnosing failures in read only memory systems and the like

A semiconductor memory such as a read only memory (ROM) is tested and faults are diagnosed and identified by examining data stored therein for patterns that could not exist if the memory is faulty, proving the memory to be functional by counterexample. Diagnosis is carried out using probabilistic algorithms that terminate quickly if the memory is not faulty, with any pathological contents of the memory masked to minimize the likelihood of misdiagnosis. Faults diagnosed in accordance with the invention include stuck or tied data or address lines.

A method for in-factory testing of flash EEPROM devices

NONVOLATILE SEMICONDUCTOR MEMORY

PURPOSE: To prevent over erasing by preforming adequate erasing operation for memory cells other then memory cells (defective cells) in which erasing is slow. CONSTITUTION: When 'erasing to/from erasing verifying' is repeated in erasing operation of a memory cell array (7), a defective count circuit (10) is operated. When it is judged that the number of cells in which erasing are not yet finished (cells in which erasing is slow) are less than the prescribed numbers, by finishing erasing operation, adequate erasing operation for almost cells excluding cells of several bits in which erasing is slow can be realized, and over erasing is prevented. COPYRIGHT: (C)1996,JPO ...

SEMICONDUCTOR CIRCUIT AND TEST METHOD FOR THE SAME

PROBLEM TO BE SOLVED: To provide a semiconductor circuit which can be tested efficiently, and a test method for the same. SOLUTION: To test a semiconductor circuit, first, a basic format for test pattern including at least one argument and a test program for testing a semiconductor circuit to be tested is created and stored in a testing device. Next, a predetermined value is set for the argument, and a test pattern including the test program and the argument set with the predetermined value is created and supplied to the semiconductor circuit to be tested. Next, the test program is stored in a first address of a memory section which is provided in the semiconductor circuit and the argument set with the predetermined value is stored in a second address of the memory section. The test program stored in the first address is then executed while referring to the argument stored in the second address. COPYRIGHT: (C)2012,JPO&INPIT ...

Verfahren zum Überwachen des Inhalts eines Datenspeichers

Schaltung und Methode zur Selbstprüfung eines Speichers in einem Gatterfeld mit bidirektionaler Symmetrie.

Prüfvorrichtung und Prüfverfahren

Prüfvorrichtung, die eine geprüfte Vorrichtung prüft, aufweisend: einen Musterspeicher, der zu der geprüften Vorrichtung auszugebende Daten speichert; eine Vorrichtungsbeurteilungsschaltung, die beurteilt, ob die geprüfte Vorrichtung gut oder schlecht ist, auf der Grundlage eines von der geprüften Vorrichtung ausgegebenen Ausgangssignals; eine Speicherschaltung für die Anzahl von Dateninformationen, die die Anzahl von Dateninformationen auf der Grundlage der Anzahl von in in dem Musterspeicher zu speichernden Eingangsdaten enthaltenen logischen H-Daten speichert; einen Zähler, der von dem Musterspeicher zu der geprüften Vorrichtung ausgegebene Ausgangsdaten empfängt, und die Anzahl von in den Ausgangsdaten enthaltenen logischen H-Daten zählt; eine Musterbeurteilungsschaltung, die beurteilt, dass die in dem Musterspeicher gespeicherten Daten korrekt sind, wenn die in der Speicherschaltung für die Anzahl von Dateninformationen gespeicherte Anzahl von Dateninformationen über die Eingangsdaten ...

Speicherdiagnosevorrichtung, Speicherdiagnoseverfahren und Programm

Ein zu diagnostizierender RAM (200) wird in n (n ist eine ganze Zahl gleich 3 oder größer) Stücke von Basisbereichen geteilt. Während einer ungenutzten Zeit der periodischen Verarbeitung, die in einem System durchgeführt wird, in welchem der RAM (200) enthalten ist, werden zwei Basisbereiche aus den geteilten Basisbereichen ausgewählt, und die beiden ausgewählten Basisbereiche werden diagnostiziert unter Verwendung eines Diagnoseverfahrens, das in der Lage ist, einen Kopplungsfehler zu erfassen. Danach werden während einer ungenutzten Zeit der periodischen Verarbeitung Operationen des Auswählens eines nicht ausgewählten Paars von Basisbereichen und des Diagnostizierens des ausgewählten Paares wiederholt, um alle Kombinationen von Paaren zu diagnostizieren.

An apparatus for generating pulses and a method of testing storage products using such apparatus

This discloses a pattern generator having a programmable product cycle timer in which a pulse train, i.e., the pattern generated can be repeated or switched from a first pulse frequency to a second pulse frequency without the usual transient switching periods between pulses. The invention accomplishes this by providing the generator with a cycle timer using a clock operating in conjunction with a down counter so that at a pre-selected time interval, before the end of the pulse is achieved, a test is made to determine if a required condition needing a different pulse frequency exists. If such a condition does not exist the present pulse frequency is reinitiated so that at count 0 it is repeated without delay. If the required condition does exist loading of the needed pulse frequency is initiated so that upon termination of the presently existing pulse at count 0, the newly selected pulse will be introduced into the product being tested without delay.

PROCEDURE AND DEVICE FOR THE INTERNAL PARALLEL TEST OF SEMICONDUCTOR MEMORIES.

Method and system for fault coverage testing memory

DATA PROCESSING SYSTEM WITH SELF TESTING AND CONFIGURATION MAPPING CAPABILITY

A data processing system employing firmware for executing a self test routine each time the system goes through the power-up cycle. The self test firmware provides for compilation of a system configuration map during each execution so that configuration and status data is made available for accessing by the system operation firmware and application software. This enables external systems to set appropriate interrupt vectors and levels and to arrange their physical I/O and device handlers so that various devices within the local system can be accessed. The routines performed in the self test operation include a CPU test, a RAM test, a real time clock test, a communication controller loop-back test, a ROM signature calculation, a controller I/O test, a system configuration map compilation, and a status display routine.

METHOD OF AND DEVICE FOR TESTING A DIGITAL MEMORY

The invention provides a compact test sequence for testing integrated memories. First, all storage positions are filled with the information "O". subsequently, in a given order of the addresses the information "O" written for each address is read; immediately thereafter a "1" is written which is immediately tested thereafter by reading again. When the last address of the said order is reached, the "1" is read in the same order for each address, and subsequently a "O" is written, which is finally tested by reading again. When the last address is reached, all addresses are read in the reverse order, and a "even" is written which is tested again. When the first address is reached, all addresses are read, filled with a "O" and tested. This process is repeated, for example, as many times as there are bits in the address, the significance of the address bits being modified in order to form the said order for example, by cyclic rotation. For example, in the first cycle the order may be the normal ...

METHOD AND ARRANGEMENT FOR DETECTING FAULTS IN A MEMORY DEVICE

TELEFONAKTIEBOLAGET L M ERICSSON, S-126 25 STOCKHOLM SWEDEN METHOD OF AND ARRANGEMENT FOR DETECTING FAULTS IN A MEMORY DEVICE of disclosure: A method and an arrangement for detecting among faultless memory elements such a faulty memory element out of which the same binary digit is read independent on which of the two binary digits has been written into the element. Two element categories are introduced. If a memory element belongs to the first category normal writing and reading processes are carried out. If a memory element belongs to the second category the writing processes as well as the reading processes are combined with an inversion of the actual transferred binary information. The category of an clement is shifted at times, for example before each writing process.

METHOD OF FUNCTIONALLY TESTING CACHE TAG RAMS IN LIMITED-ACCESS PROCESSOR SYSTEMS

METHOD OF FUNCTIONALLY TESTING CACHE TAG RAMS IN LIMITED-ACCESS PROCESSOR SYSTEMS A method of functionally testing cache tag RAMs in processor systems where the kernel is typically inaccessible is disclosed. A test program first determines whether a fault exists at all within the cache tag RAM. If a fault is determined to exist, the faulty RAM location is exercised by sequentially applying patterns of ones and zeros until the pattern of bits actually present at the faulty tag RAM location is determined. A comparison of this pattern of bits with the expected bit pattern provides information as the precise location of the fault so as to permit replacement of defective chips.

반도체 기억소자의 데이터 검사 장치

... 본 발명은 반도체 기억소자의 데이터 검사 장치에 관한 것으로서, 다수의 반도체 기억소자가 적재 될 수 있도록 형성된 파레트와, 파레트를 컨베어벨트로 이동시킬 수 있는 이동장치와, 이동된 파레트를 검사위치에 맞도록 정렬하는 정렬장치와, 정렬장치 하부에 위치하여 검사위치에 정렬된 파레트와 결합되는 지그장치와, 지그장치 상부에 형성되어 반도체 기억소자에 데이터를 입력 또는 검사하도록 파레트를 가압하는 가압장치와, 가압된 파레트에 적재된 반도체 기억소자로 동시에 데이터를 입력하는 입력부와, 입력된 데이터를 검사하여 불량인지 확인하여 스캔된 품번 바코드를 기록하는 검사부와, 파레트에 적재된 반도체 기억소자가 하나 이상 불량으로 판정되면 해당 파레트만 별도로 배출시키는 배출장치를 포함하는 것을 특징으로 한다.

METHOD TO DESCRAMBLE THE DATA MAPPING IN MEMORY CIRCUITS

An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes the backwards transformation from a given set of logical data pattern. Since the method is automatic, no knowledge of the data scrambling inside the memory circuit is required. © KIPO & WIPO 2007 ...

MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR OPERATING MEMORY DEVICE

A memory device comprises: a first memory block for transceiving a signal through a first channel; a second memory block for transceiving a signal through a second channel; and a test control unit for applying multiple command signals inputted from the outside during a test to the first channel and the second channel, and applying a first command signal discriminating writing and reading from the command signals to the first channel and the second channel as different values. One of the first memory block and the second memory block, during a test, performs a reading operation, and the other performs a writing operation. Data outputted from the memory block performing a reading operation may be inputted to the memory block performing a writing operation. COPYRIGHT KIPO 2016 (210_0) First memory block (210_1) Second memory block (210_2) Third memory block (210_3) Fourth memory block (220) Test control unit ...

SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE: To shorten a test time when plural DRAM circuits incorporated in an LSI is tested and to transfer read-out data of plural DRAM circuit at high speed. CONSTITUTION: This circuit is provided with plural DRAM circuits 11, 12, a control circuit 13 having a function receiving a test control signal and performing tests for each DRAM circuit in parallel, an input selector 14 controlled by a control circuit and having a function supplying a DRAM macro- signal to plural DRAM circuits at the time of test, and an output selector 15 controlled by the control circuit and having a function selecting and controlling each output signal of plural DRAM circuits at the time of test and outputting them to a macro-output terminal 18. © KIPO & JPO 2002 ...

MEMORY DIAGNOSTIC DEVICE, MEMORY DIAGNOSTIC METHOD, AND PROGRAM

A RAM (200) to be diagnosed is divided into n base regions (where n is an integer equal to or greater than 3), two base regions are selected from the divided base regions during an idle time in periodic processing performed in a system in which the RAM (200) in mounted, and the two selected base regions are diagnosed using a diagnostic scheme capable of detecting a coupling fault. Subsequently, an operation is repeated in which a previously unselected pair of base regions is selected and the selected pair is diagnosed in each idle time in the periodic processing, and diagnosis is performed on all pairs.

MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS

A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.

Self-test of a memory device

DRAM self-test circuitry performs an on-chip test of a DRAM memory array. The self-test circuitry writes either all ones or all zeroes to each set of physical rows having the same address within the segment to be tested, and then reads the rows a set at a time. If the data bits comprising the set do not all equal one or zero, a resultant error detection signal is generated and used to latch the failed addresses into a failed address queue. If the data bits are either all zeros or ones, the next set of rows are tested. In another embodiment, the self-test circuitry also includes a mechanism for determining the performance of the addressed memory with respect to speed as well as accuracy. When either self-test is complete, the failed addresses stored in the queue may be transmitted to an external, off-chip device or analyzed and acted on by on-chip error correction circuitry. The self-test circuitry further includes circuitry to detect data bit transitions between successive failing addresses ...

Maximizing improvement to fault coverage of system logic of an integrated circuit with embedded memory arrays

Two related methods and apparatus for determining a binary constant to be output from embedded memory arrays into system logic of an integrated circuit when the system logic is being tested, that maximizes improvement to fault coverage of the system logic, are disclosed. The present invention has particular application to digital system testing. The fault coverage of the system logic is improved due to its controllability and observability are indirectly enhanced by the enhanced controllability of the embedded memory arrays. The first related method and apparatus determines the binary constant based on a testability measure selected for the system logic. The second related method and apparatus determines the binary constant based on results from automated test patterns generation for the integrated circuit. Both methods and apparatus provide a constant that is more effective than a randomly assigned binary constant, but without the expensive computations required for a binary constant determined ...

Method for built-in self-testing of ring-address FIFOs

A dual-port, RAM-type ring-address FIFO (100) is tested by causing the FIFO to execute a composite test method comprised of set of interwoven steps (( 1 )-(31 ) or (1')-(25')). Upon execution, the steps of the composite method cause the FIFO (100) to manifest all possible memory, address and functional faults. The test method manifests faults by causing the FIFO (100) to alter the state of the various flags it normally sets and by altering the logic state of the data normally produced by the FIFO.

TESTING OF NON-VOLATILE MEMORY ARRAYS

A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for VT testing for reading at least some memory cells. A second test stage including at least one second stage read uses an adjusted step size less in magnitude than the first step size for reading at least some memory cells. Provided no bit pattern match by the second test stage and/or the adjusted step size does not meet a predetermined minimum resolution (PMR), one or more additional test stages including additional array searching are added using a fixed step size less in magnitude than the adjusted step size including at least one read until a final read determines the predetermined bit pattern is matched and a fixed step size for the final read meets the PMR.

Method for reducing SRAM test time by applying power-up state knowledge

Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic data state 425 that is obtained upon power-up of an advanced technology SRAM memory device (100). The methods (400, 500, and 600) take advantage of the observation that such SRAM devices repeatedly power-up in a preferred state 310. Accordingly, one method 500 comprises powering-up 510 the memory device and reading 520 a preferred power-up data state of each cell of the memory device without memory initialization or writes. The method 500 then captures and stores 530 a data state associated with the preferred power-up data state of each cell 100 and utilizes the stored power-up data state 310 or an inverse of the power-up data state 320 to tailor 540 a test pattern used by the test algorithm 460. For example, specific 0 and 1 test pattern data in the algorithm may be replaced by the power-up data state 310 or an inverse of the power-up ...

MEMORY PROTECTION DEVICE AND METHOD

A memory protection device is used for protecting a memory. The memory protection device includes a filtering unit and an encoding unit. The filtering unit searches an input data and outputs an encoding selection signal based on a bit component pattern of the input data. The encoding unit selects one or more encoding implementations among a plurality of encoding implementations based on the encoding selection signal from the filtering unit, to encode the input data. 1. A memory protection device for protecting a memory , the memory protection device including:a filtering unit, searching an input data and outputting an encoding selection signal based on a bit component pattern of the input data; andan encoding unit, based on the encoding selection signal from the filtering unit, selecting one or more encoding implementations among a plurality of encoding implementations to encode the input data.2. The memory protection device according to claim 1 , whereinthe filtering unit searches each row data of the input data to output the encoding selection signal based on the bit component pattern of each row data of the input data, andthe encoding unit selects the respective encoding implementations among the encoding implementations based on the encoding selection signal from the filtering unit to encode each row data of the input data, and the respective encoding implementations on each row data of the input data are the same or different.3. The memory protection device according to claim 1 , wherein the bit component pattern of each row data of the input data includes: a ratio of bit “0” and/or bit “1” of each row data claim 1 , and/or a weight of bit “0” and/or bit “1” of each row data claim 1 , and/or an extent which indicates how an external environment influences each row data.4. The memory protection device according to claim 1 , whereinif the bit component pattern of a row data of the input data is higher than a threshold value, the encoding unit selects a first ...

Method of and apparatus for diagnosing failures in read only memory systems and the like

Obtaining test data for a device

Obtaining test data for a device under test includes obtaining a first part of the test data by testing the device at first points of a range of parameters using progressive sampling, and obtaining a second part of the test data by testing the device at second points of the range of parameters using adaptive sampling.

MEMORY SYSTEM QUALITY INTEGRAL ANALYSIS AND CONFIGURATION

A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system health threshold. Formulating the comparison to these metrics can include determining an area between a baseline frequency and a curve specified by the CDF-based data. In some implementations, this area can further be defined by a lowest frequency bound and/or can be compared as a ratio to an area of a rectangle that contains the CDF curve.

FAULT DIAGNOSTICS

Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Memory built-in self-test (MBIST) test time reduction

Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.

Testing of non stuck-at faults in memory

A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

METHOD TO DESCRAMBLE THE DATA MAPPING IN MEMORY CIRCUITS

An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes the backwards transformation from a given set of logical data pattern. Since the method is automatic, no knowledge of the data scrambling inside the memory circuit is required.

PATTERN GENERATING DEVICE

PROBLEM TO BE SOLVED: To provide a pattern generating device that facilitates program prepa ration in the quality judging test of memory provided with a protocol transfer system. SOLUTION: A control circuit 2 is installed to grasp the time required for an address generator 1 to generate all address patterns of one transaction and the time required for the memory 4 to be tested to finish one of the transactions and to output the control signal c which generate a dummy pattern corresponding to the time differences between these to the address generator 1. By this, after the address generator 1 generates all address patterns in one transaction in accordance with the test pattern program, a dummy pattern which adapts to the operating condition of the memory to be tested 4 is generated and the generation timing of an address pattern (a) is automatically adjusted. COPYRIGHT: (C)1998,JPO ...

メモリテスト同時判定システム

Speicher mit programmierbarer Wortlänge in einem Gatterfeld mit bidirektionaler Symmetrie.

VERFAHREN UND ANORDNUNG ZUR ERZEUGUNG ZEITLICH UNMITTELBAR AUFEINANDERFOLGENDER IMPULSZYKLEN

Circuitry and method

Method and circuitry comprising data handling circuitry having memory (instruction cache 428 or branch prediction memory 134), which in primary mode performs data handling by accessing the memory, but in secondary mode, data handling function is independent of memory. Test circuitry (memory built-in self-test MBIST) controls a test operation during execution of a data set by a data processor which executes data processing instructions by reference to the data handling function. Test circuitry controls the data handling circuitry to transition from primary to secondary modes in response to initiation of the memory test, data processor then executes data set processing instructions by reference data handling function in secondary mode whilst memory is tested (simultaneous online testing); test circuitry also controls data handler to return to primary mode on completion of test. The data handler may comprise a branch predictor 132 to predict data processor’s next data processing instruction ...

DATA PROCESSING SYSTEM WITH SELF-TEST

Improvements in or relating to Electrical Intelligence Storage Equipment

... 1,186,416. Automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. 24 Aug., 1967, No. 39051/67. Heading H4K. [Also in Division G4] In a data store having asscoiated read, write and processing circuitry, the latter is subjected to routine testing by: reading-out a word from a selected location in the store, storing the word in a temporary memory, processing the word, e.g. by inverting 0 and 1 bits and rewriting the modified word into the store at the originally selected location; reading-out the modified word and subjecting it to further processing whereby the word as originally read-out should be obtained, and writing this word back into the store; and finally reading-out the word once more, comparing it with the word stored in the temporary memory and then rewriting it again if all is well. The three stages of the test are performed during three successive access cycles of the store's address register. The test is applied whilst the store is in normal use but preferably just before ...

SWITCHING CONFIGURATION FOR TESTING A SEMICONDUCTOR MEMORY OF MEANS PARALLEL TEST WITH DIFFERENT TEST BIT SAMPLES.

PROCEDURE FOR TESTING A WHEN MACRO CELL ON A SEMICONDUCTOR COMPONENT OF ARRANGED MEMORY ACCORDING TO THE SELF CHECK PRINCIPLE.

DEVICE FOR PARALLELS EXAMINING SEMICONDUCTOR CIRCUITS

TEST OF RAM ADDRESS DECODERS ON RESISTANCE-AFFLICTED LEADER INTERRUPTIONS

METHOD OF TESTING READ/WRITE MEMORIES

MEMORY TEST METHOD AND APPARATUS

METHOD AND SYSTEM FOR FAULT COVERAGE TESTING MEMORY

EFFICIENT ADDRESS TEST FOR LARGE MEMORIES

A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage word. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accessed by an address line failure. The method according to the ...

MEMORY TEST METHOD AND APPARATUS

A method and apparatus for memory testing is described. A first pattern of data is written into the memory in a pseudo-random address sequence determined by an address generator. The first pattern is read from the memory and checked for any error. A second pattern that is the complement of the first pattern is written into the memory in a pseudorandom address sequence determined by the address generator. The second pattern is read from the memory and checked for any errors. A third pattern of data is written into the memory in the pseudo-random address sequence determined by the address generator. The third pattern of data has the effect of complementing respective check bits which are the same for the first pattern of data and the second pattern of data. The third pattern is read from memory and checked for any error.

Storage unit test method and device using method

Integrated circuit defect detection and repair

Safety enhancement for memory controllers

A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured towrite the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memoryat the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of thememory based upon the comparison.

Verifying integrity of decoding circuits of memory matrix by performing at least N or M writing of second words in storage in such way that every line and every column has at least registered second word

L'invention améliore la technique de test des circuit de décodage en réalisant des écritures par mots. Le procédé proposé par l'invention permet d'une part de s'affranchir des incertitudes de test décrites précédemment, et d'autre part de diminuer le temps de test. Dans le procédé de l'invention, on écrit un même premier mot h00 dans toute la mémoire puis on écrit des deuxièmes mots dans la matrice de mémorisation de telle manière que chaque ligne et chaque colonne ait au moins un deuxième mot d'inscrit, les deuxièmes mots étant différents du premier mot. La lecture de tout les mots de la mémoire permet de vérifier l'intégrité des circuits de décodage. Dans l'invention, il peut être prévu que, si plusieurs deuxièmes mots sont inscrits sur une même ligne ou dans une même colonne, alors les deuxièmes mots soient différents.

VERIFICATION APPARATUS AND METHOD FOR RESISTIVE MEMORY DEVICE AND DESIGN MODEL THEREFOR

A verification apparatus for a resistive memory device according to one embodiment of the present invention includes a pattern generation part configured to generate a verification pattern for verifying a resistive memory device design model; a test object which includes a core circuit part, a peripheral circuit part disposed on one side of the core circuit part and a resistor part disposed between the core circuit part and the peripheral circuit part, includes a gate level netlist of a resistive memory device design model that is laid out to integrally connect the peripheral circuit part and the register part through a data input/output line, and outputs verification data in response to the verification pattern; a behavior model for outputting expected value data in response to the verification pattern; and a checker for outputting a verification result based on the verification data and the expected value data. It is possible to accurately verify the peripheral circuit part of the resistive ...

STORAGE INTERFACE DEVICE IN A SOLID STATE DISK TESTER, CAPABLE OF REDUCING HEAT AND NOISE

PURPOSE: A storage interface device in an SSD(Solid State Disk) tester is provided to reduce gate counts by sharing a single protocol for an interface part. CONSTITUTION: An AHCI(Advanced Host Controller Interface)(171a) interfaces with command data generated from an embedded processor. A DMA(Direct Memory Access)(171a) interfaces writing data generated from the embedded processor. An SATA(Serial-Advanced Technology Attachment) transmission layer(171c) manages a transmission layer protocol of an SATA interface between the AHCI and the DMA. An SAS(Serial Attached Small computer system interface) transmission layer(171d) manages the transmission layer protocol of an SAS interface between the AHCI and the DMA. A PCIe(Peripheral Component Interconnect express) transaction layer(171e) manages a transaction layer protocol of a PCIe interface between the AHCI and the DMA. COPYRIGHT KIPO 2013 [Reference numerals] (171c) SATA transmission layer; (171d) SAS transmission layer; (171e) PCle transaction ...

METHOD AND APPARATUS FOR TESTING CACHE RAM RESIDING ON A MICROPROCESSOR

Low-jitter clock for test system

Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.

MEMORY TESTING SUPPORT METHOD AND MEMORY TESTING SUPPORT DEVICE

This memory testing support method involves: executing processes in which a plurality of test patterns are used on memory under testing; for each test pattern, recording, in a storage unit, observation results for the value of the current flowing through the memory during the execution of the processes in which the plurality of test patterns are used; and executing processes by computer for determining, on the basis of the observation results for each test pattern recorded in the storage unit, the relative merits of the plurality of test patterns with regard to the effectiveness of testing the memory.

TESTING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT IMPLEMENTING SAID TESTING METHOD

In this testing method, test data is written to a region to be tested of a memory by means of a testing circuit, the written data is read, the read data is written at a first data disposition to a result storage region of the memory, the data written to the result storage memory is read and compared to reference data, and first comparison results are acquired. Furthermore, in the testing method, while converting the writing destination in a manner so that the data read from the region to be tested of the memory is in a second data disposition differing from the first data disposition in the result storage region of the memory by means of the testing circuit, the data is re-written to the result storage region of the memory, the re-written data is read and compared to the reference data, and second comparison results are acquired. Then, the testing method identifies defective positions of memory in accordance with the first comparison results and the second comparison results.

SEMICONDUCTOR SYSTEM

A module of memory chips includes a test chip that comprises an ALPG for generating test memory patterns (addresses and data) according to a predefined algorithm, a decision circuit for comparing data written in memory with data read from memory, and storage means for storing the results of comparison (defect addresses).

Apparatus and methods for tuning a memory interface

The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

Embedded processor

Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Device and method for testing semiconductor device

A device for testing a semiconductor memory device, the device including a code table that is configured to store at least a first received code and a second received code received via a host interface, a pattern generation engine that is configured to determine a third code based on at least one of the first and the second received codes stored in the code table and to output the third code, in response to a request to perform a test operation, received via the host interface, and a signal generation unit that is configured to generate control signals for testing the semiconductor memory device, based on the third code received from the pattern generation engine.

Detecting random telegraph noise induced failures in an electronic memory

A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

ASYNCHRONOUS MEMORY ELEMENT FOR SCANNING

A scan asynchronous memory element includes: an asynchronous memory element configured to receive an n-input; and a scan control logic circuit configured to generate an n-bit signal input and the n-input to the asynchronous memory element from a scan input. The scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern, the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a previous value when the control signal has a bit pattern other than the first and second bit patterns. 1. A scan asynchronous memory element comprising:an asynchronous memory element configured to receive an n-input, where n is an integer greater than or equal to 2; anda scan control logic circuit configured to generate the n-input to the asynchronous memory element from an n-bit signal input and a scan input, wherein the scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern,', 'the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and', 'the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a current state when the control signal has a bit pattern other than the first and second bit patterns., 'as the n input to the asynchronous memory element,'}2. The scan asynchronous memory element of claim 1 , whereinthe asynchronous memory element includes a Muller's C-element.3. The scan asynchronous memory element of claim 2 , whereinthe control signal includes an n-bit signal, and a combinational logic circuit configured to output the control signal when the control signal has a pattern other than the first and second bit patterns, and output the scan input as an n-bit scan input when the ...

Latch Based Memory Device

A method of testing a latch based memory device is disclosed. The latch based memory device includes a number of latches, electrical connections and a circuit environment of the latches. A storage functionality of the latches can be tested during a first test phase while a functionality of the electrical connections and the circuit environment of the latches can be tested during a second test phase. 1. A method of testing a latch based memory device , the latch based memory device comprising a plurality of latches , electrical connections and a circuit environment of the latches , the method comprising:testing a storage functionality of the latches during a first test phase, andtesting a functionality of the electrical connections and the circuit environment of the latches during a second test phase.2. The method according to claim 1 , further comprising:connecting, in the first test phase, at least two pairs of the latches with each other so as to form a shift register chain, wherein the shift register chain is a master slave register chain in which the at least two pairs of the latches are controlled by complementary clock signals in the first test phase.3. The method according to claim 1 , further comprisingconfiguring in the second test phase at least part of the plurality of latches to a transparent state.4. The method according to claim 3 , further comprisingperforming, in the second test phase, a scan test for evaluating the correctness of the electrical connections and the circuit environment of the latches in terms of structure of the circuit.5. The method according to claim 1 , further comprisingproviding at least one test signal for controlling and performing the first or second test phase, wherein the test signal is on a constant predefined potential during the first or second test phase, respectively.6. The method according to claim 1 , wherein the latch based memory device comprises:the plurality latches, which include a first set of latches and a ...

TESTING OF NON STUCK-AT FAULTS IN MEMORY

A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell. 1. A method for testing a read-only memory (ROM) for at least one non stuck-at fault , the method comprising:generating a golden value read from a victim cell, wherein the golden value corresponds to an uncorrupted data value of the victim cell;providing a fault-specific pattern through an aggressor cell, wherein the aggressor cell is associated with a plurality of victim cells;generating a test reading of the victim cell in response to the provided fault-specific pattern; anddetermining whether the ROM has at least one non stuck-at fault based on a comparison of the golden value and the test reading of the victim cell.2. The method as claimed in claim 1 , wherein the non stuck-at fault is at least one of an address decoder open fault claim 1 , an address decoder delay fault claim 1 , and a multiple read fault.3. The method as claimed in further comprising receiving a test signal for testing the ROM for address decoder open faults.4. The method as claimed in claim 3 , wherein the generating the golden value further comprises:obtaining a second refreshing address from a previous read sequence;generating a first refreshing address for a current read sequence based at least on the second refreshing address of the previous read sequence; andreading the victim cell of the current read sequence, wherein the victim cell is at a pre-determined distance from the aggressor cell.5. The method as claimed in claim 3 , wherein the providing comprises reading the aggressor cell.6. The method as claimed in claim 3 , wherein the ...

MEMORY TESTING SUPPORT METHOD AND MEMORY TESTING SUPPORT APPARATUS

A memory testing support method includes executing a procedure using a plurality of test patterns on a memory to be tested; recording an observation result of a current value flowing in the memory during the execution of the procedure using each of the test patterns into a storing section; and determining superiority or inferiority of the test patterns in terms of effectiveness of testing the memory based on the observation results of the test patterns recorded in the storing section. 1. A memory testing support method comprising:executing a procedure using a plurality of test patterns on a memory to be tested;recording an observation result of a current value flowing in the memory during the execution of the procedure using each of the test patterns into a storing section; anddetermining superiority or inferiority of the test patterns in terms of effectiveness of testing the memory based on the observation results of the test patterns recorded in the storing section.2. The memory testing support method as claimed in claim 1 , further comprising:selecting one of the test patterns to be used for the testing of the memory based on the determination result of superiority or inferiority; andexecuting the procedure using the selected test pattern.3. The memory testing support method as claimed in claim 1 , wherein the determining determines superiority or inferiority based on a maximum value of the current value obtained for each of the test patterns.4. The memory testing support method as claimed in claim 1 , wherein the determining determines superiority or inferiority based on magnitude of change of the current value within a predetermined time claim 1 , obtained for each of the test patterns.5. The memory testing support method as claimed in claim 1 , wherein the determining determines superiority or inferiority based on a duration during which the current value exceeds a predetermined threshold value claim 1 , obtained for each of the test patterns.6. A memory ...

TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME

A semiconductor memory apparatus includes a test circuit configured to receive a plurality of sequentially-changing test input patterns, compress the received test input patterns at each clock signal, and output the compressed patterns as variable test data. 1. A semiconductor memory apparatus comprising a test circuit configured to receive a plurality of sequentially-changing test input patterns , compress the received test input patterns at each clock signal , and output the compressed patterns as variable test data.2. The semiconductor memory apparatus according to claim 1 , wherein claim 1 , when receiving the plurality of test input patterns claim 1 , the test circuit determines whether or not the test data set in response to the test input patterns are outputted claim 1 , thereby deciding whether or not an input path has a defect.3. The semiconductor memory apparatus according to claim 1 , wherein the test circuit comprises an input unit configured to determine whether to enable the test circuit and enter a test mode based on a received test mode signal.4. A test circuit of a semiconductor memory apparatus claim 1 , comprising:a plurality of input units configured to receive a plurality of sequentially-changing test input patterns, respectively, during a test mode; anda compression unit comprising a plurality of XOR gates configured to receive the respective test input patterns received by the input units and a plurality of registers alternately connected to the XOR gates and forming a chain structure, and configured to finally output an output signal of the register positioned at the last stage as test data.5. The test circuit according to claim 4 , wherein the input unit is configured to enable the test circuit and enter a test mode when an activated test mode signal is received.6. The test circuit according to claim 4 , wherein each of the XOR gates performs a logic operation on the received test input pattern and an output signal of the register positioned ...

SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME

A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set. 1. A semiconductor memory device comprising:a memory cell array including a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell including a magnetic tunnel junction (MTJ) element and a cell transistor, the MTJ element including a free layer, a barrier layer and a pinned layer, a gate of the cell transistor coupled to a wordline, a first electrode of the cell transistor coupled to a bitline via the MTJ element, a second electrode of the cell transistor coupled to a source line;a mode register set configured to set a test mode; anda test circuit configured to perform a test operation by using the mode register set.2. The semiconductor memory device of claim 1 , wherein the test mode includes at least one of a read leveling test mode for adjusting a skew between a clock signal and a data strobe signal claim 1 , a parallel bit test mode for detecting failed cells among the STT-MRAM cells claim 1 , and a ...

MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS

A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode. 1. A memory testing apparatus comprising:an input to receive data from one or more memory devices of a plurality of memory devices, each memory device of the plurality of memory devices having a differential serializer output having first and second complementary serializer nodes and a differential deserializer input having first and second complementary deserializer nodes, wherein the first serializer node and the first deserializer node share a same sense, and the second serializer node and the second deserializer node share the same sense complementary to the first serializer and deserializer nodes, wherein the first serializer node of a first memory device is to be coupled with the first deserializer node of the first memory device, the second serializer node of the first memory device is to be coupled with the second deserializer input node of a second memory device, the first serializer node of the second memory device is to be coupled with the first deserializer node of the second memory device, and the second serializer node of the second memory device is to be coupled with the second deserializer node of the first memory device; andan error checker to check the data from the one or more memory devices for errors, the error ...

TESTING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT TO WHICH THE SAME METHOD IS APPLIED

A method includes: writing testing data to a testing target area of the memory; reading the written data; writing the readout data to a result storage area of the memory with a first data layout; and acquiring a first comparison result by reading the data written to the result storage area and comparing the readout data with check data; rewriting the data read from the testing target area of the memory to the result storage area of the memory while changing a writing destination with a second data layout different from the first data layout within the result storage area of the memory by the testing circuit; and acquiring a second comparison result by reading the rewritten data and comparing the readout data with the check data; and specifying a defective position of the memory in accordance with the first comparison result and the second comparison result. 1. A testing method by which a testing apparatus tests a memory mounted on a semiconductor integrated circuit including a testing circuit , the method comprising:writing testing data to a testing target area of the memory by the testing circuit;reading the written data from the testing target area of the memory by the testing circuit;writing the data read from the testing target area of the memory to a result storage area of the memory with a first data layout by the testing circuit;acquiring a first comparison result by reading the data written to the result storage area of the memory and comparing the readout data with check data;rewriting the data read from the testing target area of the memory to the result storage area of the memory in a way that changes a writing destination with a second data layout different from the first data layout within the result storage area of the memory by the testing circuit;acquiring a second comparison result by reading the data rewritten to the result storage area of the memory and comparing the readout data with the check data; andspecifying a defective position of the ...

Solid state drive tester

Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

SOLID STATE DRIVE TESTER

Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time. 1. A solid state drive tester comprising:a host terminal for receiving a test condition for testing a storage from a user; anda test control unit generating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern,wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.2. The solid state drive tester of claim 1 , wherein the test control unit comprises:an embedded processor for controlling the test of the storage; anda test executing unit for generating a test pattern to test the storage, transmitting the test pattern to the storage, and determining whether a fail occurs by comparing the generated test pattern with a test pattern read out from the storage in cooperation with the embedded processor.3. The solid state drive tester of claim 2 , wherein the test control unit comprises:a communication interface ...

STORAGE INTERFACE APPARATUS FOR SOLID STATE DRIVE TESTER

Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used. 1. A storage interface apparatus for a solid state driver tester , the storage interface apparatus comprising:a host terminal for receiving a test condition for testing a storage from a user; anda test control unit for generating a test pattern corresponding to the test condition to test the storage,wherein the test control unit includes a storage interface unit for interfacing the storage, the storage interface unit includes a plurality of interfaces, and the interfaces share a protocol in parts where the protocol is commonly used.2. The storage interface apparatus of claim 1 , wherein the storage interface unit includes a plurality of complex interfaces to simultaneously test a plurality of storages.3. The storage interface apparatus of claim 2 , wherein each of the complex interfaces includes a serial-ATA (SATA) interface claim 2 , a serial attached SCSI (SAS) interface claim 2 , and a PCI express (PCIe) interface claim 2 , and the SATA interface claim 2 , the SAS interface claim 2 , and the PCIe interface share a link layer protocol.4. The storage interface apparatus of claim 2 , wherein each of the complex interfaces includes a serial-ATA (SATA) interface claim 2 , a serial attached SCSI (SAS) interface claim 2 , and a PCI express (PCIe) ...

FAILURE DETECTION APPARATUS FOR SOLID STATE DRIVE TESTER

Disclosed is a failure detection apparatus for a solid state driver tester, the failure detection apparatus including: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selecting an interface according to a type of the storage to be tested to test the storage with the test pattern. The test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time. 1. A failure detection apparatus for a solid state driver tester , the failure detection apparatus comprising:a host terminal for receiving a test condition for testing a storage from a user; anda test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selecting an interface according to a type of the storage to be tested to test the storage with the test pattern,wherein the test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time.2. The failure detection apparatus of claim 1 , wherein the test control unit includes:an embedded processor for controlling a test of the storage; anda test executing unit for creating a test pattern for a test of the storage in association with the embedded processor to transmit the test pattern to the storage, and reading out the test pattern stored in the storage to compare the readout test pattern with the created test pattern in real ...

Error generating apparatus for solid state drive tester

Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.

SYSTEMS AND METHODS FOR TESTING MEMORY

Embodiments of systems and methods for testing memory are disclosed, where memory errors are detected, and, in at least one embodiment, memory units containing errors are prevented from being accessed by applications on a computing system. 1. A method of testing a memory device within a computing system , wherein a plurality of applications are executable by at least one processor of the computing system , the method comprising:performing a first memory test on the memory device;detecting, from the first memory test, at least one error in a memory unit of the memory device; preventing at least one of the plurality of applications from accessing the memory unit;', 'performing a second memory test on the memory unit;', 'determining, from the second memory test, whether the at least one error is successfully verified; and', 'if the at least one error is successfully verified, identifying the memory unit as defective., 'in response to the detecting, performing acts to verify the at least one error comprising2. The method of claim 1 , wherein the identifying comprises recording an identification of the memory unit in a persistent memory.3. The method of claim 2 , further comprising:if the at least one error is successfully verified, recording, in association with the identification of the memory unit in the persistent memory, an indication of a number of errors detected in the memory unit.4. The method of claim 1 , wherein the memory unit comprises one of:a single memory cell of the memory device; ora memory block consisting of a plurality of memory cells of the memory device.5. The method of claim 1 , wherein performing the first memory test comprises applying a first number of test patterns claim 1 , and wherein performing the second memory test on the memory unit comprises applying a second number of test patterns claim 1 , the second number being substantially greater than the first number.6. The method of claim 1 , further comprising: 'wherein the at least one error ...

MEMORY TESTING IN A DATA PROCESSING SYSTEM

In a method of memory testing in a data processing system, in response to receiving a request for a hardware memory test during boot process of the data processing system, a controller accesses a stored past memory test result. The past memory test result includes at least a first number of test loops used in a past memory test, an identification of a first test pattern, and an error that occurred in the past memory test. The controller adjusts a second number of test loops and a second test pattern to be used in the hardware memory test according to the past memory test result. The controller then performs the hardware memory test according to the adjusted second number of test loops and the second test pattern. 1. A method of memory testing in a data processing system , the method comprising:in response to receiving a request for a hardware memory test during boot process of the data processing system, a controller accessing a stored past memory test result, wherein the past memory test result includes at least a first number of test loops used in a past memory test, an identification of a first test pattern, and any error that occurred in the past memory test;the controller adjusting a second number of test loops and a second test pattern to be used in the hardware memory test according to the past memory test result ; andthe controller performing the hardware memory test according to the adjusted second number of test loops and the second test pattern.2. The method according to claim 1 , wherein the past memory test result comprises at least one of a past hardware memory test result claim 1 , a past software memory test result claim 1 , and a past runtime memory error.3. The method according to claim 1 , wherein:the adjusting includes in response to no error being present in the stored past memory test result, setting the second number of test loops for the hardware memory test to zero; andthe performing includes in response to the second number of test loops ...

Method and apparatus for diagnosing a fault of a memory using interim time after execution of an application

An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.

METHOD AND DEVICE FOR PROCESSING DATA STORED IN A MEMORY UNIT

A method for processing data stored in a memory unit. The method includes the following steps: ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit, forming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea. 116-. (canceled)17. A method for processing data stored in a memory unit , comprising the following steps:ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit; andforming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea.18. The method as recited in claim 17 , further comprising:a) storing at least temporarily the test variable; and/orb) comparing the test variable with a reference test variable for the at least one first subarea.19. The method as recited in claim 17 , wherein the ascertainment of the test pattern includes at least one of the following: (a) random or pseudo-random formation of the test pattern claim 17 , b) receiving the test pattern from an external unit claim 17 , c) reading out the test pattern from the memory unit and/or from a further memory unit claim 17 , d) deriving the test pattern from a test pattern base data.20. The method as recited in claim 19 , wherein the formation of the test pattern includes the following steps: providing a random or pseudo-random sequence of numbers claim 19 , ascertaining the at least one first subarea as a function of at least one first part of the sequence of numbers claim 19 , a start address of the first subarea in the memory area being formed as a function of the first part of the sequence of numbers.21. The method as recited in claim 17 , wherein the test pattern characterizes claim 17 , in addition to the first subarea claim 17 , at least one second subarea claim 17 , the at least one further ...

MEMORY TESTING METHOD AND MEMORY APPARATUS THEREFOR

A memory testing method for testing a memory apparatus configured with an auxiliary testing circuit is provided. The memory testing method includes: reading a test data from a memory array of the memory; and encoding the test data into an encoded data by the auxiliary testing circuit, wherein the encoded data comprises a first piece data and a second piece data. The encoded data is encoded to include a first piece data and a second piece data, where the first piece data indicates a number of a binary state in the read test data, and the second piece data indicates an error bit in the read test data. In addition, a memory apparatus for the memory testing method is also provided. 1. A memory testing method for testing a memory apparatus configured with an auxiliary testing circuit , the memory testing method comprising:reading a test data from a memory array of the memory apparatus; andencoding the test data into an encoded data by the auxiliary testing circuit, wherein the encoded data comprises a first piece data and a second piece data,wherein the first piece data indicates a number of a binary state in the read test data, and the second piece data indicates an error bit in the read test data.2. The memory testing method as claimed in claim 1 , wherein the memory apparatus is an ECC memory apparatus.3. The memory testing method as claimed in claim 1 , wherein before the step of reading the test data from the memory array of the memory apparatus claim 1 , the memory testing method further comprises:writing the test data of one of a target pattern into the memory array.4. The memory testing method as claimed in claim 3 , wherein the target pattern comprises at least one of an all-one pattern claim 3 , an all-zero pattern claim 3 , a checkerboard pattern claim 3 , and an inverse checkerboard pattern.5. The memory testing method as claimed in claim 3 , wherein the step of encoding the test data into the encode data comprises:calculating the number of the binary state ...

SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND ERROR NOTIFICATION METHOD

A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit. 1. A semiconductor memory device , comprising:a data bus terminal group for outputting read data to an external device or inputting write data from an external device;a first terminal from or into which 1-bit data is output or input;a DBI circuit that executes a Data Bus Inversion (DBI) function;an error detection circuit that detects an internal error; andan information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group,wherein the predetermined output information includes:first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted; andsecond output information indicating whether or not an internal error has been detected by the error detection circuit.2. The semiconductor memory device according to claim 1 ,wherein the information superimposing circuit further extracts predetermined input information from the 1-bit data input to the first terminal and an input bit pattern serving as the write data input to the data bus terminal ...

Manufacturing testing for ldpc codes

An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

SEMICONDUCTOR DEVICE INCLUDING DEFECT DETECTION CIRCUIT AND METHOD OF DETECTING DEFECTS IN THE SAME

A semiconductor device includes a semiconductor die having a peripheral region surrounding, a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits, and a test control circuitry configured to perform (a) a test write operation by transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop. 1. A semiconductor device comprising:a semiconductor die including a central region and a peripheral region surrounding the central region;a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits; anda test control circuitry configured to perform (a) a test write operation by sequentially transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop to read out an output data pattern.2. The ...

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

A memory device includes a system block for storing test information and includes a data block including memory cells connected to a plurality of low bank column lines and a plurality of high bank column lines. The memory device also includes a column repair controller configured to detect, based on the test information, a concurrent repair column line in which a low bank column line among the plurality of low bank column lines and a high bank column line the plurality of high bank column lines corresponding to the same column address are concurrent repaired. 1. A memory device comprising:a system block for storing test information;a data block including memory cells connected to a plurality of low bank column lines and a plurality of high bank column lines; anda column repair controller configured to detect, based on the test information, a concurrent repair column line in which a low bank column line among the plurality of low bank column lines and a high bank column line the plurality of high bank column lines corresponding to the same column address are concurrent repaired.2. The memory device of claim 1 , wherein the column repair controller comprises:a wafer test information storage configured to temporarily store wafer test information among information included in the test information;a packaging test information storage configured to temporarily store packaging test information among the information included in the test information; anda concurrent repair detector configured to generate concurrent repair information, which is a result of comparing the wafer test information and the packaging test information.3. The memory device of claim 2 , further comprising:a status register configured to store the concurrent repair information.4. The memory device of claim 2 , wherein the wafer test information storage stores a column address of a column line repaired in a wafer test of the memory device among the plurality of low bank column lines and the plurality of ...

MEMORY MODULE STORING TEST PATTERN INFORMATION, COMPUTER SYSTEM COMPRISING THE SAME, AND TEST METHOD THEREOF

A memory module includes at least one semiconductor memory device, and a test pattern memory that stores first test pattern information for testing the at least one semiconductor memory device, and the first test pattern information stored in the test pattern memory is transferred to a host in a test operation. Through the memory module having the above-described function, a memory test is possible in consideration of a unique weak characteristic of the memory module. 1. A memory module comprising:at least one semiconductor memory device; and store first test pattern information for testing the at least one semiconductor memory device, and', 'transfer the first test pattern information to a host in a test operation., 'a test pattern memory configured to,'}2. The memory module of claim 1 , wherein the test pattern memory corresponds to one of a serial component recognition device (SPD) and a register clock driver (RCD) mounted on the memory module.3. The memory module of claim 1 , wherein the at least one semiconductor memory device is configured to have the test operation performed thereon in a booting operation of the host by a Basic Input Output System BIOS of the host.4. The memory module of claim 3 , wherein the first test pattern information corresponds to a parameter for generating a test pattern used in the test operation.5. The memory module of claim 4 , wherein the memory module is configured to receive the test pattern generated by the host.6. The memory module of claim 3 , wherein the first test pattern information corresponds to a code utilized to perform the test operation.7. The memory module of claim 1 , further comprising:processing circuitry configured to generate a first test pattern based on second test pattern information stored in the test pattern memory, the first test pattern for testing the at least one semiconductor memory device.8. The memory module of claim 7 , wherein the processing circuitry is configured to test the at least one ...

AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING

An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode. 1. A method , comprising:activating a first test memory cell and a second test memory cell during a test mode;causing a first logic value to be stored in the first test memory cell and causing a second logic value to be stored in the second test memory cell;deactivating a data-storage memory cell during the test mode;generating a test pattern on the first and second test memory cells such that the first test memory cell includes a first logic value and the second test memory cell includes a second logic value different from the first logic value;causing the first test memory cell to change a signal on a bit line from the first logic value to the second logic value; andcoupling the bit line to a sense amplifier after the signal on the bit line has the second logic value.2. The method of claim 1 , further including:allowing the first test memory cell to change a signal on a bit line from a precharge logic level to another logic level; andcoupling the bit line to a sense amplifier after the signal on the bit line has the other logic level.3. The method of claim 1 , further including:allowing the first test memory cell to change a signal on a bit line from a high logic level to a low logic level; andcoupling the bit line to a sense amplifier after the signal on the bit line has the low logic level.4. The method of claim 1 , wherein activating the first test memory cell includes activating a row including the first test memory cell.5. The method of claim 1 , wherein activating the first test memory cell includes activating a column including the first test memory cell.6. The method of claim 1 , wherein activating the first test memory cell ...

MEMORY DEVICE TEST MODE ACCESS

A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation. 1. A system , comprising:a memory device;a processing device coupled to the memory device and configured to switch an operating mode of the memory device between a test mode and a non-test mode; anda test mode access component, the test mode access component configured to access the memory device while the memory device is in the test mode to perform a test mode operation.2. The system of claim 1 , wherein the system comprises an interface through which the processing device is configured to communicate with the memory device via signaling in accordance with a particular protocol claim 1 , and through which the test mode access component is configured to communicate with the memory device.3. The system of claim 2 , wherein the system comprises a storage subsystem claim 2 , and wherein the storage subsystem includes a controller comprising the processing device and the test mode access component.4. The system of claim 2 , wherein the test mode operation is a fuse identification (FID) read operation.5. The system of claim 2 , wherein signaling between the test mode access component and the interface is non-compliant with the particular protocol.6. The system of claim 5 , wherein the particular protocol is a double data rate (DDR) JEDEC standard protocol.7. The system of claim 1 , wherein the test mode access component is configured to cause claim 1 , via the signal claim 1 , the memory device to program a register of the memory device to access the memory device.8. The system of claim 7 , wherein the register comprises a mode register.9. A method claim 7 , comprising:performing, ...

SOFT BIT REFERENCE LEVEL CALIBRATION

Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin. 1. An apparatus , comprising:a communication interface; and{'claim-text': ['sense a set of non-volatile memory cells at a hard bit reference level and a plurality of test soft bit reference levels grouped around the hard bit reference level;', 'determine a metric for the test soft bit reference levels; and', 'establish new soft bit reference levels for sensing the set based on the metric for the test soft bit reference levels.'], '#text': 'a control circuit coupled to the communication interface, wherein the control circuit is configured to connect to non-volatile memory cells, wherein the control circuit is configured to:'}2. The apparatus of claim 1 , wherein:the metric comprises a percentage of the set having a value for a physical parameter within bins defined by the hard bit reference level and the plurality of test soft bit reference levels; andthe control circuit is configured to establish the new soft bit reference levels based on a target percentage for the bins.3. The apparatus of claim 2 , wherein the control circuit is further configured to:estimate a bit error rate of data stored in the set; andestablish the target percentage based on ...

Apparatus and method for acquiring data of fast fail memory

An apparatus and method for acquiring data of fast fail memory includes a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated so as to correspond thereto to a failure analyzer from the pattern generator; and a failure analyzer for analyzing the DUT data and the pattern generated so as to correspond to the DUT data, which are received from the data transmitter, thus producing failure analysis information. The data transmitter (FIFO) able to advance the failure analysis time allows failure analysis to be performed before completion of testing, thereby shortening the total failure analysis time and overcoming hardware limitations for failure analysis.

CIRCUIT ARRANGEMENT AND METHOD WITH MODIFIED ERROR SYNDROME FOR ERROR DETECTION OF PERMANENT ERRORS IN MEMORIES

A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory () and an error detection circuit (). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory () at a memory location and to read out a data word from the memory () from the memory location. The error detection circuit () is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C). Furthermore, the error detection circuit () is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset (M) of bits was written to the memory location, to determine on the basis of the data word read out from the memory () whether a memory error is present if the code word that is inverted in the subset (M) of bits is not a code word of the error detection code (C). 1. A circuit arrangement for detecting memory errors , comprising:a memory; andan error detection circuit,wherein the circuit arrangement is designed to store a code word of an error detection code or a code word that is inverted in a subset (M) of bits in the memory at a memory location and to read out a data word from the memory from the memory location,wherein the error detection circuit is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code, andwherein the error detection circuit is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset of bits was written to the memory location, to determine on the basis of the data word read out from the memory whether a memory error ...

SYSTEM FOR SIMULTANEOUSLY DETERMINING MEMORY TEST RESULT

A system for simultaneously determining a memory test result includes a pattern generation part generating a pattern signal for testing so as to transmit the signal through an address line and a command line; a delay part receiving read data through a first data line from a closest memory device that is disposed closer to the system and to receive read data through a second data line from a farthest memory device that is disposed farther from the system; and a determination part simultaneously determining the read data of the closest memory device and the read data of the farthest memory device, which are simultaneously output from the delay part, using a determination clock, wherein the delay part recognizes the read data of the closest memory device and the read data of the farthest memory device. 1. A system for simultaneously determining a memory test result result for physically distant memory devices in a pattern generator on a burn-in board , comprising:a pattern generation part for generating a pattern signal for testing to transmit the signal through an address line and a command line;a delay part for receiving through a first data line read data from a closest memory device and receiving through a second data line read data from a farthest memory device, the memory devices being mounted on the burn-in board; anda determination part for simultaneously testing the read data from the closest memory device and the read data from the farthest memory device, which are simultaneously output from the delay part, using one determination clock,wherein the delay part may recognize inputs of the read data from the closest memory device and the read data from the farthest memory device, and delay the output of the read data from the closest memory device by time difference of the inputs.2. The system of claim 1 , wherein the determination part may determine whether the read data from the closest memory device and the read data from the farthest memory device claim 1 , ...

Data Storage Device and Method for Restricting Access Thereof

A data storage device including a flash memory, a temperature sensor and a controller. The flash memory has a plurality of blocks, and each of the blocks has a plurality of pages. The temperature sensor detects surrounding ambient temperature and to produce a temperature parameter accordingly. The controller is arranged to perform a first maintenance procedure after a predetermined period since the data storage device is powered on. The controller reads the temperature sensor to obtain a first temperature parameter in the first maintenance procedure and determines a first time span according to a first predetermined condition for performing a second maintenance procedure, wherein the first predetermined condition includes the first temperature parameter, and the controller is further arranged to perform the second maintenance procedure after the first time span since the first maintenance procedure has finished. 1. A data storage device , comprising:a flash memory, having a plurality of blocks, and each of the blocks has a plurality of pages;a temperature sensor, arranged to detect surrounding ambient temperature and produce temperature parameters accordingly; anda controller, arranged to perform a first maintenance procedure after a predetermined period since the data storage device is powered on, wherein the controller is further arranged to read the temperature sensor to obtain a first temperature parameter in the first maintenance procedure, and determine a first time span according to a first predetermined condition for performing a second maintenance procedure, wherein the first predetermined condition comprises the first temperature parameter, and the controller is further arranged to perform the second maintenance procedure after the first time span since the first maintenance procedure has finished.2. The data storage device as claimed in claim 1 , wherein in the first maintenance procedure claim 1 , the controller is further arranged to perform a first ...

DEFECT DETECTING METHOD AND DEVICE FOR WORD LINE DRIVING CIRCUIT

A defect detecting method for a Word Line (WL) driving circuit includes: m WLs correspondingly connected to m different WL driving circuits are selected from a memory cell array and corresponding WL driving circuit arrays to serve as m WLs to be tested, one of which is set as a first WL and the remaining m-1 ones are set as second WLs; first potential is written into memory cells correspondingly connected to the m WLs to be tested; second potential is written into memory cells correspondingly connected to the first WL; real-time potentials of the memory cells connected to respective second WLs are sequentially read, and when difference value between the real-time potential of one target memory cell and the first potential is greater than first pre-set value, it is determined that the WL driving circuit connected to the second WL corresponding to the target memory cell has a defect. 1. A defect detecting method for a Word Line (WL) driving circuit , comprising:selecting m WLs from a memory cell array and WL driving circuit arrays corresponding to the memory cell array to serve as m WLs to be tested, setting one of the m WLs to be tested as a first WL, and setting the remaining m−1 WLs to be tested as second WLs, wherein the m WLs to be tested are respectively and correspondingly connected to m different WL driving circuits, where m is an integer greater than 1;a first write operation of writing a first potential into memory cells correspondingly connected to all transistors controlled by the m WLs to be tested;a second write operation of writing a second potential into memory cells correspondingly connected to all transistors controlled by the first WL; anda read and determination operation of sequentially reading real-time potentials of memory cells correspondingly connected to all transistors controlled by respective second WLs, and when a difference value between a read real-time potential of a target memory cell and the first potential is greater than a first pre ...

METHOD FOR TESTING MEMORY

A method for testing a memory area. The method includes jumping from a destination address to a source address, reading a data word at the source address after jumping to the source address, and examining the data word. The source address was determined based on a static test. 1. A method for testing a memory area , the method comprising:determining a source address based on a static test;jumping from a destination address to the source address;reading a data word at the source address after jumping to the source address; andexamining the data word.2. The method of claim 1 , wherein determining the source address based on the static test comprises determining a source address for which the static test has revealed that there is no erased data word present in the source address.3. The method of claim 1 , wherein the data word at the source address is correct according to the static test.4. The method of claim 1 , wherein examining the data word comprises detecting for errors in the data word and determining whether the data word is correct claim 1 , has a correctable error claim 1 , or has an uncorrectable error.5. The method of claim 1 , further comprising:jumping from the source address to the destination address before jumping from the destination address to the source address.6. The method of claim 1 , wherein examining the data word comprises determining whether the data word is a code word of an error code.7. The method of claim 1 , wherein examining the data word comprises determining a dynamic error state of the data word.8. The method of claim 1 , wherein the static test is used to determine a static error state.9. The method as claimed in claim 8 , wherein the data word has a predefined static error state.10. The method of claim 8 , wherein the static test comprises determining whether a word at an address in the memory area is an erased word or not an erased word claim 8 , and wherein the method further comprises:entering, in a map, the static error state ...

SEMICONDUCTOR DEVICES

A semiconductor device may include a power supply circuit, a word line control circuit, and a memory circuit. The power supply circuit may drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination. The word line control circuit may generates two or more word line selection signals that are sequentially counted based on the write initialization signal. The memory circuit may sequentially select a plurality of word lines based on the word line selection signals. The memory circuit may drive bit lines of memory cells connected to the selected word line to the pre-charge voltage. The memory circuit may store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line. 1. A semiconductor device comprising:a power supply circuit configured to drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination;a word line control circuit configured to generate two or more word line selection signals that are sequentially counted based on the write initialization signal; anda memory circuit configured to sequentially select a plurality of word lines based on the word line selection signals, configured to drive bit lines of memory cells connected to the selected word line to the pre-charge voltage, and configured to store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line.2. The semiconductor device of claim 1 , wherein the external voltage is set to be a ground voltage.3. The semiconductor device of claim 1 , wherein the write initialization signal is a signal that activates an initialization operation for writing the data having a level of the external voltage into the memory cells.4. The ...

MEMORY CIRCUIT DEVICE AND A METHOD FOR TESTING THE SAME

A memory circuit device and a memory test method are disclosed. The memory circuit device includes: a memory cell array, including storage lines and redundant storage lines; and a redundant decoder control circuit, configured to receive an address of a failed storage line from a testing device and activate a corresponding redundant storage line based on the address of the failed storage line, so that the redundant storage line can replace and store data in the failed storage line, wherein the address of the failed storage line is determined while testing operation status of the storage lines in the memory cell array. Embodiments of the present invention can improve repair efficiency of the memory circuit device through activating the associated redundant storage line by the redundant decoder control circuit based on the address of the failed storage line rather than under the control of an external controller. 1. A memory circuit device , comprising:a memory cell array comprising at least one storage line and at least one redundant storage line for storing data; anda redundant decoder control circuit configured to receive an address of a failed storage line from a testing device and activate a corresponding redundant storage line based on the address of the failed storage line, wherein the corresponding redundant storage line replaces the failed storage line and stores data,wherein the address of the failed storage line is determined by the testing device while testing operation status of the at least one storage line of the memory cell array, andthe redundant decoder control circuit comprises: at least one redundant storage line control unit, each of the at least one redundant storage line control unit connected to a corresponding redundant storage line, a register unit for receiving the address of the failed storage line from the testing device and storing the address of the failed storage line;', 'an enabling unit for providing, based on an activation signal, an ...

MEMORY SUB-SYSTEM SCAN

A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells. 1. A system , comprising:a memory device comprising a plurality of groups of memory cells; and receive a request to determine a reliability of the plurality of groups of memory cells; and', 'perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells., 'a processing device, operatively coupled to the memory device, to2. The system of claim 1 , wherein:the sample portion is one of a plurality of selected groups of memory cells known to have a relatively low reliability characteristic;the plurality of selected groups of memory cells are distributed among a number of logical segment of the memory device, wherein the plurality of groups of memory cells corresponds to one of the number of logical segments; andwherein the processing device is to perform a scan operation only on the plurality of selected groups of memory cells, and wherein determined reliabilities of the plurality of selected groups are representative of respective reliabilities of the number of logical segments.3. The system of claim 1 , wherein the processing device is to determine whether to perform a media management operation on the plurality of groups based on a comparison between the determined reliability of the sample portion and a ...

TESTING CIRCUIT, TESTING DEVICE AND TESTING METHOD THEREOF

A testing circuit includes: a first sampling module configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; and a second sampling module configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal. The second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal. 1. A testing circuit , comprising:a first sampling module, configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; anda second sampling module, configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal,wherein the second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal.2. The testing circuit of claim 1 , wherein the first sampling module is configured to generate the first sampled signal in response to a falling edge of the pulse signal claim 1 , and the second sampling module is configured to generate the second sampled signal in response to a rising edge of the pulse signal.3. The testing circuit of claim 1 , wherein a first delay time of the first sampling module on a first transmission path is equal to a second delay time of the second sampling module on a second transmission path.4. The testing circuit of claim 1 , wherein the first sampling module comprises:a first temporary storage unit, configured to sample a first to-be-sampled signal in response to the pulse signal so as to generate a first temporary storage signal, wherein a triggering type of the first temporary storage unit is edge triggering, and an edge of the first temporary storage signal corresponds to a first edge of the pulse signal and corresponds to an edge of the first sampled signal.5. The testing circuit of claim 4 , wherein the first temporary ...

LATCH CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.

APPARATUSES AND METHODS FOR REFRESHING MEMORIES WITH REDUNDANCY

Embodiments of the disclosure are drawn to apparatuses methods for checking redundancy information for row addresses prior to performing various refresh operations, such as auto refresh and targeted refresh operations. In some examples, refresh operations may be multi pump refresh operations. In some examples, a targeted refresh operation may be performed prior to an auto refresh operation responsive to a multi pump refresh operation. In some examples, redundancy information for the auto refresh operation may be performed, at least in part, during the targeted refresh operation. In some examples, refresh operations on word lines may be skipped when the redundancy information indicates the word line is defective or unused.

MEMORY SYSTEM AND OPERATING METHOD THEREOF

A memory system and an operating method thereof are provided. The memory system includes a storage device including a mode register suitable for activating or inactivating an auto mode and a memory suitable for storing data, and a storage device controller controlling the mode register to enter a test mode, after inactivating the auto mode, during a test operation of the storage device, and controlling the mode register to activate the auto mode again when the test operation of the storage device is completed. 1. A memory system , comprising:a memory configured to store data;a mode register configured to store codes for activating or inactivating an auto mode of a refresh operation of the memory and a test mode; anda storage device controller configured to control the mode register to:inactivate the auto mode;enter the test mode when the auto mode is inactivated;activate the auto mode when the memory enters the test mode;perform a read operation on the memory to receive information of the memory during the test mode; andstore the information.2. The memory system of claim 1 , wherein the information includes an ID of the memory.3. The memory system of claim 1 , wherein the storage device controller inactivates the auto mode when the read operation is completed claim 1 , exits the test mode claim 1 , and activates the auto mode after the read operation.4. The memory system of claim 1 , wherein the storage device controller includes a register to store the information of the memory.5. A memory system claim 1 , comprising:a memory configured to store data;a memory controller configured to control the memory and store codes for activating or inactivating an auto mode of a refresh operation of the memory and a test mode; anda storage device controller configured to control the memory controller to:inactivate the auto mode;enter the test mode when the auto mode is inactivated;activate the auto mode when the memory enters the test mode; andperform a test operation on the ...

METHOD AND SYSTEM OF TESTING SEMICONDUCTOR MEMORY

A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a DUT under the control of a DQ signal responding to a DQ enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array. The programmed logical value is captured from the DUT under the control the DQ signal. The generated logical value is compared with the captured logical value. Whether the DUT is defective is determined according to a result of the comparison. The DQ enable signal is applied to a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the field programmable gate array is applied. 1. A method of testing a semiconductor memory , the method comprising:generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array (FPGA);programming the generated logical value in a device-under-test (DUT) under control of a DQ signal responding to a DQ enable signal that is generated from an automatic test equipment and is then transferred to the FPGA;capturing the programmed logical value from the DUT under control of the DQ signal; andcomparing the generated logical value with the captured logical value and determining whether the DUT is defective according to a result of the comparison,wherein the DQ enable signal is applied at a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the FPGA is applied.2. The method of claim 1 , further comprising:after generating the logical value, generating an address signal in response to an address enable signal that is generated from the automatic test equipment and is then transferred to the FPGA.3. The method of claim 2 , wherein the address enable signal claim 2 , the DQ ...

System and Method of Simulation for Next Generation Memory Technology

A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design, multiplying an input spectrum with each of the transfer functions to provide a plurality of results, summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal. 1. A method comprising:modeling a design of a memory channel to provide a plurality of transfer functions associated with the design;multiplying, by an information handling system, an input spectrum with each of the transfer functions to provide a plurality of results;summing, by the information handling system, the results to provide an output spectrum for the design;performing, by the information handling system, an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design; anddetermining, by the information handling system, a bit error rate (BER) for the design based on the output signal.2. The method of claim 1 , wherein the plurality of transfer functions comprise a forward memory channel transfer function claim 1 , a memory channel cross-talk transfer function claim 1 , a voltage regulator transfer function claim 1 , a power plane resonance transfer function claim 1 , and a broadside coupling transfer function.3. The method of claim 2 , further comprising:receiving the forward memory channel transfer function, the memory channel cross-talk transfer function, the voltage regulator transfer function, the power plane resonance transfer function, and the broadside coupling transfer function from a circuit simulation of the design.4. The method of claim 1 , further comprising:providing an eye diagram from the output signal;wherein determining the BER for the design is based upon the eye diagram.5. The method of claim 1 , further ...

Semiconductor devices

A semiconductor device may include a power supply circuit, a word line control circuit, and a memory circuit. The power supply circuit may drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination. The word line control circuit may generates two or more word line selection signals that are sequentially counted based on the write initialization signal. The memory circuit may sequentially select a plurality of word lines based on the word line selection signals. The memory circuit may drive bit lines of memory cells connected to the selected word line to the pre-charge voltage. The memory circuit may store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line.

SCRUB MANAGEMENT IN STORAGE CLASS MEMORY

A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults. 1. A method for collecting diagnostic data from a storage class memory chip , the method comprising: removing a portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations;', 'executing a first write operation to write a first pattern on each of the plurality of memory locations;', 'executing a first read operation to obtain a first set of data written on each of the plurality of memory locations;', 'analyzing the first set of data written on each of the plurality of memory locations to determine a number of stuck-at faults in the portion; and, 'performing a scrub process on at least a portion of the storage class memory byupdating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.2. The method of claim 1 , wherein performing the scrub process further comprises:executing a second write operation to write a second pattern on each of the plurality of memory locations, wherein the first pattern and the second pattern are different from each other;executing a second read operation to obtain a second set of data written on each of the plurality of memory locations;analyzing the second set of data written ...

Method of Error Detection in a Ternary Content Addressable Memory

A method is provided for error detection in a ternary content addressable memory, TCAM, preferably in real-time, wherein the error detection is initiated with a read operation at a specified input address (), wherein an additional random access memory, RAM, is provided, wherein said RAM has the same number of locations as the TCAM, wherein in both memories, TCAM and RAM, corresponding read data entries () which each consist of data and a mask are placed at the same address locations. In addition, a method is provided for error detection in a TCAM, preferably in real-time, wherein the error detection is triggered by the found of searched input key () and starts with a read operation at a specified memory address (), wherein an additional RAM is provided, wherein said RAM has the same number of locations as the TCAM, wherein in both memories, TCAM and RAM, corresponding read data entries () which each consist of data and a mask are placed at the same address locations. 1200210. A method for error detection in a ternary content addressable memory , TCAM , preferably in real-time , wherein the error detection is initiated with a read operation at a specified input address () , an additional random access memory , RAM , is provided , wherein said RAM has the same number of locations as the TCAM , wherein in both memories , TCAM and RAM , corresponding read data entries () which each consist of data and a mask are placed at the same address locations , and wherein:{'b': '200', 'data and mask read operations from TCAM and RAM at the locations pointed by the input address () are performed and'}{'b': 220', '200', '200, 'in a first check phase () said data and mask read from the TCAM at the location pointed by the input address () are compared with the data and mask read from RAM at the location pointed by the same input address (), and'}{'b': 220', '270, 'if the result of the first check phase () is correct, a TCAM_SEARCH phase () is executed,'}{'b': 230', '240', '250', '200 ...

MEMORY MODULE ERRORS

Techniques for handling errors on memory modules are provided. An uncorrected error from a pair of memory modules may be received. Memory modules other than the pair of memory modules producing the error may be de-configured. Diagnostic tests may be run on the faded pair of memory modules. The memory module of the pair of memory modules that caused the uncorrected error may be determined. 1. A method comprising:receiving an indication of an uncorrected error from a failed pair of memory modules;de-configuring all pairs of memory modules other than the failed pair of memory modules;running diagnostic tests on the failed pair of memory modules; andidentifying which memory module of the failed pair of memory modules caused the uncorrected error, based on the diagnostic tests.2. The method of further comprising:configuring the failed pair of memory modules to operate in non-lockstep mode.3. The method of further comprising:retrieving an error history of the failed pair of memory modules from a database; andidentifying the memory module of the failed pair of memory modules based on the error history.4. The method of wherein the diagnostic tests are exhaustive diagnostic tests.5. The method of further comprising:recommending replacement of the identified memory module; andde-configuring the identified memory module.6. The method of further comprising:reconfiguring the non-failed pairs of memory modules.7. A non transitory processor readable medium containing instructions thereon which when executed by a processor cause the processor to:receive an indication of an uncorrected memory error on a server computer;set configuration parameters of memory modules not implicated by the error to indicate the memory modules are de-configured;set boot flag of the server to indicate a memory test quick boot; andinstruct the server to reboot, wherein the server initiates a memory test quick boot and performs diagnostic tests on the memory modules that are not de-configured.8. The medium ...

Variable clock divider

Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.

MEMORY DEVICE, TESTING METHOD AND USING METHOD THEREOF, AND MEMORY SYSTEM

A memory device includes: a plurality of channels, each including a memory cell array, the memory cell array including a normal cell array, the normal cell array including normal memory cells, and each of the normal memory cells being a volatile memory cell; a testing control circuit, configured to control testing of the normal cell array in the plurality of channels in response to a testing instruction, and to determine an access address of a normal memory cell failing the testing in the normal cell array in the plurality of channels to be a failure address; and a non-volatile memory cell array which includes a plurality of non-volatile memory cells and is configured to receive and store the failure address from the testing control circuit. 1. A memory device , comprising:a plurality of channels, each channel comprising a memory cell array, the memory cell array comprising a normal cell array, the normal cell array comprising normal memory cells, and each of the normal memory cells being a volatile memory cell;a testing control circuit, configured to control testing of the normal cell array in each of the plurality of channels in response to a testing instruction and to determine an access address of a normal memory cell failing the testing in the normal cell array in each of the plurality of channels to be a failure address; anda non-volatile memory cell array, configured to receive and store the failure address from the testing control circuit.2. The memory device of claim 1 , wherein the non-volatile memory cell array comprises an anti-fuse array.3. The memory device of claim 1 , wherein the non-volatile memory cell array comprises:a control block, configured to control programming of the non-volatile memory cell array and store the failure address.4. The memory device of claim 1 , wherein each of the channels further comprises a latch block claim 1 , wherein the non-volatile memory cell array further comprises:a scan host, configured to, responsive to the ...

DEFECT REPAIR CIRCUIT AND DEFECT REPAIR METHOD

Disclosed are a defect repair circuit and a defect repair method. The defect repair circuit includes: a test module, configured to perform defect test on a memory cell array in a test module to determine a defective memory cell, and output test address information and defect flag signal corresponding to the memory cell; a defect information storage module, connected with the test module, configured to store defect address information responsive to the defect flag signal, the defect address information being the test address information of the defective memory cell, and further configured to output first address information responsive to an externally input repair selection signal, the first address information being one of multiple pieces of defect address information; and a repair module, connected with the defect information storage module and configured to repair a corresponding defective memory cell according to the received first address information. 1. A defect repair circuit , comprising:a processor; anda memory configured to store instructions executable by the processor;wherein the processor is configured to:perform defect test on a memory cell array in a test mode to determine a defective memory cell, and output test address information and defect flag signal corresponding to the defective memory cell;store defect address information responsive to the defect flag signal, the defect address information being the test address information of the defective memory cell, and output first address information responsive to an externally input repair selection signal, the first address information being one of multiple pieces of defect address information; andrepair a corresponding defective memory cell according to the first address information.2. The defect repair circuit of claim 1 , wherein the processor is further configured to receive externally input second address information claim 1 , and repair the defective memory cell corresponding to the first address ...

METHOD OF PERFORMING WEAR MANAGEMENT IN NON-VOLATILE MEMORY DEVICES

A method is provided for performing wear management in a non-volatile memory device which includes a plurality of storage units. A first error count associated with the amount of error bits generated in a specific storage unit during a first access is acquired. A second error count associated with an amount of error bits generated in the specific storage unit during a second access is retrieved, wherein the second access occurs earlier than the first access. An early retirement threshold is set to a first value when the difference between the first error count and the second error count does not exceed the predetermined value, or set to a second value smaller than the first value when the difference between the first error count and the second error count exceeds the predetermined value. The specific storage unit is marked as a bad storage unit when the first error count exceeds the early retirement threshold. 1. A method of performing wear management in a non-volatile memory device which includes a plurality of storage units , the method comprising:acquiring a first error count associated with an amount of error bits generated in a specific storage unit during a first access;retrieving a second error count associated with an amount of error bits generated in the specific storage unit during a second access, wherein the second access occurs earlier than the first access;determining if a difference between the first error count and the second error count exceeds a predetermined value;setting an early retirement threshold to a first value when the difference between the first error count and the second error count does not exceed the predetermined value or to a second value smaller than the first value when the difference between the first error count and the second error count exceeds the predetermined value; andmarking the specific storage unit as a bad storage unit when the first error count exceeds the early retirement threshold.2. The method of claim 1 , further ...

SELECTIVE MARGIN TESTING TO DETERMINE WHETHER TO SIGNAL TRAIN A MEMORY SYSTEM

Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process. 120-. (canceled)21. A computing device comprising:a host processor; anda plurality of memory storages coupled to the host processor and including a first memory storage, the plurality of memory storages including executable program instructions, which when executed by the host processor, cause the host processor to:execute a margin test of the first memory storage based on a subset of first signals associated with the first memory storage;determine, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints; anddetermine, based on the first margin data, whether to execute a signal training process.22. The computing device of claim 21 , wherein the executable program instructions claim 21 , which when executed by the host processor claim 21 , is to cause the host processor to execute the margin test claim 21 , determine the first margin data and whether to execute the signal training process during a current boot process of the computing device.23. The computing device of claim 22 , wherein the executable program instructions claim 22 , which when executed by the host processor claim 22 , cause the host processor to:during a previous boot sequence of the computing device, execute another margin test on the first memory storage;during the previous boot sequence and based on the another margin test, determine second margin data to indicate whether the first memory storage complies with the one or more electrical constraints; anddetermine ...

MEMORY

A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks. 1. A memory , comprising banks , each bank comprising a U half bank and a V half bank;a first error checking and correcting unit connected with U half banks and V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; anda second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks.2. The memory of claim 1 , wherein the first error checking and correcting unit has a same number of input bits as the second error checking and correcting unit.3. The memory of claim 1 , wherein the first error checking and correcting unit has a same internal error checking algorithm as the second error checking and correcting unit.4. The memory of claim 1 , wherein the U half bank has a same storage capacity as the V half bank.5. The memory of claim 1 , wherein each U half bank comprises an even number of block data buses claim 1 , the block data buses are sequentially numbered from zero according to natural numbers claim 1 , odd-numbered block data buses O are connected with the first error checking and correcting unit claim 1 , and even-numbered block data buses E are connected with the second error checking and correcting unit.6. The memory of claim 1 , wherein each U half bank comprises an even number of block data buses claim 1 , the block data buses are sequentially numbered from zero according to ...

MEMORY SUBSYSTEM DATA BUS STRESS TESTING

A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data. 1. A memory subsystem comprising:a memory device to store data and execute memory device commands to access and manage the data;a memory controller coupled to the memory device via a data bus, to receive a test transaction, the test transaction indicating one or more memory I/O (input/output) operations to perform a test on a memory device coupled to the memory controller;a test signal generator of the memory controller to generate a test data signal pattern in response to the memory controller receiving the test data transaction, the test signal generator including multiple different pattern signal generators to generate different types of signal patterns; anda scheduler of the memory controller to schedule the test data signal pattern in accordance with a memory device I/O protocol, and sending the test data signal pattern to the memory device to cause the memory device to execute an I/O operation to implement a portion of the test transaction.2. The memory subsystem of claim 1 , wherein the memory controller is to receive the test transaction from a test engine coupled to ...

METHODS AND APPARATUSES FOR MEMORY TESTING WITH DATA COMPRESSION

Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches. 1. An apparatus , comprising:a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory, wherein each of the latch test circuits is configured to receive test data and configured to latch data from the corresponding global data line, and configured to latch a corresponding mask bit, each of the plurality of latch test circuits further configured to output data based on the corresponding mask bit; anda comparison circuit coupled to an output of each of the latch test circuits and configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicating whether the output data matches.2. The apparatus of claim 1 , wherein the output data provided by each of the latch test circuits is one of the data received from the respective memory or the test data.3. The apparatus of claim 2 , wherein the output data provided by each of the latch test circuits is the data from the respective memory cell when the mask bit has a first logical value and wherein the output data provided by each of the latch test ...

MAXIMUM DATA RECOVERY OF SCALABLE PERSISTENT MEMORY

A scalable persistent memory for a computing resource includes a scalable persistent memory region allocated in system memory of the computing resource. In case of system shutdowns, the contents of the scalable persistent memory region is transferred to a backup storage resource. Transfers to the backup storage resource occur in data blocks consisting of a plurality of data lines. A data block may be rejected by the backup storage resource if the data block is found to contain data errors. For any data block rejected by the backup storage resource during a data transfer, the rejected block is scanned in data line increments and scrubbed by replacing or overwriting any data line found to contain an error with error-free data. A scrubbed block is then stored in a known good region of system memory previously determined to be error-free. The previously rejected data block is then transferred from the known good region to the backup storage resource. Data recovery from the backup process is maximized through avoidance of entire data blocks being rejected. 1. A scalable persistent memory , comprising:a memory controller implementing an error correction protocol, coupled to a system memory and operable with a processor to allocate a scalable persistent memory region, comprising at least one data block consisting of a plurality of data lines, within said system memory;a backup storage resource, in data communication with said system memory, for storing said at least one data block of said scalable persistent memory region, said backup storage resource being operable to reject storage of a data block determined by said error correction protocol to contain a data error; scan said rejected data block in data line increments;', 'overwrite any data line of the rejected data block found to contain data errors with error-free data;', 'store said scanned data block including said overwritten data line in a known good storage region of said system memory, said known good storage ...

Memory device with error check function of memory cell array and memory module including the same

A memory device that checks an error of a memory cell and a memory module including the same are disclosed. The memory module includes a first memory device and a second memory device. The first memory device includes a first area in which normal data are stored, and a second area in which error check data are stored. The second memory device stores reliability information about the normal data that is stored in the first area of the first memory device. The first memory device outputs a result of comparing the normal data read from the first area of the first memory device to the error check data read from the second area of the first memory device.

APPARATUS AND METHOD FOR CONTROLLING MEMORY

This technology relates to a memory control apparatus for processing data into a memory device and an operating method of the memory control apparatus. A method for controlling a memory may include converting received program data with a first address into compressed data, searching a deduplication table including compressed data, a second address of a memory device in which non-compressed data corresponding to the compressed data has been written and a counter indicative of the write number of the data for the converted compressed data, and if the converted compressed data is searched for in the deduplication table, mapping a second address corresponding to the compressed data in the deduplication table to the first address, not performing a write operation of the memory device for the received program data, and updating the deduplication table. 1. An apparatus for controlling memory , the apparatus comprising:a memory device; anda controller functionally coupled to the memory device;a deduplication table for storing compressed data, a second address of the memory device in which non-compressed data corresponding to the compressed data has been written and a count value indicative of a write number of the data,wherein the controller is suitable for:compressing program data of a first address received in a data write operation;searching for the compressed data in the deduplication table; andif the compressed data is in the deduplication table, mapping a second address corresponding to the compressed data to the first address in the deduplication table and not performing a write operation of the memory device for the received program data.2. The apparatus of claim 1 , wherein if the compressed data is new claim 1 , the controller writes the program data in the second address of the memory device and registers a new entry comprising the compressed data and the second address with the deduplication table claim 1 , and wherein the compressed data comprises a hash value ...

STORAGE DEVICE THAT PERFORMS ERROR-RATE-BASED DATA BACKUP

A storage device includes a first non-volatile storage unit, a second non-volatile storage unit that includes a plurality of semiconductor memory blocks and is capable of executing data access at a speed faster than the first non-volatile storage unit, and a control unit configured to acquire an error value representing an amount of errors included in data read from a block of the second non-volatile storage unit, and carry out a backup of the data either in the first or second non-volatile storage unit, depending on the error value. 1. A storage device , comprising:a first non-volatile storage unit;a second non-volatile storage unit that includes a plurality of semiconductor memory blocks and is capable of executing data access at a speed faster than the first non-volatile storage unit; anda control unit configured to acquire an error value representing an amount of errors included in data read from a block of the second non-volatile storage unit, and carry out a backup of the data either in the first or second non-volatile storage unit, depending on the error value.2. The storage device according to claim 1 , whereinwhen the error value is greater than a first value and smaller than a second value that is greater than the first value, the control unit carries out the backup of the data in the first non-volatile storage unit, andwhen the error value is greater than the second value, the control unit carries out the backup of the data in the second non-volatile storage unit.3. The storage device according to claim 2 , whereinwhen the control unit carries out the backup of the data in the second non-volatile storage unit, the data are written in a block different from the block from which the data are read.4. The storage device according to claim 2 , whereinwhen the control unit carries out the backup of the data in the second non-volatile storage unit, the data are erased from the block from which said data are read.5. The storage device according to claim 2 , ...

ADJUSTING A RELIABILITY SCAN THRESHOLD IN A MEMORY SUB-SYSTEM

A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.

CLASSIFYING FLASH DEVICES USING ECC

An embodiment is a technique to classify a flash device. Test data to a flash device are accessed in unscramble and scramble modes under a test mode. Error correcting code (ECC) results are recorded on the test data for the unscramble and scramble modes. A device quality figure is calculated based on the ECC results for the unscramble and scramble modes. The flash device is classified using the device quality figure. 1. A method comprising:accessing test data to a flash device in unscramble and scramble modes under a test mode;recording error correcting code (ECC) results on the test data for the unscramble and scramble modes;calculating a device quality figure based on the ECC results for the unscramble and scramble modes; andclassifying the flash device using the device quality figure.2. The method of wherein accessing the test data to the flash device comprises:enabling scrambling on a flash controller for the scramble mode, the flash controller having interface to the flash device;disabling scrambling on the flash controller for the unscramble mode; andaccessing the test data to the flash device via the flash controller.3. The method of wherein accessing the test data to the flash device comprises:writing the test data to the flash device via a flash controller; andreading the test data from the flash device via a flash controller.4. The method of wherein the test mode includes at least one of a temperature condition and a program/erase (P/E) cycle condition.5. The method of wherein the temperature condition is one of a low temperature claim 4 , an average temperature claim 4 , and a high temperature.6. The method of wherein the P/E cycle condition is one of a low P/E cycle claim 4 , an average P/E cycle claim 4 , and a high P/E cycle.7. The method of wherein recording the ECC results comprises:recording at least one of a maximum number of ECCs, a minimum number of ECCs, an average number of ECCs, and a total number of ECCs and the corresponding test mode.8. The ...

Memory test device and operating method thereof

A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.

TESTING STORAGE DEVICE POWER CIRCUITRY

The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails. 1. A method for use at a storage device , the storage device including a plurality of flash memory devices , the method for testing power characteristics of the plurality of flash memory devices , the method comprising:accessing one or more memory command patterns for testing the plurality of flash memory devices;for each memory command pattern in the one or more memory command patterns, implement the memory command pattern at the plurality of flash memory devices; andidentifying the implemented memory command pattern, from among the one or more memory command patterns, that caused the greatest total current draw from the plurality of flash memory devices.2. The method of claim 1 , wherein accessing one or more memory command patterns comprises accessing a test matrix that contains the one or more memory command patterns.3. The method of claim 1 , further comprising:receiving a command to initiate a power test for the plurality of flash memory devices; andexecuting a test program embedded in the storage device in response to receiving the command; andwherein implementing the memory command pattern at the plurality of flash memory devices comprises the test program implementing the memory command pattern at the plurality of flash memory ...

Memory test method, storage medium and computer device

The present disclosure provides a memory test method, a storage medium and a computer device. The memory test method comprises: obtaining a target test pattern to be written into a plurality of chip interfaces, the plurality of chip interfaces being connected to a plurality of physical interfaces in a one-to-one correspondence; determining second information of the chip interfaces corresponding to first information of the physical interfaces, and using the first information and the second information as corresponding connection information; remapping the corresponding connection information to obtain mapped connection information; and determining, according to the target test pattern and the mapped connection information, an initial test pattern to be written into the physical interfaces.

MODELING MEMORY ARRAYS FOR TEST PATTERN ANALYSIS

A method includes receiving in a computing apparatus a model of an integrated circuit device including a memory array. The memory array is modeled as a plurality of device primitives. A test pattern analysis of the memory array is performed using the model in the computing apparatus. A system includes a memory array modeling unit and a test pattern analysis unit. The memory array modeling unit is operable to generate a model of an integrated circuit device including an memory array. The memory array is modeled as a plurality of device primitives. The test pattern analysis unit is operable to performing a test pattern analysis of the memory array using the model in the computing apparatus. 1. A method , comprising:receiving in a computing apparatus first and second models of an integrated circuit device including a memory array, wherein the memory array is modeled as a first plurality of device primitives in the first model and as a second plurality of device primitives in the second model, the second plurality of device primitives being different than the first plurality of device primitives;performing a test pattern analysis of the memory array using the first model in the computing apparatus to generate a plurality of test patterns for testing the memory array based on the first plurality of device primitives; andperforming a fault grading analysis of the memory array using the second model and the plurality of test patterns in the computing device to determine fault coverage for the second model.2. (canceled)3. The method of claim 1 , wherein the memory array comprises a plurality of bit cells and the first plurality of device primitives comprises a plurality of random access memory device primitives corresponding to the bit cells.4. The method of claim 3 , wherein the second model models the memory array as a plurality of latch device primitives corresponding to the bit cells.5. (canceled)6. The method of claim 1 , wherein the memory array comprises a plurality ...

METHODS FOR TESTING A STORAGE UNIT AND APPARATUSES USING THE SAME

The invention introduces a method for testing a storage unit, performed by a processing unit, including at least the following steps: after receiving a test write command from a host device through a first access interface, directing a second access interface to receive a first test pattern from a test writer and program the first test pattern into a PBA (Physical Block Address) of a storage unit; directing the second access interface to read a second test pattern from the PBA of the storage unit and output the second test pattern to a test reader; receiving a test result from the test reader; and generating a test message according to the test result and replying with the test message to the host device. 1. A method for testing a storage unit , performed by a processing unit , comprising:after receiving a test write command from a host device through a first access interface, directing a second access interface to receive a first test pattern from a test writer and program the first test pattern into a PBA (Physical Block Address) of a storage unit;directing the second access interface to read a second test pattern from the PBA of the storage unit and output the second test pattern to a test reader;receiving a test result from the test reader; andgenerating a test message according to the test result and replying the test message to the host device.2. The method of claim 1 , wherein the host device determines whether a block corresponding to the PBA of the storage unit is labeled as a bad block according to the test message.3. The method of claim 1 , wherein the test writer obtains first metadata from the host device and dummy data from a dummy-data generator and generates the first test pattern according to the metadata and the dummy data.4. The method of claim 3 , wherein the first metadata contains the PBA.5. The method of claim 3 , wherein the first test pattern comprises scrambled data corresponding to the dummy data claim 3 , the first metadata claim 3 , a ...

METHOD FOR TESTING STORAGE SYSTEMS, ELECTRONIC DEVICE, AND COMPUTER PROGRAM PRODUCT

Techniques test a storage system. Such techniques involve: acquiring a result of performing a first test on the storage system using a test case; if the result indicates that the storage system fails the first test, performing a second test on the storage system based on a problem of the storage system; and if the result indicates that the storage system passes the first test, determining a security level of the test case based on the result. Such techniques can effectively enhance test performance and system reliability of the storage system. 1. The method according to claim 16 , wherein executing the plurality of test cases includes:acquiring a result of performing a first test on the storage system using a test case;if the result indicates that the storage system fails the first test, performing a second test on the storage system based on a problem of the storage system; andif the result indicates that the storage system passes the first test, determining a security level of the test case based on the result.2. The method according to claim 1 , further comprising:if the result indicates that the storage system passes the first test, extending a scope of the test case as an extended test case;performing a third test on the storage system using the extended test case; andif the storage system passes the third test, determining a security level of the extended test case.3. The method according to claim 2 , wherein extending the scope of the test case comprises at least one of the following:increasing the number of features included in the test case; andincreasing the size of the features.4. The method according to claim 1 , wherein performing the second test on the storage system based on the problem of the storage system comprises:if the problem of the storage system cannot be solved,shrinking the scope of the test case as a shrunk test case, andperforming the second test on the storage system using the shrunk test case.5. The method according to claim 4 , wherein ...

SCAN OPTIMIZATION FROM STACKING MULTIPLE RELIABILITY SPECIFICATIONS

A variety of applications can include systems and/or methods of optimizing results from scanning a memory device, where the memory device has stacked multiple reliability specifications. Information about a block of multiple blocks of a memory device can be logged, where the information is associated with a combination of reliability specifications. A refresh of the block can be triggered based on exceeding a threshold condition for the combination of reliability specifications. Additional apparatus, systems, and methods are disclosed. 1. A system comprising: refrain from refreshing a block of multiple blocks of the memory device upon determining a failed scan of the block without information regarding a source of the failed scan, until a threshold condition other than the failed scan is exceeded; and', 'trigger a refresh of the block based on exceeding the threshold condition for at least one reliability specification of a combination of reliability specifications for the memory device., 'a storage device having stored instructions, executable by a processing device, to perform operations on a memory device, including operations to2. The system of claim 1 , wherein the combination of reliability specifications is associated with one or more of a scan error claim 1 , a bit rate error over time claim 1 , a bit rate error over temperature claim 1 , and a total number of data errors.3. The system of claim 1 , wherein the combination of reliability specifications includes two or more specifications selected from a data retention specification claim 1 , a cross temperature delta specification claim 1 , a number of program erase cycles specification claim 1 , and a number of read cycles specification.4. The system of claim 1 , wherein operations include operations to log operational data claim 1 , the operational data including an amount of time after the block is opened claim 1 , a number of scans after a last refresh claim 1 , or both the amount of time after the block ...

MEMORY TESTING OF THREE DIMENSIONAL (3D) STACKED MEMORY

A method includes reading, at a memory controller, data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack. The method also includes writing the data to a second DRAM die layer of the DRAM stack. The method further includes sending a request to a test engine to test the first DRAM die layer after writing the data to the second DRAM die layer. 1. A method comprising:reading, at a memory controller, first data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack comprising a plurality of stacked DRAM die layers;writing the first data to a second DRAM die layer of the DRAM stack; andafter writing the first data to the second DRAM die layer, sending a first request to a test engine to test the first DRAM die layer.2. The method of claim 1 , further comprising reading the first data in response to detecting a chip mark associated with the first DRAM die layer;3. The method of claim 2 , wherein the chip mark may be placed by firmware based on a periodic health check claim 2 , by an error correction code (ECC) decoder in response to detecting an error claim 2 , or both.4. The method of claim 1 , wherein the first request to the test engine includes a mode register set (MRS) command indicating the first DRAM die layer.5. The method of claim 4 , wherein the MRS command indicates a particular memory location of the first DRAM die layer.6. The method of claim 1 , further comprising sending a second request to the test engine to direct an access by the memory controller of the first DRAM die layer to the second DRAM die layer.7. The method of claim 6 , wherein the second request to the test engine includes a mode register set (MRS) command indicating the first DRAM die layer.8. The method of claim 1 , further comprising removing a chip mark associated with the first DRAM die layer after writing the first data to the second DRAM die layer.9. The method of claim 1 , further comprising receiving a result of testing the first DRAM die ...

MANAGING PROBABILISTIC DATA INTEGRITY SCAN INTERVALS

Exemplary methods, apparatuses, and systems include receiving read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A position in the sequence of read operations in the current set is determined such that the position that is preceded by at least a minimum number of read operations following a previous data integrity scan in a previous set of read operations. A data integrity scan is performed on a victim of the aggressor read operation at the determined position in the sequence of the current set of read operations. 1. A method comprising:receiving a plurality of read operations, the plurality of read operations divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations;selecting an aggressor read operation from the current set;determining a position in the sequence of read operations in the current set that is preceded by at least a minimum number of read operations following a previous data integrity scan in a previous set of read operations; andperforming a current data integrity scan on a victim of the aggressor read operation at the determined position in the sequence.2. The method of claim 1 , further comprising:storing an identifier of the aggressor upon reaching the aggressor read operation in the sequence of read operations in the current set; andusing the stored identifier to perform the current data integrity scan at the determined position in the sequence of read operations in the current set, the determined position differing from a position in the sequence preceding or following the aggressor read operation.3. The method of claim 1 , wherein each set includes N read operations claim 1 , the method further comprising:generating a first random number that is less than or equal to N, wherein selecting the aggressor read operation ...

Passive input/output expansion

Apparatus having first and second sets of memory devices commonly connected to receive a first enable signal and a second enable signal, respectively, and a multiplexer connected to receive the first and second enable signals. The multiplexer is configured to connect the first set of memory devices to an output of the apparatus in response to the first enable signal having a first logic level, and to isolate the first set of memory devices from the output in response to the first enable signal having a second logic level different than the first logic level. The multiplexer is further configured to connect the second set of memory devices to the output in response to the second enable signal having the first logic level, and to isolate the second set of memory devices from the output in response to the second enable signal having the second logic level.

BYTE ENABLE MEMORY BUILT-IN SELF-TEST (MBIST) ALGORITHM

A method and apparatus for memory built-in self-test (MBIST) may be configured to load a testing program from an MBIST controller, execute the testing program, and determine and write pass/fail results to a read-out register. For example, in various embodiments, the testing program may comprise one or more write operations that are configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted in order to test stability associated with a memory bitcell, create DC and AC noise due to byte enable mode stress, check at-speed byte enable mode timing, and execute a self-checking algorithm that may be designed to verify whether data is received at a data input (Din) pin. Any memory bitcells storing a value different from an expected value after performing the write operation(s) may be identified as having failed the MBIST. 1. A method for performing a memory built-in self-test (MBIST) , comprising:executing a testing program loaded from an MBIST controller, wherein the executed testing program comprises one or more write operations configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted;reading the data stored in the plurality of memory bitcells subsequent to performing the one or more write operations; andwriting MBIST pass/fail results to a read-out register, wherein the MBIST pass/fail results indicate failure with respect to any of the plurality of memory bitcells for which the data read therefrom differs from an expected value.2. The method recited in claim 1 , wherein the one or more write operations are configured to change the data stored in the plurality of memory bitcells according to one or more rotation patterns that alternate between odd and even memory addresses.3. The method recited in claim 2 , wherein the one or more rotation patterns comprise a first rotation pattern that starts with the ...

INFORMATION PROCESSING APPARATUS AND ACCESS CONTROL METHOD

A detection unit detects access status of an information recording device and forms the detected access status into access records at predetermined time intervals. A generation unit generates history information from the access records that have been formed over a predetermined period. A control unit selects an access record that has a predetermined relationship with the current time, out of the history information. A control unit determines when to start a diagnosis of the information recording device, assuming that the selected access record represents the current access status of the device. Specifically, the control unit instructs a diagnosis unit to start a diagnosis when the selected access record suggests that the diagnosis would not impose an excessive load on the information recording device. 1. An information processing apparatus comprising a processor configured to perform a procedure including:detecting access status of an information recording device and forming the detected access status into access records at predetermined time intervals;generating history information from the access records that have been formed over a predetermined period;selecting at least one of the access records that has a predetermined relationship with a current time, out of the history information; andcontrolling a start of a diagnosis of the information recording device on the basis of the selected access record.2. The information processing apparatus according to claim 1 , wherein:the selecting includes selecting a plurality of access records included within a predetermined time period starting from a time in the predetermined relationship with the current time; andthe controlling includes starting the diagnosis of the information recording device, when all of the selected access records satisfy a predetermined condition.3. The information processing apparatus according to claim 1 , wherein the procedure further comprises:controlling a halt or restart of the diagnosis of ...

LIFESPAN FORECAST FOR STORAGE MEDIA DEVICES

A method for improving a global lifespan of a storage system of a computing system is provided. The method includes: automatically determining a lifespan value of the at least one storage device to assign a global lifespan of the storage system, the global lifespan being dependent on the installation time of the at least one storage device; replacing, responsive to a time-based failure event, a storage device of the at least one storage device; and subsequently modifying, using the computing system, the global lifespan of the storage system based on the time-based failure event to define, at least in part, an optimized lifespan of the storage system. 1. A method for improving a global lifespan of a storage system of a computing system comprising at least one storage device , the method comprising the steps of:automatically determining a lifespan value of the at least one storage device to assign a global lifespan of the storage system, the global lifespan being dependent on the installation time of the at least one storage device;replacing, responsive to a time-based failure event, a storage device of the at least one storage device; andsubsequently modifying, using the computing system, the global lifespan of the storage system based on the time-based failure event to define, at least in part, an optimized lifespan of the storage system.2. The method of claim 1 , further comprising a prediction engine claim 1 , wherein the prediction engine is configured with a pre-defined algorithm claim 1 , and the automatically determining comprises determining lifespan values of each storage device of the at least one storage device from the installation time thereof claim 1 , and averaging the multiple lifespan values of each storage device to obtain a global lifespan value of the at least one storage device claim 1 , the global lifespan value being assigned to the pre-defined algorithm of the prediction engine to define the global lifespan of the storage system.3. The method ...

Memory and Its Addressing Method Including Redundant Decoding And Normal Decoding

A memory device and its addressing method are disclosed. The memory device includes: an input module for receiving an input signal including an access address, a command, and a decoding selection instruction; a memory array including memory blocks, each having memory units arranged in an array; and a control module including memory block local control units, which respectively connected to one of the memory blocks in one-to-one correspondence. The memory block local control unit includes: at least one decoding unit, which performs redundant decoding or normal decoding to the input signal. The input of the decoding unit is coupled to the input module and the output is coupled to one of the memory units. The device further includes a selection module; the input of the selection module is coupled to the input module, and the output is coupled to the decoding unit. The addressing efficiency of the memory device is improved. 1. A memory device , comprising:an input module for receiving an input signal, wherein the input signal includes an access address, a command, and a decoding selection instruction, wherein the access address includes a block address, a row address, and a column address;a memory array comprising a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of memory units arranged in an array;a control module connecting to an output of the input module, wherein the control module comprises a plurality of memory block local control units, wherein each of the plurality of memory block local control unit is connected to one of the plurality of memory blocks in one-to-one correspondence, wherein the plurality of memory block local control units each includes one decoding unit, wherein the decoding unit is configured to perform redundant decoding or normal decoding on the input signal, wherein an input of the decoding unit is coupled to the input module, an output of the decoding unit is coupled to one of the plurality ...

Devices and Methods to Write Background Data Patterns in Memory Devices

A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines. 1. A memory device comprising:a memory array comprising a plurality of memory cells; andone or more command controllers configured to receive one or more commands to initiate a Data Pattern Test mode and facilitate writing a data pattern to at least some of the plurality of memory cells, wherein the Data Pattern Test mode is configured to write the data pattern to the plurality of memory cells in the memory array while only receiving the data pattern via an external source once.2. The memory device of claim 1 , wherein the memory device comprises one or more counters configured to generate internal memory addresses to sequentially access the plurality of memory cells to write the data pattern to the memory cells.3. The memory device of claim 2 , wherein the one or more counters comprise a column address counter and a row address counter.4. The memory device of claim 3 , wherein the one or more counters comprise a bank address counter.5. The memory device of claim 1 , wherein the data pattern is written to the entire memory array.6. The memory device of claim 1 , wherein the data pattern is repeated a plurality of times across the memory cells.7. The memory device of claim 1 , wherein the one or more command controllers comprise:a Fast Zero controller configured to receive a Fast Zero command to initiate a Fast Zero mode to write logical 0s to each of the plurality of memory cells in the memory array; anda Data Pattern Test controller configured to receive a Data Pattern Test command to initiate the Data Pattern Test mode to write the data pattern to the plurality of memory cells in the memory array.8. The memory device of claim 7 , wherein ...

MEMORY SYSTEM QUALITY MARGIN ANALYSIS AND CONFIGURATION

A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system trigger threshold or an uncorrectable error correction condition threshold, which are set based on the error correction capabilities of a memory system. Formulating the comparison to these metrics can include determining a margin between the CDF-based data at a particular codeword frequency and one of the thresholds. 1. A method comprising:obtaining cumulative distribution function (CDF)-based data based on quality measures of a memory population;formulating a quality analysis by computing a margin based on a comparison of quality measure and an error amount threshold condition; andapplying results of the quality analysis to make improvements in a memory system by causing, based on the computed margin, one or more actions in relation to the memory system, the one or more actions comprising a modification to operating parameters for the memory system.2. The method of claim 1 , wherein the memory population comprises: a plurality of memory cells claim 1 , a plurality of memory pages claim 1 , a plurality of memory word lines claim 1 , a plurality of memory blocks claim 1 , a plurality of memory planes claim 1 , a plurality of memory dies claim 1 , or a plurality of memory devices claim 1 , or a combination thereof.3. The method of claim 1 , wherein the quality measures for the memory population comprise measures of bit errors per codeword.4. The method of claim 1 , wherein the CDF-based data ...

TESTING MEMORY CELLS BY ALLOCATING AN ACCESS VALUE TO A MEMORY ACCESS AND GRANTING AN ACCESS CREDIT

A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range 17-. (canceled)8. A method for testing memory cells under test of an integrated circuit , comprising:allocating an access value to a memory access;granting an access credit;forming a first signature on a data word segment of a first bit sequence;writing the data word segment of the first bit sequence to the memory cells under test;if the access value of the memory access does not exceed the access credit, reading a second bit sequence from the memory cells under test and reducing the access credit by the access value;forming a second signature on the second bit sequence; andsignaling if the second signature differs from the first signature, or signaling if the second signature matches the first signature.9. The method as claimed in claim 8 , wherein the formation of the first signature or the formation of the second signature comprises:determining a checksum on the data word segment,determining a hash on the data word segment,determining an error correction code (ECC) for the data word segment, or determining a checksum for the data word segment.10. The ...

TEST MODE SET CIRCUIT AND METHOD OF SEMICONDUCTOR DEVICE

A test mode set circuit includes: a first test mode set block suitable for setting entry into a first test mode based on a clock signal and first data outputted from a non-volatile memory during a first period of a boot-up operation; and a second test mode set block suitable for setting entry into a second test mode based on the first data and second data outputted from the non-volatile memory during a second period of the boot-up operation, or setting entry into the second test mode based on a set signal generated by a combination of a command and an address during a normal operation. 1. A test mode set circuit comprising:a first test mode set block suitable for setting entry into a first test mode based on a clock signal and first data outputted from a non-volatile memory during a first period of a boot-up operation; anda second test mode set block suitable for setting entry into a second test mode based on the first data and second data outputted from the non-volatile memory during a second period of the boot-up operation, or setting entry into the second test mode based on a set signal generated by a combination of a command and an address during a normal operation.2. The test mode set circuit of claim 1 , wherein the first and second periods of the boot-up operation are divided on a basis of a time when a value obtained by counting the clock signal reaches a maximum value.3. The test mode set circuit of claim 1 , wherein the second test mode set block sets entry into the second test mode based on the set signal generated by the combination of the command and the address in an idle state during the normal operation.4. The test mode set circuit of claim 1 , wherein the first and second test mode set blocks are reset based on an exclusive reset signal which is distinct from a global reset signal.5. The test mode set circuit of claim 1 , wherein the first test mode set block sets entry into the first test mode if at least one bit of the first data of N bits has a ...

METHOD AND SYSTEM FOR TESTING FIRMWARE OF SOLID-STATE STORAGE DEVICE, AND ELECTRONIC APPARATUS

A method for testing firmware of an SSD includes: controlling a main memory to emulate volatile and non-volatile memories of the SSD, fetching a testing sequence and a testing criterion, fetching read/write operations from binary codes generated by compiling the firmware, determining whether the read/write operations are associated with a marker, executing the read/write operations when a result of determination is affirmative, otherwise discarding a read/write of data, monitoring whether processes of executing of the read/write operations meet the testing criterion, and generating a result of a test of the firmware when it is monitored that the testing criterion is met. 1. A method for testing firmware of a solid-state storage device to be implemented by a computing apparatus which includes a central processing unit (CPU) , a main memory , and a storage that stores at least one testing criterion , the method comprising:providing, by one of the main memory and the storage, binary codes generated by compiling the firmware of the solid-state storage device according to an instruction set architecture of the computing apparatus;controlling, by the CPU, the main memory to emulate a volatile memory of the solid-state storage device to provide an emulated volatile memory;controlling, by the CPU, the main memory to emulate anon-volatile memory of the solid-state storage device to provide an emulated non-volatile memory;fetching, by the CPU, a testing sequence which includes a read request to access a logical address of the solid-state storage device and a write request to access another logical address of the solid-state storage device;fetching, by the CPU according to the testing sequence, a read operation and a write operation from the binary codes;determining, by the CPU, whether the read operation is associated with a marker indicating that data to be read from a physical address corresponding to the logical address are unrelated to firmware operation;executing, by the ...

Static random access memory free from write disturb and testing method thereof

A static random access memory (SRAM) includes a memory cell array, a row decoder, a plurality of word-line drivers and an arbiter. The memory cell array includes a plurality of memory cell rows, wherein the memory cell rows are enabled by a plurality of word-lines, respectively. The row decoder is arranged to assert one of the memory cell rows according to a row address. The plurality of word-line drivers are each coupled to the row decoder and one of the memory cell rows. The arbiter is arranged to prevent multiple memory cells at a same word-line from being accessed at a same time.

Delay fault testing of pseudo static controls

A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODULE TESTING METHOD

A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data. 1. A memory device comprising:a memory module; and a pattern generator configured to generate first main data including a first portion;', 'an error correction code (ECC) encoder configured to generate first parity data based on the first main data; and', 'a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data,, 'a built-in self-test (BIST) logic circuit configured to perform testing on memory cells of the memory module, the BIST logic circuit includingwherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.2. The memory device of claim 1 , wherein the parity control circuit is configured to send write data including the first main data and the first substituted parity data to the memory module claim 1 , receive read data including second main data and second substituted parity data from the memory module claim 1 , and generate second parity data based on the second substituted parity data and the mask data claim 1 , andthe BIST logic circuit includes an ECC decoder configured to correct an error in the second main data based on the second parity data.3. The memory device of claim 2 , wherein the parity control circuit includes:a ...

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR EARLY DETECTION OF POTENTIAL FLASH FAILURES USING AN ADAPTIVE SYSTEM LEVEL ALGORITHM BASED ON FLASH PROGRAM VERIFY

Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify are disclosed. According to one aspect, a method for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify includes performing a program verify operation after a write to a non-volatile memory, where the program verify mechanism reports a pass or fail based on an existing measurement threshold value, and dynamically adjusting the measurement threshold value used by subsequent program verify operations based on the results of previous program verify operations. 1. A method for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify , the method comprising:performing a program verify operation after a write to a non-volatile memory, wherein the program verify mechanism reports a pass or fail based on an existing measurement threshold value; anddynamically adjusting the measurement threshold value used by subsequent program verify operations based on the results of previous program verify operations.2. The method of wherein the non-volatile memory comprises memory cells organized into at least one page claim 1 , at least one page organized into at least one block claim 1 , and at least one block occupying at least one die.3. The method of wherein dynamically adjusting the measurement threshold value comprises at least one of:dynamically adjusting a threshold per page;dynamically adjusting a threshold per block; anddynamically adjusting a threshold per die.4. The method of wherein dynamically adjusting the measurement threshold value comprises determining that the program verify mechanism has reported a fail claim 1 , and claim 1 , in response to determining that the program verify mechanism has reported a fail:determining whether the failure is recoverable;in response to determining that the ...

REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED DATA BOUNDARIES

Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache. 1. A computer-implemented method executed by at least one processor for testing a computer processor device comprising:providing test data comprising a plurality of segments of test data that together make a slice of test data, wherein each of the plurality of segments are non-naturally aligned where the beginning and ending of each of the plurality of segments when placed end to end in a memory do not line up with a cache line boundary, wherein the plurality of segments comprise an odd number of words where the odd number is chosen from 5, 7, 9, and 11;placing multiple instances of the slice of test data in consecutive locations in a cache memory; andrunning a test code on the consecutive slices of test data with non-naturally aligned boundaries by branching back to rerun the test code on each of the slices of test data.2. The method of wherein the step of running a test code on the consecutive slices of test data with non-naturally aligned boundaries further comprises:executing test code with one or more test cases on a first slice of test data of the plurality of test data slices using a base offset;determining if there are additional slices of test data; andwhere there are additional slices of test data, modifying the base offset to point to a next test data slice and branching back to execute the test code with the modified base offset.3. The method of wherein the plurality ...

SEMICONDUCTOR TEST DEVICE AND SEMICONDUCTOR TEST METHOD

There is provided a semiconductor test device, including: a test information acquisition unit acquiring test information; a test information conversion unit converting the acquired test information into test vector information including a plurality of test vectors; and a test signal generation unit generating a test input signal based on the test vector information. 1. A semiconductor test device , comprising:a test information acquisition unit acquiring test information;a test information conversion unit converting the acquired test information into test vector information including a plurality of test vectors; anda test signal generation unit generating a test input signal based on the test vector information.2. The semiconductor test device of claim 1 , wherein the test vector information conversion unit converts the test information having a first clock rate into test vector information having a second clock rate faster than the first clock rate.3. The semiconductor test device of claim 1 , wherein the test information acquisition unit acquires a plurality of test information items.4. The semiconductor test device of claim 1 , further comprising a test vector information storage unit storing the test vector information.5. The semiconductor test device of claim 4 , wherein the test vector information storage unit stores a pattern of the test vector.6. The semiconductor test device of claim 1 , further comprising:a sense unit acquiring a test output signal in response to the test input signal; anda control unit determining whether a device under test is faulty, based on the test input signal and on the test output signal.7. A semiconductor test method claim 1 , comprising:acquiring test information;converting the acquired test information into test vector information including a plurality of test vectors; andgenerating a test input signal based on the test vector information.8. The semiconductor test method of claim 7 , wherein the converting of the test vector ...

PROTECTION OF THE CONTENT OF A FUSE MEMORY

The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state. 1. A method , comprising:verifying, by a finite state machine, values of a first fuse word and values of a second fuse word in a fuse-type non-volatile memory of an integrated circuit, the first fuse word being representative of a number of transitions to a first state of the integrated circuit, the second fuse word being representative of a number of transitions to a second state of the integrated circuit;allowing read access to a first area of the fuse-type non-volatile memory by a processor in the first state based on the verifying the values of the first fuse word and the values of the second fuse word; andforbidding read access to the fuse-type non-volatile memory by the processor in a second state of the integrated circuit based on the verifying the values of the first fuse word and the values of the second fuse word.2. The method of claim 1 , wherein the verifying comprises comparing the values of the first fuse word against the values of the second fuse word and based on a value of a maximum significant bit of the first fuse word.3. The method of claim 2 , wherein the first state corresponds to a state of the integrated circuit where:the value of the second fuse word is less than the value of the first fuse word, orthe maximum significant bit of the first fuse word is blown.4. The method of claim 1 , wherein the verifying is performed at each reset of the integrated circuit claim 1 , and ...

ENABLING HIGH AT-SPEED TEST COVERAGE OF FUNCTIONAL MEMORY INTERFACE LOGIC BY SELECTIVE USAGE OF TEST PATHS

A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output. 1. A device comprising:one or more cores under test;a clock control circuit coupled to the cores under test, that selectively provides a slow-speed operation or an at-speed operation for an enabled clock; and one or more memories;', 'a clock gating circuit that selectively enables clocks to drive test sequences to inputs of the memories or to capture the output of the memories;', 'a mode control circuit that selectively controls a test mode on the inputs of the memories or the outputs of the memories, wherein selective control of the test mode is implemented during the slow-speed operation or the at-speed operation of the enabled clock., 'a built-in-self-test (BIST) controller coupled to the cores under test; wherein each core under test includes2. The device of claim 1 , wherein the memories are coupled to one another claim 1 , and testing of the memories is performed independent of one another.3. The device of claim 1 , wherein the mode control circuit includes hold flip-flops to prevent switching test modes during an at-speed scan capture.4. The device of claim 3 , wherein the test mode includes a BIST mode or a functional mode.5. The device of claim 1 , wherein the mode control circuit switches to a BIST mode to initialize the memories at slow-speed operation claim 1 , wherein initialization is implemented using a BIST controller logic for one or more slow-speed scan capture cycles.6. The device of claim 1 , wherein the mode control circuit selects a functional mode to execute a memory output ...

DETECTING MISSING WRITE TO CACHE/MEMORY OPERATIONS

Using an “optimized” test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location. The optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case. 1. A method comprising: a plurality of write locations, and', 'a plurality of read locations;, 'creating an optimized test case designed to be run on a data storage device including a plurality of storage locations, the optimized test case definingwriting initialization data, on the data storage device, only to the write locations of the data storage device; andrunning the optimized test case on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location;wherein:the optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case.2. The method of wherein the running of the optimized test case is a second run of the optimized test case claim 1 , the method further comprising:initially running the optimized test case on the data storage device;further wherein:the initial running and the ...

COMBINED RANK AND LINEAR ADDRESS INCREMENTING UTILITY FOR COMPUTER MEMORY TEST OPERATIONS

Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed. 1a memory address map register configured to selectively store memory address maps for a plurality of different types of memory configurations;a rank register configured to store a plurality of rank address bits mapped from the memory address map register corresponding to one or more rank address fields of the memory address map register, wherein the rank register maps to rank address fields of the selected memory address register that are not contiguous;a non-rank register configured to store a plurality of non-rank address bits mapped from the memory address map register corresponding to one or more non-rank address fields of the memory address map register, wherein the non-rank register maps to non-rank address fields of the selected memory address register that are not contiguous;a selected address register configured to define a range of selected memory addresses within the selected address register based on a sequence of bits mapped from the rank register and the non-rank register;a ...

CONTROL METHOD FOR MEMORY DEVICE AND MEMORY CONTROLLER

A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a code word through a polar code transformation. Select a boundary bit-channel among the bit-channels according to a first ranking list for the bit-channels. Identify a target memory cell among the memory cells according to the boundary bit-channel and a generator matrix of the polar code transformation. Decrease a raw bit error rate of the target memory cell. 1. A control method for a memory device , the control method comprising:converting, by a polar encoder, a plurality of input bits on a plurality of bit-channels into a code word through a polar code transformation, wherein the code word is written to a plurality of memory cells in the memory device;selecting, by a proactive channel adjustment unit, a boundary bit-channel among the plurality of bit-channels according to a first ranking list for the plurality of bit-channels provided by a ranking unit;identifying, by the proactive channel adjustment unit, a target memory cell among the plurality of memory cells according to the boundary bit-channel and a generator matrix of the polar code transformation; anddecreasing, by the proactive channel adjustment unit, a raw bit error rate of the target memory cell;wherein the step of decreasing the raw bit error rate of the target memory cell comprises:reducing, by the proactive channel adjustment unit, a number of program/erase (P/E) cycles applied to the target memory cell.2. (canceled)3. The control method according to claim 1 , wherein the target memory cell has a corresponding logical address claim 1 , the step of reducing the number of P/E cycles applied to the target memory cell comprises:mapping, by the proactive channel adjustment unit, the logical address of the target cell to another physical memory region other than an original physical region of the target memory cell.4. The control method according to ...

DATA RETENTION ERROR DETECTION SYSTEM

A particular method includes selecting a threshold data retention time of a magnetic tunnel junction (MTJ) memory cell. A pinned layer of the MTJ memory cell has a first direction of magnetization, and a free layer of the MTJ memory cell has a second direction of magnetization. An external magnetic field that has a third direction of magnetization that is opposite to the second direction of magnetization is applied to the MTJ memory cell. A strength of the external magnetic field is determined based on the threshold data retention time. Subsequent to applying the external magnetic field, a read operation is performed on the MTJ memory cell to determine a logic value of the MTJ memory cell. The method further includes determining whether the MTJ memory cell is subject to a data retention error corresponding to the threshold data retention time based on the logic value. 1. A method comprising:selecting a threshold data retention time of a magnetic tunnel junction (MTJ) memory cell, wherein a pinned layer of the MTJ memory cell is configured to have a first direction of magnetization, and wherein a free layer of the MTJ memory cell is configured to have a second direction of magnetization;applying an external magnetic field to the MTJ memory cell, wherein the external magnetic field has a third direction of magnetization that is opposite to the second direction of magnetization, and wherein a strength of the external magnetic field is determined based on the threshold data retention time;subsequent to applying the external magnetic field, performing a read operation on the MTJ memory cell to determine a logic value of the MTJ memory cell; anddetermining whether the MTJ memory cell is subject to a data retention error corresponding to the threshold data retention time based on the logic value.2. The method of claim 1 , further comprising:before applying the external magnetic field, programming the pinned layer to have the first direction of magnetization; andbefore ...

AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING

An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode. 1. A method for automated test pattern generation (ATPG) , the method comprising the step of generating a test pattern using respective ATPG memory address locations of a memory coupled to a logic circuit under test.2. The method as claimed in claim 1 , wherein the ATPG memory address locations comprise the same column in two rows of a column mux=“m” memory claim 1 , where m≧1.3. The method as claimed in claim 2 , wherein a memory cell at said column in one of said two row lines is programmed for program value ‘0’ and a memory cell at said column in the other of said two row lines is programmed for program value ‘1’.4. The method as claimed in claim 3 , wherein selecting between program value ‘0’ and program value ‘1’ is controlled by controlling precharge devices coupled to BLT and BLB of the respective memory cells.5. The method as claimed in claim 4 , wherein claim 4 , where m>1 claim 4 , selecting between program value ‘0’ and program value ‘1’ is further controlled by controlling column mux devices coupled to BLT and BLB of the respective memory cells.6. The method as claimed in claim 5 , wherein logic levels of the column mux devices are controlled to be opposite to those of the precharge devices7. The method as claimed in claim 1 , wherein claim 1 , when the memory is organized as column mux=“m” claim 1 , where m>1 claim 1 , the ATPG memory address locations comprise different columns in a single row.8. The method as claimed in claim 7 , wherein a memory cell at one of said different columns is programmed for program value ‘0’ and a memory cell at the other column is programmed for program value ‘1’.9. The method as claimed in ...

AUTOMATIC MEMORY OVERCLOCKING

Automatic memory overclocking, including: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting passing the memory stability test; and generating a profile including the overclocked memory frequency setting. 1. A method of automatic memory overclocking , the method comprising:increasing a memory frequency setting for a memory module until a memory stability test fails;determining an overclocked memory frequency setting comprising a highest memory frequency setting passing the memory stability test; andgenerating a profile comprising the overclocked memory frequency setting.2. The method of claim 1 , wherein increasing the memory frequency setting for the memory module until the memory stability test fails comprises determining one or more memory timing settings claim 1 , and the method further comprises:determining one or more overclocked memory timing settings comprising the one or more memory timing settings corresponding to the overclocked memory frequency setting; andwherein generating the profile comprises generating the profile comprising the one or more overclocked memory timing settings.3. The method of claim 2 , wherein the one or more memory timing settings comprise one or more of: a Column Access Strobe (CAS) latency claim 2 , a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write) claim 2 , a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Read) claim 2 , a Row Precharge Time claim 2 , and/or a Row Active Time.4. The method of claim 2 , further comprising:determining one or more subtiming settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; andwherein generating the profile comprises generating the profile comprising the one or more subtiming settings.5. The method of claim 4 , wherein the one or more subtiming settings are ...

METHOD AND SYSTEM FOR PREDICTING BLOCK FAILURE IN A NON-VOLATILE MEMORY

A method and system are disclosed for improved block erase cycle life prediction and block management in a non-volatile memory. The method includes the storage device tracking information relating to a first erase cycle count at which the block erase time exceeded a predetermined threshold relative to a first erase cycle at which this occurred in other blocks. Blocks having a later relative erase cycle at which the erase time threshold is exceeded are assumed to have a greater erase cycle life than those that need to exceed the erase time threshold at an earlier erase cycle. This information is used to adjust wear leveling in the form of free block selection, garbage collection block selection and other block management processes. Alternatively or in combination, the predicted erase cycle life information is used to adjust program and/or erase parameters such as erase voltage and time. 1. A non-volatile memory device comprising:a plurality of blocks of non-volatile memory cells, each of the plurality of blocks comprising a plurality of the non-volatile memory cells; and monitor a time necessary to erase each of the plurality of blocks;', 'identify a first time when the time necessary to erase for a block takes longer than a predetermined threshold; and', 'store an indicator for each of the plurality of blocks identified as taking longer than the predetermined threshold., 'a controller in communication with the plurality of blocks, wherein the controller is configured to2. The non-volatile memory device of claim 1 , wherein the controller is configured to monitor the time necessary to erase based on a number of erase loops executed on each block claim 1 , wherein an erase loop comprises a fixed length process of applying an erase voltage and determining an erase state after applying the erase.3. The non-volatile memory device of claim 2 , wherein the predetermined threshold comprises a predetermined number of erase loops.4. The non-volatile memory device of claim 1 , ...

SYSTEMS AND METHODS FOR MEMORY MANAGEMENT IN A DYNAMIC TRANSLATION COMPUTER SYSTEM

Systems and methods for managing memory in a dynamic translation computer system are provided. Embodiments may include receiving an instruction packet and processing the instruction packet. The instruction packet may include one or more instructions for obtaining a block of virtual memory for use in an emulated operating environment from a slab of virtual memory in a host environment, maintaining a mapping between the block of virtual memory and physical memory when the block is returned to the host environment, and for filling the block of virtual memory with zeros and a pattern based, at least in part, on a detected fill type. 1. A method , comprising:obtaining, by a processor, a block of virtual memory for use in an emulated operating environment from a slab of virtual memory in a host environment;detecting, by the processor, the fill type of the block of virtual memory; andfilling, by the processor, the block of virtual memory with zeros and a pattern based, at least in part, on the detected fill type.2. The method of claim 1 , wherein the fill type is partial fill.3. The method of claim 2 , wherein filling the block comprises partially filling the Hock of virtual memory with zeros claim 2 , and filling the remainder of the block with a pattern when the fill type is detected to be a partial fill.4. The method of claim 1 , further comprising disabling local-timer interrupts.5. The method of claim 1 , further comprising receiving an inter-processor communication instruction packet claim 1 , wherein the step of obtaining is initiated after receipt of the inter-processor communication instruction packet.6. The method of claim 5 , further comprising checking the instruction packet for errors.7. A computer program product claim 5 , comprising: obtaining a block of virtual memory for use in an emulated operating environment from a slab of virtual memory in a host environment;', 'detecting the fill type of the block of virtual memory; and', 'filling the block of virtual ...