SEMICONDUCTOR INTEGRATED CIRCUIT
According of the present invention number 1 embodiment also Figure 1 shows a a plurality of DRAM circuit (macro circuit) a mixed DRAM a same semiconductor chip LSI is mounted on a block at least one of a semiconductor. Figure 2 shows a LSI DRAM of 2 in test the body by penetrating the circuit order of access in the event of a access to describe the type which represents a pattern of Figure 1. Figure 3 shows a of Figure 1 LSI 2 in the body by penetrating the circuit DRAM of test in the event of a flow right chart that indicates an order of access. Figure 4 shows a:an of the present invention number 2 embodiment also at least one of a semiconductor LSI logic mixed DRAM a block. A plurality of DRAM circuit according to of the present invention number 3 embodiment also Figure 5 shows a (macro circuit) and a logic circuit (macro circuit) 1 of a same semiconductor chip a is mounted on a block at least one of a semiconductor LSI logic mixed DRAM. In Figure 6 shows a of Figure 5 LSI DRAM of 2 for reading data alternately in such circuit carry out data transmission the optical signal to the outside when flow right chart that indicates an order of access. Figure 7 shows a plurality of also incorporating that DRAM of the existing method LSI 2 in DRAM of continuously tested circuit order of access in the event of a access to describe the flow right chart and mimetic which represents a pattern. DRAM plurality of Figure 8 of the existing method LSI incorporating that DRAM of 2 in continuously tested circuit that indicates an order of access in the event of a flow right chart. DRAM plurality of synchronous Figure 9 incorporating that DRAM of the existing method LSI 2 in same circuit of the control signal has data out of circuit DRAM in case of transmission flow right chart that indicates an order of access. Figure 10 shows a also DRAM circuit of banks which are representative of a a portion the ted 1 disclosed is a circuit. '' Description of the sign for major part of the drawings 11: number 1 DRAM circuit 12: number 2 DRAM circuit 13: control circuit 14: input selector 15: output selector 16: test control input terminal 17: macro input terminal 18: macro output terminal The present invention refers to same plurality of macroblocks on the semiconductor chip macro plurality incorporating that relates to semiconductor integrated circuit mounted, in particular data or each Macroblock circuit testing, etc. for carrying out control circuit controls a, plurality of DRAM LSI incorporating that, plurality of DRAM DRAM the selector distributes mixed circuit apparatus and d/logic mixed LSI is deposited on the.. Macro plurality incorporating that plurality of macroblocks as LSI mounted, plurality of DRAM circuit (macro circuit) a DRAM or, DRAM circuits and other kinds of macro circuit (e.g. a logical circuit) for the selector distributes mixed such as LSI logic mixed DRAM. Conventional, plurality of DRAM in LSI incorporating that, when testing the circuit DRAM plurality of each DRAM circuit. the present invention can perform test operation. Also 7 and Figure 8 shows a also, for example synchronous plurality of DRAM of the existing method LSI incorporating that DRAM of 2 in continuously tested circuit order of access in the event of a access to describe the is flow right chart and mimetic which represents a pattern. I.e., first, number 1 DRAM circuit, all column initial row access and sequentially of memory cells, this access to the next low. to low last from. Furthermore, said number 1 DRAM circuit number 2 DRAM accesses be freely carried by circuit. In this case, each access of lines circuit number 1 DRAM, bank active signal BACT low selection of activating an respective columns performed after the lead order (READ) that performs access period BPRC precharge signal and bit lines tRAS the bitstream syntax is described by a precharge period that performs precharge line requires tPR, each access of lines even for circuit in addition number 2 DRAM tRAS and precharge period access period requiring a tPR. However, as said each DRAM when a member makes an access circuit, and the time required until precharge from active each circuit each DRAM tRAS and a, and the time required until active from precharge tRP requiring an extent to a test time is too long upper: to prevent the. Figure 9, for example synchronous plurality of DRAM of the existing method LSI incorporating that of 2 in the control signal has same circuit DRAM DRAM data out of circuit in case of transmission that indicates an order of access is flow right chart. I.e., first, number 1 DRAM circuit, all column initial row accesses sequential of memory cells. Furthermore, number 2 DRAM circuit, all column initial row accesses sequential of memory cells. Number 1 DRAM and number 2 DRAM access for the circuit for the circuit while alternately switched to access, until low last from low next a repeated access. In this case, each access each row, bank active signal BACT low selection of activating an respective columns performed after the lead order that performs access period BPRC precharge signal and bit lines tRAS the bitstream syntax is described by line other after a precharge operation from a time recorded DRAM BACT bank active signal circuit, to activate defense up to requiring a tPR a precharge period. However, as said plurality of accesses alternately to the different circuit DRAM DRAM circuit when transmitting data read from, each as said active each circuit and the time required until precharge from DRAM tRAS and a, other then is pre-charged and the time required until the lock is active circuit DRAM tRP requiring an extent to overhead is to make it possible to produce time, data in high speed transmitting an. problems when try to. Also part of the ted the 1O DRAM circuit of banks 1 to represent the into a representative. Memory cells array WLi word line disposed in the row direction and a orthogonal to bit lines BLi arranged to the column direction, / BLi of the crossing sections of the positioned to correspond (matrix disposed) a 1 transistor, 1 capacitor configured MC of memory cells consisting of sub cell array part and, can lie in the sub cell array part and is located on each side of, the selected row of memory cells MC bit line from a BLi BLi/or read at S/A sense amplifier amplifying data is provided with group, column select line CSLi and the option selected by a column switch CS writing/of data via an. pixel data is read out. DRAM plurality of as said incorporating that each of the existing method LSI DRAM circuit read from the want to in order to specify the logic high. problems when a. Furthermore, each DRAM circuit when testing the test time of long down a upper. The present invention refers to said inputted into an analog multiplexer been made to, plurality of DRAM circuit read data in order to specify the logic high macro plurality it is possible to to provide a semiconductor integrated circuit mounted in. Furthermore, a plurality of other of the present invention when testing the circuit DRAM a head of a plurality macro mounted by a rope. to provide a semiconductor integrated circuit. A plurality of semiconductor integrated circuit mounted macro plurality of the present invention number 1 DRAM circuit and, each said terminal for a test control signal by setting up test control and input/output control for the circuit DRAM the body by penetrating the and a control circuit having a function, and is controlled by said control circuit, said signal input macro DRAM plurality of DRAM one of any circuit 1 has an input selector and the task of supplying a, under the control of said control circuit, the panel during normal operation and any circuit DRAM plurality of said 1 loops, then the macro-signals are selected and to output terminal, test at the time of said plurality of DRAM circuit the macro selection control output signal to output terminal having a function for having an output selector for is characterised in that it has a. A plurality of semiconductor integrated circuit mounted macro plurality of the present invention number 2 DRAM circuit and, said plurality of DRAM which are associated with the respective respectively, a pressure receiving part receiving a control signal input circuit DRAM, each corresponding to a function control of a number of control circuit and having, a pressure receiving part receiving a control signal input is controlled in such a manner that said, the panel during normal operation and any circuit DRAM plurality of said 1 loops, then the macro-signals are selected and to output terminal, test at the time of said plurality of DRAM circuit the macro selection control output signal to output terminal having a function for having an output selector for is characterised in that it has a. A plurality of semiconductor integrated circuit mounted macro plurality of the present invention number 3 DRAM circuit and, a pressure receiving part receiving a control signal input in addition simultaneously circuit DRAM plurality of said individually control a separate control function individual control circuit and, plurality of said signal input macro DRAM DRAM one of any circuit 1 has an input selector and the task of supplying a, any circuit DRAM plurality of said 1 loops, macro, thereby having a function to output terminal an output selector for is characterised in that it has a having. Hereinafter, reference to drawing of the present invention embodiment. as further described thereby, the cold air flows. 'Number 1 in the embodiment' According a plurality of DRAM circuit number 1 embodiment also Figure 1 shows a (macro circuit) a same semiconductor chip LSI is mounted on a. blocks at least one of a semiconductor. LSI chip is number 1 DRAM circuit (11) and a, number 2 DRAM circuit (12) and a, terminal for a test control signal by setting up of 2 DRAM circuit (11, 12) located on a lowest layer control a control circuit having a function (13) and a, input selector (14) and output selector (15) is provided. Each controller chip LSI input terminal to controlled control signal input (16) and a, for signal input macro DRAM macro input terminal (17) and a, between the output macro DRAM output terminal of macroblocks (18) is provided with. And, said test control input terminal (16) a control circuit (13) is connected to, macro input terminal (17) the input selector (14) is connected to a side of a, macro output terminal (18) the output selector (15) is connected to the. Input selector (14) has the address inputs to the, data input and the like a input in time series by arranging a first signal input macro DRAM, of 2 DRAM circuit (11, 12) the task of supplying a on one side of the semiconductor substrate any (panel during normal operation and) and both the task of supplying a [control circuit (13) in controlled test by] has. Output selector (15) of the 2 DRAM circuit (11, 12) on one side of the beer in any the macro selection control output signal output terminal (18) to (panel during normal operation and) and a function, of 2 DRAM circuit (11, 12) of each output signal alternately selection control the macro output terminal (18) to a function (test circuit when controlled test by) has. Also in Figure 3 shows a LSI and 2, for example synchronous of two 2 DRAM circuit (11, 12) access in the event of a test the body by penetrating the order of access to describe the type is flow right chart and which represents a pattern of Figure 1. Control circuit (13) if the control signal input, of 2 DRAM circuit (11, 12) the body by penetrating the for testing the input selector (14) by controlling the 2 signal input macro DRAM of DRAM circuit (11, 12) and inputs for both of a, output selector (15) by controlling the of 2 DRAM circuit (11, 12) alternately selects and each output signal of the macro-output terminal (18) controls the to to. At this time, two 2 DRAM circuit (11, 12) of the first low preferentially over, number 1 DRAM circuit (11) and accessing a memory cell order respective columns of, continue to, number 2 DRAM circuit (12) angled relative to each column order is accessing a memory cell. Such access, of 2 DRAM circuit (11, 12) subsequent low. to low last from. Wherein, two 2 DRAM circuit (11, 12) of one row the time required to access the BACT bank active signal after of activating an number 1 DRAM circuit (11) respective columns of the lead order (READ) that performs a scheduled duration and a scheduled rate access number 1, output selector (15) by controlling the number 1 DRAM circuit (11) of predetermined width data output time and the number 1, number 2 DRAM circuit (12) of the lead (READ) respective columns order that performs a scheduled duration and a scheduled rate access number 2, bit line precharge signal precharge line the bitstream syntax is described by BPRC that performs precharge time and, output selector (15) by controlling the number 2 DRAM film (12) of predetermined width data is the number 2 output period. Yet, precharge time and for replacing order from number 2 output period. may be. Of 2 as said DRAM circuit (11, 12) simultaneously while controlling test by performing parallel, compared to lower electrode comes short test time the test efficiency DRAM mixed LSI. can be realized. < 제 2 실시예 > The above-mentioned number 1 embodiment 2 of the LSI mixed DRAM the first deoxygenator DRAM circuit (11, 12) one control circuit 1 a (13) but control common by to, test added circuit for DRAM circuit even for a several DRAM mixed LSI, which presentation the embodiment number 1 embodiment aspect, a, examples of which. to hereinafter. Number 2 embodiment also Figure 4 shows a mixed logic LSI: an DRAM. blocks at least one of a semiconductor. Is number 1 DRAM circuit LSI chip (41a) and a, number 2 DRAM circuit (42a) and a, by setting up terminal for a test control signal number 1 DRAM circuit (41a) for conducting tests variety of to with number 1 test circuit (41b) and a, by setting up terminal for a test control signal number 2 DRAM circuit (42a) located on a lowest layer for conducting tests with test circuit number 2 (42b) and a, output selector (25) is provided. LSI chip the control input terminal (26) and a, for signal input macro DRAM macro input terminal (27) and a, between the output macro DRAM output terminal of macroblocks (28) is provided with. And, control input terminal (26) the number 1 test circuit (41a) and number 2 test circuit (42a) is consecutively connected common to, macro input terminal (27) the number 1 test circuit (41b) and number 2 test circuit (42b) is connected common to, macro output terminal (28) the output selector (25) is connected to the. Address input, data input and the like that are input to a signal input macro DRAM time series number 1 test circuit (41b) through the number 1 DRAM circuit (41a) is input into, in addition number 2 test circuit (42b) through the number 2 DRAM circuit (42a) is input to. Output selector (25) the number 1 DRAM circuit (41a) from test circuit number 1 (41b) output signal and outputs a processed Image signal number 1 number 2 DRAM circuit (42a) from test circuit number 2 (42b) number 2 outputs a processed Image signal output terminal then the macro-an output signal (25) to a function (panel during normal operation and) and, number 1 number 2 output signal and alternately selects and output signal then the macro-output terminal (25) to has a function (during test). Even in said number 2 embodiment the first deoxygenator DRAM mixed logic LSI, for example synchronous of DRAM circuit of 2 (41a, 42a) when test the body by penetrating the, operation of LSI is emitted to the access number 1 embodiment the first deoxygenator input signal is inverted to be inputted, the free surfaces effect can be achieved similar to that of examples of the number 1 embodiment. Also, as needed, test circuit number 1 (41b) and number 2 test circuit (42b) output data compression (for example 8 bit compressed into 128 bits) may be having function of.. < 제 2 실시예의 변형예 > The above-mentioned number 2 embodiment the first deoxygenator the LSI test circuit number 1 signal input macro DRAM (41b) and number 2 test circuit (42b) signals according to the channel select signal but, during drawing, as shown in dotted lines, by a control signal selects test circuit on one side of the beer in any for inputting input selector (24) .may be added. The, at the time of test number 1 test circuit (41a) both the "1", number 2 test circuit (42a) to both the, such as "0", 2 test circuit of two (41a, 42a) the other is to write data can be. < 제 3 실시예 > DRAM plurality of the above-mentioned each embodiment the control signal has same circuit for conducting tests WIPO but, plurality of DRAM circuit for separately control of, for example, , to carry out data transmission example. to hereinafter. Figure 5 shows a DRAM circuit and also a plurality of according to number 3 embodiment 1 of logic circuit (macro circuit, computer example) a is mounted on a same semiconductor chip LSI logic mixed DRAM. blocks at least one of a semiconductor. Is LSI chip logic circuit (50) and a, number 1 DRAM circuit (51) and a, number 2 DRAM circuit (52) and a, each input control signal DRAM circuit (51, 52) individually control simultaneously in addition a separate control function individual control circuit (53) and a, input selector (54) and output selector (55) is provided. The individual chip LSI input terminal to controlled control signal input (56) and a, for signal input macro DRAM macro input terminal (57) and a, between the output macro DRAM output terminal of macroblocks (58) is provided with. And, control input terminal (56) in an individual control circuit (53) is connected to, macro input terminal (57) the input selector (54) is connected to a side of a, macro output terminal (58) the output selector (55) is connected to the. Input selector (54) has the address inputs to the, data input and the like that are input to time series of 2 signal input macro DRAM DRAM circuit (51, 52) any has a function of supply on one side of the semiconductor substrate. Output selector (55) of the 2 DRAM circuit (51, 52) on one side of the beer in any the macro selection control output signal output terminal (58) has a function of to. Individual control circuit (53) if the control signal input, each DRAM circuit (51, 52) simultaneously in addition individual to control and, for example each DRAM circuit (51, 52) for reading data alternately from controlled to transmit the optical signal to the outside. Figure 6 shows a of Figure 5 LSI DRAM circuit of 2 in (51, 52) from data with using the special character as active alternately DRAM reads out when performing a semiconductor device formed outside the integrated circuit access (interleave access) that indicates an order of is flow right chart. I.e., number 1 DRAM circuit (51) BACT are supplied into the chamber and a bank active signal in, output selector (55) for number 1 DRAM circuit (51) of the output signal of the a control with selectable I /, number 1 DRAM circuit (51) from respective columns of the reading data to the output, BPRC is supplied to bit line precharge signal. In between, number 1 DRAM circuit (51) for the surface plate while supplying the READ control signal reading, number 2 DRAM circuit (52) bank active signal in BACT are supplied into the chamber and a, number 1 DRAM circuit (51) of the bit line precharge signal BPRC the surface plate while supplying the a output selector (55) a number 2 DRAM circuit (52) with selectable I/of the output signal of a control of wet liquid to flow down. The, number 1 DRAM circuit (51) from are assigned in a predetermined format is read of data batch 1, immediately, number 2 DRAM circuit (52) from respective columns of the reading data can be from the output terminal to the. And, number 2 DRAM circuit (52) for the surface plate while supplying the control signal reading READ number 1 DRAM circuit (51) bank active signal in BACT are supplied into the chamber and a, number 2 DRAM circuit (52) of the bit line precharge signal BPRC the surface plate while supplying the a output selector (55) for number 1 DRAM circuit (51) of the output signal of a control with selectable I/book. Each of the first electrode is varied by this activity DRAM circuit (51, 52) when reading out the burst cutting area alternately data from precharge from active and the time required until temporal by tRP enables to eliminate Image sensible (on appearance, can hide a tRP time) since read is transmission of data at high speed can be. As described above, according to semiconductor integrated circuit mounted macro plurality of the present invention, plurality of DRAM circuit when testing the test time of can be shortened, yet plurality of DRAM circuit read data can be taken away in order to specify the logic high. PURPOSE: To shorten a test time when plural DRAM circuits incorporated in an LSI is tested and to transfer read-out data of plural DRAM circuit at high speed. CONSTITUTION: This circuit is provided with plural DRAM circuits 11, 12, a control circuit 13 having a function receiving a test control signal and performing tests for each DRAM circuit in parallel, an input selector 14 controlled by a control circuit and having a function supplying a DRAM macro- signal to plural DRAM circuits at the time of test, and an output selector 15 controlled by the control circuit and having a function selecting and controlling each output signal of plural DRAM circuits at the time of test and outputting them to a macro-output terminal 18. © KIPO & JPO 2002 Semiconductor integrated circuit, Plurality of DRAM circuit and, Each said terminal for a test control signal by setting up test control and input/output control for the circuit DRAM the body by penetrating the and a control circuit having a function, Is controlled by said control circuit, said signal input macro DRAM plurality of DRAM one of any circuit 1 has an input selector and the task of supplying a, Is controlled by said control circuit, the panel during normal operation and any circuit DRAM plurality of said 1 selects the signal loops, then the macro-output terminal and, at the time of test output signal circuit DRAM plurality of said selection control the macro output terminal having a function to an output selector Characterized by equipped with at least one semiconductor integrated circuit. According to Claim 1, each said control circuit said DRAM circuit a test against a when in parallel, each DRAM circuit of the first row to all memory cell, DRAM circuit 1 of the operative accessing a memory cell order column each DRAM circuit and effecting the pneumatic at the same time, after this, each DRAM from low next circuit last row to all memory cell, as well operation of said initial row effecting the pneumatic sequential operation of to characterized by semiconductor integrated circuit. Semiconductor integrated circuit, Plurality of DRAM circuit and, DRAM plurality of said which are associated with the respective respectively, a pressure receiving part receiving a control signal input DRAM, each corresponding to and test input/output control circuit having a function control a number of control circuit and, Said a pressure receiving part receiving a control signal input is controlled, the panel during normal operation and any circuit DRAM plurality of said 1 loops, then the macro-signals are selected and to output terminal, test at the time of said plurality of DRAM circuit output terminal the macro selection control output signal to an output having a function selector Characterized by equipped with at least one semiconductor integrated circuit. According to Claim 3, said a corresponding to the control circuit when performing test circuit for DRAM, circuit DRAM, each corresponding to each column of the first row the operative accessing a memory cell in order to facilitate and, after this, next low from last row to all memory cell, as well operation of said initial row effecting the pneumatic sequential operation of to characterized by semiconductor integrated circuit. According to one of Claim 1 to Claim 4, said control circuit outputs connected with signal input terminal, said control signal input terminal from the macro circuit without going through the it makes it possible direct control circuit characterized by semiconductor integrated circuit. Semiconductor integrated circuit, Plurality of DRAM circuit and, A pressure receiving part receiving a control signal input in addition simultaneously circuit DRAM plurality of said individually control a separate control function individual control circuit and, Macro DRAM DRAM plurality of said signal input one of any circuit 1 has an input selector and the task of supplying a, Any circuit DRAM plurality of said 1 loops, macro, thereby having a function to output terminal an output selector Characterized by equipped with at least one semiconductor integrated circuit. According to Claim 6, individual said if signal input the control circuit outputs, each DRAM circuit reads out the sequential data from a memory connected to a word line for device feeds a control signal to the characterized by semiconductor integrated circuit. According to Claim 7, said individual control circuit DRAM circuit bank active signal in 1 of BACT are supplied into the chamber and a, said output selector for DRAM for receiving output signal from of said 1 and makes available for the selection of a controls the, from column circuit DRAM of said 1 reads out the sequential data to the output, bit line precharge signal BPRC control unit controls a, Furthermore, control signal reading circuit DRAM of said 1 READ are supplied into the chamber and a is captured in, other 1 of BACT bank active signal in circuit DRAM tank and, of said 1 BPRC DRAM circuit of the bit line precharge signal is captured in are supplied into the chamber and a, said output selector for DRAM of said other 1 for receiving output signal from and makes available for the selection of a by controlling the, said 1 of 1 circuit DRAM are assigned in a predetermined format is read of data batch, immediately, DRAM circuit of said other 1 reads out the sequential data from column it is possible to output an characterized by to the semiconductor integrated circuit.
