ПСЕВДОДВУХПОРТОВАЯ ПАМЯТЬ С СИНХРОНИЗАЦИЕЙ ДЛЯ КАЖДОГО ПОРТА

... 1. Псевдодвухпортовая память, содержащая: ! массив ячеек памяти, при этом каждая ячейка памяти массива представляет собой ячейку памяти с шестью транзисторами; ! первый порт, содержащий первое множество линий ввода адреса и линий ввода синхронизирующих импульсов, при этом первый переход от низкого уровня к высокому первого входного синхронизирующего сигнала на линии ввода синхронизирующих импульсов первого порта вызывает защелкивание адреса в первом множестве линий ввода адреса в псевдодвухпортовой памяти и инициирует первое обращение к памяти массива ячеек памяти; и ! второй порт, содержащий второе множество линий ввода адреса и линию ввода синхронизирующих импульсов, при этом: ! в первом случае: переход от низкого уровня к высокому второго входного синхронизирующего сигнала на линии ввода синхронизирующих импульсов второго порта в течение первого периода времени должен вызвать защелкивание адреса по второму множеству линий ввода адреса в псевдодвухпортовой памяти и должен вызывать инициирование ...

Ausgangsschaltung einer integrierten Halbleiterschaltungsanordnung.

Umfangreiche Datenbusarchitektur

DYNAMISCHER RAM-SPEICHER, IN WELCHEM DIE ZEITABSTIMMUNG DES ENDES DES AUSLESENS VON DATEN FRÜHER IST ALS HERKÖMMLICH

Halbleiterspeicheranordnung.

AKTIVABSCHLUSSSCHALTUNG UND VERFAHREN ZUR STEUERUNERTEN SCHALTUNGEN

Echotakt auf Speichersystem mit Warteinformationen

Ein Verfahren zum Betreiben einer Doppeldatenraten-Speichervorrichtung, mit folgenden Schritten: Bereitstellen einer bidirektionalen Leitung in einem Systembus der Speichervorrichtung, um ein WAIT_DQS-Signal zu übertragen, wobei das WAIT_DQS-Signal die Funktionalität von (i) einem WAIT-Signal, das in einem Lesezyklus anzeigt, wann gültige Daten auf einem Datenbus vorliegen, und in einem Schreibzyklus, wann ein Speicher bereit ist, um Daten anzunehmen, und (ii) einem Datenübernahme- (DQS-) Signal, das als ein Zeitgebungssignal für gültige Daten dient, aufweist; und Weiterleiten des WAIT_DQS-Signals in einer bidirektionalen Leitung in einem Systembus der Speichervorrichtung, wobei die bidirektionale Leitung mit dem Speicher und einer Systemsteuerung gekoppelt ist.

MIT VERRINGERTEM ENERGIEVERBRAUCH ARBEITENDE PUFFERSCHALTUNG.

Signalübertragungssystem

Ausgangsschaltung einer Halbleitervorrichtung

Eine Ausgangsschaltung eines Halbleiters hat Einheitspuffer, jeder Einheitspuffer hat Transistoren und Widerstände, die zwischen einen Stromquellenanschluss VDDQ und einen Ausgangsanschluss DQ geschaltet ist, und Transistoren und Widerstände, die zwiusgangsanschluss DQ geschaltet sind. Die Ein-Widerstandswerte der in den Einheitspuffern enthaltenen Transistoren sind einander im Wesentlichen gleich und die Widerstandswerte der in den Einheitspuffern enthaltenen Widerstände sind zueinander unterschiedlich. Eine Abweichung der Impedanzen als Eigenschaft eines Stromquellenwiderstands kann basierend auf einer Differenz zwischen den Widerstandswerten der Widerstände ausgeglichen werden.

Data output circuit for semiconductor component, has output driver unit to pass output driver event in response to output of level shifter circuit after maintaining data output connection in high impedance state

An output driver unit is provided for maintaining data output connection in high impedance state in response to high impedance driver data output by level shifter circuit. The output driver unit passes the output driver event in response to pull up and pull down output data signals (DOU,DOD) transferred by level shifter circuit to forward the final data (DQ) over data output connection (L5) to external. The output buffer receives and stores input data signal (DATAB) with predetermined voltage range in response to clock control signal (KDATA) to provide a pair of output data SIGNALS (DATAC,DATACB). The level shifter circuit passes high impedance control signal (HZ) through pair of output lines (L3,L4). The level shifter circuit receives pair of output data signals from output buffer depending on logical state of high impedance control signal and to transfer pull up and pull down data signals (DOU,DOD) through output lines (L3,L4). The voltage range of pull up and pull down output data signals ...

Treiber-Einrichtung, insbesondere für ein Halbleiter-Bauelement, sowie Verfahren zum Betreiben einer Treiber-Einrichtung

Halbleiter-Bauelement, mit einer Treiber-Einrichtung (1), welche aufweist: - einen an eine Versorgungs-Spannung (VDDQ) angeschlossenen Signal-Treiber (6a); und - eine Einrichtung (5) zum Aktivieren eines weiteren Signal-Treibers (6b), wenn während einer Initialisierungs-Phase des Halbleiter-Bauelements die Versorgungs-Spannung (VDDQ) unter einem vorbestimmten Schwellwert (VDDQthreshold, VDDQthreshold1) liegt, wobei falls der weitere Signal-Treiber (6b) aktiviert wurde nach der Initialisierungs-Phase des Halbleiter-Bauelements unabhängig von der Höhe der Versorgungs-Spannung (VDDQ) der aktivierte weitere Signal-Treiber (6b) aktiviert bleibt.

Steuerschaltung für Ausgangspuffer, insbesondere für eine nichtflüchtige Speicheranordnung

Output buffer

In the case of output buffers according to the prior art, the power requirement at the supply voltage terminal or earth terminal changes quickly if the output buffer switches over between supply voltage VCC and earth VSS. This produces a sudden voltage change in the supply voltage VCC and/or the earth voltage VSS. To prevent this, a capacitor is provided, which is connected to an output node of a buffer according to the invention in order to reduce the current which flows to the supply voltage terminal and/or the earth terminal while the output level is changing. A voltage drop and sudden voltage changes of the supply voltage and of the earth voltage are reduced by applying a charging voltage, to which the capacitor is charged. ...

Halbleiteranordnung

Halbleiteranordnung mit: einem Abtastverstärker (44), welcher auf den Empfang eines Lesefreigabesignals ein Signal verstärkt; einer Verzögerungseinheit (52, 54), welche eine Mehrzahl von Übertragungspfaden mit unterschiedlichen Verzögerungszeiten bereitstellen kann und das Lesefreigabesignal durch einen Übertragungspfad entsprechend einem Wahlsignal aus der Mehrzahl von Übertragungspfaden überträgt; gekennzeichnet durch eine Befehlssignalerzeugungsschaltung (122, 124), welche der Verzögerungseinheit (52, 54) als Befehlssignal ein ODER-Ergebnis einer Verknüpfung eines vorbestimmten Maximalverzögerungsbefehlssignals, welches zum Zwecke der Aufnahme eines Übertragungspfads mit der maximalen Verzögerungszeit als Übertragungspfad für das Lesefreigabesignal ausgegeben wird, und eines willkürlichen Wahlsignals zuführt, welches zum Zwecke der Wahl eines willkürlichen Übertragungspfads als Übertragungspfad für das Lesefreigabesignal ausgegeben wird.

SCHALTUNGSANORDNUNG MIT WENIGSTENS EINER SCHALTUNGSEINHEIT WIE EINEM REGISTER, EINER SPEICHERZELLE, EINER SPEICHERANORDNUNG ODER DERGLEICHEN

Schaltung zur Erzeugung eines Ausgangssignals in Abhängigkeit von zwei Eingangssignalen

Schaltbarer Bustreiberabschlusswiderstand

Verfahren zur Leserverstärkersteuerung

Kontrollieren des Ausgangsstromes in einem Rambus DRAM

Offenbart ist eine Schaltung zum Kontrollieren von Ausgangsströmen der Datenports in einem Rambus DRAM mit zwei Datenports DQA und DQB. Die offenbarten Schaltungsanordnungen sparen Energie und benötigen weniger Chipfläche als die bekannten Schaltungsanordnungen. Erste und zweite Stromermittlungsmittel geben erste und zweite Kontrollsignale jeweils durch Ermitteln der Ströme der Datenports DQA und DQB aus. Ein Stromkontrollwerterzeugungsmittel erzeugt einen nächsten Stromkontrollwert für den Datenport DQA durch Empfangen des ersten Kontrollsignals und eines vorhandenen Stromkontrollwertes des Datenports DQA und erzeugt einen anderen nächsten Stromkontrollwert für den Datenport DQB durch Empfangen des zweiten Kontrollsignals und eines vorhandenen Stromkontrollwertes des Datenports DQB. Die Stromkontrollwerterzeugungsmittel wiederholen den Prozess zur Erzeugung des nächsten Stromkontrollwertes abwechselnd, und erste und zweite Kontrollwertpuffermittel zum Puffern der entsprechenden Stromkontrollwerte ...

Circuit for generating output clock signal with optimised signal generation time for memory arrangement eliminates certain problems related to transition times - has duty cycle equaliser with 2 coupled symmetrical branches contg. multiplexer integrated with programmable signal supply points producing output signal

The circuit generates a local output clock using a duty cycle equaliser and a multiplexer depending on a differential input clock signal and a programmable shift device so that data are output from a memory cell field in synchronism with either whole clock cycles or integral fractions thereof. The duty cycle equaliser has two coupled symmetrical branches in which the multiplexer is integrated with at least two programmable signal supply points (4a-7a) that produce the output signal depending on the changeover signal and connected via switches (4-7) to the circuit outputs (10,11). The switches are operated depending on the differential input clock signal.

Data inverting device, comprises complementary-metal-oxide-semiconductor circuit, two inverting units and control unit, which is provided to control two inverting units

The data inverting device (100) comprises a complementary-metal-oxide-semiconductor circuit (1) with an input (2) and an output (3). Two inverting units (4,5) are connected with the input and the output. A control unit (6) is provided to control two inverting units such that the data, which was inverted during its output from the latter inverting unit and the data, which was not inverted while inputting into the input from the former inverting unit were not inverted from latter inverting unit. An independent claim is also included for a method for data inversion.

Halbleiterspeichervorrichtung

In einer Halbleiterspeichervorrichtung ist ein Speicherzellenarray vorgesehen und eine Vielzahl von Speicherzellen bilden in dem Speicherzellenarray eine Spalte. Die Vielzahl der Speicherzellen sind gemeinsam an eine Vielzahl von Bitleitungspaaren angeschlossen. Die Vielzahl von Bitleitungspaaren sind gemeinsam an ein I/O-Leitungspaar angeschlossen. In der Halbleiterspeichervorrichtung ist auch die Vorladeschaltung vorgesehen. Die Vorlageschaltung lädt das I/O-Leitungspaar vor. Die Vorladeschaltung hat eine Wählschaltung, die einen Vorladepegel des I/O-Leitungspaares aus einer Anzahl von Spannungspegeln wählt.

Halbleiterspeichereinrichtung und Verfahren zum Ändern von Ausgangsdaten dieser Einrichtung

Verfahren zum Ändern von Ausgangsdaten einer Halbleiterspeichereinrichtung, die mehrere Ports hat, wobei die Halbleiterspeichereinrichtung mehrere Speicherzellen (31), eine erste Bitleitung (BLA), die mit den Speicherzellen verbunden ist, eine zweite Bitleitung (BLB), die mit den Speicherzellen verbunden ist, einen ersten Port (Port A), der mit der ersten Bitleitung verbunden ist, um Eingangsdaten in die Speicherzellen über die erste Bitleitung zu schreiben, einen zweiten Port (Port B), der mit der zweiten Bitleitung verbunden ist, um Daten, die in den Speicherzellen gespeichert sind, über die zweite Bitleitung auszugeben, und eine Datenleseschaltung (41, 71) umfaßt, die mit der zweiten Bitleitung verbunden ist und die eine Latchschaltung umfaßt, um die Daten einer der Speicherzellen zu halten, wobei das Verfahren durch folgende Schritte gekennzeichnet ist: Ermitteln einer Änderung in den gespeicherten Daten in der Speicherzelle auf der Basis eines Potentials auf der zweiten Bitleitung; ...

Steuerschaltung einer Flash-Speichervorrichtung unhtung

Ein Verfahren zum Betreiben einer Flash-Speichervorrichtung mit einem ersten Bereich und einem zweiten Bereich wird bereitgestellt, in welcher ein programmierter Zustand und ein gelöschter Zustand des ersten Bereiches gegensätzlich zu denjenigen des zweiten Bereiches sind. Das Verfahren weist folgende Verfahrensschritte auf: Empfangen eines Programmierbefehls; Invertieren der Programmierdaten, wenn der empfangene Programmierbefehl ein Befehl zur Programmierung des zweiten Bereiches ist; und Programmieren der invertierten Programmierdaten in den zweiten Bereich.

Ausgabeschaltung für einen mit doppelter Datenrate arbeitenden dynamischen Speicher mit wahlfreiem Zugriff (DDR DRAM), ein mit doppelter Datenrate arbeitender dynamischer Speicher mit wahlfreiem Zugriff (DDR DRAM), ein Verfahren zum getakteten Auslesen von Daten aus mit doppelter Datenrate arbeitenden dynamischen Speicher mit wahlfreiem Zugriff (DDR DRAM) und ein Verfahren zum Liefern eines Daten-Strobe-Signals

Semiconductor device and semiconductor circuitry

Radio apparatus suitable for use with an information processor

APPARATUS FOR ROW CACHING IN RANDOM ACCESS MEMORY

Latch-based memory array

A SEMICONDUCTOR INTERGRATED CIRCUIT MEMORY

DATAPATH-OUTPUT BUFFER MULTIPLEXING.

Individual output buffers 8a, 8b, 8c are provided for each data bus, Dx, Dy, Dz in a memory and are connected directly to output pin 1. This increases the speed of the output buffer (by reducing its input capacitance) and allows data to be supplied to all output buffers in parallel and then dribbled serially to the output. The use of tri-state buffers and transmission gates is avoided. ...

Improvements relating to dynamic random access memories

An output buffer unit for use with a dynamic random access memory includes a first stage (40,41) for generating complementary logic signals. In an intermediate stage (42,43), separate from the generation of the complementary signals, the complementary signals are buffered for application to the output driver stages (44,45,46,47). By separation of the signal generation stages from the buffering stages, the speed of the logic level-to-logic level transitions can be increased.

Low noise output buffer for semiconductor memory

A multi-bit data output buffer for a semiconductor memory device, comprising a data input circuit for inputting at least two bit data, at least two bit data buffering circuits, each of at least two bit data buffering circuits buffering a corresponding one of at least two bit data from the data input circuit, and a bit data comparison circuit for controlling the amounts of current flowing to at least two bit data buffering circuits according to logic values of at least two bit data from the data input circuit. According to the present invention, the multi-bit data output buffer is capable of minimizing the generation of noise in the output data and enhancing a response speed of the output data with respect to the input data.

A logic circuit capable of adjusting the switching threshold level

An adaptive threshold logic circuit 9 is provided in which the switching threshold levels of the logic circuit are automatically changed to accommodate variations in the level of applied data signals to the switching circuit. A detector stage 11 detects the voltage level of the incoming data signals and selectively adjusts the threshold level of a threshold adaptor stage 13 in accordance with the output of the detector stage 11. The threshold adaptor stage is essentially a CMOS inverter having various switching paths turned on or off in accordance with the output of the detector stage 11. Dependent claims are included for a memory device and a processor system incorporating the adaptive threshold logic circuit 9.

Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding

Semiconductor device and data writing method

DATA OUTPUT BUFFER CIRCUIT FOR BYTE-WIDE MEMORY

Data transmission circuit for a semiconductor memory

The data transmission circuit processes data input/output at high speed by suppressing the generation of a DC current through output transistors 61, 62 when performing a data write operation after a data read operation. The data transmission circuit 100 has common input/output lines 65, 66, a sensing transistor circuit 59, 60 for sensing a potential difference of bit lines 53, 54, an input transistor circuit 63, 64 for writing data, and an output transistor circuit 61, 62 for reading data. The common input/output lines 65, 66 are electrically insulated from the output transistor circuit 61, 62 and the sensing transistor circuit 59, 60 during a data write operation. Memory cells 51. 52 exist in two different memory array blocks commonly controlled by the circuit 100. ...

PROGRAMMABLE LOGIC DEVICE

A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and a non-inverting buffer to provide a complementary pair of outputs from the buffers. In one embodiment, a memory cell is provided to control enablement of each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the complementary pair of outputs from the buffer are inputted to a multiplexer wherein a single memory cell controls the selection of the signal or its complement to be outputted from the multiplexer. The memory cells are each coupled to its corresponding latch or shift register for latching a stored state of the memory cell. Shift registers provide for external programming to emulate stored memory cell states.

Ram data output

A dual port memory has a data register 2 which outputs serial data in response to the input of the serial address which is synchronized with a serial clock, and comprises a first data 110 line for transferring data which is synchronized with an even serial address and then is output from the data register, a second data 110 line for transferring data which is synchronized with an odd serial address and then is output from the data register, and a multiplexer 14, 16 for output of the data via sense amplifier 18, 20 and latch 22, 24, 26. The memory may be a video RAM. Further aspects concern a method of serial data output including synchronising the data and a memory device alternately selecting first and second sets of I/O data lines. ...

Clock adjustment using a dummy input circuit

Synchronous semiconductor memory device

Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data

System and method for signal timing

Semiconductor memory data output circuits

Data output buffer circuit for semiconductor memory device

A voltage detection unit between a data output buffer terminal and the gate a transistor which is used to dissipate a high level voltage on the internal data line. The detection unit thus prevents an undesired electrical path from existing in the data output buffer circuit. In one embodiment, the detection unit consists of an NMOS and PMOS transistor connected in series and having a shared node connected to the voltage dissipating transistor. In another embodiment, there is also connected an invertor between the shared node and the gates of the NMOS and PMOS transistors.

Memory repair multiplexer with reduced propagation delay

The output 34 of a memory repair multiplexer 30 is fed directly to an output terminal 16a. After a short delay the output is buffered by enabling a non-inverting driver 36 coupled at its input and output to the multiplexer output node. The direct connection of the multiplexer output 34 to the output terminal 16a avoids the propagation delay of the driver 36. A data latch may be interposed between the multiplexer output 34 and the input of the driver 36 (figure 4), so that the circuit may be used in EDO mode SIMMs.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH POWER CONSUMPTION REDUCING ARRANGEMENT

Dual purpose interface using refresh cycle

DYNAMIC COLUMN BLOCK SELECTION

PSEUDO DOUBLE HAVEN MEMORY WITH A CLOCK PULSE FOR EACH HAVEN

MULTIMEDIA KARTENSCHNITTSTELLENVERFAHREN, COMPUTER PROGRAMME PRODUCT AND DEVICE

CLOCK PULSE PRODUCTION METHOD FOR MEMORY, NO IMPULSES PRODUCING

MEMORY WITH REPEATED INDEPENDENT SERIAL CONNECTION

NON VOLATILE MEMORY AND PROCEDURE WITH SOURCE LINE ERROR COMPENSATION

SYSTEMS, PROCEDURES AND DEVICES FOR THE TRANSMISSION OF DATA AND DATA MASK BIT IN A CONVENTIONAL FRAME WITH COMMON ERRONEOUS BIT CODE

DISTRIBUTED CONTROL SYSTEM OF A MEMORY DEVICE

EFFECTS CAUSED REDUCTION OF IN FOR A NOT VOLATILE MEMORY BY NOISE BY REPEATED SELECTION

PROCEDURE FOR A DOUBLE ORIGINAL DATA RATE

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

DYNAMIC COLUMN BLOCK SELECTION

SCANNING SYSTEM

Method of increasing DDR memory bandwidth in DDR SDRAM modules

SYSTEM AND METHOD FOR TRANSLATION OF SDRAM AND DDR SIGNALS

An early read after write operation memory device, system and method

Low latency multi-level communication interface

A method and apparatus for sampling data from a memory

MULTIMEDIA CARD INTERFACE METHOD, COMPUTER PROGRAM PRODUCT AND APPARATUS

METHOD AND SYSTEM FOR POWER SIGNATURE SUPPRESSION IN MEMORY DEVICES

A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.

Control module used especially in large microprocessors such as Digital Signal Processors, has arrangement which enables lower power consumption

The control module (1) includes the following elements, a dead Read-only-memory (ROM) (2), a temporary memory (6), to which the data in the ROM is to be transferred in order to be accessible from the exterior of the control module, a reading controller (3), for selecting from each reading cycle, the portions of this ROM transferred to the temporary memory. The portions selected by the reading controller, depends on the contents of this Read-only-memory.

Control method of memory system and related memory device

As the array and the peripheral signal provides a signal buffer programme memory and method of operation

Near pad ordering logic

Large data storage with data analysis function

Semiconductor memory device and method for adjusting timing between internal clock and command

A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.

Clock deskewing method, apparatus and system

An integrated circuit includes clock deskew circuitry. The deskew circuitry includes a loop circuit to align an input clock signal with an output clock signal, and also aligns transmitted data with the output clock signal.

CIRCUIT PLUG OF EXIT OF DATA Of a DEVICE OF MEMORY HAS SEMICONDUCTOR

DATA OUTPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY.

Apparatus and method for getting access to data stored in a page memory

DYNAMIC CONVERTER OF LEVEL Of a DEVICE OF MEMORY HAS SEMICONDUCTOR

Un convertisseur de niveau d'un dispositif de mémoire à semi-conducteurs comprend: - un bloc de conversion de niveau comprenant une paire de transistors (MP2, MP3) d'une première conductivité qui reçoivent une première et une seconde tension de lecture (Sas, SasB) par leurs grilles, une paire de transistors (MN4, MN5) d'une seconde conductivité; - un moyen de blocage comprenant un premier transistor (MP1), du premier type de conductivité qui applique une tension d'alimentation (Vcc) aux sources des transistors (MP2, MP3); et - un moyen de verrouillage qui amplifie une différence de la première et la seconde tension de sortie entre le premier et le second noeud de sortie pour qu'elle soit essentiellement égale au niveau de la tension d'alimentation (Vcc).

FAST ERASABLE PROGRAMMABLE COMPONENT LOGICAL

DEVICE OF MEMORY HAS SEMICONDUCTOR INCLUDING/UNDERSTANDING WAYS OF EXIT OF DATA FOR RAPID ACCESS

Dispositif de mémoire à semi-conducteurs, comprenant des chemins de sortie de données à grande vitesse pendant un mode de fonctionnement donné, caractérisé en ce que chaque chemin de sortie de données comprend en série: - un premier bloc de commande de courant répondant à un signal d'adresse donné; - un premier bloc de verrou (40); - un répétiteur (42); - un second bloc de commande de courant répondant à un signal de commande donné; - un second bloc de verrou (48); et - une mémoire tampon de sortie de données (44).

DISPOSITIF D'AUTOSYNCHRONISATION DES CIRCUITS DE SORTIE D'UNE MEMOIRE

LA PRESENTE INVENTION CONCERNE UN DISPOSITIF D'AUTOSYNCHRONISATION POUR LES CIRCUITS DE SORTIE COMPORTANT UNE PORTE " 3 ETATS " DES MEMOIRES TRAVAILLANT EN MODE HORLOGE INTERNE. CE DISPOSITIF EST CONSTITUE PAR UN CIRCUIT EN LOGIQUE SEQUENTIELLE 10 A 20 NE PERMETTANT LE PASSAGE DE LA PORTE " 3 ETATS " EN BASSE IMPEDANCE QU'AU MOMENT OU UNE INFORMATION EST DISPONIBLE EN SORTIE DES AMPLIFICATEURS DE LECTURE A. APPLICATION AUX MEMOIRES.

DATA INPUT CIRCUIT AND SEMICONCUCTOR MEMORY DEVICE INCLUDING THE SAME

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CHANGING OUTPUT DATA OF THE SAME

MEMORY SYSTEM AND CONTROL METHOD FOR THE SAME

INPUT/OUTPUT CIRCUIT FOR CMOS DRAM

The circuit relates to a level shift circuit for static column type input/output circuit. The circuit includes a separating unit for forming input lines of input/output sense amplifier by separating input/output buses (IO,IO) deposited between precharging circuit (2) and input/output sense amplifier (4), and level shift circuit for maintaining constant voltage difference between the separated input/ output buses (IO,IO) and input lines (30,40) of input/output sense amplifier corresponding to the buses (IO,IO). Copyright 1997 KIPO ...

MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM

Output enable signal generation circuit of semiconductor memory

An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).

Dynamic impedance control for input/output buffers

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Apparatus and methods for optically-coupled memory systems

Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.

Digital frequency locked delay line

A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.

Memory System with Multi-Level Status Signaling and Method for Operating the Same

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

Circuit

An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

Semiconductor memory device and methods thereof

According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.

Method for compensating a timing signal, an integrated circuit and electronic device

A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

Semiconductor memory and semiconductor memory control method

According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.

Advanced memory device having improved performance, reduced power and increased reliability

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Isolated resistive current sensor

An isolated current-sensing system for use with a resistive current sense element includes an analog front-end configured to receive a voltage from the resistive current sense element, and to provide an analog output. A processing circuit receives the analog output, and provides a measurement signal indicative of the sensed current. An isolation circuit provides an isolation barrier, and is configured to pass the measurement signal. A programmable over-current protection alarm may be included, and configured to generate an alarm signal when the analog output exceeds a programmable threshold. The processing circuit may include a voltage-to-PWM converter.

Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system

A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.

Processor with memory delayed bit line precharging

A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.

High speed multiple memory interface i/o cell

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device

A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals edge specifying information that takes a selected one of first and second states, the edge specifying information being supplied to the device to cause the device to activate a data strobe signal at a first timing when the selected one of the edge specifying information is the first state and at a second timing, that is different from the first timing, when the edge specifying information is the second state, the control circuit being further configured to generate and output onto the set of first terminals a read command, the read command being supplied to the device to cause the device to return to the controller a data signal.

Non-volatile semiconductor memory and data reading method thereof

A non-volatile semiconductor memory is provided, including a memory array having a first and a second memory planes, a page buffer, holding data transmitted by pages selected by address information from a memory array; data register, capable of serially outputting data received by the page buffer according to a clock signal. The pages selected by the first and the second memory planes are simultaneously transmitted to the page buffer. The data reading includes: transmitting the data of the second page of the second memory plane from the page buffer to the data register when the data of the first page of the first memory plane is outputted from the data register; transmitting the data of the second page of the first memory plane from the page buffer to the data register when the data of the second page of the second memory plane is outputted from the data register.

System and method for selectively performing single-ended and differential signaling

In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Line memory device and image sensor including the same

A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

Memory systems and methods for controlling the timing of receiving read data

Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.

Flash Storage Controller Execute Loop

A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission method

A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data,

Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

MULTI-CHIP SEMICONDUCTOR APPARATUS

A multi-chip semiconductor apparatus includes a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked, wherein each of the semiconductor chips includes: a first data input/output line configured to transmit data for a first memory bank; a second data input/output line configured to transmit data for a second memory bank; and a data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip. 1. A multi-chip semiconductor apparatus comprising a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked ,wherein each of the semiconductor chips comprises:a first data input/output line configured to transmit data for a first memory bank;a second data input/output line configured to transmit data for a second memory bank; anda data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip.2. The multi-chip semiconductor apparatus according to claim 1 , wherein the data TX/RX unit transmits read data transmitted from any one of the first and second data input/output lines to the first TSV in response to the selected memory bank information claim 1 , during the read operation for the corresponding semiconductor chip.3. The multi-chip semiconductor apparatus according to claim 1 , wherein the data TX/RX unit receives write data transmitted from the first TSV through any one of the first and second data input/output lines in response to the selected memory bank information claim 1 , during the write operation for the corresponding ...

MEMORY CONTROLLER AND OPERATING METHOD THEREOF

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation. 1. A memory system , comprising:a memory device including a memory cell region for storing data, the memory device looping back a first clock to generate a second clock and outputting read data that are read from the memory cell region in synchronization with the second clock; anda memory controller generating the first clock that includes a plurality of modulation sections by performing a modulation operation on a source clock according to a specific scheme, outputting the first clock to the memory device, and receiving the read data in response to the second clock,wherein the read data includes a plurality of section data corresponding to the plurality of modulation sections included in the second clock, respectively, and the memory controller verifies reliability of each of the plurality of section data included in the read data by performing a demodulation operation on the second clock according to the specific scheme.2. The memory system of claim 1 , wherein the modulation operation according to the specific scheme includes a ...

Two-Bit Memory Cell and Circuit Structure Calculated in Memory Thereof

The invention relates to a two-bit memory cell structure, and an array architecture and a circuit structure thereof in an in-memory computing chip. The double-bit storage unit comprises three transistors which are connected in series, a selection transistor in the middle is used as a switch, and two charge storage transistors are symmetrically arranged on the two sides of the double-bit storage unit. A storage array formed by the double-bit storage unit is used for storing the weight of the neural network, and multiplication and accumulation operation of the neural network is carried out in a two-step current detection mode. According to the invention, leakage current can be effectively controlled, higher weight storage density and higher reliability are realized, and neural network operation with more practical significance is further realized. 1. A circuit structure of a two-bit memory cell for in-memory computing , comprising:a memory cell array consisting of two-bit memory cell structures and used for storing a weight matrix of a neural network, and the two-bit memory cell comprises: three transistors connected in series, in which the middle transistor is a select transistor used as a switch, and a first charge storage transistor and a second charge storage transistor are symmetrically placed on two sides of the select transistor; the gate electrode of the select transistor is connected to a word line, the gate electrodes of the first charge storage transistor and the second charge storage transistor are connected to respective word lines, and the drain side of the first charge storage transistor and the source side of the second charge storage transistor are respectively connected to the cell bit line and the cell source line while the source side of the first charge storage transistor and the drain side of the second charge storage transistor are respectively connected to the drain side and the source side of the select transistor; wherein the first charge ...

DATA STORAGE DEVICE

A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation. 1. A data storage device comprising:a first memory device suitable for performing an internal operation in response to a first internal operation command; anda state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation.2. The data storage device according to claim 1 , wherein the state checking block sets an initial standby time during the initial mode based on an expected performance time of the internal operation claim 1 , and transmits an initial state read command to the first memory device when the initial standby time passes.3. The data storage device according to claim 2 ,wherein the first memory device outputs initial response data in response to the initial state read command, andwherein the state checking block determines whether the internal operation is completed based on the initial response data, and ends the state read operation or enters the repeat mode according to a determination result.4. The data storage device according to claim 3 , wherein the state checking block sets a repeat standby time during the repeat mode based on the expected performance time of the internal operation when it is determined that the internal operation is not completed claim 3 , and transmits a repeat state read command to the first memory device when the repeat standby time passes.5. The data storage device according to claim 4 ,wherein the first memory device outputs repeat ...

READING A MULTI-LEVEL MEMORY CELL

Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred. 1. A method , comprising:applying a first read voltage with a first polarity to a memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;determining whether a first snapback event occurred after applying the first read voltage;applying a second read voltage with a second polarity different than the first polarity to the memory cell based at least in part on determining that the first snapback event failed to occur;determining whether a second snapback event occurred after applying the second read voltage; anddetermining the logic state stored by the memory cell from the three or more logic states based at least in part on determining whether the first snapback event or the second snapback event occurred.2. The method of claim 1 , further comprising:applying a third read voltage with the first polarity and a magnitude greater than a magnitude of the second read voltage to the memory cell based at least in part on determining that the second snapback event failed to occur; anddetermining whether a third snapback event occurred after applying the third read voltage, wherein determining the logic state stored by the memory cell is based at least in part on determining whether the third snapback event occurred.3. A method claim 1 , comprising:applying a ...

MEMORY CONTROLLER, MEMORY SYSTEM, AND METHOD OF OPERATING MEMORY SYSTEM

Provided herein may be a memory controller, a memory system, and a method of operating the memory system. The memory controller may control the operation of a memory device. The memory controller may include a read request buffer, a command generator, and a read request monitor. The read request buffer may be configured to receive a read request from a host. The command generator may be configured to receive the read request from the read request buffer and generate a read command based on the received read request. The read request monitor may be configured to receive read request information about the read request from the read request buffer and determine, based on a stream ID of the read request, whether the read request is a sequential read request. 1. A memory system for use in a multi-stream environment , the memory system comprising:a memory device comprising a plurality of memory blocks; anda memory controller configured to receive a read request including a stream ID from a host device and determine, based on the stream ID, whether the read request is a sequential read request with respect to a previous read request.2. The memory system according to claim 1 , wherein the stream ID represents that the read request is generated by one of a plurality of applications executed by the host.3. The memory system according to claim 1 , wherein the memory controller configured to compare an address of the previous read request claim 1 , which includes the stream ID claim 1 , with an address of the read request claim 1 , and update a count value denoting a number of read requests having consecutive addresses corresponding to the stream ID claim 1 , and determine that the read request is a sequential read request when the count value is equal to or greater than a predefined threshold value.4. The memory system according to claim 3 , wherein the memory controller increases the count value by 1 when the address of the previous read request claim 3 , which includes the ...

MEMORY DEVICE, OPERATING METHOD THEREOF, AND OPERATING METHOD OF MEMORY SYSTEM INCLUDING THE SAME

A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations. 1. An operating method of a memory device , comprising:receiving a write command;checking out whether a data strobe signal toggles or maintains a uniform level after a given time passes from a moment when the write command is received;when the data strobe signal maintains the uniform level, detecting voltage levels of a plurality of data pads; andperforming an operation that is selected based on the voltage levels of the plurality of the data pads, from a plurality of predetermined operations.2. The operating method of claim 1 , wherein the plurality of the predetermined operations include an operation of writing a data pattern that is selected based on the voltage levels of the plurality of the data pads claim 1 , from a plurality of data patterns claim 1 , in the memory device.3. The operating method of claim 1 , wherein the plurality of the predetermined operations include an operation of reading a data from a selected region claim 1 , inverting the read data to produce an inverted read data claim 1 , and re-writing the inverted read data in the selected region.4. The operating method of claim 1 , further comprising:when the data strobe signal toggles, writing data received through the plurality of the data pads in the memory device in synchronization with the data strobe signal.5. The operating method of claim 1 , wherein claim 1 , when the data strobe signal maintains the uniform level claim 1 , the voltage levels of the plurality of the data pads are fixed for at least two ...

Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

Memory management method, memory storage device and memory control circuit unit

A memory management method for a memory storage device is provided. The memory management method includes: detecting effective information of at least one operation event performed by the memory storage device in a first mode; and adjusting a threshold value according to the effective information. The threshold value is configured to determine whether to instruct the memory storage device to enter the first mode.

Read voltage management based on write-to-read time difference

A request can be received to perform a read operation to retrieve data at a memory sub-system. A time to perform the read operation can be determined. A time a write operation was performed to store the data at the memory sub-system can be determined. An amount of time that has elapsed since the time the performance of the write operation until the time to perform the read operation can be determined. A read voltage from a plurality of read voltages can be selected based on the amount of time that has elapsed. The read operation can be performed to retrieve the data by using the read voltage.

SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE

While transmission of data to be transmitted and gap data to be transmitted by the same transmission path as that data is controlled so that a frequency of a data signal may become equal to or more than a certain frequency, a data output driver selects and outputs the data or the gap data as the data signal, a valid signal generation circuit outputs a valid signal that indicates whether or not the data is effective, and a reception circuit that is formed in a different die receives the data signal and the valid signal transmitted via the transmission path that includes a through silicon via and acquires the data from the data signal based on the valid signal. 1. A semiconductor device comprising:a holding circuit that holds first data to be transmitted;a data generation circuit that generates second data to be transmitted by the same transmission path as the first data;a control circuit that controls transmission of the first data and the second data so that a frequency of a data signal becomes equal to or more than a certain frequency;an output circuit that selects and outputs the first data held by the holding circuit or the second data generated by the data generation circuit as the data signal in correspondence with control by the control circuit;a valid signal generation circuit that outputs a valid signal that indicates that the data is effective when the output circuit is outputting the first data; anda reception circuit that is formed in a second die different from a first die that includes the holding circuit, the data generation circuit, the control circuit, the output circuit, and the valid signal generation circuit, receives the data signal and the valid signal transmitted from the first die via the transmission path that includes a through silicon via, and acquires the first data from the data signal based on the valid signal.2. The semiconductor device according to claim 1 , comprisingan inversion control circuit that outputs an inversion control ...

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices. 120-. (canceled)21. A memory controller component comprising:a clock transmitter to transmit a first clock signal to a dynamic random access memory device (DRAM), the DRAM having (i) command/address receive circuitry to receive read commands and write commands, (ii) read-data transmit circuitry to transmit, in response to the read commands, read data using the first clock signal, and (iii) write-data receive circuitry to sample, in response to the write commands, write data using the first clock signal;a command/address transmitter to transmit the read commands and the write commands to the DRAM in response to a second clock signal;a write-data transmitter to transmit the write data to the DRAM in response to a third clock signal;a read-data receiver to sample the read data transmitted by the DRAM in response to a fourth clock signal; and phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal and', 'circuitry to generate the second clock signal at a lower frequency than the third and fourth clock signals; and', 'clock-pause circuitry to halt transmission of the first clock signal to the DRAM during a first interval to conserve power and to re- ...

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. 1. (canceled)2. A controller to control operations of a memory component , the controller comprising: a first command that specifies a first data pattern to be stored in a first register of the memory component;', 'a second command that specifies a second data pattern to be stored in a second register of the memory component; and,', 'a third command to select one of the first data pattern or the second data pattern to be output by the memory component;, 'a first circuit to transmit commands to the memory component, the commands includinga second circuit to receive, from the memory component as a received data pattern, the one of the first data pattern or the second data pattern output by the memory component, as selected by the third command; and,calibration circuitry to based on the received data pattern, adjust a timing of a timing reference signal for sampling data at the second circuit.3. The controller of claim 2 , wherein the commands transmitted by the first circuit include a fourth command that specifies data to be accessed from a memory core of the memory component claim 2 , ...

MEMORY CONTROLLER

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: first circuitry to transmit a write command to a dynamic random access memory device (DRAM), the write command to be sampled by the DRAM in response to a first timing signal; and', 'second circuitry to transmit first write data to the DRAM, the first write data to be sampled by the DRAM in response to a second timing signal; and, 'a signaling interface, includingadjustment circuitry to offset the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM.22. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset a phase of the second timing signal from a phase of the first timing signal.23. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset the first and second timing signals at the signaling interface by a time interval that corresponds to a difference in respective propagation times claim 21 , from the memory controller component to the DRAM claim 21 , of the first and second timing signals.24. The memory controller of wherein the second circuitry to transmit the first write data to the DRAM comprises circuitry to output at least part of the first write data onto an external data signaling link at one or more times indicated by the second timing signal.25. The memory controller of wherein the circuitry to ...

FLEXIBLE POINT-TO-POINT MEMORY TOPOLOGY

An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel. 1. A method of enabling a point-to-point memory topology comprising the steps of:when two memory modules are installed, enabling a first access mode where a plurality of memory devices on each memory module are accessed using a single selectable channel, and each memory module uses a different channel; andwhen a single memory module is installed, enabling a second access mode where a first portion of said plurality of memory devices is accessed using a first channel and a second portion of said plurality of memory devices is accessed using a second channel.2. The method according to claim 1 , wherein said plurality of memory devices are part of a double data rate (DDR) dual in-line memory module (DIMM).3. The method according to claim 2 , wherein said plurality of memory devices are part of a fourth generation double data rate (DDR4) dual in-line memory module (DIMM).4. The method according to claim 1 , wherein each of said memory modules comprises a duplex registered clock driver and a plurality of duplex data buffers and the method further comprises:in a first operating mode, configuring said duplex registered clock driver and each of said plurality of duplex data buffers to facilitate communication with said plurality of memory devices of the memory module using said first and said second channels;in a second operating mode, configuring said duplex registered clock driver and each of said plurality of duplex data buffers to facilitate communication between all of said plurality of memory ...

SEMICONDUCTOR MEMORY DEVICE AND I/O CONTROL CIRCUIT THEREFOR

An I/O control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal. 1. A semiconductor memory device , comprising:a mode control unit configured to generate an output signal in response to a first control signal enable signal, a second control signal enable signal, a third control signal enable signal, a fourth control signal enable signal, and a buffer enable signal received from an I/O control circuit;a pad unit comprising an I/O mode control pad, a data I/O pad, and a data I/O strobe pad;an input driving unit configured to be driven in response to the output signal of the mode control unit and electrically coupled to the pad unit;an output driving unit configured to be driven in response to the output signal of the mode control unit and electrically coupled to the pad unit; andan I/O conversion unit configured to provide a memory region with data received from the input driving unit and to provide the output driving unit with data received from the memory region in response to the fourth control signal enable signal.2. The semiconductor memory device of claim 1 , wherein the I/O control circuit comprises:a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality ...

MEMORY DEVICE

A memory device that operates at high speed is provided. 1. A semiconductor device comprising: 'a circuit, the circuit comprises a plurality of silicon transistors, and', 'a first layer, the first layer comprising a first memory cell comprising a first transistor comprising an oxide semiconductor in a channel region; and', 'a second memory cell comprising a second transistor comprising an oxide semiconductor in a channel region,, 'a second layer over the first layer, the second layer comprisingwherein each of the first transistor and the second transistor comprises a front gate and a back gate,wherein the back gate of the first transistor is electrically connected to the back gate of the second transistor,wherein one of a source and a drain of the first transistor is electrically connected to a first electrode of a first capacitor,wherein one of a source and a drain of the second transistor is electrically connected to a first electrode of a second capacitor, andwherein a second electrode of the first capacitor and a second electrode of the second capacitor are electrically connected to a first wiring which is supplied with GND.2. The semiconductor device according to claim 1 , further comprising a third memory cell claim 1 ,wherein a part of the first wiring functioning as the second electrode of the first capacitor functions as a second electrode of a third capacitor whose first electrode is electrically connected to a third transistor comprised in the third memory cell.3. The semiconductor device according to claim 1 , wherein the first memory cell and the second memory cell are part of different memory cell arrays.4. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to the circuit via a second wiring functioning as a bit line.5. The semiconductor device according to claim 4 , wherein the bit line is ...

Electronic device configured to perform an auto-precharge operation

An electronic device may include: an input/output control signal generation circuit configured to generate an input control signal and a first output control signal during a write operation, and generate a second output control signal during a write operation with an auto-precharge operation; and a bank address output circuit configured to latch a bank address based on the input control signal, and output the latched bank address as a write bank address for the write operation or a precharge bank address for the auto-precharge operation, based on the first output control signal and the second output control signal.

PERFORMING A REFRESH OPERATION BASED ON A WRITE TO READ TIME DIFFERENCE

A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation 1. A method comprising:performing a read operation to retrieve data of a write unit at a memory sub-system;receiving an indication of a time of the performance of the read operation;receiving another indication of another time of a performance of a write operation that stored the data of the write unit at the memory sub-system;determining a difference between the time of the performance of the read operation and the another time of the performance of the write operation; andperforming, by a processing device, a refresh operation for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation.2. The method of claim 1 , further comprising:determining whether the difference between the time of the performance of the read operation and the another time of the performance of the write operation satisfies a threshold difference, wherein the refresh operation is performed responsive to the difference satisfying the threshold difference.3. The method of claim 2 , wherein the threshold difference corresponds to an amount of time that has elapsed since the performance of the write operation that stored the data of the write unit at the ...

MULTIPLE CONCURRENT MODULATION SCHEMES IN A MEMORY SYSTEM

Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ). 1. (canceled)2. An apparatus , comprising:a controller configured to communicate a first data and a second data, the first data modulated using a different modulation scheme than the second data;a first signal path coupled with the controller and a memory die, the first signal path configured to communicate the first data; anda second signal path coupled with the controller and the memory die, the second signal path configured to communicate the second data.3. The apparatus of claim 2 , further comprising:a third signal path coupled with the controller and a second memory die; anda fourth signal path coupled with the controller and the second memory die, wherein the third signal path is configured to communicate the first data and the fourth signal path is configured to communicate the second data.4. The apparatus of claim 2 , further comprising:a bus coupled with the controller and the memory die, the bus configured to communicate the first data and the second data based on a timing of a system clock of the controller.5. The apparatus of claim 2 , further comprising:a first encoder coupled with the controller and configured to modulate the first data; anda second encoder coupled with the controller and configured to modulate the second data.6. The ...

APPARATUS AND METHOD FOR IMPROVING INPUT/OUTPUT THROUGHPUT OF MEMORY SYSTEM

A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit. 1. A memory system , comprising:a plurality of memory dies; anda controller that is coupled to the memory dies through a plurality of channels, the controller comprising circuitry that:selects a second read request, including at least a portion of a plurality of first read requests transferred from an external device, so that the memory dies interleave and output data corresponding to the first read requests through the channels, andperforms a correlation operation for the selected second read request,wherein, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected ...

Apparatuses and methods including memory and operation of same

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access. 120.-. (canceled)21. A system , comprising:a host configured to generate instructions; and receive an instruction from the host; and', 'execute the instruction to perform at least one of a NAND operation or an AND operation using data values stored in the array as inputs by controlling the sensing circuitry without transferring the data values externally from the memory device., 'a memory device comprising an array of memory cells coupled to sensing circuitry comprising a first latch and a second latch, wherein the memory device is configured to22. The system of claim 21 , wherein the second latch serves as an accumulator.23. The system of claim 22 , wherein the second latch is coupled to the first latch via a pair of pass transistors.24. The system of claim 21 , wherein the first latch is a latch is a sense amplifier latch and the second latch is an accumulator latch.25. The system of claim 21 , wherein the host comprises a processor and is coupled to the memory device via a bus.26. The system of claim 21 , wherein the array comprises a plurality of columns of memory cells claim 21 , and wherein executing the instruction includes performing a respective plurality of the at least one of the NAND operation or the AND operation in parallel.27. The system of claim 21 , wherein the system is a server system claim 21 , and wherein the memory device comprises a dynamic random access ...

ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE

Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations). 1. A method , comprising:identifying a quantity of access operations performed on a memory array, the memory array comprising a plurality of memory cells each associated with a respective memory element storing a value based at least in part on a change in a material property associated with the memory element, wherein the quantity of access operations comprises a quantity of write operations and a quantity of read operations;modifying one or more parameters for a write operation based at least in part on the identified quantity of access operations; andwriting a logic state to one or more of the plurality of memory cells by performing the write operation according to the one or more modified parameters.2. The method of claim 1 , further comprising:determining that the identified quantity of access operations exceeds a threshold, wherein modifying the one or more parameters is based at least in part on the determining.3. The method of claim 1 , wherein the modifying the one or more parameters of the write operation comprises:modifying a current magnitude of the write operation.4. ...

MEMORY CONTROLLER

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: a first timing signal that requires a first time interval to propagate to the memory component;', 'write data to be sampled by the memory component synchronously with respect to the first timing signal;', 'a second timing signal that requires a second time interval to propagate to the DRAM; and', 'a write command, corresponding to the write data, to be sampled by the memory component synchronously with respect to the second timing signal; and, 'transmit circuitry to transmit to a memory componentcontrol circuitry to adjust transmit timing of at least one of the first and second timing signals based on a difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component.22. The memory controller component of wherein the second timing signal is a clock signal and the first timing signal is a strobe signal.23. The memory controller component of wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises circuitry to render alignment claim 21 , at the memory component claim 21 , between respective rising edges of the first and second timing signals.24. The memory controller component of wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second ...

CALIBRATION CIRCUIT FOR CONTROLLING RESISTANCE OF OUTPUT DRIVER CIRCUIT, MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE

A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block. 1. A memory device comprising:a calibration circuit having a pull-up code generator comprising a pull-up resistor block and configured to generate a pull-up code, and a pull-down code generator comprising a replica pull-up resistor block and a pull-down resistor block and configured to generate a pull-down code; andan off chip driver (OCD)/on die termination (ODT) circuit configured to provide a termination resistance having a resistance value set by the calibration circuit in a data reception operation and to output data at an output strength set by the calibration circuit in a data output operation,wherein, in a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.2. The memory device of claim 1 , whereinthe pull-up resistor block comprises at least one pull-up resistor set connected to a power source voltage, the ...

Data output circuits

Data output circuits are provided. The data output circuit includes a latch control signal generator and a data output portion. The latch control signal generator generates an input pulse signal and a latch control signal i, and the latch control signal includes a pulse whose width is controlled to have a predetermined time period. The data output portion latches a data loaded on an input/output (I/O) line during a pulse width period of the latch control signal to generate a latch data. Moreover, the data output portion buffers the latch data according to an output control signal generated from a read command signal to output the buffered latch data as an output data.

MEMORY DEVICE

A memory device according to an embodiment of the present invention includes: a memory chip using a magnetic memory; and a memory controller that controls read/write to the memory chip. When the memory controller receives a read request from outside the memory controller, the memory controller transmits a read command to the memory chip to read data in the memory chip. The memory controller also transmits an update command to each area of the memory chip to write back the data stored in the memory chip. 1. A memory device comprising:a memory chip using magnetoresistive elements as storage elements; anda memory controller that controls the memory chip, whereinwhen the memory controller receives a read request from an external device, the memory controller issues a read command to the memory chip to read data stored in the memory chip and sends back the data to the external device,the memory controller further issues an update command to the memory chip independently from the read request from the external device, andwhen the memory chip receives the update command, the memory chip writes back the data stored in the memory chip.2. The memory device according to claim 1 , whereinwhen the memory controller receives a write request and data to be written from the external device,the memory controller generates an error correcting code from the data to be written and stores the data to be written provided with the error correcting code in the memory chip.3. The memory device according to claim 1 , whereinthe memory controller executes a periodic update process of periodically issuing the update command to each area of the memory chip to cause each area of the memory chip to periodically write back the data.4. The memory device according to claim 2 , whereinwhen the memory controller issues the update command to the memory chip,the memory chip sends back the data stored in the area designated by the update command to the memory controller.5. The memory device according to ...

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines. 1. A semiconductor memory device comprising:a memory cell array including a plurality of word lines;a peripheral circuit configured to apply a program voltage to a selected word line among the plurality of word lines; anda control logic configured to control the peripheral circuit to apply pre-bias voltages to the plurality of word lines before the program voltage is applied to the selected word line,wherein each of the plurality of word lines includes a plurality of memory cells; andwherein the pre-bias voltages are determined based on a program sequence of the plurality of word lines.2. The semiconductor memory device according to claim 1 ,wherein the plurality of word lines are grouped into a plurality of word line groups,wherein the plurality of word lines are sequentially programmed in a direction away from a first programmed word line, andwherein the earlier a word line group among the plurality of word line groups is programmed, the lower a pre-bias voltage to be applied to word lines included in the word line group is.3. The semiconductor memory device according to claim 1 ,wherein the plurality of word lines are grouped into a plurality of word line groups,wherein the plurality of word lines are programmed in a sequence from a word line ...

FERAM-DRAM HYBRID MEMORY

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line. 1. (canceled)2. A method of operating a memory device , comprising:determining whether to access a first memory cell or a second memory cell; andapplying, to a transfer gate, a signal based at least in part on the determination, the transfer gate to selectively couple either the first memory cell or the second memory cell to a sense amplifier via a digit line.3. The method of claim 2 , the first memory cell to operate in a volatile mode and the second memory cell to operate in a non-volatile mode.4. The method of claim 2 , wherein the second memory cell is selectively coupled to its respective sense amplifier through the digit line coupled to the first memory cell.5. The method of claim 2 , wherein the second memory cell is associated with a second memory cell array claim 2 , the method further comprising:applying a portion of a supply voltage of the memory device to memory cells associated with the second memory cell array.6. The method of claim 2 , wherein the first memory cell is associated with a first memory cell array claim 2 , the method further comprising:applying a ground voltage of the memory device to memory cells associated with the first memory cell array.7. The method of claim 2 , further comprising:applying, by the sense amplifier coupled to the first memory ...

MEMORY CONTROL CIRCUIT, MEMORY, AND MEMORY CONTROL METHOD

A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage. 1. A memory control circuit comprising:an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells; anda control circuit that associates, when a second number of bits that are included in a first bit string included in the data and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, the first bit string with a first additional value and writes the first bit string and the first additional value to the storage, that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage, that generates, when the second number of the bits is larger than the first threshold and smaller than the second threshold, a fourth bit string by calculating a logical sum of the second ...

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips. 1. A system comprising:a resistor; and a terminal coupled to the resistor; and', 'a calibration circuit configured to determine whether the resistor is available based, at least in part, on timing information unique to a corresponding chip., 'a plurality of chips, each chip of the plurality of chips including2. The system of claim 1 , wherein the timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.3. The system of claim 2 , wherein the calibration circuit of each chip of the plurality of chips includes:a driver circuit coupled to the terminal; andan arbiter circuit configured to enable and disable the driver circuit for the fixed duration of time based on the liming information unique to each respective chip among the plurality of chips.4. The system of claim 2 , wherein the calibration circuit of each chip of the plurality of chips includes:a driver circuit coupled to the terminal; andan arbiter circuit configured to disable the driver circuit to change a voltage of the terminal for a predetermined time in the beginning of the fixed duration of time and further configured to enable the driver circuit after the predetermined time.5. The system of claim 1 , wherein the calibration circuit of each chip of the plurality of chips includes an arbiter circuit claim 1 , andwherein an order in which the plurality of chips requesting calibration ...

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips. 1. An apparatus comprising:a driver circuit coupled to a terminal of a chip; andan arbiter circuit configured to enable the driver circuit to change a voltage of the terminal before determining a resistor coupled to the terminal is available for a calibration operation of the chip, wherein the arbiter circuit enables the driver circuit based at least in part, on timing information unique to the chip.2. The apparatus of claim 1 , further comprising a calibration control circuit coupled to the driver circuit wherein the calibration control circuit is configured to adjust an impedance of the driver circuit when the resistor is available for the calibration operation.3. The apparatus of claim 1 , wherein the driver circuit includes a pull-up circuit and a pull-down circuit.4. The apparatus of claim 3 , wherein the pull-up circuit includes a first plurality of transistors coupled in parallel between a first power supply terminal and a node and the pull-down circuit includes a second plurality of transistors coupled in parallel between a second power supply terminal and the node.5. The apparatus of claim 1 , further comprising a comparator configured to compare a first voltage to a reference voltage and provide a comparator result to the arbiter circuit.6. The apparatus of claim 5 , further comprising a reference voltage generator configured to provide the reference voltage to the comparator.7. The apparatus ...

Memory module

A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE

Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode. 1. (canceled)2. A memory module comprising:at least one non-volatile memory controller;at least one command buffer coupled to the non-volatile memory controller, to receive one or more local commands from the non-volatile memory controller, the command buffer comprising a set of control setting access logic to access one or more control setting registers, wherein a portion of the control setting registers comprises a protected register space, the control setting access logic to restrict access to the protected register space by the non-volatile memory controller in a first control mode; anda proprietary access engine to interpret one or more proprietary access commands from the non-volatile memory controller to access the protected register space in the first control mode.3. The memory module of claim 1 , wherein the proprietary access engine comprises a set of proprietary control setting access logic to interpret the proprietary access commands to write to and/or read from the protected register space.4. The memory module of claim 2 , ...

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE

A storage device including: a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller, a temperature information controller configured to generate a first temperature code corresponding to an internal temperature at a time at which an internal operation corresponding to a first internal operation command among the plurality of internal operation commands is performed and temperature code generation information representing information that the first temperature code has been generated during a set period and a operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input, based on the first temperature code and the temperature code generation information, in response to the second internal operation command. 1. A memory device comprising:a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller;a temperature information controller configured to generate a first temperature code corresponding to an internal temperature at a time at which an internal operation corresponding to a first internal operation command among the plurality of internal operation commands is performed and temperature code generation information representing information that the first temperature code has been generated during a set period; andan operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input, based on the first temperature code and the temperature code generation ...

STORAGE DEVICE AND OPERATING METHOD OF THE STORAGE DEVICE

A memory device includes: memory cells; an operation mode determiner for determining any one of a normal operation mode and a memory communication operation mode of communicating data with another memory device; a pad control signal generator for generating a pad control signal for determining a pad to receive a signal corresponding to a data movement command of the memory controller according to the determined operation mode; a pad controller for receiving the signal through the determined pad according to the pad control signal; an internal command generator for generating an internal operation command corresponding to the data movement command according to the determined operation mode; and an operation controller for performing one of a read operation of reading first target data from the memory cells and a program operation of storing second target data in the memory cells, based on the internal operation command. 1. A memory device comprising:a plurality of memory cells;an operation mode determiner configured to determine any one of a normal operation mode and a memory communication operation mode of communicating data with another memory device according to an operation mode command input from a memory controller;a pad control signal generator configured to generate a pad control signal for determining a pad to receive a signal corresponding to a data movement command of the memory controller according to the determined operation mode;a pad controller configured to receive the signal corresponding to the data movement command through the determined pad according to the pad control signal;an internal command generator configured to generate an internal operation command corresponding to the data movement command according to the determined operation mode; andan operation controller configured to perform one of a read operation of reading first target data to be output to the another memory device from the plurality of memory cells and a program operation of ...

Timing delay control circuits and electronic devices including the timing delay control circuits

An electronic device includes a strobe signal generation circuit and a data output control circuit. The strobe signal generation circuit delays a mode register command by a first predetermined delay period to generate a mode register strobe signal during a mode register read operation. The strobe signal generation circuit adjusts a timing of the mode register strobe signal by detecting variation of timings of first and second variable delay mode register commands, which is generated based on the mode register command, during the mode register read operation. The data output control circuit delays an operation code, which is generated based on the mode register command, by a second predetermined delay period to generate a delayed operation code. The data output control circuit outputs the delayed operation code as data in synchronization with the mode register strobe signal.

Reading circuits and methods

A reading circuit is provided in the invention. The reading circuit includes a pre-charger, a bit-line selecting circuit, and a latch circuit. The pre-charger receives a pre-charging control signal and the pre-charger is opened or closed according to the pre-charging control signal. The bit-line selecting circuit is coupled with the pre-charger at a node and selects a bit line for reading data according to a selecting signal. The latch circuit is coupled with the pre-charger at a node and outputs and latches the data of the bit line.

SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal. 1. An apparatus comprising:a first power source terminal supplied with a first power potential;a second power source terminal supplied with a second power potential;a data terminal, wherein the data terminal is disposed between the first and second power source terminals;a calibration terminal, wherein the calibration terminal is disposed such that the second power source terminal is between the data terminal and the calibration terminal;a third power source terminal supplied with a third power potential, wherein the third power source terminal is disposed between the second power source terminal and the calibration terminal;an output buffer, wherein the output buffer comprises a first circuit and a second circuit, wherein the first circuit is coupled between the first power source terminal and the data terminal to drive the data terminal toward the first power potential and wherein the second circuit is coupled between the data terminal and the second power source terminal to drive the data terminal to the second power potential; anda calibration circuit, wherein the calibration circuit is configured to perform a calibration operation on the output buffer, wherein the calibration circuit composes a third circuit serving as a replica of the first circuit, a fourth circuit serving as a replica of the second circuit and a fifth circuit serving as a replica ...

MEMORY DEVICE FOR GENERATING DATA STROBE SIGNAL BASED ON PULSE AMPLITUDE MODULATION, MEMORY CONTROLLER, AND MEMORY SYSTEM INCLUDING THE SAME

A memory device includes a memory cell array and a data input and output circuit configured to output a data signal (DQ signal) including data read from the memory cell array and a data strobe signal (DQS signal) including a toggle pattern associated with an operating condition of the memory device based on n-level pulse amplitude modulation (PAMn), wherein n is an integer greater than or equal to 4.

Multi-level signal receivers and memory systems including the same

A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M−1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M−1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M−1) reference voltages, At least two sense amplifiers of the (M−1) sense amplifiers have different sensing characteristics.

SEMICONDUCTOR INTEGRATE CIRCUIT

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data. 1. A semiconductor integrated circuit comprising:a data transmitting circuit that transmits transmission data through a plurality of signal lines and a strobe signal in synchronization with the transmission data, a plurality of data output circuits that output the transmission data and set an output of the data output circuit to a high impedance state, each of the plurality of data output circuits being provided for a corresponding one of the plurality of signal lines;', 'a plurality of data selection circuits, each of which selects one of the transmission data and preliminary-set fixed data, and outputs the selected data to a corresponding one of the data output circuits; and', 'a control circuit that controls the data output circuits and the data selection circuits so that each of the data output circuits outputs the fixed data during a period between when the high impedance state of the output of the data output circuits terminates and when the data output circuits start to output the transmission data., 'wherein the data transmitting circuit comprises2. The semiconductor integrated circuit according to claim 1 , wherein a resistor that ...

SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

SECURE MECHANISM IN SECURITY CHIP

A memory device, including a secure command decoder implementing security logic configured to detect commands carrying an encrypted immediate data payload from a requesting host, authenticate the host as source of the command, decode the immediate data and perform a memory access command called for by a command portion of the decrypted immediate data upon the storage cells of the memory device using the non-command portion of the decrypted immediate data, as well as to encrypt any result from executing the command portion prior to returning the result to the requesting host, and an input/output interface for I/O data units supporting multiple hosts. 2. The device of claim 1 , further comprising:the command decoder circuit receiving a command sequence including: a command code field and an intermediate data payload, wherein:the command code field includes an op code indicating one of (i) an unencrypted command; and (ii) a secured command in which the intermediate data payload includes an encrypted memory access command op code, an encrypted address field indicating a location or locations from which data is to be read, and one or more encrypted input variables including an encrypt result indicator.3. The device of claim 2 , further comprising:the security logic circuitry having encrypt/decrypt circuits that encrypt data read from memory resulting from reading data when the op code indicates a secured command, the encrypted memory access command op code indicates a read from memory, and encrypt result indicator of the one or more encrypted input variables indicates encrypting the result.4. The device of claim 1 , further comprising:the command decoder circuit receiving a command sequence including: a command code field and an intermediate data payload, wherein:the command code field includes an op code indicating one of (i) an unencrypted command; and (ii) a secured command in which the intermediate data payload includes an encrypted memory access command op code, an ...

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

DATA BUFFER AND MEMORY DEVICE HAVING THE SAME

There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level. 1. A data buffer comprising:a first amplifier configured to output data obtained by inverting input data in a first mode, the first amplifier configured to output data that is of a low level to an output node based on the input data in a second mode in which a swing level of data is different from that of data in the first mode; anda second amplifier configured to output data obtained by inverting the input data together with the first amplifier in the first mode, the second amplifier configured to output data that is of a high level to the output node based on the input data in the second mode.2. The data buffer of claim 1 , wherein the first amplifier includes:a first switch coupling, to the output node, a node to which a positive voltage is applied; anda second switch coupling the output node to a ground, based on the input data.3. The data buffer of claim 2 , wherein the first switch:couples the node to which the positive voltage is applied and the output node in the first mode; andblocks the node to which the positive voltage is applied from coupling the output node in the second mode.4. The data buffer of claim 2 , wherein the second switch couples the output node and the ground claim 2 , based on the input data claim 2 , in the first mode and the second mode.5. The data buffer of claim 1 , wherein the second amplifier includes:a third switch coupling, to the output node, a node to which a ...

MEMORY DEVICE AND CENTRAL PROCESSING UNIT

A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data line; and a line swap circuit configured to connect the first and second internal data lines with first and second external data lines based on an externally received driving signal. The line swap circuit is configured such that, when the driving signal has a first logic level, the line swap circuit connects the first and second internal data lines with the first and second external data lines, respectively, and when the driving signal has a second, different logic level, the line swap circuit swaps the first and second external data lines so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line. 1. A memory device comprising:a first memory cell array connected to a first internal data line;a second memory cell array connected to a second internal data line; anda line swap circuit configured to connect the first internal data line and the second internal data line with a first external data line and a second external data line based on a driving signal received from the outside, when the driving signal has a first logic level, the line swap circuit connects the first internal data line and the second internal data line with the first external data line and the second external data line, respectively, and', 'when the driving signal has a second logic level different from the first logic level, the line swap circuit swaps the first external data line and the second external data line so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line., 'the line swap circuit being configured such that,'}2. The memory device of claim 1 ,wherein the line swap circuit is configured to operate in response to the driving ...

Apparatuses and methods for adjusting delay of command signal path

Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING AND CONTROLLING A SEMICONDUCTOR DEVICE

An exemplary embodiment includes a method of controlling a semiconductor device. The semiconductor device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, a row decoder for receiving a row address and selecting a word line corresponding to the row address, a column decoder for receiving a column address and selecting a bit line corresponding to the column address, a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line, and a data output driver. The method includes setting a calibration code for a driver control code, to control an initial current strength of the data output driver, and changing the calibration code to change the driver control code during a read or write operation for the memory cell array. 1. A method of controlling a semiconductor device , the semiconductor device comprising:a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines;a row decoder for receiving a row address and selecting a word line corresponding to the row address;a column decoder for receiving a column address and selecting a bit line corresponding to the column address;a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line; anda data output driver including a first driver including a plurality of first transistors having different sizes from each other and a second driver including a plurality of second transistors having the same size as each other, the first driver and the second driver outputting the data to an output pad and driven to provide impedance to the output pad, the method comprising:at a first time, outputting a first calibration code for the first driver and a second calibration code for the second driver to control the impedance provided to the output pad; andat a second ...

Memory modules, memory systems including the same, and methods of calibrating multi-die impedance of the memory modules

A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.

IN-MEMORY COMPUTING METHOD AND IN-MEMORY COMPUTING APPARATUS

An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data. 1. An in-memory computing method , adapted to perform multiply-accumulate (MAC) operations by a processor using a memory , wherein the memory comprises a plurality of intersecting input lines and output lines , a plurality of memory cells respectively arranged at intersections of the input lines and the output lines , and a plurality of sensing amplifiers respectively connected to the output lines , the method comprising:respectively performing a pre-processing operation on input data and weight data to be written into the input lines and the memory cells to divide the input data and the weight data into a primary portion and a secondary portion;writing the input data and the weight data divided into the primary portion and the secondary portion into the input lines and the memory cells in batches to perform the multiply-accumulate operations to obtain a plurality of computation results;filtering out the computation results according to a numeric value of each of the computation results; andperforming a post-processing operation on the filtered computation results ...

MEMORY DEVICES CONFIGURED TO GENERATE PULSE AMPLITUDE MODULATION-BASED DQ SIGNALS, MEMORY CONTROLLERS, AND MEMORY SYSTEMS INCLUDING THE MEMORY DEVICES AND THE MEMORY CONTROLLERS

A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers. 1. A memory device comprising:a memory cell array; anda data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal, wherein the data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) with a DQ parameter that corresponds to an operating frequency condition, and wherein n is an integer greater than or equal to four.2. The memory device of claim 1 , wherein the data input/output circuit is configured to output first and second DQ signals that are scaled with different DQ parameters respectively in response to first and second read commands received under different operating frequency conditions.3. The memory device of claim 2 , wherein at least one of an interval between adjacent levels of the n levels and a transition slope between adjacent levels of the n levels in the first DQ signal is different from an interval between adjacent levels of the n levels or a transition slope between adjacent levels of the n levels of the second DQ signal.4. The memory ...

TIMING SIGNAL DELAY COMPENSATION IN A MEMORY DEVICE

Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof. 1. A method , comprising:receiving, at a delay component of a memory device, a first timing signal and an impedance configuration signal;configuring an impedance of the delay component based at least in part on the impedance configuration signal; andgenerating a second timing signal based at least in part on the first timing signal and the impedance configuration signal, wherein the second timing signal is delayed relative to the first timing signal based at least in part on the configured impedance of the delay component.2. The method of claim 1 , wherein configuring the impedance of the delay component comprises:configuring a resistance between a source of a transistor and a drain of the transistor based at least in part on biasing a gate of the transistor with the impedance configuration signal.3. The method of claim 1 , wherein generating the second timing signal comprises:generating the second timing signal with a rising edge that is delayed, relative to a rising edge of the first timing signal, with a delay that is based at least in part on configuring the impedance of the delay component.4. The method of ...

POWER SUPPLY WIRING IN A SEMICONDUCTOR MEMORY DEVICE

The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer. 19-. (canceled)10. A semiconductor device , comprising:an uppermost metal layer including a power supply enhancing wiring;power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer;at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer; and a plurality of sense amplifiers;', 'a plurality of memory mats coupled to the sense amplifiers, the memory mats including first and second edge mats; and, 'a memory bank, includinga global input/output line coupled to the sense amplifiers and disposed over the first edge mat and not disposed over the second edge mat;wherein the at least one memory device component disposed in vertical alignment with the via includes the second edge mat.11. (canceled)12. The semiconductor device of claim 11 , wherein the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer is a first via claim 11 , the semiconductor device further comprising:a column decoder adjacent to the second edge mat; anda second via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the second via is disposed in vertical alignment with the column decoder.13. The semiconductor device of ...

Apparatuses and methods for storing a data value in multiple columns

An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

MANAGING THRESHOLD VOLTAGE DRIFT BASED ON OPERATING CHARACTERISTICS OF A MEMORY SUB-SYSTEM

Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics. 1. A method comprising:establishing a plurality of sets of values corresponding to operating characteristics of a memory sub-system;for each of the plurality of sets of values corresponding to the operating characteristics, identifying a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system;storing a data structure including the read voltage level for each set of values of the operating characteristics;in response to a read command, determining a current set of values of the operating characteristics;identifying, using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics; andexecuting, by a processing device, the read command using the stored read voltage level corresponding to the current set of values of the operating characteristics.2. The method of claim 1 , further comprising performing a look up operation associated with the data structure to determine the stored read voltage level corresponding to the current set of values of the operating characteristics.3. The method of claim 1 , wherein the operating characteristics comprise at least one of ...

METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION

Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level. 117-. (canceled)18. An apparatus comprising:an interface operable to access a memory, the memory comprising a register to store a termination impedance setting for termination of an input-output (I/O) interface of the memory; and send a signal to set a default termination impedance value with the termination impedance setting of the register, wherein the default termination impedance value to be applied to the I/O interface in response to de-assertion of a termination signal to activate termination of the I/O interface of the memory, and', 'send a termination signal to switch from the default termination impedance value to a different termination impedance value for the I/O interface of the memory, wherein the default termination impedance value and the different termination impedance value are both finite values., 'a logic unit operable to'}19. The apparatus of claim 18 , wherein the I/O interface of the memory comprises a Double Data Rate 4 (DDR4) interface of the memory.20. The apparatus of claim 18 , wherein the memory comprises a Dynamic Random Access Memory (DRAM).21. The apparatus of claim 18 , wherein the memory resides in a memory module which is a Dual In-Line Memory Module (DIMM) with one or more Dynamic Random Access Memories (DRAMs).22. The apparatus of claim 18 , wherein the termination signal is to cause at ...

MEMORY CONTROLLER AND OPERATING METHOD THEREOF

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation. 1. A memory controller configured to control a memory device , the memory device being coupled to the memory controller through a channel , the memory controller comprising:an idle time monitor configured to output an idle time interval of the memory device, the idle time interval being between an end time of a previous operation of the memory device and a start time of a current operation; anda clock signal generator configured to generate a clock signal based on the idle time interval and output the clock signal to the memory device through the channel to perform the current operation.2. The memory controller according to claim 1 , wherein the clock signal generator comprises:a frequency controller configured to determine a frequency for generating the clock signal based on the idle time interval.3. The memory controller according to claim 1 , wherein the clock signal generator comprises:a signal generator configured to generate the clock signal based on a determined frequency.4. The memory controller according to claim 1 , wherein the ...

ADAPTIVE APPLICATION OF VOLTAGE PULSES TO STABILIZE MEMORY CELL VOLTAGE LEVELS

A request to apply a plurality of voltage pulses to memory cells of a memory device can be received. A number of the voltage pulses can be applied the memory cells of the memory device, where a voltage pulse of the number of the voltage pulses places the memory cells of the memory device at a voltage level associated with a defined voltage state. A set of bit error rates associated with the memory cells of the memory device at the voltage level can be determined. Responsive to determining that the set of bit error rates does not satisfy a threshold condition, an additional number of the voltage pulses to the memory cells of the memory device can be applied. 1. A method comprising:receiving a request to perform a seasoning operation on memory cells of a memory device;responsive to receiving the request, applying, by a processing device, a set of voltage pulses to the memory cells of the memory device, a voltage pulse of the set of the voltage pulses placing the memory cells of the memory device at a voltage level associated with a defined voltage state;determining a set of bit error rates associated with the memory cells of the memory device at the voltage level in view of a data mapping pattern for the memory cells of the memory device, wherein the data mapping pattern assigns a voltage level associated with a reset state to at least a portion of the memory cells of the memory device;determining whether the set of bit error rates satisfies a threshold condition; andresponsive to determining that the set of bit error rates does not satisfy the threshold condition, applying another set of the voltage pulses to the memory cells of the memory device.2. The method of claim 1 , wherein the defined voltage state is associated with a programmed state claim 1 , the method further comprising:determining a first voltage pulse duration associated with placing a memory cell in the programmed state; andapplying the set of voltage pulses at a second voltage pulse duration that is ...

Tracking mechanisms

A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated.

SIGNALING INTERFACE WITH PHASE AND FRAMING CALIBRATION

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices. 120-. (canceled)21. A method of operation within a memory controller , the method comprising:outputting a first timing signal to a memory device to time transmission of a data signal from the memory device to the memory controller;sampling the data signal in response to a second timing signal during first and second calibration intervals to generate respective first and second calibration data sequences;adjusting a phase of the first timing signal, based at least in part on whether the first calibration data sequence matches a first expected data pattern, to phase-adjust the data signal relative to the second timing signal; andadjusting a first control value that defines framing boundaries between respective multi-bit values conveyed in the data signal based at least on whether the second calibration data sequence matches a second expected data pattern.22. The method of wherein each bit conveyed in the data signal is valid at an input of the controller for a respective bit interval claim 21 , and wherein adjusting the phase of the first timing signal comprises adjusting a phase of the data signal within a phase range corresponding to the respective bit interval.23. The method of wherein the first calibration data ...

METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DIRECTED TO WRITE-ONLY MODE REGISTER BITS AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices. 1. A method comprising:receiving, at a memory device, a mode register read command targeting a write-only bit of a mode register; andin response to the mode register read command, outputting data indicative of a status of the memory device that is independent of a value stored in the write-only bit.2. The method of claim 1 , further comprising determining that a status information mode of the memory device is enabled claim 1 , and wherein outputting the data is based at least in part on the determination.3. The method of claim 2 , wherein determining that the status information mode of the memory device is enabled includes reading a setting stored in another mode register of the memory device.4. The method of claim 1 , wherein the data indicative of the status of the memory device comprises device settings claim 1 , environmental conditions claim 1 , usage statistics claim 1 , metadata claim 1 , feature support claim 1 , feature implementation claim 1 , device status claim 1 , temperature claim 1 , or a combination thereof.5. The method of claim 1 , wherein the memory device is a dynamic random-access memory (DRAM) device.6. A memory device comprising:a memory array;a mode register including a mode register bit that is configured to be read-only with when addressed by ...

Invert operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.

LEVEL SHIFTER SPARE CELL

A method for configuring level shifter spare cells includes providing a power rail connectable to a corresponding power domain, and providing a spare cell including a level shifter circuit. The level shifter circuit has first and second terminals that are connectable to the power rail, and the first and second terminals are floating with respect to the power rail. 1. A method for configuring level shifter spare cells , the method comprising:providing at least one power rail connectable to a corresponding power domain, wherein the power domain has a power level;providing at least one spare cell comprising a level shifter circuit, wherein the level shifter circuit has a first terminal and a second terminal that are connectable to the at least one power rail; andfloating the first and second terminals with respect to the at least one power rail.2. The method of claim 1 , wherein the method further comprises:coupling the first terminal of the level shifter circuit with one of the at least one power rail; andcoupling the second terminal of the level shifter circuit with the one or another of the at least one power rail.3. The method of claim 2 , wherein the coupling of the second terminal of the level shifter circuit with the one or another of the at least one power rail comprises coupling the second terminal with the power rail to which the first terminal is coupled such that the level shifter circuit operates as a buffer circuit.4. The method of claim 2 , wherein the coupling of the first terminal and the coupling of the second terminal leave at least one of the power rails not coupled to another power rail through the level shifter circuit.5. The method of claim 1 , wherein the providing at least one spare cell comprises providing a number of the spare cells claim 1 , wherein the number of the spare cells is less than n*(n−1) claim 1 , wherein n is a number of the power domains.6. The method of claim 1 , wherein the providing the at least one spare cell comprises ...

Channel controlling device for improving data reading efficiency

A channel controlling device includes: a multiplexing circuit coupled to a plurality of channels for selecting a specific channel from the channels to output a channel data according to a selecting signal, wherein the channels correspond to a plurality of predetermined digital numbers; a sorting circuit arranged to queue the predetermined digital numbers to form a plurality of queued digital numbers according to a data output order of the channels; and an arbitration circuit, arranged to determine the selecting signal according to the plurality of queued digital numbers.

SIGNAL AMPLIFIER, SIGNAL RECEIVING CIRCUIT INCLUDING THE SAME, AND DEVICE INCLUDING THE SAME

A signal amplifier includes a first amplifier, a second amplifier, and an output. The first amplifier amplifies a first input signal to form a first amplified output signal. The first input signal has a common mode voltage in a first voltage range, and the first amplified output signal has a common mode voltage in a second voltage range different from the first voltage range. The second amplifier amplifies a second input signal to form a second amplified output signal. The first input signal has the common mode voltage in the second voltage range and the second amplified output signal has the common mode voltage in the second voltage range. The output outputs the first amplified output signal or the second amplified output signal as an amplified output signal. 1. A signal amplifier , comprising:a first amplifier to amplify a first input signal to form a first amplified output signal, the first input signal having a common mode voltage in a first voltage range and the first amplified output signal having a common mode voltage in a second voltage range different from the first voltage range;a second amplifier to amplify a second input signal to form a second amplified output signal, the first input signal having the common mode voltage in the second voltage range and the second amplified output signal having the common mode voltage in the second voltage range; andan output to output the first amplified output signal or the second amplified output signal as an amplified output signal.2. The signal amplifier as claimed in claim 1 , wherein:the first amplifier is to output a first bias voltage in the first voltage range,the output is to output a second bias voltage in the second voltage range, andthe signal amplifier includes a bias controller to adjust a level of power supplied to the first amplifier and the second amplifier based on the first bias voltage and the second bias voltage.3. The signal amplifier as claimed in claim 1 , further comprising:an enable controller ...

Semiconductor memory device having a plurality of chips and capability of outputting a busy signal

One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Input-output line sense amplifier having adjustable output drive capability

An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

SEMICONDUCTOR DEVICE AND SYSTEM PERFORMING CALIBRATION OPERATION

A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device. 1. A semiconductor device comprising:a calibration circuit configured to perform a calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in a controller; andan output circuit coupled to the signal transmission line, a resistance value of the output circuit being set based on a result of the calibration operation.2. The semiconductor device according to claim 1 , wherein the calibration circuit generates a pull-up code and a pull-down code by being coupled to the reference resistor.3. The semiconductor device according to claim 2 , wherein the output circuit includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs claim 2 , and wherein resistance values of the plurality of pull-up resistor legs are set based on the pull-up code claim 2 , and resistance values of the plurality of pull-down resistor legs are set based on the pull-down code.4. The semiconductor device according to claim 1 , wherein the reference resistor is provided in an output circuit of another semiconductor device that is coupled to the signal transmission line.5. A semiconductor system comprising:a first semiconductor device including an output circuit coupled to a signal transmission line; anda second semiconductor device including:an output circuit coupled with the signal transmission line; anda calibration circuit configured to perform a calibration operation by being coupled, through the signal transmission line, to a reference resistor provided in the first semiconductor device,wherein a resistance value of the output circuit of the ...

FIRST-PASS CONTINUOUS READ LEVEL CALIBRATION

Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device performs a cRLC operation on the memory cell to calibrate a read level threshold between a first first-pass programming distribution and a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell. 1. A system comprising:a memory component; and determine that a first programming pass of a programming operation has been performed on a memory cell of the memory component; and', calculate a center bit error count;', 'calculate a difference error count; and', 'adjust the read level threshold of the memory cell based on the center bit error count and the difference error count., 'perform a continuous read level calibration (cRLC) operation on the memory cell to calibrate a read level threshold between a first first-pass programming distribution and a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell, wherein, to perform the cRLC operation, the processing device is further to], 'a processing device, operatively coupled with the memory component, to2. The system of claim 1 , wherein the processing device is further to:perform a second cRLC operation on the memory cell to calibrate a second read level threshold between the second first-pass programming distribution and a third first-pass programming distribution before the second programming pass of the programming operation is performed on the memory cell.3. The system of claim 1 , wherein the processing device is further to:perform one or more cRLC operations on the memory cell to calibrate a read level threshold between each pair of a plurality of first ...

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips. 1. A method comprising:floating a voltage of an external pad for a first period of time;pulling down the voltage of the external pad to a first voltage state for a second period of time; andpulling down or floating the voltage of the external pad for individual ones of a plurality of clock cycles, wherein whether the voltage of the external pad is pulled down or floated for a clock cycle of the plurality of clock cycles is based, at least in part, on timing information unique to a chip of a plurality of chips.2. The method of claim 1 , further comprising claim 1 , prior to pulling down the voltage of the external pad to the second voltage state for the second period of time claim 1 , comparing the voltage of the external pad to a reference voltage to determine whether the voltage of the external pad is at the first voltage state or a second voltage state claim 1 , wherein when the voltage of the external pad is determined to be the first voltage state claim 1 , the method further comprises repeating floating the voltage of the external pad for the first period of time.3. The method of claim 1 , further comprising comparing the voltage of the external pad to a reference voltage to determine whether the voltage of the external pad is at the first voltage state or a second voltage state after each clock cycle of the plurality of clock cycles claim 1 , wherein when the voltage of the external pad is ...

MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY COMPUTATION

Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array. 1. A memory device for performing a computation , the memory device comprising:first circuitry to couple the memory device to a memory controller and to receive first data from the memory controller;a first array of memory cells;a second array of memory cells; store the first data to the first array;', 'communicate the first data from the first array to the second array;', 'communicate from the second array a first signal which indicates a logic state based on a bit of the first data; and', 'store a result of a data computation at the second array; and, 'second circuitry coupled to operate the first array and the second array tothird circuitry coupled to receive the first signal and to perform the data computation based on the first signal.2. The memory device of claim 1 , wherein respective rows and columns of the first array and the second array each extend in parallel with a first plane claim 1 , wherein the first array is offset from the second array in a direction orthogonal to the first plane.3. The memory device of claim 2 , wherein the second circuitry to operate the first array to store the first data to the first array comprises the second circuitry to decode an address of a memory location at the first array claim 2 , wherein the second circuitry and the second array each extend in the first plane.4. The memory ...

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

A semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines. 1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells;a peripheral circuit configured to perform a program operation for the memory cells included in the memory cell array; anda control logic configured to control the peripheral circuit and the memory cell array such that during a program operation for the memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the memory cells to precharge channel regions of the memory cells,wherein different pre-bias voltages are applied to the word lines depending on relative positions of the word lines.2. The semiconductor memory device according to claim 1 ,wherein the word lines are grouped into a plurality of word line groups, andwherein the closer a word line group to which a word line belongs is to a first-programmed memory cell in the memory cell array, the lower a pre-bias voltage to be applied to the word line is.3. The semiconductor memory device according to claim 1 ,wherein the word lines are grouped into a plurality of word line groups,wherein the memory cells are programmed in a sequence from a memory cell adjacent to a source select transistor, andwherein the ...

SEMICONDUCTOR MEMORY AND SEMICONDUCTOR SYSTEM USING THE SAME

A semiconductor memory includes a plurality of path circuits for transmitting data inputted from an exterior source or device to a chip. The semiconductor memory is configured to generate a plurality of pre-error detection signals by detecting whether data transmitted between the plurality of path circuits have errors, and selectively output the plurality of pre-error detection signals. 1. A semiconductor memory comprising:a plurality of path circuits for transmitting an external data inputted from an exterior source or device to a chip,wherein the semiconductor memory is configured to generate a plurality of pre-error detection signals by detecting whether data transmitted between the plurality of path circuits have errors, and selectively output the plurality of pre-error detection signals.2. The semiconductor memory according to claim 1 , wherein the plurality of path circuits comprise:a physical layer; anda through electrode region for transmitting data transmitted through the physical layer to another chip.3. The semiconductor memory according to claim 2 , wherein the plurality of path circuits further comprise:a direct access electrode region for transmitting the data inputted from the exterior source or device to the physical layer.4. The semiconductor memory according to claim 1 , wherein the semiconductor memory is configured to generate the plurality of pre-error detection signals by using data transmitted between the plurality of path circuits and a parity bit provided from the exterior source or device.5. The semiconductor memory according to claim 1 , wherein the semiconductor memory comprises:a plurality of error detection circuits configured to generate the plurality of pre-error detection signals according to the data transmitted between the plurality of path circuits and a parity bit; anda multiplexer configured to output an error detection signal by selecting one among the plurality of pre-error detection signals according to a control signal.6. ...

PROGRAMMABLE LOGIC CIRCUIT, INFORMATION PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

A programmable logic circuit includes multiple logic blocks that are connected communicatively, wherein multiple modules are reconfigured in any of the logic blocks, and wherein the modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory. 1. A programmable logic circuit comprising:a plurality of logic blocks that are connected communicatively,wherein a plurality of modules are reconfigured in any of the plurality of logic blocks, andwherein the plurality of modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory.2. The programmable logic circuit according to claim 1 ,wherein the first time and the second time are predicted.3. The programmable logic circuit according to claim 1 ,wherein the memory is reconfigured in any of the plurality of logic blocks.4. The programmable logic circuit according to claim 2 ,wherein the memory is reconfigured in any of the plurality of logic blocks.5. The programmable logic circuit according to claim 1 ,wherein the first module comprises one or more first modules, andwherein start of execution of the second module is delayed from the start time point of execution of any of the one or more first modules in accordance with a combination of the one or more first modules and the second module.6. The programmable logic circuit according to claim 2 ,wherein the first module comprises one or more first ...

TECHNIQUES FOR READ OPERATIONS

Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch. 1. (canceled)2. An apparatus , comprising:a first source follower coupled with a reference voltage supply and configured to output a first signal representative of a reference voltage provided by the reference voltage supply;a second source follower coupled with a digit line of a memory cell and configured to output a second signal representative of a logic state stored by the memory cell; anda reference capacitor coupled with the first source follower and configured to modify a reference voltage offset associated with the first signal.3. The apparatus of claim 2 , further comprising:a first switching component coupled with the reference capacitor and a gate of the first source follower, the first switching component configured to establish a first conductive path between the reference capacitor and the first source follower.4. The apparatus of claim 3 , further comprising:a second switching component coupled with the reference capacitor and a first voltage source, the second switching component configured to establish a second conductive path between the first voltage source and the reference capacitor.5. The ...

Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled by a third power supply

Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.