Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

BACKGROUND OPERATIONS IN MEMORY

The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device. 1. An apparatus , comprising:a memory device; and send a ready/busy signal to a host via a ready/busy signal bus; and', 'send a command to the memory device to perform a background operation in response to sending the ready/busy signal to the host; and, 'a controller coupled to the memory device via a register clock driver, wherein the controller is configured to 'perform a background operation in response to receiving the command from the controller.', 'wherein the memory device is configured to2. The apparatus of claim 1 , wherein the ready/busy signal indicates that the controller is busy.3. The apparatus of claim 2 , wherein the controller is busy in response to a dual in-line memory module (DIMM) executing a command.4. The apparatus of claim 3 , wherein the DIMM includes the memory device and a different memory device.5. The apparatus of claim 4 , wherein the DIMM executing the command includes the memory device transferring data to the different memory device.6. The apparatus of claim 3 , wherein the DIMM sends a second ready/busy signal to the host in response to completing the execution of the command.7. The apparatus of claim 6 , wherein the DIMM receives a command from the host in response to sending the second ready/busy signal.8. The apparatus of claim 1 , wherein the background operation includes performing ...

Techniques for power management using loopback

Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.

Methods for error count reporting with scaled error count information, and memory devices employing the same

An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register. 1. A memory device , comprising:a first memory portion;a second memory portion;a mode register;an external terminal; and perform the refresh operation at the first memory portion,', 'perform a read of the mode register, and', 'provide on-die termination at the second memory portion during at least a portion of the read of the mode register., 'circuitry configured, in response to receiving a command to perform a refresh operation at the first memory portion and an indication at the external terminal indicating that a mode register read function is enabled, to2. The memory device of claim 1 , wherein the circuitry is further configured to decode the command at the second memory portion in response to the indication indicating that the mode register read function is enabled.3. The memory device of claim 1 , wherein the circuitry is further configured to decode the command at the first portion in response to an indication received at a first external terminal that the refresh operation is directed to the first memory portion.4. The memory device of claim 3 , wherein the first external terminal is ...

APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

APPARATUSES AND SYSTEMS HAVING BALL GRID ARRAYS AND ASSOCIATED MICROELECTRONIC DEVICES AND DEVICE PACKAGES

Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

MEMORY DEVICES WITH PROGRAMMABLE LATENCIES AND METHODS FOR OPERATING THE SAME

A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation. 1. A memory device comprising:a memory array of DRAM cells;operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device; anddelay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command, the one or more bits indicating a duration by which to delay the performance of the memory operation.2. The memory device of wherein the memory operation is one of a read operation claim 1 , a write operation claim 1 , an erase operation claim 1 , a terminate operation claim 1 , and a status operation.3. The memory device of wherein the duration is a number of clock cycles by which to delay the performance of the memory operation.4. The memory device of wherein the one or more bits include a single bit indicating that the duration is either 0 or a predetermined delay.5. The memory device of wherein the one or more bits include a plurality of bits indicating that the duration is one of at least two predetermined delays.6. (canceled)7. The memory device of wherein the memory device is a memory die claim 1 , and wherein the operation circuitry and the delay circuitry are on the memory die.8. The memory device of wherein the memory device is a memory module claim 1 , wherein the memory array is in a memory die of the memory module claim 1 , and wherein the delay circuitry is off of the memory die.9. The memory device of wherein the memory device is one of a DIMM claim 1 , an RDIMM claim ...

Methods of synchronizing memory operations and memory systems employing the same

A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.

INDIVIDUALLY ADDRESSING MEMORY DEVICES DISCONNECTED FROM A DATA BUS

Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided. 1. A memory device , comprising:at least one command contact; andat least one data contact, detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and', 'in response to the detected condition, enter a first operating mode with a lower nominal power rating than a second operating mode., 'wherein the memory device is configured to2. The memory device of claim 1 , wherein the memory device is configured to detect the condition based at least in part on detecting a command signal at the at least one command contact and determining that the at least one data contact is grounded.3. The memory device of claim 2 , wherein the command signal comprises a reset signal.4. The memory device of claim 1 , wherein the at least one command contact includes a first strobe contact and a second strobe contact claim 1 , and wherein the memory device is configured to detect the condition based at least in part on determining that the first and second strobe contacts are driven to opposing high and low levels.5. The memory device of claim 4 , wherein the first strobe contact and the second strobe contact are coupled to a first-in first-out (FIFO) counter claim 4 , and wherein determining that the first and second strobe contacts are ...

METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DIRECTED TO WRITE-ONLY MODE REGISTER BITS AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices. 1. A method comprising:receiving, at a memory device, a mode register read command targeting a write-only bit of a mode register; andin response to the mode register read command, outputting data indicative of a status of the memory device that is independent of a value stored in the write-only bit.2. The method of claim 1 , further comprising determining that a status information mode of the memory device is enabled claim 1 , and wherein outputting the data is based at least in part on the determination.3. The method of claim 2 , wherein determining that the status information mode of the memory device is enabled includes reading a setting stored in another mode register of the memory device.4. The method of claim 1 , wherein the data indicative of the status of the memory device comprises device settings claim 1 , environmental conditions claim 1 , usage statistics claim 1 , metadata claim 1 , feature support claim 1 , feature implementation claim 1 , device status claim 1 , temperature claim 1 , or a combination thereof.5. The method of claim 1 , wherein the memory device is a dynamic random-access memory (DRAM) device.6. A memory device comprising:a memory array;a mode register including a mode register bit that is configured to be read-only with when addressed by ...

Methods for triggering oscilloscopes and oscilloscopes employing the same

A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.

REFRESH OPERATION IN MULTI-DIE MEMORY

Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device. 1. A method comprising:receiving a first refresh command directed to a first memory array of a three-dimensional stacked (3DS) memory device;receiving a second refresh command directed to a second memory array of the 3DS memory device;determining that execution of the second refresh command will overlap in time with execution of the first refresh command; andbased on the determining, delaying the execution of the second refresh command to the second memory array for a time period that is based at least in part on an operating characteristic of the 3DS memory device, a user-defined value, or an industry specification, or any combination thereof.2. The method of claim 1 , wherein delaying execution of the second refresh command to the second memory array for the time period further comprises: 'wherein the maximum delay allowed is based on a time of a last previous refresh operation to the row of the second memory array and a maximum refresh interval of the second memory array; and', 'computing a value of a maximum delay allowed before a next refresh operation to a row of the second memory array,'} 'wherein the minimum delay is based at least in part on an operating characteristic of the 3DS memory device, a user-defined value, a multiple of a time period associated with execution of the first refresh command, or an industry specification, or any combination thereof;', 'computing a value of a minimum delay of the second ...

ERROR INJECTION METHODS USING SOFT POST-PACKAGE REPAIR (sPPR) TECHNIQUES AND MEMORY DEVICES AND MEMORY SYSTEMS EMPLOYING THE SAME

Methods for operating a memory system are disclosed herein. In one embodiment, a method comprises receiving first data to be written at a logical address of a memory array, storing the first data at a first physical address corresponding to the logical address, and remapping the logical address to a second physical address, for example, using a soft post package repair operation. The method can further include receiving second data different from the first data to be written at the logical address, storing the second data at the second physical address, and remapping the logical address to the first physical address. In some embodiments, the method can comprise storing first and second ECC data corresponding to the first and second data, respectively. The method can further comprise outputting the first data and/or the second ECC data in response to a read request corresponding to the logical address. 1. A method , comprising:receiving first data to be written at a logical address;storing the first data at a first physical address corresponding to the logical address;remapping the logical address to a second physical address;receiving second data different from the first data to be written at the logical address;storing the second data at the second physical address;remapping the logical address to the first physical address; andin response to a read request corresponding to the logical address, outputting the first data from the first physical address.2. The method of claim 1 , wherein the first data corresponds to the second data with one or more errors intentionally injected.3. The method of claim 2 , wherein the one or more errors comprise a bit insertion claim 2 , a bit deletion claim 2 , or a bit inversion.4. The method of claim 1 , further comprising enabling a soft post-package repair (sPPR) function prior to receiving the first data.5. The method of claim 1 , wherein remapping the logical address to the second physical address comprises performing soft post ...

TECHNIQUES FOR POWER MANAGEMENT USING LOOPBACK

Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state. 1. (canceled)2. A method , comprising:sending, from a memory device to a power management integrated circuit (PMIC) via a first loopback pin of the memory device, a first signal to activate one or more components of the PMIC; andsending, from the memory device to a transistor configured to selectively couple the memory device with the PMIC, a second signal to activate the transistor outside a testing phase of operation.3. The method of claim 2 , wherein the second signal is sent via a second loopback pin of the memory device.4. The method of claim 3 , wherein the first loopback pin and the second loopback pin are configured for use during a testing phase of operation.5. The method of claim 3 , further comprising:inducing a third signal on a conductive path coupled with the PMIC based at least in part on sending the first signal via the first loopback pin, the third signal for activating the one or more components of the PMIC.6. The method of claim 5 , further comprising:toggling the first signal sent via the first loopback pin between different voltage levels, wherein inducing the third signal on the conductive path is based at ...

APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory. 1. A method , comprising:receiving, at a memory module, a command initiated by a host device to operate the memory module in a mode that is based at least in part on a power failure event, wherein the mode of operation comprises communicating data from a synchronous dynamic random-access memory (SDRAM) of the memory module to a non-volatile memory (NVM) of the memory module for the power failure event;transferring the data from the SDRAM to the NVM via a control circuit of the memory module in response to the command; andprogramming a mode register of the memory module with information that indicates the mode of operation, wherein the programming is based at least in part on transferring the data from the SDRAM to the NVM.2. The method of claim 1 , further comprising avoiding command signaling from the host while in the mode of operation.3. The method of claim 1 , further comprising transferring the data from the NVM back to the SDRAM via the control circuit based at least in part on a reapplication of power to the memory module.4. The method of claim 1 , further comprising resuming another mode of operation based at least in part on a reapplication of power to the memory module.5. The method of claim 4 , wherein the other mode of operation comprises restoring the data from the NVM to the SDRAM via the control circuit based at least in part on the reapplication of power to the memory ...

MEMORY DEVICES WITH PROGRAMMABLE LATENCIES AND METHODS FOR OPERATING THE SAME

A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation. 1. A memory device comprising:a volatile memory array;operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device; anddelay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command, the one or more bits indicating a duration by which to delay the performance of the memory operation.2. The memory device of wherein the memory operation is one of a read operation claim 1 , a write operation claim 1 , an erase operation claim 1 , a terminate operation claim 1 , and a status operation.3. The memory device of wherein the duration is a number of clock cycles by which to delay the performance of the memory operation.4. The memory device of wherein the one or more bits include a single bit indicating that the duration is either 0 or a predetermined delay.5. The memory device of wherein the one or more bits include a plurality of bits indicating that the duration is one of at least two predetermined delays.6. The memory device of wherein the memory device is a memory die claim 1 , and wherein the operation circuitry and the delay circuitry are on the memory die.7. The memory device of wherein the memory device is a memory module claim 1 , wherein the memory array is in a memory die of the memory module claim 1 , and wherein the delay circuitry is off of the memory die.8. The memory device of wherein the memory device is one of a DIMM claim 1 , an RDIMM claim 1 , and an NVDIMM. ...

METHODS OF SYNCHRONIZING MEMORY OPERATIONS AND MEMORY SYSTEMS EMPLOYING THE SAME

A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference. 1. A memory system , comprising:a first memory device having a first latency corresponding to a first command;a second memory device having a second latency corresponding to a second command, wherein the second latency differs from the first latency by a latency difference; and send the first command to the first memory device at a first time, and', 'send the second command to the second memory device at a second time,, 'a host operably coupled to the first and second memory devices, and configured towherein the first time and the second time are separated by a delay corresponding to the latency difference.2. The memory system of claim 1 , wherein:in response to the first command, the first memory device performs a first operation at a third time, andin response to the second command, the second memory device performs a second operation at the third time.3. The memory system of claim 2 , wherein the third time differs from the first time by the first latency claim 2 , and from the second time by the second latency.4. The memory system of claim 1 , wherein the host is further configured to:poll the first and second memory devices to determine the first and second latencies.5. The memory system of claim 1 , wherein at least one of the first command and the second command is a termination command configured to place ...

Memory mapping for memory, memory modules, and non-volatile memory

Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

WORD LINE CHARACTERISTICS MONITORS FOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom. 1. An apparatus , comprising:a memory array;a word line driver coupled to a word line of the memory array; and activate the word line driver;', 'determining a delay between activating the word line driver and a voltage of the word line reaching a threshold; and', 'generating an alert signal based, at least in part, on determining that the delay exceeds a value., 'peripheral circuitry coupled with the memory array and the word line driver, the peripheral circuitry configured to2. The apparatus of claim 1 , wherein the peripheral circuitry is configured to activate the word line driver in response to:receiving an access command directed to the word line from a host device coupled with the apparatus;initiating a refresh operation directed to the word line; orinitiating an error checking and scrubbing (ECS) operation directed to the word line.3. The apparatus of claim 1 , further comprising:a reference component coupled with the peripheral circuitry, the reference component configured to determine the value.4. The apparatus of claim 3 , ...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion. 1. A method of operating a memory system , comprising:receiving a first command instructing a first portion of the memory system to perform a first communication with a memory host;transmitting, from the first portion of the memory system to a second portion of the memory system, a signal instructing the second portion to enter an on-die termination mode; andperforming, with the first portion, the first communication while the second portion is in the on-die termination mode.2. The method of claim 1 , wherein a voltage of the signal indicates an impedance level of the on-die termination mode.3. The method of claim 1 , wherein a duration of the signal indicates an impedance level of the on-die termination mode.4. The method of claim 1 , wherein the second portion exits the on-die termination mode after the first communication is completed.5. The method of claim 1 , wherein the transmitting of the signal occurs on a first on-die termination terminal of the first portion electrically connected to a second on-die termination terminal of the second portion.6. The method of claim 5 , wherein the first and second on-die termination terminal are input/output terminals.7. The method of claim 1 , wherein the first command includes a first indication on a first chip ...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode. 1. A method of operating a memory system , comprising:receiving a first command instructing a first memory device of the memory system to perform a first communication with a memory host and instructing a second memory device of the memory system to enter an on-die termination mode;performing, with the first memory device, the first communication while the second memory device is in the on-die termination mode based at least in part on the first command;receiving a second command instructing the first memory device to perform a second communication with the memory host; andperforming, with the first memory device, the second communication while the second memory device is in the on-die termination mode based at least in part on the first command.2. The method of claim 1 , further comprising:receiving a third command instructing the second memory device of the memory system to exit the on-die termination mode; andthe second memory device of the memory system exiting the on-die termination mode based at least in part on the third command.3. The method of claim 1 , ...

MEMORY MODULE MUTIPLE PORT BUFFER TECHNIQUES

The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate. 1. A dual in-line memory module (DIMM) comprising:a circuit board having an external interface;first memory devices mounted to the circuit board; a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate;', 'a second port coupled to data lines of a first plurality of the first memory devices; and', 'a third port coupled to data lines of a second plurality of the first memory devices; and, 'a first multiple-port buffer circuit mounted to the circuit board, the first multiple-port buffer circuit comprisingwherein the second and third ports are configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.2. The DIMM of claim 1 , wherein the memory devices include a first rank of memory and a second rank of memory.3. The DIMM of claim 2 , wherein the second port is configured to exchange data between the external interface and the first rank.4. The DIMM of claim 3 , wherein the second port is not configured to exchange data between the external interface and the second rank.5. The DIMM of claim ...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode. 1. A method of operating a memory system , comprising:receiving a first command instructing a memory device of the memory system to enter an on-die termination mode;in response to the first command, placing the memory device in the on-die termination mode;receiving a second command instructing the memory device to perform a data communication; and exiting the memory device from the on-die termination mode,', 'performing, with the memory device, the data communication, and', 'reverting the memory device to the on-die termination mode after performing the data communication., 'in response to the second command2. The method of claim 1 , wherein the first command includes a number of bursts or clock cycles for which the second memory device is to remain in or to continue reverting to the on-die termination mode.3. The method of claim 1 , wherein the memory device is configured to remain in or to continue reverting to the on-die termination mode until receiving a third command instructing the memory device to exit the on-die termination mode.4. The method of claim 1 , ...

INDIVIDUALLY ADDRESSING MEMORY DEVICES DISCONNECTED FROM A DATA BUS

Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided. 1. A memory module , comprising: at least one command contact, and', 'at least one data contact,, 'a plurality of memories, each of the plurality of memories including detect a condition in which the at least one command contact thereof is connected to a controller and the at least one data contact thereof is disconnected from the controller, and', 'perform an action based at least in part on detecting the condition., 'wherein at least one of the plurality of memories is configured to2. The memory module of claim 1 , wherein the action includes changing an on-die termination level.3. The memory module of claim 1 , wherein the action includes entering a mode in which signals received at the at least one command contact are ignored.4. The memory module of claim 1 , wherein the condition is a first condition and the action is a first action claim 1 , and wherein the at least one of the plurality of memories is configured to perform a second action based at least in part upon detecting a second condition in which the data contact is connected to the controller.5. The memory module of claim 1 , further comprising: a plurality of connector data contacts, each of the plurality of connector contacts coupled to a corresponding one of the at least one data contacts of one of the plurality of memories, and', 'a plurality of ...

Apparatuses and methods for configuring i/os of memory for hybrid memory modules

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Error correction in row hammer mitigation and target row refresh

Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

DUAL SPEED MEMORY

The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports. 1. An apparatus , comprising:a first number of memory devices coupled to a host via a first number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports; anda second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.2. The apparatus of claim 1 , wherein the first number of memory devices are configured to transfer data between the first number of memory device and the host while the second number of memory devices are configured to transfer data between the first number of memory device and the second number of memory devices.3. The ...

APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory. 1. A method , comprising:receiving, at a memory module from a host, a command to perform a save operation, wherein the save operation includes saving data of a volatile memory of the memory module to a non-volatile memory (NVM) of the memory module;in response to the command, programming, by the memory module, a mode register of the volatile memory with information that configures the volatile memory to enable transfer of the data from the volatile memory to the NVM.2. An apparatus , comprising:a volatile memory;a non-volatile memory (NVM);a control circuit coupled between the NVM and the volatile memory and configured facilitate a save operation to cause transfer of data from the volatile memory to the NVM in response to a command to perform the save operation; anda mode register coupled with the SDRAM and programmable, by the control circuit, with information that configures the volatile memory to enable transfer of the data to the NVM. This application is a continuation of U.S. patent application Ser. No. 15/841,126 filed on Dec. 13, 2017, which is a continuation of U.S. patent application Ser. No. 15/470,698 filed on Mar. 27, 2017 and issued as U.S. Pat. No. 10,423,363 on Sep. 24, 2019, which is a continuation of U.S. patent application Ser. No. 13/965,008, filed on Aug. 12, 2013 and issued as U.S. Pat. No. 9,921,980 on Mar. 20, 2018. These applications and patents are incorporated ...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion. 1. A method of operating a memory system , comprising:receiving, at a first portion of a memory system, a first command instructing the first portion of the memory system to perform a first communication with a memory host;transmitting, from the first portion of the memory system to a second portion of the memory system, a signal instructing the second portion to enter an on-die termination mode, wherein the signal bypasses a command decoder of the second portion of the memory system; andentering, based at least in part on the signal, the on-die termination mode with the second portion.2. The method of claim 1 , wherein a voltage of the signal indicates an impedance level of the on-die termination mode.3. The method of claim 1 , wherein a duration of the signal indicates an impedance level of the on-die termination mode.4. The method of claim 1 , wherein the second portion exits the on-die termination mode after the first communication is performed.5. The method of claim 1 , wherein the transmitting of the signal occurs on a first on-die termination terminal of the first portion electrically connected to a second on-die termination terminal of the second portion.6. The method of claim 5 , wherein the first and second on-die termination terminal are input/ ...

MEMORY DEVICES CONFIGURED TO PROVIDE EXTERNAL REGULATED VOLTAGES

Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices. 1. A memory system , comprising:a power supply configured to provide a supply voltage to a memory device; one or more external inputs configured to receive the supply voltage;', 'a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage;', 'one or more memories configured to receive the output voltage from the voltage regulator; and', 'one or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices; and, 'the memory device includingthe one or more connected devices, wherein the one or more connected devices are configured to receive the output voltage from the one or more external outputs and do not receive the supply voltage from the power supply.2. The memory system of claim 1 ,wherein the output voltage comprises a first output voltage and a second output voltage,wherein the one or more memories are configured to receive the second output voltage from the voltage ...

INDIVIDUALLY ADDRESSING MEMORY DEVICES DISCONNECTED FROM A DATA BUS

Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided. 1. A memory module , comprising: at least one command contact, and', 'at least one data contact,, 'a plurality of memories, each of the plurality of memories including detect a condition in which the at least one command contact thereof is connected to a controller and the at least one data contact thereof is disconnected from the controller, and', 'enter, based at least in part on detecting the condition, a reduced-power mode., 'wherein at least one of the plurality of memories is configured to2. The memory module of claim 1 , further comprising: a plurality of connector data contacts, each of the plurality of connector contacts coupled to a corresponding one of the at least one data contacts of one of the plurality of memories, and', 'a plurality of connector command contacts, each of the plurality of connector command contacts coupled to a corresponding one or more of the at least one command contacts of the plurality of memories., 'a connector including3. The memory module of claim 1 , wherein the at least one command contact of each of the plurality of memories is coupled to a common command/address bus.4. The memory module of claim 1 , wherein the at least one of the plurality of memories is configured to detect the condition by detecting a command signal at the at least one command contact and determining ...

Methods for error count reporting with scaled error count information, and memory devices employing the same

An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

Memory devices configured to provide external regulated voltages

Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

MEMORY DEVICES CONFIGURED TO PROVIDE EXTERNAL REGULATED VOLTAGES

Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices. 1. A memory system , comprising:a power supply configured to provide a supply voltage having a first voltage level to a memory device; one or more external inputs configured to receive the supply voltage;', 'a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level;', 'one or more memories configured to receive the output voltage from the voltage regulator; and', 'one or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices; and, 'the memory device includingthe one or more connected devices.2. The memory system of claim 1 ,wherein the supply voltage comprises a first supply voltage and a second supply voltage,wherein the one or more external inputs are a first one or more external inputs,further comprising a second one or more external inputs configured to receive the second supply voltage having a ...

MEMORY DEVICES CONFIGURED TO PROVIDE EXTERNAL REGULATED VOLTAGES

Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices. 1. A memory device , comprising:one or more external inputs configured to receive a supply voltage having a first voltage level;a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level;one or more memories configured to receive the output voltage from the voltage regulator; andone or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices.2. The memory device of claim 1 ,wherein the supply voltage is a first supply voltage,wherein the one or more external inputs are a first one or more external inputs,further comprising a second one or more external inputs configured to receive a second supply voltage having a third voltage level different from the first voltage level, andwherein the voltage regulator is further configured to receive the second supply voltage from the second one or more external ...

Power management in memory

The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

DUAL SPEED MEMORY

The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.

Background operations in memory

The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device.

Memory mapping for memory, memory modules, and non-volatile memory

Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

Command bus in memory

The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

INDIVIDUALLY ADDRESSING MEMORY DEVICES DISCONNECTED FROM A DATA BUS

Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided. 1. A memory system , comprising:a controller; and at least one command contact, and', 'at least one data contact,', detect a condition in which the at least one command contact thereof is connected to the controller and the at least one data contact thereof is disconnected from the controller', 'enter, based at least in part on detecting the condition, a reduced-power mode., 'wherein at least one of the plurality of memories is configured to], 'at least one memory module coupled to the controller, the at least one memory module including a plurality of memories, each of the plurality of memories including2. The memory system of claim 1 , wherein the controller includes a plurality of controller data contacts insufficient in number to be uniquely coupled to the at least one data contact of each of the plurality of memories of the at least one memory module.3. The memory system of claim 1 , wherein the at least one memory module further includes: a plurality of connector data contacts, each of the plurality of connector contacts coupled to a corresponding one of the at least one data contacts of one of the plurality of memories, and', 'a plurality of connector command contacts, each of the plurality of connector command contacts coupled to a corresponding one or more of the at least one command contacts of the ...

METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register. 1. A memory device , comprising:a memory;a mode register; and perform the refresh operation at the memory, and', 'perform a read of the mode register., 'circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to2. The memory device of claim 1 , wherein the read of the mode register includes outputting data from the mode register from the memory device.3. The memory device of claim 2 , wherein the outputted data includes information corresponding to a temperature of the memory.4. The memory device of claim 2 , wherein the outputted data includes information corresponding to a refresh rate of the memory.5. The memory device of claim 1 , wherein the command has a duration on a command/address bus of the memory device of a single clock cycle of the memory device.6. The memory device of claim 1 , wherein the command includes a flag bit indicating that the read of the mode register is to be performed.7. A method of operating a memory system claim 1 , comprising:receiving a command instructing a portion of the memory system to perform a first operation; ...

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register. 1. A memory device , comprising:a first memory portion;a second memory portion;a mode register; and perform the refresh operation at the first memory portion,', 'perform a read of the mode register, and', 'provide on-die termination at the second memory portion during at least a portion of the read of the mode register,, 'circuitry configured, in response to receiving a command to perform a refresh operation at the first memory portion, towherein the command includes one or more flag bits (i) indicating to the first portion of the memory device that the read of the mode register is to be performed, (ii) indicating to the second portion of the memory device that the on-die termination is to be provided, or (iii) both.2. The memory device of claim 1 , wherein the read of the mode register includes outputting data from the mode register from the memory device.3. The memory device of claim 2 , wherein the outputted data includes information corresponding to a temperature of the first memory portion.4. The memory device of claim 2 , wherein the outputted data includes information corresponding to a ...

METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register. 1. A memory device , comprising:a first memory portion;a second memory portion;a mode register; and perform the refresh operation at the first memory portion,', 'perform a read of the mode register, and', 'provide on-die termination at the second memory portion during at least a portion of the read of the mode register., 'circuitry configured, in response to receiving a command to perform a refresh operation at the first memory portion, to2. The memory device of claim 1 , wherein the read of the mode register includes outputting data from the mode register from the memory device.3. The memory device of claim 2 , wherein the outputted data includes information corresponding to a temperature of the first memory portion.4. The memory device of claim 2 , wherein the outputted data includes information corresponding to a refresh rate of the first memory portion.5. The memory device of claim 1 , wherein the command has a duration on a command/address bus of the memory device of a single clock cycle of the memory device.6. The memory device of claim 1 , wherein the mode register corresponds to the ...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode. 1. A method of operating a memory system , comprising:receiving a first command instructing a memory device of the memory system to enter an on-die termination mode;in response to the first command, placing the memory device in the on-die termination mode; andmaintaining the memory device in the on-die termination mode for longer than a duration of a communication of the memory system.2. The method of claim 1 , wherein the first command includes a number of bursts or clock cycles for which the second memory device is to remain in the on-die termination mode.3. The method of claim 1 , wherein maintaining the memory device in the on-die termination mode for longer than a duration of a communication of the memory system comprises maintaining the memory device in the on-die termination mode until receiving a second command instructing the memory device to exit the on-die termination mode.4. The method of claim 1 , further comprising:receiving a second command instructing the memory device to exit the on-die termination mode; andin response to the second command, exiting ...

INDIVIDUALLY ADDRESSING MEMORY DEVICES DISCONNECTED FROM A DATA BUS

Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided. 1. A memory module , comprising:a plurality of memories, each of the plurality of memories including at least one data contact, detect a condition in which the at least one data contact thereof is disconnected from a controller, and', 'perform an action based at least in part on detecting the condition., 'wherein at least one of the plurality of memories is configured to2. The memory module of claim 1 , wherein the action includes changing an on-die termination level.3. The memory module of claim 1 , wherein the action includes entering a mode in which signals received from the controller are ignored.4. The memory module of claim 1 , wherein the condition is a first condition and the action is a first action claim 1 , and wherein the at least one of the plurality of memories is configured to perform a second action based at least in part upon detecting a second condition in which the data contact is connected to the controller.5. The memory module of claim 1 , further comprising: 'a plurality of connector data contacts, each of the plurality of connector contacts coupled to a corresponding one of the at least one data contacts of one of the plurality of memories.', 'a connector having6. The memory module of claim 5 , wherein the connector is a DIMM connector.7. The memory module of claim 1 , wherein each of the ...

Apparatuses, systems, and methods for identifying multi-bit errors

Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Methods for on-die memory termination and memory devices and systems employing the same

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

Refresh operation in multi-die memory

Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

Word line characteristics monitors for memory devices and associated methods and systems

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom.

Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Memory devices with multiple pseudo-channels

A memory module is provided, comprising a connector and a plurality of memory devices. Each memory device includes a memory array and a plurality of data connections, wherein a first subset of the plurality of data connections are configured to communicate data with a first portion of the memory array, and a second subset of the plurality of data connections are configured to communicate data with a second portion of the memory array. The first subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to first external contacts of the connector in a first addressable pseudo-channel, and the second subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to second external contacts of the connector in a second addressable pseudo-channel.

Apparatuses and systems having ball grid arrays and associated microelectronic devices and device packages

Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

Memory module mutiple port buffer techniques

Techniques for power management using loopback

Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.

Memory mapping for memory, memory modules, and non-volatile memory

Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

Memory devices configured to provide external regulated voltages

Error correction in row hammer mitigation and target row refresh

Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

Error correction in row hammer mitigation and target row refresh

Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

Power management in memory

The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

Command bus in memory

The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

Background operations in memory

The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device.

Memory mapping for memory, memory modules, and non-volatile memory

Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

Write command timing enhancement

Methods, systems, and devices for write command timing enhancement are described. A host device may transmit (e.g., issue), to a memory device, an activation command and an associated write command according to a delay that is different (e.g., shorter) than a row access to column access delay associated with read commands. In some examples, the delay between the activation command and the associated write command may be a function of the row access to column access delay associated with read commands and one or more additional parameters, such as a timing constraint or a speed parameter of the memory device.

Memory mapping for memory, memory modules, and non-volatile memory

Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

Memory mapping for memory, memory modules, and non-volatile memory

Methods of synchronizing memory operations and memory systems employing the same

A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

Methods for error count reporting with scaled error count information, and memory devices employing the same

An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

Methods for error count reporting with scaled error count information, and memory devices employing the same

An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

Methods for error count reporting with scaled error count information, and memory devices employing the same

An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

Methods for on-die memory termination and memory devices and systems employing the same

Methods for triggering oscilloscopes and oscilloscopes employing the same

A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.

Error correction in row hammer mitigation and target row refresh

Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

Refresh operation in multi-die memory

Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

Indicating a blocked repair operation

Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.

Memory mapping for memory, memory modules, and non-volatile memory

Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

Indicating a blocked repair operation

Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.

APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

Memory mapping for memory, memory modules, and non-volatile memory

Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

Refresh operation in multi-die memory