FAST ERASABLE PROGRAMMABLE COMPONENT LOGICAL

The present invention relates to the field of programmable logic modules, and more particularly relates to the improvement of the performances of EPROM networks.

The preparation and use of erasable programmable read-only memories or EPROMs ( Erasable Programmable Read-Only Memories) is well-known technique. Recently, combined with the components EPROM programmable logic arrays are generally known to provide components in the terminology of "programmable logic components" or PLDs (Logical Programmable Devices ). In many cases, the components are also erasable programmable logic, and are then referred to as "erasable programmable logic components" or EPLDs ( Erasable Logical Programmable Devices ).

Typically, for each component, a memory element is configured as an array, each input of the programmable logic component being split into an inverting input and a non-inverting input, and each input forming a pair of row lines of the matrix of the memory array. The row lines are conventionally called "word lines". The memory cells of each column are connected to each other by column lines, which are generally referred to as "bit lines". The array's bit lines are used to form the output of the memory array. These outputs bit lines thus are NOR gates, but referred to, by Boolean transformation, in the form of terms of a product of n terms. These outputs are then subjected to a logical OR to give a sum of the products. It is known well, in the prior art, the technique of using a memory array with entries on the various row lines, and the technique of performing the sum of the product outlets from the columns of the array. The US-A 609,98 6-4 and the US-A 617,47 9-4, both the names of Hartmann et al ., and the US-A -4 124,899 names and Birkner al ., are examples.

Though it is known, in the prior art, very various programmable logic components, they all require a connection to the input lines to access the EPROM cell. Typically, the input lines are connected to the control gate of a floating gate EPROM cell, the output of the cell of the programmed state or not programmed (erased) of the EPROM cell of the floating gate, as well as the state of the input signal, in the case of the erased state. The the signal path from the inlet to the outlet the memory array, noticeable that the EPROM cell is in the signal path. In other words, the input signal must access the EPROM can be obtained before an output signal the programmable logical component. The presence of the EPROM cell in the signal path restricts the performance of the programmable logic component, in particular the speed and consumption. This is that should be accessed to a given EPROM cell before it can obtain an output signal and that it is possible to access the EPROM cell in question that after showing the input signal to the control gate. It will be appreciated therefore that the performance can be improved if of a programmable logic device which may be removed from the signal path of the component the memory cell.

A original architecture for improving the performance of a programmable logic device by removing from the signal path the memory cell. In one embodiment, the input signals are applied to a combination of adapters and level of buffers to obtain a buffered signal and its complement. The memory cells of the array are connected to the corresponding buffer such that the condition of each memory cell controls the activation of its suitable buffer. Because only can read the memory cells prior to the arrival of an input signal, there is a need for a less duration to produce an output signal by the programmable logic component in response to the input signals.

In another embodiment, a multiplexer is mounted so that they receive the pair of signals from the buffers. Again, the memory cell is removed from the path of the signal and is used the state of a memory cell to control its respective multiplexer to effect the selection between the input signal and its complement.

In a separate embodiment, the outputs of the memory cells are applied to a shift register to lock in the register the state of the memory cell. Once the information is locked, the memory cells may be disabled to conserve power. Then the locked information is used to activate the buffers to operate the multiplexer of the embodiment previously described. Can be mounted in series a plurality of shift registers, signals external of programming that can be applied to the shift registers for actuating the pads or the multiplexers. By using a external programming via the shift registers, can be allow the programmable logic modules emulate the state of programmed cells effectively without programming the memory cells.

Finally, use is made of a distributed configuration of buffers to directly placing the components forming the pad to the location memory cells instead of the input of the memory array.

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One will now describe in detail the present invention, with reference to the accompanying drawings.

Figure 1 is a simplified block scheme illustrating the essential elements of a programmable logic device. Figure 2 is a block diagram of the prior art, showing the elements of a memory array in which the memory cells are present in the path of the signal.

Figure 3 is a block diagram equivalent to that of Figure 2, for two inputs of the memory array.

Figure 4 is a block diagram showing an architecture of the present invention, wherein the memory cells are removed from the signal path.

Figure 5 is a block diagram of a other embodiment of the present invention, wherein the memory cel- Iules are removed from the signal path and wherein the memory cells are used to control a multiplexer in the signal path.

Figure 6 is a block diagram corresponding to the configuration of Figure 4, but by use of shift registers to lock conditions stored in the memory cells.

Figure 7 is a block diagram corresponding to the configuration of Figure 5, but in which shift registers are used to lock conditions stored in the memory cells.

Figure 8 is a block diagram illustrating a way to perform a lock operable in the architecture of Figure 7.

Figure 9 is a block diagram illustrating a way to perform, on one of the inputs of the memory array, a buffer stage non-distributed.

Figure 10 is a block diagram illustrating a distributed buffer design of the present invention.

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One will describe an original architecture for improving the performance of a programmable logic device by removing the memory cell of the signal path. In the description that will follow, is will give many details such as memory cells particular, particular circuit components, etc to allow a complete understanding of the present invention. Of course, the person skilled in the art will understand that the present invention may be practiced without these particular details. Conversely, well known circuits have not been described in detail to not unnecessarily aloudir the description of the present invention.

Figure 1 represents a block scheme illustrating the essential elements of a programmable logic device. A plurality of input lines, designated Io-In, are connected to a memory array 10 input thereto. The memory array 10 is formed of a plurality of memory cells configured in a matrix array such that each of the entries Io-In gives a signal on the lines of the rows of the matrix. The outputs of the memory cells are connected to appropriate column lines, and these column lines are connected to sense amplifiers 11. The sense amplifiers 11 detect the signal column output and deliver an output signal corresponding to the state of the column lines. Can be used in various ways the output signal of the sense amplifier 11. Typical In a programmable logic component, the output signals of the sense amplifiers 11 are applied to macro cells 12. Typically, each macro-cell 12 responds to a predetermined number of product terms (terms P) that are normally jointly subjected to a logical OR to give a sum of product terms. The outputs of the macro cells 12 is then linked to the outside of the programmable logic component, or are fed back to the memory array 11 to provide inputs of feedback the memory array 10. Although the need that shown in Figure 1 four macro cells 12, their real number is only a choice of execution, and depends on the size of the memory array 10 and terms P of the array of the memory array 10. Operation sense amplifiers 11 and macro cells 12 is well known to the prior art.

In the 2 shown, is represented a portion of a prior art circuit 20, typically incorporated to the memory array 10 and formed of a plurality of memory cells 27. In this circuit 20 of the prior art, each entry Io-In is input to a level 21. The level adapter 21 illustrated in figure 2 is also an inverter. The output of the level adapter 21 is applied to one of the inputs of an inverting buffer 22 and a non-inverting buffer 23. The output of each of the buffers 22 and 23 is connected to the line of respective row of the memory array to have, for each entry, a pair of row lines. For example, for inputting Io, the corresponding output of the buffer 22 is on the row line 0 of the memory array and the output of the buffer 23 on the row 0 / (is preferred herein symbolism "/" to designate a supplement). Normally, the row lines are connected to the control gate of the EPROM cells of that row. Furthermore, most memory arrays will have a distinct row line assigned to the complement of the input signal, which has been shown in the species by the row lines connected to the output of the buffer 23.

On Figures 2, there is represented that the first two stages and the last, the first stage has been represented with an A input and the second input II corresponding to the input B. Furthermore, the circuit 20 of Figure 2 only shows the memory cells 24 of the column 0. The outputs of the memory cells 24 of the column 0 are all connected together to the line 26, which is generally called "bit lines". It should be noted that the connecting together all the memory cells 24 of the column 0 is application of a Boolean function AND of all inputs, and the complement inputs. In the example of Figure 2, the EPROM cell 30 designates the position (row 0, column 0), while the EPROM cell 31 designates the position (row 0 /, column 0). The cell 32 designates the position (row 1, column 0) and the cell 32 designates the position (row 1 /, column 0). It has illustrated in figure 3 a CMOS circuit equivalent showing the column of the memory cells for inputs A and B.

In operation, each of the cells forming the EPROM 27 cell column 24 is, during the programming phase of the component, is left programmed or erased. 27 If a given cell is in the erased state or not programmed, the conduction or non-conduction of the cell 27 will depend on the state of the input signal applied to its control gate. However, whether a cell EPROM 27 is given to the programmed state, the cell will not lead 27. Therefore, only cells that are erased will respond to an input signal applied to its control gate. Operation EPROM 27 is well known prior art.

Notably, the circuit 20 of the prior art provides some output value on the bit line 26, this output dependent on the state of the input signals and the stored state of each of the EPROM cells connected to the bit line 26 given. Most that also a given EPROM cell 27 is in the effective path of the signal of the memory array. For example, when considering the part of the circuit corresponding to the input 20 Io, the EPROM cells 30 and 31 are present in the path of the effective signal. In other words, when the enable signal on the input line A Io, the signal A is applied to the control gate cells 30 and 31 before it can only obtain on the bit line 26 a signal output of the cells 30 and/or 31. If the cells 30 and/or 31 must change state conduction due to the input signal, the transistor of the cell is to change state, for example from the off-state to the conducting state, before that memory cell can deliver a suitable output signal. A duration non-negligible is required so that a transistor from the conductive state to the non-conductive state, or vice versa. The transition period can increase significantly if the voltage swing of the bit line 26 may be passed from one high voltage to ground potential. In other words, a transition period between 5 V and ground potential takes less time than a transition between 15 V and ground potential. Furthermore, if a number of cells of a given column are simultaneously conductive, a call large current may occur * on the bit line 2,6, extending the period of time before which the sense amplifier will restore its stationary state.

In order to reduce the response time of a memory cell 27 and, thus, improve the speed of assembly the programmable logical component, prior art circuits, such as circuit 20, have used a current driver circuit for driving the bit line 26. On Figure 2, is represented a current driver circuit 29, mounted between the power supply, Vcc referenced and the bit line 26. The current source 29, which is typically a transistor device, remains active to provide a flow of stationary state during d^f a high speed operation mode of the component. In a situation of stationary state, the bit line 26 is biased at a predetermined bias point. When conduction of the memory cell occurs, the sense amplifier connected to the bit line 26 detects a change from the bias point is in the form of a state change on the bit line 26. This technique has however a major drawback. Though it is to operate at higher speed, the programmable logic component needs a significantly higher current due to the continuous operation of the current source 29. This increase current generally necessary increased power consumption, and a energy loss also increased.

On Figure 4, is represented a layout according to the present invention, wherein the cells EPROM 27a have been removed from the signal path. The cells EPROM 30a, 31a, 32a and 33a are equivalent to the cells EPROM 30 TO 33, with the addition of suffix, of Figures 2 and 3. However, in the circuit of Figure 4 the control gate of each of the cells EPROM is connected TO a voltage, for example 5 V, which causes the conduction of the cell if the cell is erased. The outputs of the various cells 27a are not connected to the bit line, but to an adapter/respective buffer level 37 or 38 (herein referred to as simply "buffer") to activate the respective buffer 37 or 38. Each of the entries Io to In (only Io and II having been shown in Figure 4) is connected to an adapter/inverting buffer level 37, each of the latter being also connected to a level adapter non-inverting/buffer 38. It should be noted that the buffers 37 and 38 may be formed of separate components, on the one hand for the adapters and level on the other hand for the pads. The outputs of the buffers 37 and 38 are connected to the bit line 26a, as well as the outputs of other buffer 37 and 38 of the same column. In the circuit of Figure 4, the outputs of each pair are connected together and then connected in input of a NAND gate, which performs the function AND on all terms which are applied to it as input. On Figure 4, the two inputs Io Ii are combined and output from a door AND 35 to provide a product term for determining the operator and logic for A B. Each of the EPROM cells 27a is connected to its respective buffer 37 or 38 order to activate this, only if the cell is erased. For example, in Figure 4, the buffer 41 is activated by the state of the cell 30a and the buffer 42 is activated by the state of the cell 31a. If A corresponds to an entry Io, A/will appear in output if the buffer 41 is activated due to the erased state of the cell 30a, and A will appear in output if the buffer 42 is activated due to the erased state of the cell 3la. If the two memory cells 30a and 31a are programmed, the input signal will then be without effect on the output. If, for some reason, the cells 30a and 31a are both in the erased state, the output line buffers 41 and 42 will be pulled high due to the conduction of the two transistors P-type series 39a and 39b, whose respective gates are connected to the cells 30a and 31a. Each pair of memory cells is equivalent for each of the entries. The use of the door AND 35 selects a predetermined number of input that must be applying the operator AND.

Notably, , in Figure 4, there is represented that the EPROM cell and 27a that, to simplify, is not represented its load transistor. However, it will be understood that the EPROM cell of Figure 4, those of the following figures, requires a load transistor to operate properly. Examples of such loads are the component 29 of Figure 3 or the component 61 of Figure 8.

It will be appreciated that the architecture of the present invention to remove cells EPROM memory 27a of the signal path in the component. In other words, each of the EPROM cells 27a controls the activation of its respective buffer 37 or 38. 27a Since the EPROM cells are removed from the signal path, EPROMs, can provide each of the activating or deactivating its respective buffer 37 or 38 before an input signal is applied to the input terminal of the memory array. Therefore, once an input signal is applied to one of the input lines Io to In, this signal will simply need to be applied through the respective buffer to obtain the appropriate output on the bit line 26a. Improved performance in terms of speed, by can access the EPROM cells 27a before the input signal is present.

On Figure 5, is represented a circuit 40 which is an alternative implementation of the present invention. Each input is applied to the buffers 37 and 38, as was the case with the circuit of Figure 4. Although the need represented in Figure 5 that two inputs Io and II, the actual number of entries is a single choice execution. Each combination of buffers 37 and 38 outputs a non-inverted and inverted version of the input signal. The outputs of the buffers 37 and 38 which are connected together, as was the case in the circuit of Figure 4. Instead, each combined output of each set of buffers 37 and 38 is applied in input of a multiplexer 43. The selection of the input of the multiplexer 43 which is to be applied in output is determined by the stored state of a cell EPROM 27b connected to the corresponding multiplexer 43. For example, for inputting Io, if the cell is in the programmed state 4,7 it will cause selection by the multiplexer of one of the inputs A or A/and, if the cell 47 is in the erased state, it will select the other input A/or A, respectively.

Most that, in the circuit 40, for a given row/column position in the case of using a single cell EPROM 27 for controlling the operation of the multiplexer 43. The output of the multiplexer 43 is connected on the input side to the respective AND gate 44 whose output supplies the product term to a sense amplifier. It should be noted that the number of inputs connected to a given AND gate 44 determines the-number of product terms, and that execution of a single choice. It should be noted that the circuit 40 has one additional component in the path of the multiplexer 43 in the signal path, but, on the contrary, the actual number of EPROM cells has been reduced by half, since it requires only a single EPROM cell to control each multiplexer 43 in order to perform the selection between an input and its complement. Most also that the EPROM cell 27b has, is again, been removed from the path of the signal to make it possible to improve the performance speed of the programmable logic component.

The Figure 6 one embodiment as an alternative of the circuit of Figure 4. Again, there is shown in A B and that two inputs, the actual number of the latter being a single choice execution. The circuit 45 of Figure 6 at each of its inputs connected to buffers 37 and 38 having outlets leading respectively of the inverted and non-inverted versions of the input signal. These outputs are connected together to the input of a NAND gate 49. The output AND gates 49 is input of an OR gate 48 whose output gives the sum of the product terms. A number of gate output signals AND equivalents are input to the OR gate 48. The actual configuration of product terms is, is again, arbitrary, and the configuration of the door AND shown figure 6 has been given only for illustration. It should be noted that other logic gates may, by Boolean transformations, perform functions equivalent logic.

The alternate configuration of the circuit 45 uses a shift register combined with the EPROM cell 27a to activate each of the buffers 37 or 38. Instead of connecting each cell EPROM 27a directly to the buffer 37 or 38, as was the case of the circuit of Figure 4, the output of each cell EPROM 27a is connected to a shift register 49. In other words, the cell 30a is mounted so as to apply an input signal to the shift register 5% the cell 31a to the shift register 51, the cell 32a to the shift register 52 and the cell 33a to the shift register 53. The output of each shift register 49 is connected to its corresponding buffer 37 or 38. For example, the shift register 50 is connected to the pad 41 and the register 51, the buffer 42. Furthermore, the shift registers corresponding to a column of given EPROM cells are all mounted together in series, such that the output of the shift register 50 is not only connected to the buffer 41, but also connected to the input to the shift register 51. The, output of the shift register 51 is connected to the buffer 42 and 52 corresponding to the shift register of the next buffer of the column, andc. The whole first register 50, which corresponds to the first memory cell 30a of the column, receives an external signal input, and the latest shift register in the set corresponding to the last memory cell of the column provides an output signal for external use. Is provided for each column of memory cells a series of shift registers 49.

In operation, is used the shift registers 49 for locking the output of the EPROM cells 27a on their respective pads 37 or 38 before the input signal is presented. The memorized state of each cell EPROM 27a is determined by causing latching the output of each memory cell 27a in its corresponding shift register 49. When the shift register 49 has locked the exit of its corresponding 27a memory cell, the reading of each memory cell is then completed and the read operation may terminate. In other words, after the information is locked in the shift registers 49, the memory cells 27a does not need to be conductive, and can be off all the cells. This service memory cells 27a can save energy, because no cells EPROM 27a need be conductive after the information has been locked. The information latched is output from each of the shift registers 49 to the corresponding buffer 37 or 38. Here, can be applied as input the input signals. Notably, the memory cells 27a, is again, are not in the signal path.

If the only thing needed with the shift registers 49 is the locking, can be replaced the shift register 49 by bolts. However, in this alternative embodiment is used the shift registers 49 for other purposes. It should be noted that, to certain purposes, for example for testing, evaluation and debug, it is advantageous to quickly change the sequence of programming of the programmable logic component. For example, in a programmable logic device using EPROM cells, should be programming a particular programming configuration in the various EPROM cells for performing an evaluation of the performance of the device. By were to alter the configuration of programming, the cells should then be erased and reprogrammed. Ultraviolet erasable In an EPROM, must be, typically, a time interval d ' üne time for erasing and reprogramming a new configuration. Even from using the components "flash EPROM" most recent, it is still good for erasing and reprogramming a second configuration. 45 With the circuit of the present invention, can be reduced the duration of the sequence of reprogramming, up to a duration of the order of 10^-5 by second configuration. To time interval between shortest possible configurations, the registers is used TO offset 49. Instead reprogramme cells 27a, is supplied as input, from the outside, the desired programming configurations. Information is transferred in series with offset in the sequence of registers 49 to emulate the output of the memory cells. Instead reprogram the memory cells 27a, latching the information in each shift register. When this locking is completed, the circuit 45 will respond to an input signal in the same manner as if the memory cells 27a had been programmed. The speed result from the registers TO offset operate at a rate much higher than that of the erasure and scheduling, EPROM cells.

Furthermore, the configuration of the EPROM cells 27a and shift registers 49 of the circuit 45 is also capable of shifting the locked information TO from a given memory cell and then applied to the buffers corresponding to the column members of a different row. Beneficially that there are provided for each column of memory cells a sequence of registers TO offset 49 connected in series. Furthermore, the output of the very last shift register for the series of registers is provide an output signal to the exterior of the component, output signal indicative of a sequence of data corresponding to the information stored in the EPROM cells 27a.

On Figure 7/is represented in shift registers of the circuit 40 of Figure 5. The adapters level/plugs 37 and 38, the multiplexers 43 and the door AND 44 operate in a similar fashion to that of the same circuit elements 40 illustrated in figure 5. However, in the circuit 55, instead of directly connecting the multiplexers 43 to the EPROM cells 27b, the outputs of the EPROM cells 27b are locked through shift registers 4 9b. The EPROM cells 27b and the shift registers operate 49b equivalent to those of like members of Figure 6. However, in the case of Figure 7, in the case of using a single EPROM cell for controlling the multiplexer 43, as was possible in the circuit 40. The output of the EPROM cell 27b is locked in its corresponding shift register 49b, which selects one of the two inputs of each of the multiplexers 43 to be connected to the output thereof. Can be applied to the shift registers external input signals, in the same way as in the case of circuit 45 of Figure 6. The external inputs of the shift registers 49b permit programming sequence more rapidly without the need to remember the scheduling information in the various cells 27b EPROM. Furthermore, the door AND 44 has been represented with four inputs although the actual number of entries forming a product term is a single choice execution.

With reference to Figure 8, it takes one embodiment represented in CMOS circuits 45 of the circuit of Figure 6. The circuit 60 only shows the components that conform to a single given signal path, in other words A in the example. A P-type transistor 61 is connected in series with an EPROM memory cell 27b between Vcc and Vss, which is in this case the ground potential. The transistor 61 and the memory cell 27b operate in the manner of a pair of CMOS transistor block. 02 A timing signal is applied to the gate of the transistor 61 and the load input of the bistable 62. The output of the memory cell 27b, which is taken to the drain of the memory cell 27b, is applied to the input of a lever type Dl D Loadable 62. The latch 62 operates in the manner of a springloaded bolt 02, Ds but with its input connected to the output of the preceding stage, and its output connected to the input Ds of the next stage, which allows the bolt element D 62 operate in the manner of a shift register. 01 A second timing signal is applied to the clock input of the flip-flop type D 62.

The transistors 63-66 function as a multiplexer 43, the transistors 63 and 65 being components n-type and the transistors 64 and 66 being components such as P. The transistors 63 and 64 are conductive together to accommodate passage the signal A while, alternately, the transistors 65 and 66 guide order to be able to let the signal pass A/to the outlet. The non-inverting output of the register 62 is connected to the gates of the transistors 63 and 66. The inverting output of the register 62 is connected to the gates of the transistors 64 and 65. Therefore, in operation, if the non-inverting output Q is at high level, the transistors 63 and 64 are conductive, while the transistors 65 and 66 which are conductive in the other state.

In operation, when the timing signal 02 goes low, is uses the information stored in the memory cell 27b. The memory cell 27b will conduct whether it is in the erased state, it will not be conductive and if programmed. Once the output of the memory cell 27b is stabilized, the timing signal 02 causes the locking of this information in the register 62. Once the information is locked in the register 62, the clock signal 02 need not remain high to continue reading information stored in the memory cell 27b. Information locked in the register 62 causes the conduction of one of the CMOS transistor pairs 63, 64 or 65, 66, producing the transmission is either the signal of the signal A A /.

On Figure 9, is represented a memory array 10a equivalent to the memory array 10 of Figure 1, with a plurality of memory cells configured 27c columns 71. With a principle architecture of the prior art, for example as that of the circuit 20 of Figure 2, just a single adapter assembly buffer level 21 and 22 and 23 for each line as input Io. The outputs of the buffers 22 and 23 are then applied to their respective row lines 72 and 73, these row lines are connected to the corresponding row of cells. Although this configuration of the prior art can be readily performed with the circuitry of the present invention, it is preferable to use a variant of the architecture, shown Figure 10.

On Figure 10, is represented a memory array 10b having a plurality of memory cells configured 27d columns 71a. The Io an input line, the input being connected to the corresponding row of memory cells of each column 71a 27d. However, in the alternative, the pads 37 and 38 are distributed between the various memory cell areas 74 so that, instead of having, as illustrated in figure 9, a pair of line buffers for a complete row, in the architecture of Figure 10 are buffers 37 and 38 to each memory location 74, as suggested by the dotted line 75. The distribution principle of Figure 10 requires only a single row line 76, instead of the double line 72 and 73 of Figure 9. This distribution has the additional advantage of reducing the number of row lines and allow for different configurations for each buffer memory location 74. Most that, although in the preferred embodiment are the buffers 37 and 38, and optionally the multiplexers 43 and the shift registers 49, which are distributed, could be easily apply the principle of double line 72 and 73 of the prior art to implement the present invention.

It should be noted that, although a programmable logic device has described particular using the architecture of the present invention wherein the EPROM cell is removed from the signal path, this configuration can be realized easily in other components, and that is it is not limited to a programmable logic device. Furthermore, could be conveniently be used, for the memory cells that has been described, other components of memory as EPROMs. Furthermore, the EPROM cells illustrated figure 4 to 7 require a load transistor for proper operation, but it has not been represented for not to complicate the drawing. These components of cell load EPROM are well known. One embodiment in CMOS has been shown in the form of a transistor 61 of Figure 8. In this regard, for a CMOS implementation in the case of Figures 4 and 7, is connected-type transistor P between Vcc and the output of each of the memory cells to act filler component. Finally, the configuration illustrated by the transistors 39a and 39b of Figure 4 may be easily adapted to the circuits of other drawings.