СИСТЕМА И СПОСОБ ТЕСТИРОВАНИЯ И КОНФИГУРИРОВАНИЯ FPGA

Группа изобретений относится к программируемым логическим устройствам. Техническим результатом является уменьшение пространства кристалла, выделенного для адресации ячеек запоминающих устройств, улучшение тестирования. Программируемая пользователем вентильная матрица (FPGA), выполненная с возможностью реализации логической функции, при этом FPGA содержит множество аппаратных поисковых таблиц (LUT), причем линии выбора или выходы каждой LUT программируемым образом взаимно подключаются к линиям выбора или выходам другой LUT посредством множества программируемых переключателей, множество триггеров в конфигурации сдвигового регистра, при этом каждая LUT имеет по меньшей мере один вход, соединенный с выходом соответствующего триггера, и каждый программируемый переключатель соединен с выходом дополнительного соответствующего триггера; причем FPGA выполнена с возможностью работы в первом режиме, в котором сдвиговый регистр загружается заранее определенными тестовыми значениями, и во втором режиме ...

ИНТЕГРИРОВАННАЯ В СБИС ТЕХНОЛОГИИ КМОП/КНИ С n+ - И p+ - ПОЛИКРЕМНИЕВЫМИ ЗАТВОРАМИ МАТРИЦА ПАМЯТИ MRAM С МАГНИТОРЕЗИСТИВНЫМИ УСТРОЙСТВАМИ С ПЕРЕДАЧЕЙ СПИНОВОГО ВРАЩЕНИЯ

Изобретение относится к схемам матриц ячеек памяти MRAM (Magnetic Random Access Memory) с передачей спинового значения. Технический результат заключается в увеличении плотности размещения отдельных транзисторных структур технологии МОП и запоминающих ячеек матрицы, а также повышении стойкости к нестационарным переходным процессам от воздействия ионизирующих излучений. Устройство матричного типа содержит множество устройств на магнитных туннельных переходах («MTJ») с передачей спинового вращения, организованных в матрицу запоминающих ячеек; устройство организации записи/чтения информации для конкретного устройства «MTJ», соединенное с соответствующими устройствами «MTJ» для изменения полярности намагниченности свободного слоя каждого устройства «MTJ», блок усилителя чтения данных на выходе матрицы запоминающих ячеек, выполненный с возможностью обнаруживать уровень сигнала и формировать двоичный выходной сигнал на основе сравнения уровня сигнала в разряде матрицы запоминающих ячеек в компараторе ...

ПРОГРАММНО-УПРАВЛЯЕМАЯ ЛОГИЧЕСКАЯ СХЕМА, ИСПОЛЬЗУЮЩАЯ МАГНИТОРЕЗИСТИВНЫЕ УСТРОЙСТВА С ПЕРЕДАЧЕЙ СПИНОВОГО ВРАЩЕНИЯ

Раскрыты системы, схемы и способы для программно-управляемой логической схемы, использующей технологию магниторезистивной оперативной памяти с передачей спинового вращения (STT-MRAM). Запоминающие элементы на магнитном туннельном переходе могут быть сформированы в матрицы ввода и матрицы вывода. Матрицы ввода и матрицы вывода могут быть соединены вместе для формирования сложных матриц, которые обеспечивают возможность реализации логических функций. Технический результат - расширение функциональных возможностей. 3 н. и 17 з.п. ф-лы, 7 ил., 3 табл.

Логическая матрица с программируемой памятью

Изобретение относится к вычислительной технике и может быть использовано для реализации управляющих и коммутирующих устройств в микропроцессорных системах. Цель изобретения - увеличение информационной емкости логической матрицы, достигаемое путем динамической перестройки триггеров. Устройство содержит с первого по четвертый блоки 1 - 4 памяти, с первого по N-й коммутационные блоки 5 1 - 5 N, блок 6 дешифраторов, вход 7 начальной установки устройства, группу управляющих входов 8, первые 9 - 12 и вторые 13 - 16 адресные входы с первого по четвертый блоков памяти, а также информационные выходы 17 - 20 этих блоков, первые группы входов 21 и выходов 22, вход-выход 23, синхровход 24, вход 25 начальной установки управляющих входов 26 I-го коммутационного блока, первый 27 и второй 28 синхровходы устройства, вторые группы выходов 29 и информационных входов 30 I-го коммутационного блока. 1 з.п. ф-лы, 3 ил.

Programmierbare integrierte Logik-Array-Einrichtung mit verbesserter Verbindbarkeit zu Mikroprozessoren.

Programmierbare logic Array

PROGRAMMIERBARE LOGIKVORRICHTUNG MIT REGIONALER UND UNIVERSELLER SIGNALWEGLENKUNG

Schnelles NOR-NOR programmierbares logisches Feld mit Einphasentakt

INTEGRIERTE HALBLEITER-SCHALTUNGSEINRICHTUNG MIT ABSCHALTBETRIEB DES LEISTUNGSVERBRAUCHES.

LOGIKSCHALTKREISE MIT ERHÖHTEN ARITHMETISCHEN DICHTEN

Es werden integrierte Schaltkreise mit programmierbaren Logikbereichen bereitgestellt. Die programmierbaren Logikbereiche können in kleinere Logikeinheiten organisiert sein, die manchmal als eine Logikzelle bezeichnet werden. Eine Logikzelle kann vier Nachschlagetabellen (LUTs) mit 4 Eingängen enthalten, die an eine Addiererübertragskette gekoppelt sind. Jede der vier LUTs mit 4 Eingängen kann zwei LUTs mit 3 Eingängen und einen Auswahlmultiplexer enthalten. Die Übertragskette kann bei drei oder mehr Volladdierschaltkreise enthalten. Die Ausgänge der LUTs mit 3 Eingängen können direkt mit Eingängen der Volladdierschaltkreise in der Übertragskette verbunden sein. Durch Bereitstellen mindestens der gleichen Anzahl oder mehr an Volladdierschaltkreisen wie die Gesamtanzahl an LUTs mit 4 Eingängen in der Logikzelle wird die arithmetische Dichte der Logik erhöht.

LOSE POLARISIERTES, HETEROGENES, REKONFIGURIERBARES GATTERFELD

BEFEHLSABWICKLUNGSFOLGESTEUERUNG FUER MIKROPROZESSOR MIT FESTSTELLUNGSNETZ FUER BEFEHLSZYKLUSPHASEN.

Programmierbare logische Schaltung.

Programmierbarer Logikbaustein

Aufgabe ist es, einen programmierbaren Logikbaustein zu schaffen, in dem Logikblöcke durch einen programmierbaren Schalter miteinander verbunden sind, wobei der programmierbare Schalter durch einen darin eingebauten Oxidhalbleiter-Transistor gekennzeichnet ist. Der extrem niedrige Sperrstrom des Oxidhalbleiter-Transistors sieht eine Funktion als nichtflüchtiger Speicher vor aufgrund seiner Fähigkeit, ein Potenzial einer Gate-Elektrode eines Transistors zu halten, der mit dem Oxidhalbleiter-Transistor verbunden ist. Die Fähigkeit des Oxidhalbleiter-Transistors, als nichtflüchtiger Speicher zu fungieren, ermöglicht, dass die Konfigurationsdaten zum Steuern der Verbindung der Logikblöcke auch bei Fehlen des Stromversorgungspotenzials aufrechterhalten werden. Daher kann der Neueinschreibvorgang der Konfigurationsdaten beim Einschalten des Bausteins wegfallen, was zur Verringerung des Energieverbrauchs des Bausteins beiträgt.

ELEKTRONISCHER SCHALTKREIS MIT EINEM FELD PROGRAMMIERBARER LOGISCHER ZELLEN

PROGRAMMIERBARE LOGISCHE SCHALTUNG (PLA) SOWIE HERSTELLUNGS- UND PRUEFVERFAHREN

FPGA mit Setz-/Rücksetzleitungen

Electronic memory circuit

Electronic memory circuit for storing information, in particular switching control information for the optional switching of circuit elements of monolithically integrated semiconductor circuits, having two series connections each comprising an EPROM transistor (E1, E2) and an MOS transistor (M1, M2) connected between the two poles (VDD, GND) of a voltage supply source, the control gates of the two EPROM transistors (E1, E2) being connected jointly to a reference voltage source (REF) and the gates of the two MOS transistors (M1, M2) being connected to the point of connection of the EPROM transistor (E1, E2) and of the MOS transistor (M1, M2) of the other series connection, respectively. ...

Shift register with reduced wiring complexity

LOGIC ARRAYS

... 1473029 Logic INTERNATIONAL BUSINESS MACHINES CORP 16 Sept 1975 [30 Dec 1974] 37918/75 Heading G4H A logic array has a plurality of input lines crossing a plurality of output lines with logical elements located at at least some of the intersections, there being different signal sources coupled to opposite ends of at least some of the input lines so that two different signals can be placed on each of such lines, and distributed segmentations in such input lines to separate from one another on different segments two different sets of logical elements coupled to the same input line so that the two different signals each feed only one set of logical elements, thus increasing the number of logic functions that can be performed for a given number of intersections. The disclosure is essentially as in Specification 1,473,028 (referred to).

Fpga with parallel and serial user interfaces

SOFTWARE PROGRAMMABLE LOGIC ARRAY

A software programmable logic array ("SPLA") is disclosed for creating a logic array which can be dynamically programmed to provide any combination of predetermined outputs from any combination of desired inputs. The foregoing is accomplished by providing a first plane 13 of programmable bits for producing a plurality of AND terms which are input to a second plane 17 of programmable bits for producing a plurality of OR terms, which are then input into a third plane 21 of programmable bits for producing a plurality of outputs, each having a desired polarity. In the AND plane each bit can be programmed to produce O (ie. regardless of input), I, input or inverse of input, prior to the ANDing. In the OR plane each bit can be programmed to produce O or input, prior to the ORing. In the third plane, each bit can be programmed to produce input or inverse of input. ...

PROGRAMMABLE ARRAY LOGIC CIRCUIT WITH TESTING AND VERIFICATION CIRCUITRY

Redundancy circuitry for logic circuits

Redundant circuitry for a logic circuit such as a programmable logic device allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic area 22a. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.

Programmable logic array integrated circuit devices

Logic circuits using polycrystalline semiconductor thin film transistors

A large scale integrated (LSI) or a very large scale integrated (VLSI) logic circuit comprises a plurality of polysilicon tin film transistors TFTs. The circuit, which may include a delay circuit, is asynchronous and does not comprise a clock. Thus, operations to be performed by the TFTs need not be performed within a single clock period - rather the operation of each stage of TFTs in the circuit is dependent on receiving a signal either from an input to the circuit or from a preceding stage in the circuit. Problems with variations in the threshold voltage between the TFTs are therefore avoided.

Programmable logic device configuration apparatus, and configuration method

PROGRAMMABLE LOGIC ARRAY WITH SINGLE CLOCK DYNAMIC LOGIC

TESTING PROGRAMMABLE LOGIC ARRAYS

PROGRAMMABLE LOGIC DEVICE

A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and a non-inverting buffer to provide a complementary pair of outputs from the buffers. In one embodiment, a memory cell is provided to control enablement of each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the complementary pair of outputs from the buffer are inputted to a multiplexer wherein a single memory cell controls the selection of the signal or its complement to be outputted from the multiplexer. The memory cells are each coupled to its corresponding latch or shift register for latching a stored state of the memory cell. Shift registers provide for external programming to emulate stored memory cell states.

Configurable logic cell

Segmented localized conductors for programmable logic devices

IMPROVED CONFIGURABLE CELLULAR ARRAY (CAL II)

Expandable macrocell with reduced set-up time

A macrocell 100 for use in a programmable logic device (PLD) includes two reprogrammable look-up tables 102, 104 for increased fan-in, and two flip-flops 126, 128 that increases fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. The second register 126 can be used for receiving fast input signals 120 form an input to the PLD to reduce setup time. The allocation input and output lines allow cascading of macrocells. Programmable elements 108 - 124 may be implemented by RAM, EPROM, or fuse link memory cells. ...

An FPGA DRAM cell sensing circuit with a stepped word line waveform

Field device for determining or monitoring a physical or chemical process variable

High-density erasable programmable logic device architecture using multiplexer interconnections

A programmable logic device is presented comprises a global interconnect array 105 whose lines are fed via programmable multiplexers 110,210 to logic array blocks 130. The global interconnect array lines are fed to the multiplexers in a specific pattern (algorithm disclosed) which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories. Each logic array block 130 comprises macrocells 260,270 and an EPROM programmable interconnect array 240.

Improvements in or relating to electrical circuit assemblies

... 989,629. Circuit assemblies. SCHWEIZERISCHE WAGONS - UND AUFZUGEFABRIK A.G. SCHLIEREN-ZURICH. Aug. 21, 1961 [Sept. 2, 1960], No. 30139/61. Heading H1B. A logical switching assembly comprises a four-sided frame, opposite sides 3, 4 of which have slots at their upper edges to receive a plurality of parallel strip-like conductors 7 and the remaining sides 5, 6 of which have slots at their lower edges to receive a further plurality of parallel strip-like conductors 8, interconnection being made between selected ones of the conductors 7 and 8 where they cross by components whose terminal leads engage in retaining clips 15 formed in the material of or attached to the strips 7 and 8. The assembly is completed by a further structure comprising an insulating block 25 housing a plurality of transistors, the emitter leads of which are all connected to a common conductor 34 and the collector and base leads of which are connected to selected ones of the strips 7 and 8 respectively. The retaining clips ...

Logic circuits using polycrystalline semiconductor thin film transistors

Constant voltage device

... 1,017,416. Voltage stabilizers. STANDARD TELEPHONES & CABLES Ltd. Feb. 8, 1963 [Feb. 13, 1962], No. 5237/63. Heading G3X. [Also in Divisions H3 and H4] A voltage stabilizer comprises a first voltage divider constituted by a resistance R L , a transistor Q 1 and a resistance R c connected to a voltage source +18, -18, in parallel with a second voltage divider R 1 , Q 2 , R 2 . The base of transistor Q 2 is connected to an unregulated reference potential such as ground, and the collector of transistor Q 2 is connected to the base of transistor Q 2 . The arrangement is such that voltage variations on the voltage divider including transistor Q 2 are used to control the gain of transistor Q 1 , the direction of gain control opposing source variations. Thus a stabilized voltage can be taken from the output CP of transistor Q 1 . As used in a telephone system, Fig. 4, the resistance R L is constituted by a switch path comprising a resistor, a winding to which voice currents are inductively applied ...

Field programmable gate arrays using polycrystalline semiconductor thin film transistors

Switching network

... 1,021,818. Automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. March 20, 1964 [March 25, 1963], No. 11851/64. Heading H4K. [Also in Division H1] Multi-stage cross-point switching networks are constructed out of printed circuit cards carrying the matrices. The networks are said to be designed to have occupation values of interstage paths which, for a given grade of service and traffic volume, require the total number of cross-point devices (PNPN transistors) to be a minimum. The networks are also said to be capable of expansion at a linear cost per added increment of line capacity. In the 100 line network of Fig. 2 ten 10 Î 5 primary matrices are followed by five 6x10 secondary matrices. Half the horizontals of the secondary matrices are graded over 45 to the originating sides of links 21 the terminating sides of which have access to the other half of the horizontals of the secondary matrices by way of a tertiary matrix 33 and a grading panel 46. Trunks are connected over the tertiary ...

Improvements in and relating to integrated circuit logic matrices

... 1,135,992. Integrated circuits. INTERNATIONAL STANDARD ELECTRIC CORP. 12 Oct., 1967 [20 Oct., 1966], No. 46537/67. Heading H1K. In an integrated circuit logic matrix the input conductors are provided in pairs, e.g. ce1, ce2, the conductors of each pair being connected to each output conductor, e.g. cs1, by a combination of two fuses fs1, fs2 and a coupling component such as a diode cl1. The output of the diode cl1 is connected to the output conductor cs1 while the input of the diode is connected through one fuse fs1 to the input conductor ce1 and through the second fuse fs2 to the other input conductor ce2 of the pair. One or both of the fuses in each pair may be blown prior to operation of the matrix, dependent upon the desired circuit function. In the embodiment the diodes cl1 &c. are all formed in a common Si body provided with deposited A1 conductors ce1, ce2, cs1 &c., and the fuses fs1, fs2 &c. comprise portions of conductors having reduced cross-section which may be melted as desired ...

Hybrid programmable logic device and method

Programmable logic array integrated circuits with enhanced elements

RECURSIVE PROGRAMMABLE LOGIC ARRAYS

METHOD FOR MANIPULATING DIGITAL SIGNALS ON ORDERED DATA BUS LINES

APPARATUS FOR PERFORMING LOGICAL OPERATIONS

... 1523859 Logic INTERNATIONAL BUSINESS MACHINES CORP 18 May 1977 [30 June 1976] 20896/77 Heading G4H In a logic-performing matrix of devices (e.g. FETs), with orthogonal input and output conductors, first and second groups of the devices are coupled to a source of operating potential in respective first and second states of switching means. The two states are used at different times and select different logic functions to be performed. A first such matrix (AND) may feed another such (OR), and integrated circuitry may be used.

INTEGRATED CIRCUIT WITH BUILDING BLOCKS

KONFIGURIEBARE SERIAL INTERFACE FOR PROGRAMMABLE LOGIC CIRCUIT

STRENGTHENED PASSPORT GATE PASS FOR LEAKAGE CURRENT DECREASE

INTEGRATED CIRCUIT

RECONFIGURE-CASH LOGIC DEVICE

INTEGRATED CIRCUIT

PROGRAMMABLE LOGICAL CIRCUIT WITH CONFIGURABLE RELEASE OF THE EXIT.

PROGRAMMABLE MEMORY/CLOGIC MATRIX.

PROTECTION CIRCUIT FOR PROGRAMMABLE LOGIC ARRAY.

PROGRAMMING CIRCUIT FOR EXPENDITURE FOR INPUT OF A PROGRAMMABLE LOGIC ARRAY.

INTEGRATED MONOLITH.

PROGRAMMABLE SWITCHING CONFIGURATION.

CONFIGURABLE CONNECTING STRUCTURE

SEGMENTING OF TRACES IN FPGA WIRING CHANNELS

PROCEDURE FOR THE SELF SYNCHRONISATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE COMPONENT

DEVICE AND PROCEDURE FOR THE DYNAMIC DEFINITION OF PARTIAL FIELDS WITHIN A PROGRAMMABLE GATE FIELD

BAUSTEINSCHALTUNG DIE AUS BINAER AUSGENUTZTEN SPEICHERTRANSISTOREN MIT SCHWEBENDEM GATE AUF- GEBAUT IST

INTEGRIERTE SCHALTUNG ZUM ERZEUGEN MINDESTENS EINER LOGISCHEN KOMBINATION ZUZUFUEHRENDER LOGISCHER EINGANGSSIGNALE

SCALE-CASH ARCHITECTURE FOR PROGRAMMABLE LOGICAL DEVICES WITH HIGH DENSITY AND ZWEIEBENIGEN HIERARCHICAL CONNECTING RESOURCES

PROCEDURE FOR INDEPENDENT DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AS WELL AS COMPONENTS WITH TWO ONES OR MULTIDIMENSIONAL ONE PROGRAMMABLE ONE CELL STRUCTURES (FPGAS, DPGAS, O.DGL.)

PROGRAMMABLE CONNECTING ARCHITECTURE

UMKONFIGURIERBARE INTEGRATED CIRCUIT WITH INSERTED ERROR SEARCHING SYSTEM FOR A SIMULATION SYSTEM

Switching configuration for communications, in particular telephone systems

SCALE-CASH MULTISTAGE ONES CONNECTING ARCHITECTURE

INTERNAL BUS SYSTEM FOR DFPS, AS WELL AS COMPONENTS WITH TWO ONES OR MULTIDIMENSIONAL ONE PROGRAMMABLE ONE CELL STRUCTURES, FOR THE MANAGEMENT OF LARGE DATA SETS AT HIGH NETWORKING EXPENDITURE

CONFIGURABLE LOGICAL FIELD

A semi-conductor integrated circuit

Unit for processing numeric and logical operations, for use in processors (cpus)and in multicomputer systems

Integrated circuit

PROGRAMMABLE MEMORY CELL AND ARRAY

SYSTEM OF FINITE STATE MACHINES

PROGRAMMABLE LOGIC CELL AND ARRAY

A reconfigurable integrated circuit with a scalable architecture

PROGRAMMABLE LOGIC ARRAY

Electrode means, comprising polymer materials, with or without functional elements and an electrode device formed of said means

A programmable array logic circuit macrocell using ferromagnetic memory cells

FUNCTIONALLY REDUNDANT LOGIC NETWORK ARCHITECTURES WITH LOGIC SELECTION MEANS

A PROGRAMMABLE LOGIC ARRAY DEVICE USING EPROM TECHNOLOGY

DRIVER CIRCUIT FOR 3 STATE GATE ARRAY

Programmable logic module and architecture for field programmable gate array device

SPRING-LOCKED CONCATENATION OF HOUSINGS FOR ELECTRICAL CONNECTIONS

FLOOR PLANNING FOR PROGRAMMABLE GATE ARRAY HAVING EMBEDDED FIXED LOGIC CIRCUITRY

Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interconnecting logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interconnecting logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. The invention is directed towards the various needs and requirements of the layout and floor planning of a device having both fixed logic circuitry and programmable logic circuitry. The various designs are geared towards many goals including allowing fail-safe operation, facilitating the ease of interface between ...

ELECTRONICALLY ALTERABLE DIODE LOGIC CIRCUIT

ELECTRONICALLY ALTERABLE DIODE LOGIC CIRCUIT A crosspoint (X-Y) matrix array of electrically reprogrammable memory logic elements, such as an array of dual dielectric insulated gate field effect transistor (IGFET) structures, is interconnected in a single electrically reprogrammable diode logic array circuit, both for computing the logic function(s) of many variables and for writing and erasing the function(s). Each logic element's high current path is in series with a separate unidirectional diode in order to prevent sneak paths. Electrical access circuitry is also provided for computing the logic function(s) of many variables, each function being electrically alterable.

DRIVER CIRCUIT FOR A THREE-STATE GATE ARRAY USING LOW DRIVING CURRENT

A driver circuit for simultaneously setting up a plurality of output buffers of a 3-state gate array into and out of a floating state using low control current. A buffer driver transistor is provided for each output buffer with the primary control path of that transistor introducing a control circuit to the respected output buffer. A common driver transistor has a primary current path which provides a control signal to the control electrodes of a plurality of buffer driver transistors. Clamp means are provided for discharging the conductor means to ground upon turn-off of the common driver transistor. Clamp means preferably includes a clamp transistor having a primary current path coupled between the conductor means and ground and having a differentiator coupled to the common driver transistor for detecting the leading edge of turn-off of that transistor and in response thereto momentarily, dynamically turning on the clamp transistor to couple the conductor means to ground and thereby discharge ...

EAROM CELL MATRIX AND LOGIC ARRAYS WITH COMMON MEMORY GATE

EAROM CELL MATRIX AND LOGIC ARRAYS WITH COMMON MEMORY GATE A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line. The logic state stored in the cell is defined by the presence or absence ...

LOGIC ARRAY HAVING IMPROVED SPEED CHARACTERISTICS

An integrated circuit Read-Only Memory (ROM) with improved speed of operation is disclosed as generally representative of similarly improved logic arrays. The ROM includes parallel rows of conductors oriented normal to parallel doped regions which form column conductors. The ROM is implemented with field-effect transistors and comprises two decoder fields and a data field. The transistors of the decoder fields serve to define open circuits between adjacent column conductors in accordance with binary input signals applied to the decoder fields. In the illustrative ROM, a first column conductor is connected to a return terminal of a power supply and a second column conductor is connected to a "pull-up" circuit. The illustrative circuit provides for the connection of power supply return connections to both ends of the one column conductor and provides for the connection of pull-up circuits to both ends of the second column conductor. The row conductors are connected to gates of transistors ...

LOW POWER PARTITIONED PLA

A LOW POWER PARTITIONED PLA A logic array includes a plurality of gated current sources which receive respective input signals, each of said gated current sources is coupled to a respective row conductor and sends current to that row conductor when the received input signal is in a predetermined state; the respective row conductors are partitioned into several groups; a respective high capacitance column conductor is provided for each group; within each group, diodes selectively couple current from the row conductors to the respective high capacitance column conductor; a low capacitance column conductor is provided; and a circuit generates current on the low capacitance column conductor representing the logical NAND of selected input signals when current is coupled from any group of row conductors to the high capacitance column conductor for that group.

TRANSFER BUS MATRIX

A transfer bus matrix provides a single channel of a plurality of conductors to which multiple inputs and multiple outputs are connected by ports or control gates which allow them to be selectively interconnected by control means. Individual matrices or groups of matrices may be involved, including a multistage matrix having individual substage matrices using a transfer bus. Each matrix may be monitored by monitor means having connections to each of the conductors and a multistage matrix may be monitored in each substage and arranged so that each single input may be selectively monitored at various stages throughout the multistage matrix.

HIGH DENSITY LOGIC ARRAY

HIGH DENSITY LOGIC ARRAY This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic performed on the variables fed to the other end. The arrays are compounded. Two arrays are arranged on opposite sides of a third array and the output signals from the two arrays function as input variables to the third array. Input lines in the third array can also be broken to separate array logic functions performed in the third array on variables fed to the opposite ends of such lines.

Ring based impedance control of an output driver

In one embodiment, there is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

Semiconductor device and method of adjusting characteristic thereof

To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Configurable integrated circuit with built-in turns

Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC's wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g., buffer circuits), while other direct connections do not have any intervening circuits. Also, in some embodiments, the nodes in the configurable array are all similar (e.g., have the same set of circuit elements and same internal wiring between the circuit elements).

Transistor substrate dynamic biasing circuit

A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

Method for improving writability of sram memory

A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Memory and method for sensing data in a memory using complementary sensing scheme

In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

Resilient Integrated Circuit Architecture

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Phase change memory device

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

Reconfigurable Integrated Circuit Architecture With On-Chip Configuration and Reconfiguration

The exemplary embodiments provide a reconfigurable integrated circuit capable of on-chip configuration and reconfiguration, comprising: a plurality of configurable composite circuit elements; a configuration and control bus; a memory; and a sequential processor. Each composite circuit element comprises: a configurable circuit; and an element interface and control circuit, the element interface and control circuit comprising an element controller and at least one configuration and control register to store one or more configuration and control words. The configuration and control bus is coupled to the plurality of configurable composite circuit elements, and comprises a plurality of address and control lines and a plurality of data lines. The sequential processor can write configurations to the configuration and control registers of an addressed configurable composite circuit element to configure or reconfigure the configurable circuit.

High resolution output driver

High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

Semiconductor device, circuit board device, and information processing device

In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Element Controller for a Resilient Integrated Circuit Architecture

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit

In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Differential data sensing

A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Timing operations in an ic with configurable circuits

Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

Semiconductor integrated circuit and power-supply voltage adaptive control system

A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

Semiconductor device

The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

Programmable logic circuit using three-dimensional stacking techniques

A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.

Selecting four signals from sixteen inputs

An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.

Systems and methods for detecting and mitigating programmable logic device tampering

Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.

Logic circuit and semiconductor device

The logic circuit includes an input terminal, an output terminal, a main logic circuit portion that is electrically connected to the input terminal and the output terminal, and a switching element electrically connected to the input terminal and the main logic circuit portion. Further, a first terminal of the switching element is electrically connected to the input terminal, a second terminal of the switching element is electrically connected to a gate of at least one transistor included in the main logic circuit portion, and the switching element is a transistor in which a leakage current in an off state per micrometer of channel width is lower than or equal to 1×10 −17 A.

Semiconductor device

A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor.

Semiconductor Device

As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a first capacitor and a second capacitor. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region.

Driver Calibration Methods and Circuits

Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Three dimensional integrated circuits

A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer.

Logic circuit emulator and control method therefor

A logic circuit emulator comprises multiple sub-systems, in which each sub-system outputs to another one of the sub-systems a permission notification to permit the another sub-system to proceed to next emulation clock cycle depending on whether or not the state of an own sub-circuit has advanced. In case a signal that is output from an own sub-circuit and that is to be sent to a sub-circuit of the other sub-system has changed, each sub-system outputs a transfer request to transfer the signal to the another sub-system before the next emulation clock cycle. In case a signal is not being sent from the own sub-circuit to the sub-circuit of the another sub-system, and a permission notification is received but no transfer request is being received from the other sub-system, a clock signal is output for the own sub-circuit to advance the own sub-circuit to the next emulation clock cycle.

Semiconductor device operates on external and internal power supply voltages and data processing system including the same

The semiconductor device including an output terminal; and an output unit coupled to the output terminal. The output unit includes an output buffer coupled to the output terminal and operating on a first power supply voltage, a first control circuit operating on a second power supply voltage, receiving an impedance adjustment signal and a data signal and making the output buffer drive the output terminal to a first logic level designated by the data signal with impedance designated by the impedance adjustment signal, and a level shifter coupled between the output buffer and the first control circuit. The second power supply voltage is smaller in level than the first power supply voltage. The level shifter includes a first circuit portion operating on the second power supply voltage and a second circuit portion operating on the first power supply voltage.

Circuits and Methods for Programmable Transistor Array

A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit. 1. A programmable transistor array , comprising:a semiconductor substrate; anda plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other;wherein the arrangement of the BTUs is subject to restricted design rules such that the NTUs are adjacent other NTUs and DTUs but not PTUs across the rows, and the PTUs are adjacent other PTUs and DTUs but not DTUs across the rows.2. The programmable transistor array of claim 1 , wherein the NTUS and PTUs further comprise:at least two gate conductors running the single direction and overlying a source/drain diffusion region to form source/drain areas adjacent the gate conductors;gate dielectric material lying between the gate conductors and the semiconductor substrate;source/drain contacts for coupling the source drain regions to other circuit elements using a first level of metal; andgate contacts for coupling the gate conductors to other circuit elements using the first level of metal.3. The ...

TERMINATION DEVICE SYSTEM

A termination device system is provided that includes a device required to be terminated with a resistor and a termination circuit. The termination circuit includes a termination resistor circuit and a judgment circuit connected to the termination resistor circuit. The termination resistor circuit includes at least one controlled termination unit. Each controlled termination unit includes a termination connecting end for connecting the device required to be terminated with a resistor, a controlled switch and a resistor, and provides, based on on/off of the controlled switch, a termination resistor for the device connected to the termination connecting end. The judgment circuit judges whether the device is required to be connected to the termination resistor based on a control instruction of a control device controlling the device connected to the termination connecting end, to output an on/off control signal to the controlled switch of the termination resistor circuit to control on/off. 1. A termination resistor circuit , comprising:at least one controlled termination unit, each of which comprising a termination connecting end for connecting a device required to be terminated with a resistor, a controlled switch and a resistor, for providing a termination resistor for the device connected to the termination connecting end based on on/off of the controlled switch.2. The termination resistor circuit as in claim 1 , wherein the at least one controlled termination unit comprises a voltage divider resistor circuit for performing voltage division on a power supply voltage claim 1 , wherein the voltage divider resistor circuit comprises resistors and controlled switches.3. The termination resistor circuit as in claim 1 , wherein the termination resistor circuit is a termination chip claim 1 , and each controlled termination unit is within the termination chip.4. The termination resistor circuit as in claim 1 , wherein the termination resistor circuit comprises a ...

Device

A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

System of at Least One Assembly Comprising at Least One Integrated Circuit, the Said Integrated Circuits Being Interconnected According to a Matrix Architecture, Featuring at Least One Optical Interconnection

A system of one or more integrated circuits is interconnected to a matrix architecture of rows and columns, a row receiving at least one input for signals, and a column providing at least one output for signals, the interconnections between two integrated circuits of a row and the interconnections between two integrated circuits of a column being electrical, and an assembly of at least one integrated circuit comprising at least one input integrated circuit and at least one output integrated circuit, an input integrated circuit being optionally an output integrated circuit, and at least one optical interconnection connecting an input of a row of the system to a respective input of the input integrated circuits of the assemblies, belonging to said row, or for connecting an output of a column of the system to a respective output of the output integrated circuits of the assemblies, belonging to the said column.

NON-SEQUENTIALLY CONFIGURABLE IC

Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit. 125-. (canceled)26. An integrated circuit (IC) comprising:a plurality of reconfigurable circuits for performing a particular user design, the user design defined to perform a set of M operations in one user design cycle, each operation of the set of M operations performed by one of the reconfigurable circuits in a reconfiguration cycle, wherein different subsets of the set of M operations are performed by subsets of the reconfiguration circuits in a plurality of reconfiguration cycles that fall within the user design cycle, each subset of reconfigurable circuits comprising at most N reconfigurable circuits, wherein N is less than M; anda plurality of configuration data storage that stores a plurality of reconfiguration data sets for reconfiguring the plurality of reconfigurable circuits in a plurality of reconfiguration cycles.27. The IC of claim 26 , wherein a first subset of reconfigurable circuits and a second subset of reconfigurable circuits share at least one reconfigurable circuit.28. The IC of claim 26 , wherein a first subset of reconfigurable circuits and a second subset of reconfigurable circuits are different sets of reconfigurable circuits.29. The IC of claim 28 , wherein a first subset of the set of M operations is logically dependent on a second subset of the set of M operations.30. The IC of claim 29 , wherein ...

Safety component in a programmable components chain

An electronic circuit includes a plurality of programmable components connected in an electronic chain. An interface is adapted to connect the programmable components to an external controller wherein the controller is adapted to program the programmable components. A component isolation element is connected to the interface at an input end and to the electronic chain of the programmable components at an output end wherein the isolation element is adapted to isolate one component of the programmable components from the electronic chain and wherein the one component is a safety component.

SYSTEM AND METHOD FOR REDUCING RECONFIGURATION POWER USAGE

A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration. 163-. (canceled)64. An integrated circuit (“IC”) comprising:a group of reconfigurable circuits, each of the reconfigurable circuits for configurably performing a plurality of different operations in different reconfiguration cycles based on stored configuration data;a select driver for selecting different sets of stored configuration data in different reconfiguration cycles for the group of reconfigurable circuits, wherein the select driver comprises a clock input for receiving a clock signal, wherein the select driver selects a different set of stored configuration data in each reconfiguration cycle in which the select driver receives the clock signal; anda gating circuit for selectively blocking the signal from reaching the clock input in a set of reconfiguration cycles controlled by configuration data of the gating circuit.65. The IC of further comprising a plurality of multiplexers (MUXs) for selectively providing the different sets of configuration data to the reconfigurable circuits.66. The IC of claim 65 , wherein at least one of the plurality of MUXs comprises a set of inputs that determine which of a plurality of stored configuration data values will be provided to the reconfigurable circuit.67. The IC of claim 66 , wherein the set of inputs are communicatively coupled to the select driver.68. The IC of claim 65 , wherein the MUXs are one-hot select MUXs.69. The IC of claim 65 , wherein the select driver selects different sets of stored configuration data by activating a selected set of inputs of the MUXs claim 65 , wherein the inputs are ...

SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE

A system including a read module and a sequence detector module. The read module is configured to read a plurality of memory cells located along a bit line or a word line of a memory array and to generate a plurality of read signals. The sequence detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes (i) a first signal and (ii) a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal includes interference from the second memory cell. 1. (canceled)2. A system comprising: read a plurality of memory cells located along a bit line or a word line of a memory array, and', 'generate a plurality of read signals based on reading the plurality of memory cells located along the bit line or the word line of the memory array; and, 'a read module configured to'} detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals, and (ii) a plurality of reference signals associated with the plurality of memory cells,', 'wherein one of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes (i) a first signal and (ii) a second signal,', 'wherein the first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line, and', 'wherein the second signal includes interference from the second memory cell., 'a sequence detector module configured to'}3. The system of claim 2 , further comprising a reference generator module configured to generate the plurality of reference signals by (i) writing reference data to the ...

TERMINATION CIRCUIT AND DC BALANCE METHOD THEREOF

A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers. 1. A termination circuit for a plurality of memories controlled by a controller , comprising:a plurality of drivers, each coupled to the memories via a transmission line;a plurality of resistors, each coupled to the corresponding driver via the corresponding transmission line; anda plurality of capacitors, each coupled between the corresponding resistor and a reference voltage,wherein the controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.2. The termination circuit as claimed in claim 1 , wherein the controller further provides data to the memories via the drivers claim 1 , wherein the controller further records the data provided to the memories via each of the drivers and obtains a plurality of statistic values according to a quantity of logic “0” and a quantity of logic “1” of the recorded data.3 ...

Output buffer, operating method thereof and devices including the same

A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals.

HIGH-FREQUENCY SEMICONDUCTOR SWITCHING CIRCUIT

A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages. 1. A high-frequency semiconductor switching circuit comprising:a semiconductor substrate;one common input-output terminal, three or more individual input-output terminals, and three or more control terminals corresponding to the three or more individual input-output terminals, these terminals being formed on the semiconductor substrate;three or more path switching FET stages formed on the semiconductor substrate and each provided between the common input-output terminal and a corresponding one of the three or more individual input-output terminals;one or more shunt FET stages formed on the semiconductor substrate and each provided between ground and at least one of the three or more individual input-output terminals; anda diode-switch logic circuit including diodes and switches formed on the semiconductor substrate such that a group of a part of the diodes and a part of the switches corresponds to each of the one or more shunt FET stages, the diode-switch logic circuit being configured to control the three or more path switching FET stages and the one or more shunt FET stages, wherein:the diode-switch logic circuit is configured to respectively apply control voltages, respectively input to the three or more control terminals, to gates of the three or more path switching ...

HIGH-SPEED DRIVER CIRCUIT

An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream. 1. An inverter-type high speed driver circuit comprising:a first inverter branch and a second inverter branch, wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor, wherein the impedance tuning units are configured to adapt conductivity of a respective inverter branch to set an output impedance of the driver circuit; wherein each of the impedance tuning units is controlled in accordance with a data stream.2. The driver circuit according to claim 1 , wherein each impedance tuning unit comprises a plurality of parallelized impedance tuning transistors separately controlled by respective weighted data control signals claim 1 , and wherein an impedance weighting unit is provided to generate weighted data control signals as a result of an incoming data signal and a given impedance setting signal.3. The driver circuit according to claim 1 , wherein each of the inverter branches comprises a resistor in series to the parallel circuit.4. The driver circuit according to claim 1 , wherein the inverter branches are interconnected at a node wherein a resistor is serially connected between an output of the driver circuit and the node.5. The driver circuit according to ...

METHOD AND SYSTEM FOR A RUN-TIME RECONFIGURABLE COMPUTER ARCHITECTURE

A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements. 139-. (canceled)40. A method for optimizing a circuit for a reconfigurable computer architecture , comprising: 1) identifying each plane of the input circuit design;', '2) obtaining circuit parameters within each plane;', '3) obtaining a user optimization objective;, 'a) determining a folding level for an input circuit design byb) partitioning the input circuit design into logical functions and logical function clusters;c) scheduling each of the logical functions and logical function clusters to a folding stage;d) mapping each logical function and logical function cluster to a specific look-up table (LUT) or LUT cluster;e) performing temporal placement;f) generating routing; andg) generating a layout for each folding stage and a configuration bitmap for use with each of one or more folding cycles run by the reconfigurable computer architecture.41. The method of claim 40 , wherein the input circuit design comprises a register transfer level design or a gate level VHDL design.42. The method of claim 40 , further comprising memory mapping for embedded memories.43. The method of claim 42 , wherein claim 42 , for logic intensive applications claim 42 , the memory mapping occurs after partitioning the input circuit design into logical functions and logical function clusters.44. The method of claim 42 , wherein claim 42 , for memory intensive applications claim 42 , the memory mapping occurs prior to partitioning the input circuit design into logical functions and logical function clusters.45. The method of claim 40 , further comprising claim 40 , prior ...

MEMORY CONTROL DEVICE

A memory control device that can reduce a power consumption at the time of writing a memory. The memory control device includes a data output buffer circuit that burst-transfers data to a memory device through a data bus, and a mask signal output buffer circuit that outputs, to the memory device, a mask signal indicative of data that prohibits write into a memory cell within the memory device among the data. The data output buffer circuit puts an output node into a high impedance state when the mask signal is indicative of write prohibition. 1. A memory control device , comprising:a data output buffer circuit that burst-transfers data to a memory device through a data bus; anda mask signal output buffer circuit that outputs, to the memory device, a mask signal indicative of data that prohibits write into a memory cell within the memory device among the data,wherein the data output buffer circuit puts an output node into a high impedance state when the mask signal is indicative of write prohibition.2. The memory control device according to claim 1 ,wherein when the mask signal is switched from a state in which th mask signal is not indicative of the write prohibition to a state in which the mask signal is indicative of the write prohibition, the data output buffer circuit delays a timing at which the output node is put into a high impedance state, and extends a period during which the data is output.3. The memory control device according to claim 1 ,wherein when the mask signal is switched from a state in which th mask signal is indicative of the write prohibition to a state in which the mask signal is not indicative of the write prohibition, the data output buffer circuit fastens a timing at which the data is output from the output node, and extends a period during which the data is output.4. The memory control device according to claim 1 , further comprising:an output control signal output node that generates an output control signal for controlling a high ...

Adaptive termination

A system for receiving data is provided the system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.

CONFIGURATION CONTEXT SWITCHER

Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. 145-. (canceled)46. An integrated circuit (IC) comprising:an unclocked state element for switchably receiving different configuration data sets, each bit of a received configuration data set being a logic bit comprising first and second physical bits, the first physical bit for setting the state of the unclocked state element and the second physical bit for resetting the state of the unclocked state element; anda configurable circuit for configurably performing one of a plurality of operations based on the state of the unclocked state element.47. The IC of claim 46 , wherein the unclocked state element is a SR latch.48. The IC of claim 46 , wherein the unclocked state element is in an interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive the different configuration data sets.49. The IC of further comprising a plurality of storage circuits for storing the different configuration data sets.50. The IC of claim ...

Hierarchically-Scalable Reconfigurable Integrated Circuit Architecture With Unit Delay Modules

The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect bus, is completed within a predetermined unit time delay which is independent of application placement and application data routing on the reconfigurable IC. 1. A reconfigurable integrated circuit comprising:a plurality of zones, each zone of the plurality of zones comprising:a plurality of composite circuit elements, each composite circuit element comprising: a configurable circuit element circuit and an element interface and control circuit, the element interface and control circuit comprising an input queue and an output queue;a plurality of cluster queues, each cluster queue comprising an element interface and control having an input queue and an output queue; anda first full interconnect bus coupling every output queue within the zone to every input queue within the zone;wherein any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word ...

Boolean logic in a state machine lattice

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. 1. A semiconductor device comprising:a first local bit line coupled to a plurality of memory cells arranged in a first area;a second local bit line coupled to a plurality of memory cells arranged in a second area;a local sense amplifier of a differential type amplifying a voltage difference between the first and second local bit lines;a global bit line arranged in an extending direction of the first and second local bit lines;a first switch controlling an electrical connection between the first local bit line and the global bit line; anda second switch controlling an electrical connection between the second local bit line and the global bit line.2. The semiconductor device according to claim 1 , further comprising a global sense amplifier of a single-ended type connected to one end of the global bit line.3. The semiconductor device according to claim 1 , further comprising a control circuit controlling the first and second switches claim 1 ,wherein in response to a selected memory cell of the memory cells, the control circuit renders one of the first and second switches conductive and renders the other thereof non-conductive.4. The semiconductor device according to claim 3 , wherein the control circuit renders the first switch conductive when the selected memory cell is in the first area claim 3 , and renders the second switch conductive when the selected memory cell is in the second area.5. The semiconductor device according to claim 4 , ...

Configuration Context Switcher with a Latch

Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

ADAPTIVE BUFFER

An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system. 115.-. (canceled)16. A circuit , comprising:a node configured to be coupled to load that includes a signal-propagation medium, the load having an impedance;a driver configured to drive a calibration signal onto the node; anda calibrator coupled to the node and configured to generate, in response to the calibration signal, an impedance signal that is related to the impedance of the load.17. The circuit of wherein the node includes an output node.18. The circuit of wherein the node includes an input node.19. The circuit of wherein the driver has an output impedance and is configured to adjust the output impedance in response to the impedance signal.20. The circuit of claim 16 , further comprising a receiving stage coupled to the node claim 16 , having an input impedance claim 16 , and configured to adjust the input impedance in response to the impedance signal.21. The circuit of claim 16 , further comprising a transmitting stage coupled to the node claim 16 , having an output impedance claim 16 , and configured to adjust the output impedance in response to the impedance signal.22. The circuit of wherein the driver includes driver elements that selectively activate in response to the impedance signal to adjust the output impedance of the driver claim 16 ,23. The circuit of wherein the driver has an output impedance and is configured to set the output impedance approximately equal to the impedance of the load in response to the impedance signal.24. The circuit of claim 16 , further comprising a transmitting stage coupled to the node claim 16 , having an output impedance claim 16 , and configured to set the output impedance approximately equal to the impedance of the load in response to the impedance signal.25. The circuit of wherein:the driver includes a calibration portion that is configured to drive the ...

RECONFIGURABLE CIRCUIT

A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmable wiring group. The reconfigurable circuit is also characterized in being provided with a fourth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the functional block input wiring group, and/or a fifth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the branch lines of the functional block output wiring. 1. A reconfigurable circuit , comprising:a first programmable wiring group disposed in a first direction;a second programmable wiring group disposed in a second direction intersecting the first direction;a first switching element array connecting the first programmable wiring group to branch line group of input line group of a function block at those intersecting points, or connecting branch line group of the first programmable wiring group to the input ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE CONTROL METHOD

A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provided in reconfigurable logic circuit. 1. A semiconductor device , comprising:a reconfigurable logic circuit that includes a plurality of resistance change elements; a logical configuration of the reconfigurable logic circuit being decided depending on whether each of the plurality of resistance change elements is in a first resistance state or in a second resistance state whose resistance value is lower than a resistance value of the first resistance state;a resistance value monitor circuit that includes a resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not the pre-programmed resistance change element retains the first resistance state; anda controller that, in case it is detected that the resistance change element provided in the resistance value monitor circuit does not retain the first resistance state, applies a voltage used in programming from the second resistance state to the ...

Current mirror modified level shifter

A current mirror modified level shifter includes a pair of PMOS including a PMOS (M PL ) and a PMOS (M PR ), wherein a Vot node connected to a drain of the PMOS (M PR ); a pair of NMOS including NMOS (M NL ) and a NMOS (M NR ), wherein sources of the PMOS (M PL ) and the PMOS (M PR ) are coupled to a high voltage (HV), respectively; gates of the PMOS (M PL ) and the PMOS (M PR ) coupled together through a Vm node which located between the gates of the PMOS (M PL ) and the PMOS (M PR ); and a suspended PMOS (M PM ) coupled to drain of the PMOS (M PL ), the Vm node being coupled to a Va node between drain of the suspend PMOS (M PM ) and drain of the NMOS (M NL ).

Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device

Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal. 1. An apparatus , comprising:a first transistor configured to receive an input signal and adjust a resistance of a second transistor based, at least in part, on the input signal, the first transistor configured to provide an output signal based, at least in part, on the input signal,wherein a rate at which the output signal is provided is based, at least in part, on a magnitude of the resistance of the second transistor.2. The apparatus of claim 1 , wherein the resistance is an ON-resistance.3. The apparatus of claim 1 , wherein the input signal comprises an analog signal and the output signal comprises a digital signal.4. The apparatus of claim 3 , wherein the first transistor is configured to provide the output signal having a first state when the input signal has a voltage less than a reference voltage and to provide the output signal having a second state when the input signal has a voltage greater than the reference voltage.5. The apparatus of claim 1 , wherein a terminal of the first transistor and a terminal of the second transistor are capacitively coupled.6. The apparatus of claim 1 , ...

Pld architecture for flexible placement of ip function blocks

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Field programmable gate arrays using resistivity-sensitive memories

Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.

Resilient Integrated Circuit Architecture

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

IMPEDANCE CALIBRATION DEVICE AND METHOD

An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code. 1. An impedance calibration device , comprising:a variable impedance;an operational unit, used for receiving a first analog signal and a second analog signal and performing a difference operation to generate an output voltage, wherein the first analog signal has variation amount information of the variable impedance, and the second analog signal is a reference signal;an analog-digital converter, coupled to the operational unit, and used for receiving the output voltage to generate an adjustment code; anda controller, coupled to the analog-digital converter and the variable impedance, and used for adjusting a resistance value of the variable impedance according to the adjustment code.2. The impedance calibration device according to claim 1 , further comprising:a gain controller, coupled between the operational unit and the analog-digital converter, and used for adjusting a voltage of the output voltage.3. The impedance calibration device according to claim 2 , wherein the output voltage is mapped to a full dynamic range of the analog-digital converter.4. The impedance calibration device according to claim 1 , wherein the controller adjusts the resistance value of the variable impedance according to a maximum variation amount of the variable impedance and a full dynamic range of the analog-digital converter.5. The impedance calibration device according to claim 1 , wherein the first analog signal is a first current generated ...

Signal sensing circuit

A signal sensing circuit converts a received current input into a voltage output and provides the voltage output to an analog-to-digital converter (ADC) to generate a digital output signal. The voltage output is associated with a circuit having a first reference impedance, and a reference voltage of the ADC is associated with a circuit having a second reference impedance, wherein the circuit having the first reference impedance and the circuit having the second reference impedance are formed by the same material, so that the ratio between the changes in the current input and the changes in the value of the digital output signal is a constant.

TERMINATION CIRCUIT FOR ON-DIE TERMINATION

In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage. 1. A termination circuit for a terminal of a semiconductor device , the terminal associated with an expected voltage swing , the termination circuit comprising:a transistor connected between the terminal and a power supply at a supply voltage;analog control circuitry for controllably enabling and disabling on-die termination, comprising calibrator circuitry with access to a reference resistance, the calibrator circuitry configured to carry out a calibration process for selecting one of a plurality of analog calibration voltages that would cause the transistor to impart a resistance substantially equal to a multiple of the reference resistance if supplied thereto as gate voltage,wherein the control circuitry is configured to drive the gate of the transistor with said one of a plurality of analog calibration voltages when on-die termination is enabled, said one of a plurality of analog calibration voltages being outside a range of voltages defined by the supply voltage and the expected voltage swing.2. The termination circuit defined in claim 1 , wherein the supply voltage is Vdd claim 1 ,3. The termination circuit defined in ...

SEMICONDUCTOR INTEGRATED CIRCUIT

One embodiment provides a semiconductor integrated circuit, including: a first input wire; a second input wire; a first look-up table (LUT) comprising: a plurality of first memories; a first number of first switches connected to the first input wire; and a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and a second LUT including: a plurality of second memories; a third number of third switches connected to the second input wire; and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories. 1. A semiconductor integrated circuit , comprising:a first input wire;a second input wire; a plurality of first memories;', 'a first number of first switches connected to the first input wire; and', 'a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and, 'a first look-up table (LUT) comprising a plurality of second memories;', 'a third number of third switches connected to the second input wire; and', 'a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories., 'a second LUT comprising2. The semiconductor integrated circuit of claim 1 , further comprising:a multiplexer configured to select the information output from the first LUT and the information output from the second LUT.3. The semiconductor integrated circuit of claim 1 ,{'b': '2', 'wherein the second number is .'}4. The semiconductor integrated circuit of claim ...

PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS

In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc. 1. An integrated circuit , comprising: a L-level permutable switching network (L-PSN) ,{'b': 2', '1, 'claim-text': {'b': '2', 'claim-text': [{'b': 1', '1', '1', '1, 'for i=[:L], (I[i]/D[i])>, D[i]>, L≧, each of the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors;'}, {'b': '0', 'claim-text': {'b': 0', '1, 'sub': 'i=[1:L]', 'wherein (I[]/ΠD[i])>; and'}, 'an 0-th level of conductors of I[] number of conductors,'}, {'b': 1', '1', '1, 'claim-text': {'b': 1', '2', '1, 'sub': 'i=[1:L]', 'wherein D[L+]> and each of the D[L+] sets of conductors comprises Π=D[i] number of conductors;'}, 'an (L+)-th level of conductors of I[L+] number of conductors comprising D[L+] sets of conductors,'}], 'wherein the (L+) levels of conductors comprises, 'wherein the L-PSN comprises (L+) levels of conductors and (L+) sets of switches{'b': 1', '1', '1', '1, 'wherein each i-th set of the (L+) sets of switches comprises (I[i-]×D[i]) number of switches for i=[:L+];'}{'b': 1', '1', '1', '1', '1, 'wherein the I[i-] number of conductors of the (i-)-th level of conductors selectively couple to (I[i]/ D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective I[i-] number of switches of the i-th set of switches for i=[:L+] without requiring traversal of any other conductors;'}{'b': 1', '1', '1', '1, 'sub': 's', 'a j-th level of I[j] number of conductors comprising D[j] sets of (I[j]/D[j]) number of conductors for at least one j selected from [:L+], a prime number k> and D[j]=D[j]×(I[j-]/I[j]);'}{'b': 1', '1', '1, 'sub': s', 's, 'claim-text': [{'b': 1', '1', '1', '1', '1, 'sub': s', 's', 's, 'claim-text': {'sub': 's', 'wherein ...

NONVOLATILE MEMORY, ELECTRONIC APPARATUS, AND VERIFICATION METHOD

A gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to a memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to a reference cell array is included. An electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line. 1. A nonvolatile memory comprising:a memory cell array having a first bit line connected to N memory cells;a reference cell array having a second bit line connected to M reference cells, the M being smaller than the N;a comparator which compares a first electric current which flows along the first bit line with a second electric current which flows along the second bit line; anda gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in the N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in the M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to the memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to the reference cell array,wherein an electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current ...

PROGRAMMABLE LSI

An object is to achieve both suppression of operation delay and reduction in power consumption of a programmable LSI. A compiler generates, from source code, configuration data needed in a programmable LSI and a time schedule that shows a timing of using the data in the programmable LSI (a timing at which the data is held in a configuration memory) and a timing of storing the data in the programmable LSI before the data is used. Supply of new configuration data to the programmable LSI from the outside (storage of new configuration data) and data rewrite in the configuration memory in the programmable LSI (circuit reconfiguration) are performed independently and concurrently on the basis of the time schedule. 1. A semiconductor device comprising:a programmable LSI comprising a logic circuit unit; anda compiler configured to generate a time schedule and plural pieces of configuration data,wherein the compiler is configured, independently and concurrently on the basis of the time schedule, to store the plural pieces of configuration data in the programmable LSI and reconfigure a configuration of the logic circuit unit in accordance with each of the plural pieces of configuration data.2. The semiconductor device according to claim 1 ,wherein the programmable LSI further comprises a bank group, andwherein the bank group is configured to store the plural pieces of configuration data.3. The semiconductor device according to claim 2 ,wherein the bank group comprises a plurality of memory cells, andwherein each of the memory cells comprises an input bit line, an output bit line, an input word line, an output word line, a reference potential line, a first transistor, a second transistor, and a third transistor.4. The semiconductor device according to claim 3 ,wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,wherein the second transistor comprises a ...

METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT WITH MICRO CIRCUITS AND POST PROCESSING

A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit. 1. A computer-implemented method of camouflaging an application specific integrated circuit (ASIC) , wherein the ASIC comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions , the method comprising the steps of:identifying, using the computer, at least one gap between the plurality of interconnected functional logic cells having no functional logic therein;placing, using the computer, one filler cell or combination of filler cells into the identified gap, wherein at least one of the filler cells has a physical design layout similar to but different from at least one of the functional logical cells; anddefining, using the computer, a routing of the placed one filler cell or combination of filler cells;wherein the placed one filler cell or routed combination of filler cells camouflages the interconnected functional logic cells and the placed one filler cell or combination of filler cells perform none of the one or more ASIC logical functions.2. The method of claim 1 , wherein:at least one of the filler cells has a physical design layout that is substantially the same physical design layout as at least one of the interconnected functional logic cells.3. The method of claim 2 , wherein the physical design layout of at least one of the filler cells is modified from the physical design layout of the at least one functional logical ...

Program Binding System, Method and Software for a Resilient Integrated Circuit Architecture

The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established.

METHOD FOR DRIVING SEMICONDUCTOR DEVICE

A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included. 1. A method for driving a semiconductor device ,the semiconductor device comprising:a memory comprising a first transistor, a first capacitor, a second transistor, and a second capacitor;a multiplexer comprising a third transistor and a fourth transistor;a first input terminal configured to input a first signal, and a second input terminal configured to input a second signal; andan output terminal configured to output the first signal or the second signal,wherein one of a source and a drain of the first transistor is electrically connected to the first capacitor,wherein one of a source and a drain of the second transistor is electrically connected to the second capacitor,wherein a source of the third transistor is electrically connected to the first input terminal, and a drain of the third transistor is electrically connected to the output terminal, andwherein a source the fourth transistor is electrically connected to the second input terminal, and a drain of the fourth transistor is electrically connected to the output terminal,the method comprising the steps of:holding a first potential in one of a first node and a second node; ...

Voltage compensated level-shifter

Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.

Integrated circuit and method for operating the same

A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock.

SEMICONDUCTOR DEVICE, METHOD OF RETRIEVING DATA, AND MICROCOMPUTER

A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing inverted data of the reference data; a sense amplifier unit; and a data output unit. In a first retrieving process, the sense amplifier unit differentially amplifies the data and the reference data, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference. In a second retrieving process, the sense amplifier unit differentially amplifies the data and the inverted data, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the predetermined retrievable voltage difference. The data output unit determines and outputs the data according to a result of the first retrieving process and the second retrieving process. 1. A semiconductor device comprising:a data memory cell for storing data;a reference data memory cell for storing reference data to be compared with the data;an inverted data memory cell for storing inverted data of the reference data;a sense amplifier unit; anda data output unit,wherein said sense amplifier unit is configured to perform a first retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the reference data stored in the reference data memory cell, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference,said sense amplifier unit is configured to perform a second retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the inverted data stored in the inverted data memory cell, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the ...

SEMICONDUCTOR MEMORY DEVICE AND ERASURE VERIFICATION METHOD FOR SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device including a plurality of memory blocks each including a bit line to which a plurality of memory cells are connected, and a dummy bit line to which a plurality of dummy cells are connected; a reference cell; and a sense amplifier including a first input terminal to which selected memory cell of the plurality of memory cells is to be electrically connected via the bit line, and a second input terminal to which the reference cell is to be electrically connected, the dummy bit line of one memory block of the plurality of memory blocks different from another memory block of the plurality of memory blocks including the selected memory cell being to be electrically connected to the second input terminal of the sense amplifier. 1. A semiconductor memory device comprising:a plurality of memory blocks each including a bit line to which a plurality of memory cells are connected, and a dummy bit line to which a plurality of dummy cells are connected;a reference cell; anda sense amplifier including a first input terminal to which a selected memory cell of the plurality of memory cells is to be electrically connected via the bit line, and a second input terminal to which the reference cell is to be electrically connected,the dummy bit line of one memory block being to be electrically connected to the second input terminal of the sense amplifier, the one memory block being different from another memory block including the selected memory cell.2. The semiconductor memory device according to claim 1 , whereinthe semiconductor memory device is an electrically erasable nonvolatile semiconductor memory device, andthe dummy bit line of the one memory block is electrically connected to the second input terminal of the sense amplifier when an erasure verification of the selected memory cell is performed.3. The semiconductor memory device according to claim 2 , whereinwhen the erasure verification is performed, the plurality of dummy cells are set to erase ...

Generating Interface Adjustment Signals in a Device-To-Device Interconnection System

Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

ON-DIE TERMINATION CIRCUIT

An on-die termination circuit includes: a clock signal generation block configured to output a clock signal in response to a clock enable signal, a termination block configured to perform a termination operation on an input/output pad in response to the clock signal, a first termination control signal, and a second termination control signal, a first termination control block configured to generate the first termination control signal in response to the clock signal and a latency control signal, a second termination control block configured to control a latency of a second command and to generate the second termination control signal in response to the clock signal and the latency control signal, and a clock enable signal generation block configured to generate the clock enable signal in response to the first command, the first termination control signal, and the second is command. 2. The on-die termination circuit according to claim 1 , wherein the first command corresponds to an on-die termination command.3. The on-die termination circuit according to claim 1 , wherein the second command corresponds to a write command.4. The on-die termination circuit according to claim 1 , wherein the clock signal generation block corresponds to a delay-locked loop.5. The on-die termination circuit according to claim 1 , wherein the first termination control block comprises:a timing control block configured to control the timing of an external command by a set time and to generate the first command;a variable delay unit configured to delay the first command and to generate a preliminary control signal; anda first latency shift block configured to delay the preliminary control signal by a predetermined latency in response to the latency is control signal on the basis of the delay-locked clock signal, and to generate the first termination control signal.6. The on-die termination circuit according to claim 5 , wherein the first latency shift block comprises:a shift control unit ...

APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES

A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface. 110-. (canceled)11. A memory interface comprising:a data output signal for providing, from a memory circuit, configuration data for configuring at least one of a first integrated circuit and a second integrated circuit; and the first integrated circuit is configured to initiate its configuration by providing the operation code to the memory device via the data input signal of the memory interface, and', 'the first integrated circuit is configured to initiate configuration of the second integrated circuit by passing a signal to the second integrated circuit., 'a data input signal for providing an operation code from the first integrated circuit to the memory circuit, wherein12. The memory interface of claim 11 , wherein a chip enable output of the first integrated circuit couples to a chip enable input of the second integrated circuit and wherein passing a signal to the second integrated circuit comprises asserting a chip enable signal from the chip enable output of the first integrated circuit to the chip enable input of the second integrated circuit.13. The memory interface of claim 11 , wherein the memory interface further comprises a chip enable signal to perform at least one of the group of selecting claim 11 , deselecting claim 11 , enabling claim 11 , and disabling the memory circuit.14. The memory interface of claim 11 , wherein the memory interface further comprises a handshaking signal for indicating availability of the memory circuit to the first integrated circuit.15. The memory interface of claim 11 , wherein the memory interface further ...

SEMICONDUCTOR DEVICE

A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed. 1. A semiconductor device , comprising:a first memory cell;a second memory cell;a first bit line extending in a first direction and being connected to the first memory cell;a second bit line extending in the first direction and being connected to the second memory cell;a first power line; anda sense amplifier circuit comprising a first transistor and a second transistor, the first transistor including a first gate electrode that is formed over a first channel region and connected to the first bit line, a first diffusion region that is connected to the second bit line and includes a first side edge defining the first channel region and a second diffusion region that is connected to the first power line and includes a second side edge defining the first channel region, and the second transistor including a second gate electrode that is formed over a second channel region and connected to the second bit line, a third diffusion region that is connected to the first bit line and includes a third side edge defining the second channel region and a fourth diffusion region that is ...

Low Supply Voltage Logic Circuit

A low supply voltage logic circuit includes a first current source operable to generate a first current dependent on a first control signal and to generate a first leakage current. A second current source is operable to generate a second current dependent on a second control signal and to generate a second leakage current. A third current source has a third current path between the output terminal and the first supply voltage terminal and is operable to generate a third current through the third current path to compensate for the second leakage current. A fourth current source has a fourth current path between the output terminal and the second supply voltage terminal and is operable to generate a fourth current through the fourth current path to compensate for the first leakage current.

SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION

A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments. 1a connector for connecting to the outlet for coupling to the digital data signal carried over the wire pair; anda termination circuit selectively couplable to said connector and constructed for terminating the digital data signal propagated over the wire pair when said device is connected to said connector,wherein said device is switchable between a first state in which said termination circuit is coupled to said connector and a second state in which said termination circuit is not coupled to said connector.. A device for use with a wire pair in walls of a building and connected to an outlet, the wire pair being connected in a bus topology for carrying a digital data signal, said device comprising: This is a continuation of U.S. application Ser. No. 13/245,433, filed on Nov. 14, 2011, which is a continuation of U.S. application Ser. No. 12/724,952, filed on Mar. 16, 2010, which is a continuation of U.S. application Ser. No. 12/252,025, filed Oct. allowed, which is a continuation of U.S. application Ser. No. 12/026,321, filed Feb. 5, 2008, now U.S. Pat. No. 7,453,284, issued on Nov. 18, 2008, which is a continuation of U.S. application Ser. No. 11/346,396, filed on Feb. 3, 2006, now U.S. Pat. No. 7,336,096, issued on Feb. 26, 2008, which is a division of U.S. application Ser. No. 11/100,453, filed on Apr. 7, 2005, now U.S. Pat. No. 7,068,066, issued on Jun. 27, 2006, which is a continuation of U.S. application Ser. No. ...

Reconfigurable integrated circuit device and writing method thereof

A reconfigurable integrated circuit device includes a memory unit for storing configuration information. The memory unit has a nonvolatile memory transistor having a gate connected to a first wire, a first terminal connected to a second wire, and a second terminal connected to a third wire. The memory unit also includes a switch circuit connected to the third wire. The switch circuit alters the configuration of the integrated circuit device by, for example, opening and closing to make wiring connections or disconnections. The integrated circuit device additionally includes a data supply circuit for supplying bit data and a first power supply circuit for supplying voltages to the first wire for storing bit data in the first nonvolatile memory transistor and for storing bit data as a charge level on the third wire.

Semiconductor device

A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor.

COMPACT VOLATILE/NON-VOLATILE MEMORY CELL

The invention concerns a memory device comprising at least one memory cell comprising: a first transistor () coupled between a first storage node () and a first supply voltage (GND, V); a second transistor () coupled between a second storage node () and said first supply voltage, control terminals of the first and second transistors being coupled to the second and first storage nodes respectively; and a single resistance switching element (), wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances (R, R), wherein said first storage node is coupled to a first access line (BL) via a third transistor () connected to said first storage node, and said second storage node is coupled to a second access line (BLB) via a fourth transistor () connected to said second storage node. 1. A memory device comprising at least one memory cell comprising:a first transistor coupled between a first storage node and a first supply voltage;a second transistor coupled between a second storage node and said first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; anda single resistance switching element, wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances, wherein said first storage node is coupled to a first access line via a third transistor, and said second storage node is coupled to a second access line via a fourth transistor.2. The memory device of claim 1 , wherein said single resistance switching element is coupled between said first transistor and said first supply voltage claim 1 , a first branch of said memory cell comprising said element and said first transistor claim 1 , and a second branch of said memory cell comprising said ...

On-chip impedance network with digital coarse and analog fine tuning

System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

METHODS AND APPARATUSES INCLUDING A VARIABLE TERMINATION IMPEDANCE RATIO

Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions of a termination circuit coupled to an output pin are selectively activated to change an impedance of the termination circuit to change the centerline voltage of the data signal driven to the output pin. One such apparatus includes pull-up impedances and pull-down impedances that can be activated to change the centerline voltage of the data signal. Additional embodiments are also described. 1. A memory device comprising:a memory array for storing data;a termination register configured to store termination values;a termination control circuit coupled to the termination register; andan I/O circuit, coupled to the memory array and the termination control circuit, for transmitting data from and receiving data to the memory array, the I/O circuit comprising a plurality of driver and receiver circuits, each of the plurality of driver and receiver circuits having an adjustable pull-up impedance and an adjustable pull-down impedance that are adjusted by the termination control circuit in response to the stored termination values.2. The memory device of and further comprising a control circuit to control operation of the memory device claim 1 , the control circuit coupled to the termination register.3. The memory device of wherein the control circuit is configured to write the termination values to the termination register.4. The memory device of wherein each adjustable pull-up impedance and each adjustable pull-down impedance comprises a plurality of resistance circuits coupled together in parallel claim 1 , each resistance circuit having a fuse in series with a resistance.5. The memory device of wherein the plurality of resistance circuits for the adjustable pull-up impedance are coupled in parallel between an output pin of the memory device and a supply voltage.6. The memory device of wherein the plurality of ...

DATA VERIFICATION DEVICE AND A SEMICONDUCTOR DEVICE INCLUDING THE SAME

A semiconductor device includes a data verification device. The data verification device includes a data storage unit for storing data to be input to a memory region in response to a first or second control signal, an input data verifier for deactivating an output of a sense amplifier in response to the first control signal and transmitting the input data stored in the data storage unit to an external pad, and a sense-amplifier verifier for transmitting the input data stored in the data storage unit to the sense amplifier upon in response to the second control signal. 1. A data verification device comprising:a data storage unit configured to store input data in response to a first or second control signal generated in a test mode;an input data verifier configured to deactivate an output of a sense amplifier in response to the first control signal, and transmit the input data provided by the data storage unit to an external pad; anda sense-amplifier verifier configured to transmit the input data provided by the data storage unit to the sense amplifier in response to the second control signal, wherein the sense amplifier senses the input data transmitted thereto and transmits sensed data to the external pad.2. The data verification device according to claim 1 , wherein the data storage unit includes a latch that stores the input data in response to the first or second control signal.3. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the input data verifier in response to the first control signal.4. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the sense-amplifier verifier in response to the second control signal.5. The data verification device according to claim 1 , wherein the data storage unit is coupled to a data input buffer claim 1 , and receives the input data through the data input buffer and stores the input data.6. The data verification device ...

CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES

Clock, distribution circuitry for a structured ASIC device includes a deterministic portion, and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served, from that predetermined, location. 1. (canceled)2. Clock distribution circuitry for an integrated circuit , the clock distribution circuitry comprising:a deterministic clock distribution portion; andat least one user-configurable clock distribution conductor located within a predetermined area of the integrated circuit, where configurable logic elements (LEs) on the predetermined area of the integrated circuit are custom-configurable by a user to selectively:provide clock distribution buffer circuitry for routing, through the user-configurable clock distribution conductor, a clock signal from the deterministic clock distribution portion to clock utilization circuitry within the predetermined area of the integrated circuit, orprovide logic functions when not providing the clock distribution buffer circuitry.3. The clock distribution circuitry defined in claim 2 , wherein the LEs are operable to provide logic functions in response to being released from routing the clock signal to the clock utilization circuitry at any of various locations within the predetermined area.4. The clock distribution circuitry defined in claim 2 , wherein the deterministic clock distribution portion includes:a predetermined arrangement of conductor segments; anda plurality of buffer circuits between successive conductor segments of the conductor segments.5. The clock distribution circuitry defined in claim 2 , wherein the LEs employ ...

Apparatus and methods for digital configuration of integrated circuits

Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.

Circuits and Methods of a Self-Timed High Speed SRAM

Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power. 1. A SRAM memory , comprising:a plurality of SRAM cells having a bitlines (BL) and wordline (WL) that can be selected for access;at least one reference cell having a reference bitline in (BLin) and a reference bitline (RBL) that can be selected from one of a plurality of wordlines or from at least one reference wordline, the reference cell being selectable not earlier than any selected SRAM cells and the RBL being activatable not later than any selected SRAM cells to activate the selected BL;at least one sense amplifier to sense signals coupled to the selected BL from the at least one selected SRAM cell and convert the signals into digital data; andwherein the sense amplifier can be activated by the RBL signal to track the wordline and BL propagating delay.2. A SRAM memory as recited in claim 1 , wherein the at least one reference cell is placed near the far end of a driver to drive a selected wordline or a reference wordline.3. A SRAM memory as recited in claim 1 , wherein the reference cell has at least one inverter with an input coupled to BLin and an output NB coupled to RBL claim 1 , and wherein the RBL is activated by setting BLin at a voltage close to a supply voltage once the wordline or reference wordline is selected.4. A SRAM memory as ...

CENTRAL INPUT BUS TERMINATION TOPOLOGY

An input bus termination (IBT) system for an integrated circuit that includes a termination switch coupled to a plurality of input lines of an integrated circuit, each of the plurality of input lines coupled to a common node of the termination switch through a resistor, wherein the termination switch is to generate a termination voltage at the common node based on the composite potential generated by the plurality of input lines at the common node when an input signal is received across the plurality of input lines. 1. An input bus termination (IBT) system for an integrated circuit , comprising:a termination switch coupled to a plurality of input lines of an integrated circuit, each of the plurality of input lines coupled to a common node of the termination switch through a resistor, wherein the termination switch is to generate a termination voltage at the common node based on the composite potential generated by the plurality of input lines at the common node when an input signal is received across the plurality of input lines.2. The IBT system of claim 1 , wherein the termination switch comprises:a first circuit to increase the voltage at the common node when the composite potential falls below a first threshold voltage.3. The IBT system of claim 2 , wherein the termination switch further comprises:a second circuit to decrease the voltage at the common node when the composite potential rises above a second threshold voltage.4. The IBT system of claim 3 , wherein the first and second circuits are coupled together at the common node.5. The IBT system of claim 4 , further comprising a capacitor that couples the common node to a ground or a common power supply line.6. The IBT of claim 4 , wherein the termination voltage is between the first and second threshold voltages.7. The IBT system of claim 1 , wherein the resistors coupling each of the plurality of input lines to the common node are of equal resistance values.8. The IBT of claim 1 , wherein the termination ...

System and Method For Reducing Reconfiguration Power Usage

A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

CONFIGURABLE DECODER WITH APPLICATIONS IN FPGAS

The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address. The invention may include a second reconfigurable memory device that outputs the z-bit source word, based upon an x-bit source address input to the second memory device, where x Подробнее

Mixed-Signal Integrated Circuit

A mixed-signal integrated circuit includes an analog circuit comprising at least one digital block embedded in the analog circuit, the at least one digital block comprising a plurality of functional bits and a plurality of configuration bits, the plurality of functional bits providing for a functionality of the analog circuit according to a designed functionality and the plurality of configuration bits being usable for configuring a plurality of operational modes of the analog circuit; and a digital circuit comprising a scan chain configured to scan at least part of the functional bits of the digital block embedded in the analog circuit with respect to the designed functionality, wherein the scan chain is further configured to set at least part of the configuration bits of the digital block embedded in the analog circuit according to a selected operational mode of the plurality of operational modes of the analog circuit.

REGISTER ARRAY HAVING GROUPS OF LATCHES WITH SINGLE TEST LATCH TESTABLE IN SINGLE PASS

A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal. 1. A register array comprising: a first latch;', 'a second latch; and', 'a test latch connected to the first latch and the second latch,, 'a plurality of groups of latches, each of the groups of latches comprisesduring functional operation the first latch and the second latch process data, in response to the same read/write clock signal, and a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch;', 'a single scan signal is input to the first latch; and', 'the first latch and the second latch are connected to the test latch to cause the single scan signal to cascade from the first latch through the test latch to the second latch, and be output by the second latch, to use a single test clock and the single scan signal to test both the first latch and the second latch within a single cycle of the original test clock signal., 'during test operation2. The register array according to claim 1 , the first latch and the second latch are physically symmetrical.3. The register array according to claim 1 , the first latch and the second latch each comprise a ...

Electronic Systems For Integrated Circuits And Voltage Regulators

An electronic system includes first, second, third, and fourth integrated circuit dies. The third integrated circuit die has a first voltage regulator circuit. A supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a supply voltage input of the first integrated circuit die. The first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage. The fourth integrated circuit die has a second voltage regulator circuit that generates a second supply voltage in response to the first power ready signal. A supply voltage output of the second voltage regulator circuit is coupled to provide the second supply voltage to a supply voltage input of the second integrated circuit die. 1. An electronic system comprising:first and second integrated circuit dies;a third integrated circuit die comprising a first voltage regulator circuit, wherein a supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a supply voltage input of the first integrated circuit die, and wherein the first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage; anda fourth integrated circuit die comprising a second voltage regulator circuit that generates a second supply voltage in response to the first power ready signal, wherein a supply voltage output of the second voltage regulator circuit is coupled to provide the second supply voltage to a supply voltage input of the second integrated circuit die.2. The electronic system of further comprising:a fifth integrated circuit die, wherein the second voltage regulator circuit generates a second power ready signal that indicates when the second supply voltage has reached a second threshold voltage; anda sixth integrated circuit die comprising a third voltage regulator circuit ...

HYSTERESIS CONTROL SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided. 1. A programmable logic device (PLD) comprising:a first hysteresis control circuit configured to generate a first hysteresis control signal based on a core voltage and a first input/output (I/O) voltage; and a first buffer circuit configured to receive a first input voltage and generate a first buffer voltage based on the first input voltage;', 'a first hysteresis generator configured to generate a first hysteresis voltage based on the first hysteresis control signal and the first I/O voltage; and', 'a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the first hysteresis voltage., 'an I/O cell associated with an I/O fabric of the PLD and powered by the first I/O voltage, the I/O cell comprising2. The PLD of claim 1 , further comprising a processing circuit configured to:receive configuration data associated with the PLD; andprogram an array of configuration memory cells of the PLD based on the configuration data, the array of configuration memory cells comprising a plurality of logic block memory cells associated with a logic fabric ...

Method and Apparatus for Collecting Signal Values in FPGA Based Emulation Machine

Systems and methods for collecting signal values in FPGA based emulation machine. A single LUT is used to observe three observable points within a VLSI. A 6-input LUT is used to implement scan cells. Each scan cell implements a 4:1 multiplexer using the 6-input LUT. Each scan cell also uses three registers. The first and second register are used to sample and hold signals from the first two of the three observable points associated with that scan cell. The third register is used to capture the output of the 4:1 multiplexer. 1. A scan cell of a field programmable logic array (FPGA) based emulation machine , the scan cell comprising:a) four scan cell data inputs,b) a scan cell data output;c) two scan cell selection control inputs;d) a scan cell clock input;e) a first register having a register clock input coupled to the scan cell clock input, a D-input coupled to a first of the three scan cell data inputs and a Q-output;f) a second register having a register clock input coupled to the scan cell clock input, a D-input coupled to a second of the three scan cell data inputs and a Q-output; i. the first multiplexer data input coupled to the Q-output of the first register;', 'ii. the second multiplexer data input coupled to the Q-output of the second register;', 'iii. the third multiplexer input coupled to the third scan cell data input; and', 'iv. the fourth multiplexer input coupled to the fourth scan cell data input;', 'v. the first multiplexer selection control input coupled to a first of the two scan cell selection control inputs;', 'vi. the second multiplexer selection control input coupled to the second scan cell selection control input; and, 'g) a multiplexer having 4 multiplexer data inputs, two multiplexer selection control inputs and a multiplexer data outputh) third register having a register clock input coupled to the scan cell clock input, a D-input coupled to the multiplexer data output and a Q-output coupled to the scan cell data output.2. The scan cell of ...

TECHNOLOGY TO DYNAMICALLY MODULATE MEMORY DEVICE READ GRANULARITY

Technology to dynamically modulate read granularity of a memory device. A computing system may include a controller and one or more memory devices coupled to the controller, the one or more memory devices including instructions, which when executed by the controller, may cause the computing system to determine whether a read to a memory device satisfies a sub-page read policy. In addition, the instructions, when executed, may cause the computing system to issue a sub-page read command to retrieve data from the memory device at sub-page granularity when the read satisfies the sub-page read policy. Moreover, the instructions, when executed, may cause the computing system to issue a full-page read command to retrieve the data at full-page granularity when the read does not satisfy the sub-page read policy or when a read for a segment of sequentially stored data does not satisfy the sub-page read policy. 1. A computing system comprising:a controller; andone or more memory devices coupled to the controller, the one or more memory devices including instructions, which when executed by the controller, cause the computing system to:determine whether a read to a memory device satisfies a sub-page read policy; andissue a sub-page read command to retrieve data from the memory device at sub-page granularity when the read satisfies the sub-page read policy.2. The computing system of claim 1 , wherein the instructions claim 1 , when executed claim 1 , cause the computing system to:determine whether the read satisfies a physical requirement;determine whether the read satisfies a random read requirement; anddetermine whether the read satisfies a maximum sub-page read size.3. The computing system of claim 1 , wherein the instructions claim 1 , when executed claim 1 , cause the computing system to:determine whether a read size of the read matches a current sub-page read size; andset the current sub-page read size to the read size to implement a new sub-page read size.4. The computing ...

IMPEDANCE COMPENSATION BASED ON DETECTING SENSOR DATA

A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold. 122-. (canceled)23. A memory device comprising:a register selectively writeable by the memory device with an impedance calibration update flag, to indicate to a memory controller that an impedance calibration update is ready at the memory device; andI/O (input/output) hardware to receive commands from the memory controller when coupled to the memory controller, including an impedance calibration latch signal (ZQCAL LATCH) in response to detection by the memory controller of the impedance calibration update flag being set, to set a new calibration setting in the memory device.24. The memory device of claim 23 , wherein the I/O hardware is to periodically receive a polling request from the memory controller to check the impedance calibration update flag.25. The memory device of claim 23 , wherein the register comprises a Mode Register claim 23 , and the I/O hardware is to periodically receive a command to read the Mode Register to check the impedance calibration update flag.26. The memory device of claim 23 , wherein the I/O hardware is to receive the impedance calibration latch signal with receipt first of an impedance calibration start signal (ZQCAL START).27. The memory device of claim 23 , wherein the memory device is to compute a comparison between a previous impedance calibration setting an updated calibration setting claim 23 , and only set the impedance calibration update flag ...

Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In an embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an atomic operation when an incoming operand set arrives at the plurality of processing elements.

PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH MEMORY SYSTEM PERFORMANCE, POWER REDUCTION, AND ATOMICS SUPPORT FEATURES

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system. 1. A processor comprising:a plurality of processing elements;an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; anda streamer element to prefetch the incoming operand set from two or more levels of a memory system.2. The processor of claim 1 , wherein the streamer element is to prefetch based on a programmable memory access pattern.3. The processor of claim 2 , wherein the streamer element includes a plurality of tracking registers to fetch ahead of a demand stream.4. The processor of claim 3 , wherein the plurality of tracking registers includes an x-dimension register to fetch ahead in a first dimension of a multidimensional streaming fetch pattern.5. The processor of claim 4 , wherein the plurality of tracking registers includes a y-dimension ...

PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH PERFORMANCE, CORRECTNESS, AND POWER REDUCTION FEATURES

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. At least one of the plurality of processing elements includes a plurality of control inputs. 118-. (canceled)19. The processor of claim 20 , wherein:the at least one of the plurality of processing elements is configurable as a floating-point multiplier, at least an other of the plurality of processing elements is configurable as a floating-point adder, and the at least one and the at least an other of the plurality of processing elements are coupled together to perform a fused multiply-add.20. A processor comprising:a plurality of processing elements, wherein at least one of the processing elements is to perform a floating-point operation with selectable precision control; andan interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. This invention was made with Government support under contract number H98230A-13-D-0124 awarded by the Department of Defense. The Government has ...

Fast Fourier Transform (FFT) Based Digital Signal Processing (DSP) Engine

A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine. 1. A digital signal processing (DSP) block comprising: a first FFT engine configured to convert a signal between a time-domain and a frequency-domain, wherein the first FFT engine is a fixed size FFT engine; and', 'a second FFT engine communicatively coupled to the first FFT engine, wherein the second FFT engine is a variable size FFT engine., 'a Fast Fourier Transform (FFT) unit configured to perform an FFT operation, the FFT unit comprising2. The DSP block of claim 1 , the FFT unit comprising a scale/offset block configured to perform a multiplication operation claim 1 , an addition operation claim 1 , or a combination thereof claim 1 , wherein the scale/offset block is communicatively coupled to at least one of the first FFT engine claim 1 , the second FFT engine claim 1 , or a combination thereof.3. The DSP block of claim 1 , comprising an input buffer configured to receive a dataset and configured to route the dataset to the FFT unit.4. The DSP block of claim 3 , comprising an output buffer configured to receive an output of the FFT unit.5. The DSP block of claim 4 , comprising a feedback loop configured to route the output to the input buffer.6. The DSP block of claim 5 , comprising a second FFT unit claim 5 , wherein the second FFT unit is configured to receive ...

Techniques For Reducing Uneven Aging In Integrated Circuits

A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations. 1. A computer readable non-transitory medium storing executable instructions for reducing uneven aging in a programmable integrated circuit , the executable instructions comprising:instructions executable by a design tool to generate configurations of a user design for the programmable integrated circuit, wherein each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations;instructions executable by the design tool to direct configuration circuitry in the programmable integrated circuit to implement the user design in a first one of the configurations; andinstructions executable by the design tool to direct the configuration circuitry to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.2. The computer readable non-transitory medium of further comprising:instructions executable by the design tool to direct the configuration circuitry to move the user design from the second one of the configurations back to the first ...