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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 52278. Отображено 100.
05-01-2012 дата публикации

Nonvolatile memory apparatus

Номер: US20120002480A1
Автор: In Suk YUN
Принадлежит: Hynix Semiconductor Inc

A nonvolatile memory device includes: a data transmission line configured to transmit internal configuration data; a data path control unit configured to control a data transmission path direction of the data transmission line according to control of a test signal; and a configuration data latch unit configured to latch a signal transmitted through the data transmission line or drive a latched signal to the data transmission line, according to control of the test signal.

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Номер записи: 1
05-01-2012 дата публикации

Output enable signal generation circuit of semiconductor memory

Номер: US20120002493A1
Автор: Hee Jin Byun
Принадлежит: Hynix Semiconductor Inc

An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).

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Номер записи: 2
24-10-2017 дата публикации

Отказоустойчивый цифровой преобразователь информации для управления дискретными процессами

Номер: RU0000174640U1
Автор: Виктор Федорович Мелехин, Игорь Валерьевич Егоров
Принадлежит: Федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский политехнический университет Петра Великого"

Полезная модель относится к отказоустойчивым цифровым преобразователям информации для управления дискретными процессами. Технический результат заключается в повышении надежности преобразователя. Указанный результат достигается за счет применения отказоустойчивого цифрового преобразователя информации для управления дискретными процессами, который содержит мажорирующий блок, и конечный автомат с памятью, включающий входную комбинационную схему, блок памяти, выходную комбинационную схему и цепь обратной связи, подключенную ко входу входной комбинационной схемы. В качестве блока памяти установлен троированный блок, и выходы каждого экземпляра троированного блока подключены к входам мажорирующего блока, выходы которого подключены ко входам входной комбинационной схемы и по цепи обратной связи со входами входной комбинационной схемы, мажорирующий блок содержит два элемента задержки, выходы которых подключены к двум экземплярам троированного блока памяти, а их входы подключены к внешнему входу синхронизации, мультиплексор, входы которого подключены к выходам входной комбинационной схемы и к выходам мажорирующего блока, а выход подключен к входам блоков памяти, и блок регистрации ошибок, входы которого подключены к выходам мажорирующего блока и внешнему входу синхронизации. Ц 1 174640 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ > © а х& < р. — = о) >= „> 2 272 р... И 2%. ее п РЦ ‘’ (50) МПК СОбЕ 11007 (2006.01) (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2017120753, 14.06.2017 (24) Дата начала отсчета срока действия патента: 14.06.2017 Дата регистрации: 24.10.2017 Приоритет(ы): (22) Дата подачи заявки: 14.06.2017 (45) Опубликовано: 24.10.2017 Бюл. № 30 Адрес для переписки: 195251, Санкт-Петербург, ул. Политехническая, 29, Центр интеллектуальной собственности ФГАОУ ВО "СПбПУ" (72) Автор(ы): Егоров Игорь Валерьевич (КП), Мелехин Виктор Федорович (КП) (73) Патентообладатель(и): федеральное государственное автономное ...

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Номер записи: 3
05-01-2012 дата публикации

Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction

Номер: US20120005420A1
Автор: Christopher S. Johnson
Принадлежит: Round Rock Research LLC

One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

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Номер записи: 4
12-01-2012 дата публикации

Semiconductor memory device and method of operating the same

Номер: US20120008429A1
Автор: Mi Sun Yoon
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the original data groups. The semiconductor memory device also includes data decoding logic for generating the original data groups from the converted data groups and the inverted flag data. A peripheral circuit may be enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells. A control logic may be enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit.

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Номер записи: 5
12-01-2012 дата публикации

Precharging circuit and semiconductor memory device including the same

Номер: US20120008446A1
Автор: Seung-Bong Kim
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.

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Номер записи: 6
19-01-2012 дата публикации

Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory

Номер: US20120014185A1
Автор: Shigekazu Yamada
Принадлежит: Micron Technology Inc

An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.

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Номер записи: 7
26-01-2012 дата публикации

Dynamic impedance control for input/output buffers

Номер: US20120019282A1
Автор: Bruce Millar
Принадлежит: Mosaid Technologies Inc

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

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Номер записи: 8
02-02-2012 дата публикации

Semiconductor memory apparatus having sense amplifier

Номер: US20120026773A1
Автор: Myoung Jin LEE
Принадлежит: Hynix Semiconductor Inc

Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

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Номер записи: 9
02-02-2012 дата публикации

Managed hybrid memory with adaptive power supply

Номер: US20120026802A1
Автор: Emanuele Confalonieri
Принадлежит: Individual

Subject matter disclosed herein relates to a memory device, and more particularly to a managed hybrid memory that includes a power supply.

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Номер записи: 10
09-02-2012 дата публикации

Level shifter for use with memory arrays

Номер: US20120033508A1
Автор: Chad A. Adams, Elizabeth L. Gerhard, Jeffrey M. Scherer, Sharon H. Cesky
Принадлежит: International Business Machines Corp

In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from the first voltage domain to the second voltage domain; and (4) isolation circuitry that selectively isolates the first voltage domain from the second voltage domain so as to selectively prevent current flow between the first voltage domain and the second voltage domain. Numerous other aspects are provided.

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Номер записи: 11
09-02-2012 дата публикации

Apparatus and methods for optically-coupled memory systems

Номер: US20120036303A1
Автор: Kevin J. Ryan, Terry R. Lee
Принадлежит: Round Rock Research LLC

Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.

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Номер записи: 12
16-02-2012 дата публикации

Scatter-Gather Intelligent Memory Architecture For Unstructured Streaming Data On Multiprocessor Systems

Номер: US20120042121A1
Автор: Christopher J. Hughes, Daehyun Kim, Partha Kundu, Yen-Kuang Chen
Принадлежит: Individual

A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

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Номер записи: 13
16-02-2012 дата публикации

Memory systems and memory modules

Номер: US20120042204A1
Автор: Michael John Sebastian Smith, Suresh Natarajan Rajan
Принадлежит: Google LLC

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

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Номер записи: 14
01-03-2012 дата публикации

Sampling phase correcting host controller, semiconductor device and method

Номер: US20120049919A1
Автор: Masayoshi Murayama, Noriyo Fujii
Принадлежит: Toshiba Corp

One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

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Номер записи: 15
01-03-2012 дата публикации

Synchronous semiconductor memory device

Номер: US20120051159A1
Автор: Kang-Youl Lee
Принадлежит: Hynix Semiconductor Inc

A synchronous semiconductor memory device includes a data alignment reference pulse generation unit configured to generate a data alignment reference pulse in response to a data strobe signal, a data alignment suspension signal generation unit configured to generate a data alignment suspension signal in response to the data alignment reference pulse, a data strobe termination signal, and a write pulse, and a data alignment unit configured to align input data in response to the data alignment reference pulse and stop aligning the input data in response to the data alignment suspension signal.

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Номер записи: 16
08-03-2012 дата публикации

Memory Device Having Multiple Power Modes

Номер: US20120057424A1
Автор: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Richard M. Barth
Принадлежит: Individual

A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

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Номер записи: 17
15-03-2012 дата публикации

Pre-charge sensing scheme for non-volatile memory (nvm)

Номер: US20120063238A1
Автор: Avri Harush, Oleg Dadashev, Yaal Horesh, Yoram Betser
Принадлежит: Individual

The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.

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Номер записи: 18
15-03-2012 дата публикации

Digital frequency locked delay line

Номер: US20120063551A1
Автор: Curt Schnarr
Принадлежит: Individual

A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.

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Номер записи: 19
15-03-2012 дата публикации

Apparatus and method for read preamble disable

Номер: US20120066433A1
Автор: Clifford Alan Zitlaw, Feng Liu, Wendy P. Lee-kadlec
Принадлежит: SPANSION LLC

A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.

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Номер записи: 20
15-03-2012 дата публикации

System and method of page buffer operation for memory devices

Номер: US20120066442A1
Автор: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

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Номер записи: 21
15-03-2012 дата публикации

Apparatus and method for programmable read preamble

Номер: US20120066464A1
Автор: Anthony Le, Clifford Alan Zitlaw
Принадлежит: SPANSION LLC

A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.

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Номер записи: 22
22-03-2012 дата публикации

Different types of memory integrated in one chip by using a novel protocol

Номер: US20120072647A1
Автор: Fu-Chang Hsu, Peter Wung Lee
Принадлежит: Aplus Flash Technology Inc

A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I 2 C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

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Номер записи: 23
05-04-2012 дата публикации

Delay locked loop circuit of semiconductor memory apparatus

Номер: US20120081160A1
Автор: Hoon Choi, Hyun Woo Lee
Принадлежит: Hynix Semiconductor Inc

Various embodiments of a delay locked loop circuit of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the delay locked loop circuit may include an input correction unit configured to correct a duty ratio of an input clock based on a duty control signal and generate a reference clock; a delay line configured to delay the reference clock by a delay time and generate a delay locked clock; an output correction unit configured to correct a duty ratio of the delay locked clock based on the duty control signal and generate a corrected clock; and a control signal generation unit configured to generate the duty control signal when a correction activation signal is enabled.

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Номер записи: 24
19-04-2012 дата публикации

Memory devices and memory systems including discharge lines and methods of forming

Номер: US20120092946A1
Автор: Jae Hee OH, Ji-Hyun Jeong, Jin-Young Kim, Ki Whan SONG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.

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Номер записи: 25
26-04-2012 дата публикации

Data output buffer and memory device

Номер: US20120099383A1
Автор: Jin-Il Lee, Kwang-Il Park, Seung-Jun Bae, Si-Hong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

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Номер записи: 26
26-04-2012 дата публикации

Memory module with memory stack and interface with enhanced capabilities

Номер: US20120102292A1
Автор: David T. Wang, Frederick Daniel Weber, Keith R. Schakel, Michael J.S. Smith, Suresh N. Rajan
Принадлежит: Google LLC

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

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Номер записи: 27
03-05-2012 дата публикации

System and Method for Simulating an Aspect of a Memory Circuit

Номер: US20120109621A1
Автор: David T. Wang, Frederick Daniel Weber, Keith R. Schakel, Michael John Sebastian Smith, Suresh Natarajan Rajan
Принадлежит: Google LLC

A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.

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Номер записи: 28
03-05-2012 дата публикации

Data signal mirroring

Номер: US20120109896A1
Автор: Michael M. Abraham, Peter Feeley
Принадлежит: Micron Technology Inc

Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.

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Номер записи: 29
03-05-2012 дата публикации

Data paths using a first signal to capture data and a second signal to output data and methods for providing data

Номер: US20120110368A1
Автор: Eric Lee
Принадлежит: Micron Technology Inc

Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

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Номер записи: 30
10-05-2012 дата публикации

Semiconductor memory device and driving method of semiconductor memory device

Номер: US20120113707A1
Автор: Yasuhiko Takemura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.

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Номер записи: 31
17-05-2012 дата публикации

Semiconductor device having pull-up circuit and pull-down circuit

Номер: US20120119578A1
Автор: Hiroki Fujisawa, Shunji Kuwahara
Принадлежит: Elpida Memory Inc

To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

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Номер записи: 32
24-05-2012 дата публикации

Memory instruction including parameter to affect operating condition of memory

Номер: US20120127807A1
Автор: Federico Pio
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to techniques to operate memory.

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Номер записи: 33
31-05-2012 дата публикации

Memory Modules and Devices Supporting Configurable Core Organizations

Номер: US20120134084A1
Автор: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Frederick A. Ware, Richard E. Perego
Принадлежит: RAMBUS INC

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

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Номер записи: 34
31-05-2012 дата публикации

Charge pump control scheme using frequency modulation for memory word line

Номер: US20120134218A1
Автор: Hung-Chang Yu, Yue-Der Chih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage.

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Номер записи: 35
31-05-2012 дата публикации

Semiconductor device and method of controlling the same

Номер: US20120134222A1
Автор: Hiroki Fujisawa, Kazuhisa Ureshino
Принадлежит: Elpida Memory Inc

A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word line; a second signal unit outputting a second signal for activating or inactivating a bit line and the sense circuit; a third signal unit outputting a third signal for starting or stopping a supply of an overdrive voltage to the sense circuit; and a fourth signal unit outputting a fourth signal for inactivating the word line. The period during which the third signal remains activated is determined in accordance with the magnitude of an external voltage. In the fourth signal unit, the timing to generate the fourth signal is determined independently of the magnitude of the external voltage.

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Номер записи: 36
07-06-2012 дата публикации

Write circuitry for hierarchical memory architectures

Номер: US20120140582A1
Автор: Anand Mishra, Nitin Jain, Siddharth Gupta
Принадлежит: STMICROELECTRONICS PVT LTD

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

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Номер записи: 37
07-06-2012 дата публикации

Programming memory cells with additional data for increased threshold voltage resolution

Номер: US20120144101A1
Автор: Frankie F. Roohparvar, Vishal Sarin
Принадлежит: Micron Technology Inc

Methods for programming memory and memory devices are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.

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Номер записи: 38
14-06-2012 дата публикации

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Номер: US20120146132A1
Автор: Leonard Forbes
Принадлежит: Micron Technology Inc

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

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Номер записи: 39
21-06-2012 дата публикации

Sense amplifier structure for a semiconductor integrated circuit device

Номер: US20120154046A1
Автор: Duk Su Chun
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.

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Номер записи: 40
21-06-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120155205A1
Автор: Kie Bong Ku
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory apparatus includes a buffer control unit configured to deactivate a buffer control signal in response to an auto-refresh start pulse, and activate the buffer control signal in response to an auto-refresh end pulse, a command buffer configured to buffer an external command and output an internal command when the buffer control signal is activated, an address buffer configured to buffer an external address and output an internal address when the buffer control signal is activated, and a clock buffer configured to buffer an external clock and output an internal clock when the buffer control signal is activated.

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Номер записи: 41
21-06-2012 дата публикации

Memory Module With Reduced Access Granularity

Номер: US20120159061A1
Автор: Craig E. Hampel, Frederick A. Ware
Принадлежит: RAMBUS INC

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

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Номер записи: 42
28-06-2012 дата публикации

Auto-precharge signal generator

Номер: US20120163100A1
Автор: Sun Young Hwang, Yin Jae Lee
Принадлежит: Hynix Semiconductor Inc

An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set signal generator is configured to generating a set signal in response to receiving the control signal and the precharge control signal. The auto-precharge signal generator is configured to generate an auto-precharge signal in response to receiving the set signal and a period set signal.

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Номер записи: 43
28-06-2012 дата публикации

Memory circuit and a tracking circuit thereof

Номер: US20120163109A1
Автор: Lakshmikantha V. Holla, Santhosh Narayanaswamy, SHARAD Gupta
Принадлежит: Texas Instruments Inc

Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.

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Номер записи: 44
05-07-2012 дата публикации

Memory system with sectional data lines

Номер: US20120170346A1
Автор: Luca Fasoli, Tianhong Yan
Принадлежит: SanDisk 3D LLC

The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

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Номер записи: 45
05-07-2012 дата публикации

Internal voltage generation circuit and semiconductor integrated circuit

Номер: US20120170392A1
Автор: Hee Joon LIM
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes first and second bank groups, a first internal voltage control unit configured to generate a first enable pulse which is enabled when a first read operation or a first write operation is performed for banks included in the first bank group, and a first internal voltage generation unit configured to generate and supply a first internal voltage to the first bank group in response to the first enable pulse, wherein an enable period of the first enable pulse is set to be longer in the first write operation than in the first read operation.

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Номер записи: 46
05-07-2012 дата публикации

Column address counter circuit of semiconductor memory device

Номер: US20120170398A1
Автор: Jee Yul KIM
Принадлежит: Hynix Semiconductor Inc

The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most significant counter unit configured to generate the most significant bit of the column address in response to a mask clock, where the mask clock is toggled when the internal clock is toggled by a set number of times.

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Номер записи: 47
05-07-2012 дата публикации

Semiconductor memory device, test circuit, and test operation method thereof

Номер: US20120173942A1
Автор: Bok-Moon Kang, Chang-Ho Do, Tae-Hyung Jung, Yeon-Woo Kim
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

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Номер записи: 48
19-07-2012 дата публикации

Memory module cutting off dm pad leakage current

Номер: US20120182777A1
Автор: Seok-Il Kim, Seung-jin Seo, You-Keun Han
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.

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Номер записи: 49
19-07-2012 дата публикации

Memory System with Multi-Level Status Signaling and Method for Operating the Same

Номер: US20120182780A1
Автор: Steven Cheng
Принадлежит: SanDisk Technologies LLC

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

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Номер записи: 50
26-07-2012 дата публикации

Memory channel having deskew separate from redrive

Номер: US20120188832A1
Автор: Pete D. Vogt
Принадлежит: Individual

A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.

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Номер записи: 51
26-07-2012 дата публикации

Timing adjustment circuit for a memory interface and method of adjusting timing for memory interface

Номер: US20120188833A1
Автор: Hideaki Kito, Hiroaki Iijima, Satoshi Ota, Shigehiro Tsuchiya, Yosuke Yamahara
Принадлежит: Toshiba Corp

According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.

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Номер записи: 52
26-07-2012 дата публикации

Integrated circuit with staggered signal output

Номер: US20120188835A1
Автор: Benedict C. Lau, Bret Stott, Ian P. Shaeffer
Принадлежит: RAMBUS INC

A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

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Номер записи: 53
26-07-2012 дата публикации

Ddr flash implementation with direct register access to legacy flash functions

Номер: US20120191898A1
Автор: Ramkarthik Ganesan, Saad Monasa
Принадлежит: Individual

A Double Data Rate (DDR) nonvolatile memory for use with a wireless device. A host processor transfers commands and data through a DDR interface of the nonvolatile memory. The DDR nonvolatile memory implements legacy flash functions while maintaining DDR behavior.

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Номер записи: 54
02-08-2012 дата публикации

Method for Selectable Guaranteed Write-Through With Early Read Suppression

Номер: US20120195107A1
Автор: Jesse D. Smith, Peter T. Freiburger, Todd A. Christensen
Принадлежит: International Business Machines Corp

A static random access memory with write-through capability includes a memory cell configured to store a bit of data. A write enable signal is configured to enable writing a write value from a write line input into the static random access memory cell and to enable reading a read value from the memory cell onto a DOT line. A local evaluation circuit is configured to place the write value from the write line onto the DOT line during a single clock cycle in which the value is being written into the memory cell. An early read suppression circuit is configured to electrically isolate the DOT line from a data out line thereby preventing a leakage current loss from the local evaluation circuit and is also configured to make the value placed on the DOT line to be read from the data out line during the single clock cycle.

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Номер записи: 55
02-08-2012 дата публикации

Semiconductor device

Номер: US20120195136A1
Автор: Hideyuki Yoko
Принадлежит: Elpida Memory Inc

A semiconductor device according to the present invention includes plural controlled chips CC 0 to CC 7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A 13 to A 15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A 13 to A 15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A 13 to A 15 reach the controlled chips earlier than the command signal ICMD.

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Номер записи: 56
02-08-2012 дата публикации

Circuit

Номер: US20120198265A1
Автор: Thomas Hein
Принадлежит: Qimonda AG

An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

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Номер записи: 57
02-08-2012 дата публикации

System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain

Номер: US20120198267A1
Автор: Alexander Raykhman, Philip Crary, Srinjoy Das
Принадлежит: Qualcomm Atheros Inc

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 58
09-08-2012 дата публикации

Memory System with Calibrated Data Communication

Номер: US20120204054A1
Автор: Benedict Chung-Kwong Lau, Bruno W. Garlepp, Donald C. Stark, Jared Levan Zerbe, Jun Kim, Kevin S. Donnelly, Leung Yu, Mark A. Horowitz, Roxanne Vu, Stefanos Sidiropoulos, Tsyr-Chyang Ho
Принадлежит: RAMBUS INC

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

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Номер записи: 59
23-08-2012 дата публикации

Write control circuit and semiconductor device

Номер: US20120213014A1
Автор: Jun Nagayama, Masahito Isoda, Tomoharu Awaya, Tsuyoshi Koyashiki
Принадлежит: Fujitsu Semiconductor Ltd

In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.

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Номер записи: 60
30-08-2012 дата публикации

Write bandwidth in a memory characterized by a variable write time

Номер: US20120218814A1
Автор: John A. Bivens, Luis A. Lastras-Montano, Michele M. Franceschini
Принадлежит: International Business Machines Corp

A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

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Номер записи: 61
30-08-2012 дата публикации

Integrated circuit

Номер: US20120218840A1
Автор: Jinyeong MOON
Принадлежит: Hynix Semiconductor Inc

An integrated circuit includes a plurality of data lines on which data aligned by a plurality of pulse signals are loaded, a plurality of transfer lines, a data transfer unit configured to transfer the data of the plurality of data lines to the plurality of transfer lines in response to a correlation signal, a data output unit configured to output the data of the transfer line corresponding to a transmission signal activated among a plurality of transmission signals, a correlation signal generation unit configured to generate the correlation signal using a latency value and a logic value of one of the plurality of transmission signals when a command is inputted to the correlation signal generation unit, and a pulse signal generation unit configured to sequentially activate the plurality of pulse signals when the command is inputted.

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Номер записи: 62
30-08-2012 дата публикации

Utilizing two algorithms to determine a delay value for training ddr3 memory

Номер: US20120218841A1
Автор: Brandon L. Hunt
Принадлежит: LSI Corp

A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

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Номер записи: 63
30-08-2012 дата публикации

Semiconductor memory apparatus

Номер: US20120218849A1
Автор: Kie Bong Ku
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory apparatus includes a memory cell array including a plurality of chips, a control circuit configured to control an internal operation of the memory cell array, a power circuit configured to supply power to the control circuit, and a mode setting circuit configured to output a flag signal for power supply control based on a mode register set command and data received through a data input/output pad, in response to a clock enable signal.

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Номер записи: 64
06-09-2012 дата публикации

Three dimensional memory system with intelligent select circuit

Номер: US20120224410A1
Автор: Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

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Номер записи: 65
06-09-2012 дата публикации

Memory storage apparatus, memory controller, and audio playing method

Номер: US20120226371A1
Автор: Chang-Hsueh Huang, Chih-Yung Wu, Yu-Ju Su, Yuan-Pin Chang
Принадлежит: Phison Electronics Corp

A memory storage apparatus and a memory controller and an audio playing method thereof are provided. The memory storage apparatus includes a connector, a rewritable non-volatile memory module, the memory controller, and an audio playing unit. The audio playing unit is coupled to the memory controller via at least one signal control pin and has a speaker and an audio control circuit. The memory controller transmits status information to the audio playing unit via the signal control pin. Besides, the audio control circuit decodes an audio file according the status information and controls the speaker to play the decoded audio file. Thereby, a user can be effectively alerted about the current status of the memory storage apparatus.

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Номер записи: 66
13-09-2012 дата публикации

Semiconductor device

Номер: US20120229197A1
Автор: Atsuhiko Ishibashi, Masahiro Araki
Принадлежит: Renesas Electronics Corp

The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

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Номер записи: 67
13-09-2012 дата публикации

Semiconductor memory device and methods thereof

Номер: US20120230125A1
Автор: Nak-Won Heo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.

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Номер записи: 68
20-09-2012 дата публикации

Method for compensating a timing signal, an integrated circuit and electronic device

Номер: US20120239960A1
Автор: Anton Rozen, Leonid Fleshel, Michael Priel
Принадлежит: FREESCALE SEMICONDUCTOR INC

A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

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Номер записи: 69
20-09-2012 дата публикации

Synchronous data processing system and method

Номер: US20120239961A1
Автор: PRABHJOT Singh, Prakash Makwana
Принадлежит: FREESCALE SEMICONDUCTOR INC

A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

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Номер записи: 70
27-09-2012 дата публикации

Signal receiving circuit, memory controller, processor, computer, and phase control method

Номер: US20120242385A1
Автор: Noriyuki Tokuhiro
Принадлежит: Fujitsu Ltd

A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.

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Номер записи: 71
27-09-2012 дата публикации

Non-Sequential Encoding Scheme for Multi-Level Cell (MLC) Memory Cells

Номер: US20120243311A1
Автор: Dadi Setiadi, Patrick J. Ryan, Yiran Chen
Принадлежит: SEAGATE TECHNOLOGY LLC

Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.

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Номер записи: 72
27-09-2012 дата публикации

Semiconductor memory device and method of setting operation environment therein

Номер: US20120243365A1
Автор: Kazushige Kanda, Toshihiro Suzuki
Принадлежит: Toshiba Corp

A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.

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Номер записи: 73
27-09-2012 дата публикации

Neighborhood operations for parallel processing

Номер: US20120246380A1
Автор: Avidan Akerib, Eli Ehrman, Moshe Meyassed, Oren Agam, Yehoshua Meir, Yukio Fukuzo
Принадлежит: Individual

A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.

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Номер записи: 74
04-10-2012 дата публикации

Semiconductor memory device and controlling method thereof

Номер: US20120250393A1
Автор: Masanobu Shirakawa
Принадлежит: Individual

According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, a peripheral circuit, a sense amplifier configured to sense the memory cells via the peripheral circuit, and a control circuit configured to control operations of the memory cell array and the sense amplifier. The control circuit is configured to boost a potential of a selected bit line, which is one of a first even bit line and a first odd bit line of a first side, by charge sharing of a second even bit line and a second odd bit line which are nonselected bit lines and physically neighbor the first even bit line or the first odd bit line of the first side, which is connected to a selected one of the memory cells.

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Номер записи: 75
04-10-2012 дата публикации

Semiconductor memory and semiconductor memory control method

Номер: US20120250425A1
Автор: Katsumi Abe, Masahiro Yoshihara
Принадлежит: Individual

According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.

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Номер записи: 76
25-10-2012 дата публикации

Data input device for semiconductor memory device

Номер: US20120269008A1
Автор: Ming-Chien Huang
Принадлежит: Elite Semiconductor Memory Technology Inc

A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs internal data to the flip-flop unit. The combinational logic circuit receives an external data strobe signal to generate a first data strobe signal and a second data strobe signal. The flip-flop unit stores the data in synchronization with the first data strobe signal and outputs the stored data in synchronization with the second data strobe signal. A last rising edge of the second data strobe signal is generated prior to onset of the postamble ringing on the external data strobe signal, so that a data transferred path in the flip-flop unit is closed prior to onset of the postamble ringing.

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Номер записи: 77
25-10-2012 дата публикации

Delay circuit and latency control circuit of memory, and signal delay method thereof

Номер: US20120269017A1
Автор: Jeong-Tae Hwang
Принадлежит: Hynix Semiconductor Inc

A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.

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Номер записи: 78
15-11-2012 дата публикации

Gain cell semiconductor memory device and driving method thereof

Номер: US20120287700A1
Автор: Yasuhiko Takemura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten.

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Номер записи: 79
15-11-2012 дата публикации

Memory controller and operating method of memory controller

Номер: US20120290901A1
Автор: JaePhil Kong, Yongwon CHO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A controller to control a memory system including a memory device. The controlling the memory system may include calculating an error location polynomial in a received read vector with a key equation solving unit of the memory system to read data from the memory device, estimating the number of errors in the received read vector with a control unit of the memory system according to at least one of the calculated error location polynomial and information on the error location polynomial, searching error locations of the received read vector according to the calculated error location polynomial with a chien search unit of the memory system with the control unit. A cycle-per power consumption of the chien search unit may be adjusted with the control unit. A maximum correction time may be adjusted according to the number of errors of the read vector.

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Номер записи: 80
22-11-2012 дата публикации

Semiconductor Device

Номер: US20120293242A1
Автор: Kiyoshi Kato
Принадлежит: Semiconductor Energy Laboratory Co Ltd

As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a first capacitor and a second capacitor. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region.

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Номер записи: 81
22-11-2012 дата публикации

Memory device and signal processing circuit

Номер: US20120294102A1
Автор: Takahiko Ishizu
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. A memory device includes a logic circuit including a first node and a second node, a first memory circuit connected to the first node, a second memory circuit connected to the second node, and a precharge circuit connected to the first node, the second node, the first memory circuit, and the second memory circuit. When reading data is performed, the precharge circuit outputs a precharge potential to the first node and the second node. The first memory circuit and the second memory circuit each include a transistor in which a channel is formed in an oxide semiconductor film.

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Номер записи: 82
29-11-2012 дата публикации

Field side sub-bitline nor flash array and method of fabricating the same

Номер: US20120299079A1
Автор: Lee Wang
Принадлежит: Individual

Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

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Номер записи: 83
29-11-2012 дата публикации

Memory cell operation

Номер: US20120300530A1
Автор: John K. Zahurak, Roy E. Meade
Принадлежит: Micron Technology Inc

Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

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Номер записи: 84
29-11-2012 дата публикации

Integrated circuit memory device

Номер: US20120300555A1
Автор: Choong-Sun Shin, Joo-Sun Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2̂K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

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Номер записи: 85
29-11-2012 дата публикации

Advanced memory device having improved performance, reduced power and increased reliability

Номер: US20120300563A1
Автор: Charles A. Kilmer, Daniel M. Dreps, George L. Chiu, Hillery C. Hunter, Kevin C. Gower, Kyu-Hyoun Kim, Paul W. Coteus, Warren E. Maule
Принадлежит: International Business Machines Corp

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

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Номер записи: 86
06-12-2012 дата публикации

Isolated resistive current sensor

Номер: US20120306657A1
Автор: Miguel Angel Acena, Youssef Ghabbour
Принадлежит: Lear Corp

An isolated current-sensing system for use with a resistive current sense element includes an analog front-end configured to receive a voltage from the resistive current sense element, and to provide an analog output. A processing circuit receives the analog output, and provides a measurement signal indicative of the sensed current. An isolation circuit provides an isolation barrier, and is configured to pass the measurement signal. A programmable over-current protection alarm may be included, and configured to generate an alarm signal when the analog output exceeds a programmable threshold. The processing circuit may include a voltage-to-PWM converter.

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Номер записи: 87
06-12-2012 дата публикации

Apparatus including memory system controllers and related methods

Номер: US20120311232A1
Автор: Kent A. Porterfield
Принадлежит: Micron Technology Inc

Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria.

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Номер записи: 88
13-12-2012 дата публикации

Infrastructure for performance based chip-to-chip stacking

Номер: US20120313647A1
Автор: Alan James Drake, Eren Kursun, Gary Dale Carpenter, Phillip John Restle
Принадлежит: International Business Machines Corp

A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.

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Номер записи: 89
13-12-2012 дата публикации

Semiconductor memory device and method of driving semiconductor memory device

Номер: US20120314513A1
Автор: Yoshiyuki Kurokawa
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.

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Номер записи: 90
13-12-2012 дата публикации

Asynchronous/synchronous interface

Номер: US20120314517A1
Автор: Chih Liang Chen, Dean K. Nobunaga, June Lee
Принадлежит: Micron Technology Inc

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

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Номер записи: 91
13-12-2012 дата публикации

Synapse for function cell of spike timing dependent plasticity (stdp), function cell of stdp, and neuromorphic circuit using function cell of stdp

Номер: US20120317063A1
Автор: Hyun Surk Ryu, Jae Yoon Sim, Jun Haeng Lee
Принадлежит: Academy Industry Foundation of POSTECH, SAMSUNG ELECTRONICS CO LTD

A synapse for a spike timing dependent (STDP) function cell includes a memory device having a variable resistance, such as a memristor, and a transistor connected to the memory device. A channel of the memory device is connected in series with a channel of the transistor.

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Номер записи: 92
20-12-2012 дата публикации

Semiconductor memory device, information processing system including the same, and controller

Номер: US20120320686A1
Автор: Toru Ishikawa, Yasushi Takahashi
Принадлежит: Elpida Memory Inc

A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.

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Номер записи: 93
20-12-2012 дата публикации

Low voltage sensing scheme having reduced active power down standby current

Номер: US20120320687A1
Автор: Tae Kim
Принадлежит: Individual

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

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Номер записи: 94
27-12-2012 дата публикации

Boosting circuit

Номер: US20120326770A1
Автор: Hiroki Murakami
Принадлежит: Winbond Electronics Corp

A boosting circuit, includes an output circuit including a first transmission circuit, transmitting charges of a first boosting node to a first output node according to a first transmission control signal, a detection circuit, detecting the voltage level of the first output node, and a pre-charge circuit pre-charging the first boosting node according a detection signal of the detection circuit; a first pump circuit includes a second transmission circuit, transmitting charges to a second output node according to a second transmission control signal, and a first capacitance unit, coupled to the first boosting node, boosting the voltage level of the first boosting node according to charges transmitted in the second output node; and a control circuit, coupled to the output circuit and the first pump circuit, controls the second transmission control signal according to the voltage level of the first output node.

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Номер записи: 95
27-12-2012 дата публикации

Random Access Memory Controller Having Common Column Multiplexer and Sense Amplifier Hardware

Номер: US20120327703A1
Автор: Meny Yanni
Принадлежит: Marvell Israel MISL Ltd

Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry is shared between the column multiplexer and the sense amplifier so that the memory controller includes a single instance of the common circuitry for the column multiplexer and sense amplifier pair. The common circuitry includes a common pre-charge circuit, a common equalizer, or a common keeper circuit.

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Номер записи: 96
27-12-2012 дата публикации

Programming of phase-change memory cells

Номер: US20120327709A1
Автор: Abu Sebastian, Angeliki Pantazi, Charalampos Pozidis, Nikolaos Papandreou, Urs Frey
Принадлежит: International Business Machines Corp

A method and apparatus for programming a phase-change memory cell. A bias voltage signal (V BL ) is applied to the cell. A measurement portion (m) of this bias voltage signal has a profile which varies with time. A measurement (T M ), which is dependent on a predetermined condition being satisfied, is then made. The predetermined condition is dependent on cell current during the measurement portion (m) of the bias voltage signal. A programming signal is generated in dependence on the measurement (T M ), and the programming signal is applied to program the cell.

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Номер записи: 97
27-12-2012 дата публикации

Semiconductor memory apparatus and bit line equalizing circuit

Номер: US20120327731A1
Автор: Mi Hyeon JO
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory apparatus comprise s bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.

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Номер записи: 98
03-01-2013 дата публикации

Semiconductor memory device

Номер: US20130003433A1
Автор: Tomoo Hishida, Yoshihisa Iwata
Принадлежит: Toshiba Corp

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

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Номер записи: 99
03-01-2013 дата публикации

Digit line comparison circuits

Номер: US20130003467A1
Автор: Dean A. Klein
Принадлежит: Micron Technology Inc

A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

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Номер записи: 100