Write buffer for resistive random access memory

A circuit includes a current generator and a voltage generator. The current generator is configured to generate a predetermined current flowing toward a selected cell in a memory array via a node during a write operation. The voltage generator is configured to generate a predetermined voltage. The voltage level at the node is clamped at a predetermined value associated with the predetermined voltage as the selected cell is switched between a low resistance state and a high resistance state during the write operation.

Method of setting a reference current in a nonvolatile memory device

A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.

Novel two-transistor flash cell for large endurance application

An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell is composed of a program transistor and read transistor with a control gate connected to a word line, a source connected the source select line, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The program transistor has a drain connected a first bit line and a read transistor has a drain connected to the second bit line. Each memory cell has a floating gate connector joining the floating gate of the read transistor to the floating gate of the read transistor. The nonvolatile memory device has a voltage controller that programs the each memory cell by programming the program transistor and reading the read transistor.

MRAM Smart Bit Write Algorithm with Error Correction Parity Bits

Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location. 1. A method , comprising:(a) attempting to write an expected multi-bit word to a memory location in memory;(b) after attempting to write the multi-bit word, reading an actual multi-bit word from the memory location;(c) comparing the actual multi-bit word with the expected multi-bit word to identify a number of erroneous bits as well as a number of correct bits stored in the memory location; and(d) re-writing the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.2. The method of claim 1 , wherein the memory is a magnetic random access memory (MRAM) device comprising an array of MRAM cells.3. The method of claim 1 , wherein acts (b) claim 1 , (c) claim 1 , and (d) are repeated in an iterative manner in an attempt to correct the number of erroneous bits.4. The method of claim 3 , further comprising:incrementing or decrementing a counter value for each iteration of acts (b), (c), and (d); andceasing repetition of acts (b), (c), and (d) based on whether the counter value has a pre-determined relationship with a predetermined count threshold.5. The method of claim 4 , further comprising:when repetition of acts (b), (c), and (d) is ceased, attempting to correct any remaining erroneous bits using an error correction code.6. The method of claim 1 , further comprising:determining if the number of erroneous bits in the multi-bit word is ...

SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. 1. A method comprising: forming a first and second doped regions disposed within the substrate, the first and second doped regions interfacing in a channel region, the first region underlying a first shallow trench isolation (STI) feature and the second doped region underlying a second STI feature, the first and second doped regions being doped with a first type dopant, the first doped region having a different concentration of dopant than the second doped region; and', 'forming a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions, the source region being formed within the first doped region and the drain region being formed within the second doped region, the source and drain regions being doped with a second type dopant, the second type dopant being complementary to the first type dopant., 'forming a metal oxide device over a substrate, wherein forming the metal oxide device includes2. The method of further comprising forming a cascade metal oxide device over the substrate claim 1 , wherein ...

Program methods for split-gate memory

An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.

Reference generation in an integrated circuit device

A method for generating a reference voltage in an integrated circuit device that is powered by a low voltage power includes generating a coarse first reference voltage using a coarse reference generator, routing the coarse first reference voltage to a boost regulator as an input reference voltage by a hand-off switch circuit, the boost regulator generating an initial-state stepped-up supply based on the first reference voltage, and generating at least two outputs of a second, more accurate, reference voltage from the stepped-up supply voltage using a fine-resolution reference generator. The second reference can be then looped back to the boost regulator, thus, generating a more accurate steady-state stepped-up supply voltage.

Sample-and-Hold Current Sense Amplifier and Related Method

A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier. 1. A device comprising:an amplifier; and a first transistor;', a first terminal electrically connected to a gate electrode of the first transistor; and', 'a second terminal electrically connected to a direct current (DC) bias node of the device;, 'a first capacitor having, a first terminal electrically connected to a first current source; and', 'a second terminal electrically connected to the gate electrode of the first transistor;, 'a first switch having, a first terminal electrically connected to the first current source; and', 'a second terminal electrically connected to a drain electrode of the first transistor; and, 'a second switch having, a first terminal electrically connected to the drain electrode of the first transistor; and', 'a second terminal electrically connected to a first input terminal of the amplifier., 'a third switch having], 'a first switched current sampler comprising2. The device of claim 1 , wherein the first current source is a memory bit cell.3. The device of claim 1 , wherein the first current source is ...

READ ARCHITECTURE FOR MRAM

A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison. 1. A read architecture for reading random access memory (RAM) cells , comprising:a multi-level sense amplifier, the multi-level sense amplifier comprising a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output;a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier, the storage module storing a first set of sense outputs corresponding to a first read of a RAM cell and storing a second set of sense outputs corresponding to a second read of the RAM cell; anda decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.2. The read architecture of claim 1 , wherein the RAM cell is programmable to a high resistance state and a low resistance state claim 1 , wherein the RAM cell is programmed to a low resistance state for the second read.3. The read architecture of claim 2 , wherein the sense thresholds are selected such that at least two sense outputs change between the first read and the second read when the RAM cell is programmed in the high resistance state for the first read.4. The read architecture of claim ...

Adjusting reference resistances in determining MRAM resistance states

Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position.

Nonvolatile memory device and method of setting a reference current in a nonvolatile memory device

A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.

SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF

A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

Program methods for split-gate memory

An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.

Package with multiple plane I/O structure

A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.

Method of converting between non-volatile memory technologies and system for implementing the method

A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.

Products derived from embedded flash/EEPROM products

A method of fabricating ROM products through the use of embedded flash/EEPROM prototypes is disclosed. This is accomplished by first forming a Flash/EEPROM prototype, performing programming simulations on the prototype, developing a ROM code and mask, and then forming a ROM product in the same manufacturing line by skipping certain Flash/EEPROM steps and then implanting the ROM code into the final ROM product. The method improves turn-around-time in the manufacturing line, and reduces cost to the customer. A method of doing business is also disclosed directed to providing ROM products to a customer without much redesign time and effort on the part of the customer.

Sub-1V bandgap reference circuit

A bandgap reference circuit is disclosed operating under a predetermined low voltage source. The circuit has a first circuit with a first differential amplifier for generating a first current, a second circuit with a second differential amplifier for generating a second current, and a bandgap reference voltage output module for combining the first current and the second current to output a bandgap reference voltage, wherein the first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.

Resistance-based random access memory

A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node.

Memory devices with improved refreshing operation

A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes a location-related memory cell and a refresh module. The location-related memory cell is coupled to a bit line. The refresh module is configured to refresh the location-related memory cell by reading data stored in the location-related memory cell and then writing the data back to the location-related memory cell in a condition that a target memory cell that is coupled to the bit line is programmed or erased. A method for memory cell programming and erasing with refreshing operation is also disclosed herein.

Multiple power domain electronic device and related method

An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.

MRAM smart bit write algorithm with error correction parity bits

Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.

Reference cell circuit for split gate flash memory

A reference cell circuit 50 for split gate flash memory. The reference cell circuit 50 includes an odd split gate cell 52 and an even split gate cell 54. The control gate 56 of the odd cell 52 is coupled to an address bit line XADR[0], and the control gate 64 of the even gate cell is coupled to the output of an inverter 66 which inverts the signal from XADR[0]. The floating gates 58, 68 of the odd cell 52 and even cell 54 are each coupled to a constant voltage signal Vdd. By placing signals on line XADR[0], cells 52, 54 may be selectively activated and deactivated.

Sub-1V bandgap reference circuit

A bandgap reference circuit is disclosed operating under a predetermined low voltage source. The circuit has a first circuit with a first differential amplifier for generating a first current, a second circuit with a second differential amplifier for generating a second current, and a bandgap reference voltage output module for combining the first current and the second current to output a bandgap reference voltage, wherein the first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.

SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. 1. A semiconductor device comprising:a substrate including a metal oxide device, the metal oxide device including:first and second doped regions disposed within the substrate and interfacing in a channel region, the first region underlying a first shallow trench isolation (STI) feature and the second doped region underlying a second STI feature, the first and second doped regions being doped with a first type dopant, the first doped region having a different concentration of dopant than the second doped region; anda gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions, the source region being formed within the first doped region and the drain region being formed within the second doped region, the source and drain regions being doped with a second type dopant, the second type dopant being opposite of the first type dopant.2. The semiconductor device of wherein the substrate includes a cascade metal oxide device claim 1 , the cascade metal oxide device including:a first gate structure traversing a ...

Method of marginal erasure for the testing of flash memories

Voltage-dropping components are bypassed during testing of the erasing of a flash memory device thereby effectively lowering the applied erase voltage to the marginal level desired (VME). These voltage-dropping components may be a plurality of diode-connected NMOS transistors. If a plurality of diode-connected NMOS transistors are used, the voltage applied to the flash macro is reduced by m*Vt, where m is the number of bypassed diode connected NMOS transistors and Vt is the threshold voltage of the NMOS transistors. In normal operation, the voltage dropping components are placed in series with the charge pump, thereby returning the voltage applied to the flash macro to the normal level (VNE).

Adaptive control of programming currents for memory cells

A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation.

Resistive Memory Array

A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line. 1. A circuit comprising:a current source module connected to a first bit/source line and a second bit/source line;a current sink module connected to the first bit/source line and the second bit/source line; anda memory bank connected to the first bit/source line and the second bit/source line and bounded by the current source module and the current sink module;wherein when each of the current source module and the current sink module receives a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.2. The circuit of claim 1 , wherein the current source module comprises:a current source unit connected to the first bit/source line; anda logic gate comprising an output end connected to the current source unit and two input ends;wherein when the logic gate receives the select signal with the first state at one of the input ends and receives the triggering pulse at the other one of the input ends from the first bit/ ...

High-endurance memory device

A memory device includes a set of memory cells, each of which is capable of being selected to generate a sensing current depending on a logic state thereof, and a set of reference cells, each of which is capable of being selected to generate a reference current. A sense amplifier is coupled to the memory cells and the reference cells for comparing the sensing current with the reference current to generate a signal representing the logic state of the selected memory cell. The memory cells and the reference cells are subject to the same operation cycles, such that a difference between the sensing current and the reference current remains a constant.

Multiple-time programmable memory

A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.

Logic compatible arrays and operations

An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a first erase line in the first direction, wherein the first erase line is connected to erase gates of the memory cells in the first row of the array; and a first word-line in the first direction, wherein the first word-line is connected to word-line nodes of the memory cells in the first row of the array.

Bandgap reference and related method

A device includes a proportional-to-absolute-temperature (PTAT) current source having a bandgap reference voltage node, and a negative temperature dynamic load having an input terminal electrically connected to the bandgap reference voltage node.

Multiple power domain electronic device and related method

An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.

Nano-crystal gate structure for non-volatile memory

A non-volatile memory device is disclosed having a charge storage layer that incorporates a plurality of nano-crystals. A substrate having a source region and a drain region is provided. Select and control gates are formed on the substrate. The charge storage layer is provided between the control gate and the substrate. The nano-crystals in the charge storage layer have a size of about 1 nm to about 10 nm, and may be formed of Silicon or Germanium. Writing operations are accomplished via hot electron injection, FN tunneling, or source-side injection. Erase operations are accomplished using FN tunneling. The control gate is formed of a single layer of polysilicon, which reduces the total number of processing steps required to form the device, thus reducing cost.

Read architecture for MRAM

A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.

High-voltage switch circuit

A high-voltage switch circuit is disclosed, which includes at least one voltage source input terminal for providing at least one voltage source (HV 1 ), and a passing circuit (T 0 ) for controllably passing the voltage source. The present invention also includes a pumping circuit ( 202 ) for raising voltage level of one output terminal (C) thereof. At least one switch circuit (T 6 or T 7 ) under control of a switch signal is used so that the voltage source controllably propagates to one output terminal (OUT 1 , OUT 2 ) of the switch circuit through the passing circuit. Finally, a circuit (T 4 ) is used for forcing the output terminal of the pumping circuit and one internal node (A) of the pumping circuit to an equal potential, so that the voltage source propagates to the output terminal of the switch circuit through the forcing circuit when the output terminal of the switch circuit is coupled to a ground.

Dual-voltage generation system

A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.

Charge pump circuit and method of operating same

In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of a first capacitive element. The second node is coupled with a first end of a second capacitive element. A first end of a first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element and a first end of a second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage.

Low dropout regulator and related method

A device includes an error amplifier, a standby current source, a charging current source, a voltage divider, and a first switch. The error amplifier has a negative input terminal and a positive input terminal. The standby current source has a control terminal electrically connected to an output terminal of the error amplifier. The voltage divider has an input terminal electrically connected to an output terminal of the standby current source, and an output terminal electrically connected to the positive input terminal of the error amplifier. The charging current source has a control terminal electrically connected to the output terminal of the error amplifier. The first switch has a first terminal electrically connected to an input terminal of the charging current source, and a second terminal electrically connected to a first power supply node.

Memory controller, memory device and method of operating

A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell.

MRAM smart bit write algorithm with error correction parity bits

Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.

Structure and inhibited operation of flash memory with split gate

A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities.

Reference cell configuration for sensing resistance states of MRAM bit cells

A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states R H and R L , providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by R H and R L , such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.

MRAM WITH CURRENT-BASED SELF-REFERENCED READ OPERATIONS

A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element. 1. A self-referenced read circuit for determining an initially unknown value stored in an MRAM bit cell , the bit cell having a magnetic tunnel junction element with a pinned layer establishing a permanent magnetic field reference direction , and a free layer with a changeable magnetic field component that is selectively alignable parallel to the reference direction in a low resistance state of the magnetic tunnel junction element , and anti-parallel to the reference direction in a high resistance state of said element , the self-referenced reading circuit comprising:a current bias source and a switching circuit coupled to apply a read current bias to the magnetic tunnel junction element, thereby establishing current amplitude and potential difference conditions representing the unknown resistance state;a storage element responsive to the read circuit, operable for storing a value representing the unknown resistance state;a write circuit operable to impose one of the resistance states on the magnetic tunnel junction element after operation of the storage circuit to store said value;wherein the switching ...

Memory word line boost using thin dielectric capacitor

A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor dielectric thickness. The word line boost circuit is configured to supply a high voltage that is higher than a power supply voltage to the word line during an operation of the memory by utilizing the capacitor.

Accommodating balance of bit line and source line resistances in magnetoresistive random access memory

A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.

Reconfigurable programmable logic device with P-channel non-volatile memory cells

A system is disclosed for constructing a reconfigurable programmable logic device (PLD) comprising a first P-channel nonvolatile memory cell with a first source, a first drain and a first gate coupled to a first input node, a second P-channel nonvolatile memory cell with a second source, a second drain and a second gate coupled to a second input node, and an NMOS transistor with a third source and a third drain, wherein the first and second sources are commonly connected to a positive voltage supply (Vcc), the first, second and third drains are commonly connected to an output node and the third source is coupled to a complementary low voltage supply (Vss).

Semiconductor device with split gate memory cell and fabrication method thereof

A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

Redundancy circuits and operating methods thereof

A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third IO interface and a fourth memory array coupled with a fourth TO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

Charge pump control scheme for memory word line

A memory includes a word line, a charge pump coupled to the word line, and a charge pump control circuit coupled to the charge pump. The charge pump control circuit is configured to turn on the charge pump if the word line voltage is lower than a first threshold voltage and turn off the charge pump if the word line voltage is higher than a second threshold voltage.

Memory devices with improved refreshing operations

A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

Bandgap Reference and Related Method

A device includes a proportional-to-absolute-temperature (PTAT) current source having a bandgap reference voltage node, and a negative temperature dynamic load having an input terminal electrically connected to the bandgap reference voltage node.

Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities

This invention provides a memory array and its peripheral circuit with byte-erase capability. The advantage of this invention is the ability to access bytes for program, erase, and read operations. This invention allows this access with the addition of one word line switch and one source line switch for each byte to be accessed for program, erase, and read operations. Also, this invention utilizes a new bias condition to lessen the voltage stress on the high voltage device. In addition, this invention utilizes separate and dedicated power supplies for the local word line driver circuits and for the local source line driver circuits. This is coupled with the partitioning of the main memory array into sub-arrays of 8 columns. This allows the placing of high voltage only on the selected 8 column (byte) subarray. This also substantially lessens the voltage stress on the memory cells and enhances long-term reliability.

Design for test to emulate a read with worse case test pattern

In the present invention a read test is performed on a selected cell. During the read test, a high impedance is connected to the bit lines of unselected memory cells which are connected to a common source line with the selected cell. The high impedance is created by a tri-state buffer that has a test mode control, and prevents leakage current from flowing from the common source line through unselected, erased cells. The inhibiting of the leakage current permits improved test margins to be applied to the reading of a selected cell.

Method and apparatus for MRAM sense reference trimming

A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current.

Antifuse and method of making the antifuse

A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.

Structure and method for forming conductive path in resistive random-access memory device

An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit lines. The resistive elements of the bit cells are coupled to source lines that are parallel to word lines and perpendicular to the vertical bit lines. The bit lines are maintained at different biases. A high voltage is applied to one of the source lines coupled to adjacent resistive elements of bit cells disposed along more than one vertical bit line. When the associated transistors are turned on by a sufficiently high gate voltage, the desired RRAM resistive elements along one of the bit lines are formed without stressing other bit cells of the array.

Source line high voltage driver circuit with improved reliability and read performance

A source line high voltage driver circuit 50 for use with a semiconductor memory device which has several other substantially identical circuits 50. Circuit 50 includes a latching circuit portion which selectively applies a high voltage signal to source line SL during a write/program cycle, and a cascode circuit which is used to discharge source line SL and which is formed by two transistors 72, 74. The drain terminal of transistor 72 is coupled to source line SL, and the source terminal of transistor 74 is coupled to ground. The drain terminal of transistor 74 and the source terminal of transistor 72 are each coupled to a node N5 which is electrically coupled to the node N5 of every other circuit 50 within the semiconductor memory device.

Word-line voltage generator

A programmable memory circuit includes a memory array having a plurality of floating gate memory cells disposed in a first and second row and at least a first and second column and a reference circuit for providing a word line voltage to the memory array for programming selected memory cells from a selected one of the first and second rows. The word line voltage is dependent at least in part upon a bit line reference voltage and upon a threshold voltage of a reference floating gate cell associated with the selected one of the first and second rows.

Operating Resistive Memory Cell

A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source. 1. A circuit comprising:a first diode-connected P-type metal-oxide-semiconductor (PMOS) transistor and a first diode-connected N-type metal-oxide-semiconductor (PMOS) transistor cascade-connected at a sensing node, wherein the sensing node senses an injection current injected through the sensing node; anda second P-type metal-oxide-semiconductor (PMOS) transistor and a second N-type metal-oxide-semiconductor (PMOS) transistor cascade-connected at an output node, wherein the gates of the first diode-connected P-type metal-oxide-semiconductor (PMOS) transistor and the second P-type metal-oxide-semiconductor (PMOS) transistor are connected and the gates of the first diode-connected N-type metal-oxide-semiconductor (PMOS) transistor and the second N-type metal-oxide-semiconductor (PMOS) transistor are connected;wherein when an amount of the injection current increases to exceed or decreases to reach a threshold value, a voltage state of a voltage of the output node switches.2. The circuit of claim 1 , wherein when the injection current is of a positive value claim 1 , the voltage state of the voltage of the output node switches from a low voltage state to a high voltage state when the amount of the injection decreases to reach the threshold value and the voltage state of the voltage of the output node switches from a high voltage state to a low ...

SOURCE LINE HIGH VOLTAGE DRIVER CIRCUIT WITH IMPROVED RELIABILITY AND READ PERFORMANCE

A source line high voltage driver circuit 50 for use with a semiconductor memory device which has several other substantially identical circuits 50. Circuit 50 includes a latching circuit portion which selectively applies a high voltage signal to source line SL during a write/program cycle, and a cascode circuit which is used to discharge source line SL and which is formed by two transistors 72, 74. The drain terminal of transistor 72 is coupled to source line SL, and the source terminal of transistor 74 is coupled to ground. The drain terminal of transistor 74 and the source terminal of transistor 72 are each coupled to a node N5 which is electrically coupled to the node N5 of every other circuit 50 within the semiconductor memory device.

Memory devices with improved refreshing operation

A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.

Memory device having RRAM-based non-volatile storage array and repair function

A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.

Memory devices

A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.

Differential MRAM structure with relatively reversed magnetic tunnel junction elements enabling writing using same polarity current

A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array.

Method and apparatus for MRAM sense reference trimming

A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current.

Charge pump

In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of the first capacitive element. The second node is coupled with a first end of the second capacitive device. A first end of the first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive device and a first end of the second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element.

STRUCTURE AND INHIBITED OPERATION OF FLASH MEMORY WITH SPLIT GATE

A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities.

Redundancy circuits and operating methods thereof

A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.

BACK-BIAS VOLTAGE REGULATOR HAVING TEMPERATURE AND PROCESS VARIATION COMPENSATION AND RELATED METHOD OF REGULATING A BACK-BIAS VOLTAGE

Disclosed herein is a back-bias voltage regulator circuit for regulating a back-bias voltage used to control leakage current in at least one transistor within a primary circuit. In one embodiment, the back-bias voltage regulator circuit includes a voltage divider circuit configured to receive a back-bias voltage from a charge pump, and to generate a divided voltage signal by dividing the back-bias voltage based on a ratio of resistances of resistive elements within the voltage divider. In addition, the regulator circuit includes an output circuit configured to receive the back-bias voltage from the charge pump and having an output node for outputting the back-bias voltage, as well as a reference voltage circuit configured to generate a reference voltage signal based on a threshold voltage of the at least one transistor in the primary circuit. Also in such an embodiment, the regulator circuit includes a comparison circuit configured to compare the divided voltage signal to the reference ...

Memory array with byte-alterable capability

This invention provides a memory array and it support signals and a method for byte access for programming, erasing and reading memory cells. The advantage of this array and method is the ability to access bytes for program, erase, and read operations. This array and method uses an added isolation transistor to isolate the high voltage from the unselected byte. In addition, it utilizes a separate source line for each byte in a row. This source line is also shared by a byte in a different row. The array has very little peripheral circuit overhead requirement and it avoids programming disturbances of unselected memory cells.

Systems, devices and methods for memory operations

Systems, devices and methods are provided for memory operations. An example system includes: a latch circuit shared by a plurality of memory blocks of a memory device and configured to provide one or more regulation signals for a memory operation; a source line circuit shared by the plurality of memory blocks and configured to provide a source line voltage to the plurality of memory blocks for the memory operation based at least in part on the one or more regulation signals; and a plurality of driver circuits configured to provide a plurality of drive signals to the plurality of memory blocks based at least in part on the one or more regulation signals.

Memory devices

A device is disclosed that includes an I/O memory block. The I/O memory block includes memory cells, bit lines and a source line. The number of the formed bit lines is at least 4. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.

Stabilizing circuit

A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V.

Fast-switching word line driver

A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level.

Sample-and-hold current sense amplifier and related method

A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.

Operating method of memory having redundancy circuitry

In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.

REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF

A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO) interface and a fourth memory array coupled with a fourth IO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

Semiconductor device with self-aligned interconnects

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

Method of marginal erasure for the testing of flash memories

Voltage-dropping components are bypassed during testing of the erasing of a flash memory device thereby effectively lowering the applied erase voltage to the marginal level desired (VME). These voltage-dropping components may be a plurality of diode-connected NMOS transistors. If a plurality of diode-connected NMOS transistors are used, the voltage applied to the flash macro is reduced by m*Vt, where m is the number of bypassed diode connected NMOS transistors and Vt is the threshold voltage of the NMOS transistors. In normal operation, the voltage dropping components are placed in series with the charge pump, thereby returning the voltage applied to the flash macro to the normal level (VNE).

Selective error correction in a data storage device

The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.

Non-volatile memory cell devices and methods, having a storage cell with two sidewall bit cells

Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data.

Dual-voltage generation system

A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.

PACKAGE WITH MULTIPLE PLANE I/O STRUCTURE

A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit. 1. A method of forming a package , the method comprising:bonding one or more dies forming a chip stack, the chip stack having a first outermost die and a second outermost die opposite the first outermost die;bonding the first outermost die to a first side of a first substrate, a second side of the first substrate having a first set of input/output pads; andbonding the second outermost die to a first side of a second substrate, a second side of the second substrate having a second set of input/output pads.2. The method of claim 1 , further comprising forming a molding compound adjacent the chip stack.3. The method of claim 2 , wherein forming the molding compound is performed after bonding the first outermost die to the first side of the first substrate and bonding the second outermost die to the first side of the second substrate.4. The method of claim 3 , wherein the molding compound extends from the first substrate to the second substrate.5. The method of claim 1 , wherein the first set of input/output pads is arranged in an array.6. The method of claim 5 , wherein the second set of input/output pads is arranged in an array.7. A method of forming a package claim 5 , the method comprising:bonding a chip stack to a first side of a first substrate, the first side of the first substrate having a first set of contact pads, a second side of the first substrate having a second set of contact pads; andbonding the chip stack to a first side of a second substrate, the first side of the first substrate having a third set of ...

Memory array and its peripheral circuit with byte-erase capability

This invention provides a memory array and its peripheral circuit with byte-erase capability. The advantage of this invention is the ability to access bytes for program, erase, and read operations. This invention allows this access with the addition of one word line switch and one source line switch for each byte to be accessed for program, erase, and read operations. Also, this invention utilizes a new bias condition to lessen the voltage stress on the high voltage device. In addition, this invention utilizes separate and dedicated power supplies for the local word line driver circuits and for the local source line driver circuits. This is coupled with the partitioning of the main memory array into sub-arrays of 8 columns. This allows the placing of high voltage only on the selected 8 column (byte) subarray. This also substantially lessens the voltage stress on the memory cells and enhances long-term reliability.

High-endurance memory device

A memory device includes a set of memory cells, each of which is capable of being selected to generate a sensing current depending on a logic state thereof, and a set of reference cells, each of which is capable of being selected to generate a reference current. A sense amplifier is coupled to the memory cells and the reference cells for comparing the sensing current with the reference current to generate a signal representing the logic state of the selected memory cell. The memory cells and the reference cells are subject to the same operation cycles, such that a difference between the sensing current and the reference current remains a constant.

Method of converting between non-volatile memory technologies and system for implementing the method

A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.

Method of Setting a Reference Current in a Nonvolatile Memory Device

A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.

Array architecture and write operations of thyristor based random access memory

A memory cell includes a plurality of thyristors each having a first end and a second. The memory cell further includes a plurality of bit-lines. Each of the plurality of thyristors are electrically coupled to one of the plurality of bit-lines at a first end. A local word line is electrically coupled to the second end of each of the thyristors. A selector is electrically coupled to the local word line. The selector is configured to selectively electrically couple the local word line to a data line.

Word-line voltage generator

A programmable memory circuit includes a memory array having a plurality of floating gate memory cells disposed in a first and second row and at least a first and second column and a reference circuit for providing a word line voltage to the memory array for programming selected memory cells from a selected one of the first and second rows. The word line voltage is dependent at least in part upon a bit line reference voltage and upon a threshold voltage of a reference floating gate cell associated with the selected one of the first and second rows.

Memory with dynamic feedback control circuit

A memory comprising a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is configured to boost the word line voltage to a predetermined voltage value greater than a target threshold voltage, change a clock frequency of a clock signal supplied to the charge pump from a non-zero frequency to a zero frequency if the word line voltage is above the predetermined voltage value, and change the clock frequency from the zero frequency to the non-zero frequency if the word line voltage is below the target threshold voltage.

Program and erase methods and structures for byte-alterable flash memory

An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells in the first row, a source line connecting source nodes of all flash memory cells in the first row, a word line connecting word-line nodes of all flash memory cells in the first row, and a local control-gate (CG) line connecting control-gates of flash memory cells only in the unit, wherein each local CG line is disconnected from remaining local CG lines in the first row. The array further includes bit-lines each connecting bit-line nodes of flash memory cells in a same column.

Two-transistor flash cell for large endurance application

An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell is composed of a program transistor and read transistor with a control gate connected to a word line, a source connected the source select line, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The program transistor has a drain connected a first bit line and a read transistor has a drain connected to the second bit line. Each memory cell has a floating gate connector joining the floating gate of the read transistor to the floating gate of the read transistor. The nonvolatile memory device has a voltage controller that programs the each memory cell by programming the program transistor and reading the read transistor.

Diode formed of PMOSFET and schottky diodes

A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.

Hybrid non-volatile memory device

The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell array for storing address mapping information that indicates one or more locations of one or more memory cells in the second memory cell array. The second memory cell array endures substantially more programming cycles than the first memory cell array does.

Low-dropout regulator

A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.

Memory device having RRAM-based non-volatile storage array

A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.

Memory devices with improved refreshing operation

A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.

Program and erase methods and structures for byte-alterable flash memory

An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells in the first row, a source line connecting source nodes of all flash memory cells in the first row, a word line connecting word-line nodes of all flash memory cells in the first row, and a local control-gate (CG) line connecting control-gates of flash memory cells only in the unit, wherein each local CG line is disconnected from remaining local CG lines in the first row. The array further includes bit-lines each connecting bit-line nodes of flash memory cells in a same column.

Operating resistive memory cell

A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source.

Low Dropout Regulator and Related Method

A device includes an error amplifier, a standby current source, a charging current source, a voltage divider, and a first switch. The error amplifier has a negative input terminal and a positive input terminal. The standby current source has a control terminal electrically connected to an output terminal of the error amplifier. The voltage divider has an input terminal electrically connected to an output terminal of the standby current source, and an output terminal electrically connected to the positive input terminal of the error amplifier. The charging current source has a control terminal electrically connected to the output terminal of the error amplifier. The first switch has a first terminal electrically connected to an input terminal of the charging current source, and a second terminal electrically connected to a first power supply node. 1. A device comprising:an error amplifier having a negative input terminal and a positive input terminal;a standby current source having a control terminal electrically connected to an output terminal of the error amplifier; an input terminal electrically connected to an output terminal of the standby current source, and', 'an output terminal electrically connected to the positive input terminal of the error amplifier;, 'a voltage divider havinga charging current source having a control terminal electrically connected to the output terminal of the error amplifier; and a first terminal electrically connected to an input terminal of the charging current source, and', 'a second terminal electrically connected to a first power supply node., 'a first switch having2. The device of claim 1 , wherein:the standby current source has a first dimension;the charging current source has a second dimension; andthe first dimension is smaller than the second dimension.3. The device of claim 2 , wherein:the first dimension is transistor width of a transistor of the standby current source; andthe second dimension is transistor width of a ...

Charge pump control scheme using frequency modulation for memory word line

A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage.

CHARGE PUMP CONTROL SCHEME FOR MEMORY WORD LINE

A memory includes a word line, a charge pump coupled to the word line, and a charge pump control circuit coupled to the charge pump. The charge pump control circuit is configured to turn on the charge pump if the word line voltage is lower than a first threshold voltage and turn off the charge pump if the word line voltage is higher than a second threshold voltage. 1. A memory , comprising:a word line;a charge pump coupled to the word line; anda charge pump control circuit coupled to the charge pump,wherein the charge pump control circuit is configured to turn on the charge pump if the word line voltage is lower than a first threshold voltage and turn off the charge pump if the word line voltage is higher than a second threshold voltage.2. The memory of claim 1 , further comprising a clock generator coupled between the charge pump and the charge pump control circuit.3. The memory of claim 2 , wherein the charge pump control circuit comprises a memory cell and a current detection circuit claim 2 , wherein the current detection circuit is configured to detect a cell current of the memory cell.4. The memory of claim 3 , wherein the current detection circuit comprises a current mirror circuit.5. The memory of claim 3 , wherein the current mirror circuit comprises a first PMOS transistor and a second PMOS transistor claim 3 , wherein a first drain of the first PMOS transistor is coupled to a first gate of the first PMOS transistor claim 3 , a second gate of the second PMOS transistor claim 3 , and the memory cell.6. The memory of claim 5 , wherein the current mirror circuit further comprises a first NMOS transistor and a second NMOS transistor claim 5 , wherein a second drain of the second PMOS transistor is coupled to a third drain of the first NMOS transistor claim 5 , a third gate of the first NMOS transistor claim 5 , and a fourth gate of the second NMOS transistor.7. The memory of claim 3 , wherein the charge pump control circuit further comprises a feedback control ...

Concurrent operation of plural flash memories

A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.

REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF

A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays. 1. A memory circuit , comprising:a group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface; andat least one redundancy bit line configured to selectively repair the group of memory arrays.2. The memory circuit of claim 1 , wherein the at least one redundancy bit line includes a plurality of redundancy bit lines disposed adjacent to each other and adjacent to the group of memory arrays.3. The memory circuit of claim 1 , further comprising:at least one information row coupled with the group of memory arrays, whereinthe at least one information row includes a plurality of word lines and a plurality of bit lines, and at least two of the word lines are configured to register bits of a failing address of a memory cell of the memory circuit.4. The memory circuit of further comprising:a combination logic for redundancy hit coupled with the group of memory arrays, whereinthe combination logic for redundancy hit is configured to compare the failing address and an external address, andif the failing address matches the external address, the combination logic for redundancy hit outputs a redundancy hit signal having a first state to enable the at least one redundancy bit line, andif the failing address does not match the external address, the combination logic for redundancy hit outputs the redundancy hit signal having a second state to disable the at least one redundancy bit line.5. The memory circuit of further comprising:a plurality of groups of memory arrays, anda plurality of combination logics for redundancy hit ...

CONCURRENT OPERATION OF PLURAL FLASH MEMORIES

A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. 1. A device comprising:a first circuit including a first memory and a charge pump that provides a signal used by the first memory, the first circuit configured to perform an erase, program or read operation to the first memory; anda second circuit including a second memory, the second memory being configured without a charge pump, the second memory connected to use the signal from the charge pump of the first circuit, the second circuit configured to read from the second memory while the erase, program or read operation is being performed.2. The device of claim 1 , wherein the first and second memories are flash memories.3. The device of claim 1 , wherein the first circuit has a first set of control inputs claim 1 , and the second circuit has a second set of control inputs independent from the first set of control inputs.4. The device of claim 1 , wherein charge pump is configured to output a high voltage signal.5. The device of claim 1 , wherein:the first and second circuits are formed on a single integrated circuit chip, andthe first and second circuits are configured for operating concurrently on separate data streams.6. The device of claim 1 , further comprising:at least one common ...

POWER SWITCH AND OPERATION METHOD THEREOF

A power switch includes a control circuit, a cross-coupled amplifier, a first switching circuit coupled between a first output terminal and the first controlled ground terminal, and a second switching circuit coupled between a second output terminal and the second controlled ground terminal. The control circuit is configured to connect the second controlled ground terminal to a ground during a first period that a voltage level at the first output terminal is switched from the ground to a first voltage level and to set the second controlled ground terminal at an elevated ground level during a second period that the voltage level at the first output terminal remains at the first voltage level. 1. A power switch comprising:a control circuit having a first controlled ground terminal and a second controlled ground terminal;a first switching circuit coupled between a first output terminal and the first controlled ground terminal and configured to be turned on or turned off in response to a voltage level of the first controlled ground terminal;a second switching circuit coupled between a second output terminal and the second controlled ground terminal and configured to be turned on or turned off in response to a voltage level of the second controlled ground terminal; anda cross-coupled amplifier having a power node configured to be set at a first voltage level, a first input/output node coupled to the first switching circuit, and a second input/output node coupled to the second switching circuit, connect the second controlled ground terminal to a ground during a first period that a voltage level at the first output terminal is switched from the ground to the first voltage level; and', 'set the second controlled ground terminal at an elevated ground level during a second period that the voltage level at the first output terminal remains at the first voltage level, the elevated ground level being between the ground and the first voltage level., 'wherein the control circuit ...

MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR

A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness. 1. A memory , comprising: a first capacitor having a first capacitor dielectric thickness; and', 'a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness., 'a boost circuit configured to supply a voltage higher than a supply voltage to a word line, the boost circuit including2. The memory of claim 1 , wherein the transmission gate comprises an n-well device.3. The memory of claim 2 , wherein the boost circuit further includes a second capacitor having a second capacitor dielectric thickness greater than the first capacitor dielectric thickness claim 2 , the second capacitor configured to provide a voltage higher than the supply voltage to a bulk of the n-well device.4. The memory of claim 2 , wherein an area of the first capacitor is 25% of an area of the n-well device.5. The memory of claim 1 , wherein the boost circuit further includes:a pulse generator configured to generate a first pulse;a delay buffer configured to delay the first pulse by a delay time; anda second capacitor configured to boost a voltage of a bulk in the transmission gate, wherein the first capacitor is configured to receive the first pulse delayed by the delay time and the second capacitor is configured to receive the first pulse.6. The memory of claim 1 , further comprising a second capacitor configured to boost a voltage of a bulk in the transmission gate claim 1 , wherein the second capacitor is configured to be disconnected from the word ...

VOLTAGE DIVIDING CIRCUIT

A voltage divider is disclosed that includes a plurality of components connected in series having respective input terminals, respective output terminals, and a reference voltage node at the connection between one of the input terminals and one of the output terminals. The voltage divider also includes a level shifter having a input terminal coupled to the reference voltage node and having a output terminal supplying an output reference voltage. 1. A voltage divider comprising:a plurality of components connected in series having respective input terminals, respective output terminals, and a reference voltage node at the connection between one of the input terminals and one of the output terminals; anda level shifter having an input terminal coupled to the reference voltage node and having an output terminal configured to supply an output reference voltage.2. The voltage divider of claim 1 , wherein the level shifter comprises a transistor and a controllable current source.3. The voltage divider of claim 2 , wherein the transistor is configured to have a gate coupled to the reference voltage node claim 2 , a source claim 2 , a bulk coupled to ground claim 2 , and a drain coupled to the output terminal of the level shifter.4. The voltage divider of claim 2 , wherein the controllable current source has an input coupled to the output terminal of the level shifter and an output coupled to ground.5. The voltage divider of claim 2 , wherein an output of the level shifter is configured to be smaller than a threshold voltage of the transistor.6. The voltage divider of claim 1 , wherein the plurality of components includes N components connected in series claim 1 , wherein N is an integer claim 1 , and wherein a first component includes a first input terminal which is coupled to a voltage source claim 1 , and wherein an Nth component of the plurality has an input terminal connected to an output terminal of the (N−1)th component and has an output terminal connected to ground.7 ...

FAST-SWITCHING WORD LINE DRIVER

A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level. 1. A word line driver of a semiconductor memory , comprising:logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state;a capacitor configured to be charged to a third voltage level that is greater than the first and second voltage levels; andfirst and second transistors for selectively coupling the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state,wherein the fourth voltage level is greater than the first voltage level and less than the second voltage level.2. The word line driver of claim 1 , wherein the first state is a standby state in which read and write operations are not being performed claim 1 , and the second state is a write state.3. The word line driver of claim 2 , wherein the third state is a read state.4. The word line driver of claim 1 , wherein the first voltage level is set at ground and the fourth voltage level is set at an operating voltage level for core devices of the semiconductor memory.5. The word line driver of claim 4 , wherein the third voltage level is an operating voltage level for input/output circuitry ...

ADJUSTING REFERENCE RESISTANCES IN DETERMINING MRAM RESISTANCE STATES

Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position. 1. A digital memory , comprising:an array of magnetoresistive memory bit cells, each of the bit cells comprising at least one magnetic tunnel junction element having at least two magnetic layers in a stack including a pinned layer with a permanent magnetic field establishing a reference direction, and a free layer with a magnetic field component that is selectively alignable parallel to the reference direction, thereby providing a state of low electrical resistance through the stack, and anti-parallel to the reference direction, thereby providing a state of high electrical resistance through the stack;a current bias source for supplying a current to at least a selected one of the bit cells coupled to a comparison circuit for comparing a resistance related parameter of the at least one magnetic tunnel junction element of the selected bit cell to a reference for distinguishing between the high and low resistance states;wherein the reference is based on at least one of a resistance of plural associated magnetic tunnel junction elements, and a resistance determined by a ...

Reference generation in an integrated circuit device

A method for generating a reference voltage in an integrated circuit device that is powered by a low voltage power includes generating a coarse first reference voltage using a coarse reference generator, routing the coarse first reference voltage to a boost regulator as an input reference voltage by a hand-off switch circuit, the boost regulator generating an initial-state stepped-up supply based on the first reference voltage, and generating at least two outputs of a second, more accurate, reference voltage from the stepped-up supply voltage using a fine-resolution reference generator. The second reference can be then looped back to the boost regulator, thus, generating a more accurate steady-state stepped-up supply voltage.

DIFFERENTIAL MRAM STRUCTURE WITH RELATIVELY REVERSED MAGNETIC TUNNEL JUNCTION ELEMENTS ENABLING WRITING USING SAME POLARITY CURRENT

A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array. 1. A digital memory apparatus , comprising:at least one array of magnetoresistive memory bit cells, each said bit cell in at least a subset of the array comprising at least a first magnetic tunnel junction element and at least a second magnetic junction element, wherein each of the first and second magnetic tunnel junction elements comprises a pinned magnetic layer with a permanent magnetic field aligned in a reference direction, and a free magnetic layer with a magnetic field changeably aligned parallel to the reference direction in a low resistance state or anti-parallel to the reference direction in a high resistance state;wherein the first and second magnetic tunnel junction elements are configured to maintain complementary resistance states such that one of the first and second magnetic tunnel junction elements is in a low resistance state when the other is in a high resistance state, and vice versa, thereby representing a changeable bit cell logic value;wherein one of the first and second magnetic tunnel junction elements has a normal order ...

Methods and Apparatus for Non-Volatile Memory Cells

Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data. Methods for operating the non-volatile memory cells are disclosed.

STRUCTURE AND METHOD FOR FORMING CONDUCTIVE PATH IN RESISTIVE RANDOM-ACCESS MEMORY DEVICE

An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit lines. The resistive elements of the bit cells are coupled to source lines that are parallel to word lines and perpendicular to the vertical bit lines. The bit lines are maintained at different biases. A high voltage is applied to one of the source lines coupled to adjacent resistive elements of bit cells disposed along more than one vertical bit line. When the associated transistors are turned on by a sufficiently high gate voltage, the desired RRAM resistive elements along one of the bit lines are formed without stressing other bit cells of the array. 1. A resistive random-access memory (RRAM) device comprising:a plurality of bit cells, each including a transistor and resistive element, said bit cells arranged in vertical columns, each said bit cell having said transistor having one source/drain coupled to a vertical bit line and the other source/drain coupled to a first terminal of said resistive element;a plurality of word lines coupled to respective gates of said transistors and arranged in a horizontal direction; anda plurality of source lines arranged in said horizontal direction and each coupled to an opposed terminal of at least one of said resistive elements,wherein a first source line of said source lines is coupled to two adjacent bit cells of said plurality of bit cells and biased at a sufficiently high voltage to enable said resistive elements of said two adjacent bit cells to have a conductive path formed therein, said two adjacent bit cells disposed along a first vertical bit line.2. The RRAM device as in claim 1 , wherein each said bit cell comprises a 1T1R bit cell.3. The RRAM device as in claim 1 , wherein said first source line ...

CONCURRENT OPERATION OF PLURAL FLASH MEMORIES

A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. 1. A device comprising:a first circuit providing a signal used by a first memory, the first circuit configured to perform an operation in the first memory; anda second circuit connected to use the signal from the first circuit, the second circuit configured to read from a second memory while the operation is being performed.2. The device of claim 1 , wherein the first and second memories are flash memories.3. The device of claim 1 , wherein the first circuit has a first set of inputs claim 1 , and the second circuit has a second set of inputs independent from the first set of inputs.4. The device of claim 1 , wherein the first circuit is configured to output a voltage signal.5. The device of claim 1 , wherein:the first and second circuits are formed on a single integrated circuit chip, andthe first and second circuits are configured for operating concurrently on separate data streams.6. The device of claim 1 , further comprising:at least one common address input pin, wherein at least one first address of a memory cell to be accessed in the first memory and at least one second address of a memory cell to be accessed in the second memory are both received via the at least one common address ...

Diode Formed of PMOSFET and Schottky Diodes

A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET. 1. A device comprising: a gate;', 'a first source/drain region connected to the gate;', 'a second source/drain region on an opposite side of the gate than the first source/drain region;, 'a P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) comprising a first anode connected to the first source/drain region; and', 'a first cathode connected to a body of the PMOSFET; and, 'a first Schottky diode comprising a second anode connected to the second source/drain region; and', 'a second cathode connected to the body of the PMOSFET., 'a second Schottky diode comprising2. The device of the further comprising a charge pump comprising the PMOSFET claim 1 , the first Schottky diode claim 1 , and the second Schottky diode therein.3. The device of the claim 2 , wherein the charge pump comprises a Dickson charge pump.4. The device of the claim 2 , wherein the charge pump comprises a plurality of pump cells connected in series and identical to each other claim 2 , and wherein the PMOSFET claim 2 , the first Schottky diode claim 2 , and the second Schottky diode are in one of the plurality of pump cells.5. The device of the claim 4 , wherein the first source/drain region is connected to an output node of the one of the plurality of pump cells claim 4 , and the second source/drain region is connected to an input node of the one of the plurality of pump cells.6. The device of the further comprising:a semiconductor substrate;an n-type well ...

METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING

A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current.

CHARGE PUMP

In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of a first capacitive element. The second node is coupled with a first end of a second capacitive element. A first end of a first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element and a first end of a second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage. 1. A charge pump circuit comprising:a first circuit configured to provide a first node with a first first-voltage level or a first second-voltage level;a second circuit configured to provide a second node with a second first-voltage level or a second second-voltage level;a charge transfer circuit coupled between the first node and the second node, and configured to transfer charge between the first node and the second node;a first capacitive element;a second capacitive element;a first voltage transfer circuit; anda second voltage transfer circuit, the first node is coupled with a first end of the first capacitive element,', 'the second node is coupled with a first end of the second capacitive element,', 'a first end of the first voltage transfer circuit is configured to receive an input voltage,', 'a second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element, and a first end of the second voltage transfer circuit, and', 'a second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage., 'wherein'} ...

METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD

A method of designing a charge trapping memory array includes designing a memory array layout. The memory array layout includes a first type of transistors; electrical connections between memory cells of the memory array layout; a first input/output (I/O) interface; and a charge pump. The method further includes modifying the memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes modifying the memory array layout, using the processor, to modify the charge pump based on an operating voltage of the second type of transistors. 1. A method of designing a charge trapping memory array , the method comprising: a first type of transistors,', 'electrical connections between memory cells of the memory array layout,', 'a first input/output (I/O) interface, and', 'a charge pump;, 'designing a memory array layout, the memory array layout comprisingmodifying the memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors; andmodifying the memory array layout, using the processor, to modify the charge pump based on an operating voltage of the second type of transistors.2. The method of claim 1 , wherein replacing the first type of transistors with the second type of transistors comprises replacing floating gate transistors with charge trapping transistors.3. The method of claim 1 , wherein replacing the first type of transistors with the second type of transistors comprises replacing high voltage transistors with low voltage transistors.4. The method of claim 1 , further comprising modifying the first I/O interface to form a second I/O interface having different I/O pin locations from the first I/O interface.5. The method of claim 1 , wherein the memory array layout comprises maintaining I/O pin locations of the first I/O interface.6. The method of ...

Memory devices

A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed

Fuse structure

A fuse structure comprises a first conductive layer on a first level. The first conductive layer comprises a fuse line extending in a first direction. The fuse line has a first end portion, a second end portion opposite the first end portion, and a fuse link portion connecting the first end portion and the second end portion. The first conductive layer also comprises lines parallel to the fuse line, the lines being aligned in the first direction and being separated from one another by a first distance measured in the first direction. The fuse structure also comprises a second conductive layer on a second level different from the first level and coupled with the first conductive layer. The second conductive layer has parallel lines extending in a second direction, the parallel lines being separated by a second distance measured in a third direction orthogonal to the second direction.

MEMORY DEVICES WITH IMPROVED REFRESHING OPERATION

A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level. 1. A memory device , comprising:a plurality of memory cells coupled to a bit line, wherein at least one memory cell of the plurality of memory cells is configured to store predetermined data; anda refresh module configured to refresh the at least one memory cell if a target memory cell of the plurality of memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.2. The memory device of claim 1 , wherein the refresh module is further configured to read the predetermined data from the at least one memory cell and then rewrite the predetermined data back to the at least one memory cell claim 1 , in order to refresh the at least one memory cell.3. The memory device of claim 1 , wherein if the at least one memory cell is a programmed memory cell claim 1 , the refresh module is further configured to determine if a current level of the at least one memory cell is lower than a programmed verifying current level.4. The memory device of claim 3 , wherein the refresh module is further configured to refresh the at least one memory cell if the current level of the at least one memory cell is higher than or equal to the programmed verifying current level.5. The memory device of claim 1 , wherein if the at least one memory cell is an erased memory cell claim 1 , the refresh module is further configured to determine if a current level of the at least one memory cell is higher than an erased verifying current level.6. The ...

Multiple Power Domain Electronic Device and Related Method

An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.

Operating method of memory having redundancy circuitry

In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.

MEMORY DEVICES WITH IMPROVED REFRESHING OPERATION

A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes a location-related memory cell and a refresh module. The location-related memory cell is coupled to a bit line. The refresh module is configured to refresh the location-related memory cell by reading data stored in the location-related memory cell and then writing the data back to the location-related memory cell in a condition that a target memory cell that is coupled to the bit line is programmed or erased. A method for memory cell programming and erasing with refreshing operation is also disclosed herein. 1. A memory device , comprising:a location-related memory cell coupled to a bit line; anda refresh module configured to refresh the location-related memory cell by reading data stored in the location-related memory cell and then writing the data back to the location-related memory cell in a condition that a target memory cell that is coupled to the bit line is programmed or erased.2. The memory device of claim 1 , wherein the refresh module is further configured to determine if a voltage level of the target memory cell is higher than or equal to a programmed verifying voltage level in the condition that the target memory cell is programmed.3. The memory device of claim 2 , wherein the refresh module is further configured to write the data back to the location-related memory cell when the voltage level of the target memory cell is lower than or equal to the programmed verifying voltage level claim 2 , in the condition that the target memory cell is programmed.4. The memory device of claim 3 , wherein the voltage level of the target memory cell corresponds to boundary values of a distribution curve that is associated with the stored data.5. The memory device of claim 1 , wherein the refresh module is further configured to determine if a voltage level of the target memory cell is lower than an erased verifying voltage level claim 1 , in the ...

METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD

A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference. 1. A method of designing a charge trapping memory array , the method comprising: a first type of transistors,', 'electrical connections between memory cells of the floating gate memory array layout,', 'a first input/output (I/O) interface,', 'a first type of charge pump, and', 'an I/O block;, 'designing a floating gate memory array layout, the floating gate memory array layout comprisingmodifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors;determining an operating voltage difference between the I/O block and the second type of transistors; andmodifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.2. The method of claim 1 , wherein replacing the first type of transistors with the second type of transistors comprises changing a charge storing material of the transistors.3. The method of claim 1 , wherein modifying the first charge pump comprises replacing the first charge ...

MEMORY DEVICES

A device is disclosed that includes an I/O memory block. The I/O memory block includes memory cells, bit lines and a source line. The number of the formed bit lines is at least 4. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells. 1. A device , comprising:an input/output (I/O) memory block comprising:a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns;at least four bit lines electrically connected to the plurality of memory cells configured to provide logical data to the plurality of memory cells; anda source line connected to the plurality of memory cells configured to provide the logical data to the plurality of memory cells, the source line having a main portion; anda plurality of branch portions connected to the main portion, each of the plurality of branch portions electrically connected to the memory cells in one of the plurality of rows of the matrix.2. The device of claim 1 , wherein the I/O memory block is electrically connected to a periphery circuit claim 1 , the periphery circuit comprising:a multiplexer electrically connected to the at least four bit lines to select one of the at least four bit lines; anda switch group electrically connected to the multiplexer to allow the logical data to be applied on the selected bit line and the source line in accordance with a first, second, third and fourth switching signal.3. The device of claim 2 , wherein the switch group comprises:a first switch electrically connected to the multiplexer to allow a ground voltage to be applied on the selected bit line in accordance with the first switching signal;a third switch electrically connected between the multiplexer and the first terminal of the voltage source to electrically connect the selected bit line to the voltage source in accordance with the third switching signal; anda ...

SENSING CIRCUIT, MEMORY DEVICE AND DATA DETECTING METHOD

A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage. 1. A sensing circuit , comprising:a sensing resistor;a reference resistor, a ratio of a resistance of the reference resistor to a resistance of the sensing resistor defining a sensing ratio of the sensing circuit; and a first input coupled to the sensing resistor, the first input configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor,', 'a second input coupled to the reference resistor, the second input configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor, and', 'an output, the comparator configured to generate at the output an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage., 'a comparator having'}2. The sensing circuit of claim 1 , whereinthe sensing resistor includes opposite ends coupled to a ...

MEMORY DEVICES

A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed. 1. A method , comprising:selecting a target memory cell from a plurality of memory cells of a matrix in a memory device;programming or erasing the target memory cell belonging to a line of the matrix by applying a selecting voltage to the target memory cell and a first location-related cell belonging to the line of the matrix; andperforming a first refreshing operation to refresh the first location-related memory cell.2. The method of claim 1 , wherein the first refreshing operation comprises:reading data stored in the first location-related memory cell; andwriting the data back to the first location-related memory cell.3. The method of claim 2 , wherein the first refreshing operation comprises:determining if a voltage level of the first location-related memory cell is lower than a predetermined verifying voltage level; andrewriting the data back to the first location-related memory cell when the voltage level is higher than or equal to the predetermined verifying voltage level.4. The method of claim 2 , wherein the first refreshing operation further comprises:determining if a current level of the first location-related memory cell is lower than a predetermined verifying current level; andrewriting the data back to the first location-related memory cell when the current level is higher than or equal to the predetermined verifying current level.5. The method of claim 2 , wherein ...

MEMORY DEVICE

A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells. 1. A device comprising: a first storage array comprising a plurality of first storage cells; and', 'a second storage array comprising a plurality of second storage cells configured to be in place of the first storage cells; and, 'a storage region comprisinga resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array configured to record at least one corresponding relationship between the first storage cells and the second storage cells.2. The device as claimed in claim 1 , further comprising:a controller configured to receive an access address, compare the access address with a defect address, and access the first storage array according to a repair address fixed in the RRAM-based non-volatile storage array in a case that the access address matches the defect address.3. The device as claimed in claim 2 , wherein the RRAM-based non-volatile storage array is configured to record a corresponding relationship between the defect address and the repair address in a case that one of the first storage cells corresponding to the defect address is failed.4. The device as claimed in claim 2 , further comprising:a volatile register configured to receive and store the defect address and the repair address read from the RRAM-based non-volatile storage array when the device is powered-up, and provide the defect address to the controller.5. ...

MEMORY CONTROLLER, MEMORY DEVICE AND METHOD OF OPERATING

A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell. 1. A device , comprising:a word line driver configured to be coupled to memory cells of a memory device via corresponding word lines; anda bit line driver configured to be coupled to the memory cells via corresponding bit lines; the bit line driver is configured to supply a selected bit line voltage to a selected bit line among the bit lines and supply an unselected bit line voltage to an unselected bit line among the bit lines, the selected bit line coupled to a memory cell selected to be written to among the memory cells, the unselected bit line coupled to a memory cell unselected to be written to among the memory cells,', 'the word line driver is configured to supply a selected word line voltage to a selected word line among the word lines and supply an unselected word line voltage to an unselected word line among the word lines, the selected word line coupled to the selected memory cell, the unselected word line coupled to the unselected memory cell, and', 'the unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell., 'wherein, in a write operation,'}2. The device of claim 1 ...

Resistance-based random access memory

A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node.

ACCOMMODATING BALANCE OF BIT LINE AND SOURCE LINE RESISTANCES IN MAGNETORESISTIVE RANDOM ACCESS MEMORY

A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances. 1. A magnetoresistive memory apparatus , comprising:plural bit cells, each bit cell having at least one magnetoresistive element characterized by different resistances in different logic states of the bit cell, and each said bit cell occupying a bit cell position in a memory array having plural memory words, each memory word being addressable by a word line signal during a memory access operation involving one of reading from and writing to bit cells in the memory word;a read-write circuit for the bit cell position, the read/write circuit having one of an input and an output coupled to a bit line, and the bit cell being coupled between the bit line and a source line by at least one switching transistor when the bit cell is addressed during the memory access operation, such that relative lengths of the bit line and the source line vary oppositely as a function of a location of the bit cell in the memory array;a drive control coupled to vary an input to the switching transistor as a function of relative resistance of the bit line and the source line.2. The memory apparatus of claim 1 , wherein the memory access operation ...

RESISTIVE MEMORY ARRAY AND FABRICATING METHOD THEREOF

The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure. 1. A method of fabricating a resistive memory array , comprising:forming a plurality of insulators and a conductive structure on a first substrate, wherein the insulators are electrically connected to the conductive structure;performing a resistor-forming process to transform the insulators into a plurality of resistors by applying a forming voltage through the conductive structure;polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors;providing a second substrate having a plurality of transistors and a plurality of interconnect pads respectively electrically connected to the transistors;bonding respectively the interconnect pads and the contact points; andremoving the first substrate from the resistors and the conductive structure.2. The method of claim 1 , wherein forming the insulators and the conductive structure on the first substrate comprises:forming a first conductive layer on the first substrate;forming a plurality of first vias on the first conductive layer, wherein the plurality of first vias are electrically connected to the first conductive layer;forming the insulators on the first vias, wherein the insulators are respectively electrically connected to the first vias;forming a ...

WRITE BUFFER FOR RESISTIVE RANDOM ACCESS MEMORY

A circuit includes a current generator and a voltage generator. The current generator is configured to generate a predetermined current flowing toward a selected cell in a memory array via a node during a write operation. The voltage generator is configured to generate a predetermined voltage. The voltage level at the node is clamped at a predetermined value associated with the predetermined voltage as the selected cell is switched between a low resistance state and a high resistance state during the write operation. 1. A circuit , comprising:a current generator configured to generate a predetermined current flowing toward a selected cell in a memory array via a node during a write operation; anda voltage generator configured to generate a predetermined voltage,wherein the voltage level at the node is clamped at a predetermined value associated with the predetermined voltage as the selected cell is switched between a low resistance state and a high resistance state during the write operation.2. The circuit of further comprising a first set of transistors claim 1 , wherein the current generator and the first set of transistors form a current mirror circuit.3. The circuit of claim 2 , wherein a gate of each of the first set of transistors is coupled to an output of the current generator claim 2 , and a drain of one of the first set of transistors is coupled to the node.4. The circuit of claim 2 , wherein one of the first set of transistors is configured to operate in a saturation mode.5. The circuit of further comprising a second set of transistors claim 1 , wherein a gate of each of the second set of transistors receives the predetermined voltage claim 1 , and a source of one of the second set of transistors is coupled to the node.6. The circuit of further comprising a detector coupled to a drain of one of the second set of transistors claim 5 , wherein the detector is configured to determine whether a write operation associated with a selected cell is done.7. The ...

Multiple Power Domain Electronic Device and Related Method

An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.

METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD

A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques. 1. A semiconductor arrangement comprising: a first layer comprising a first optical transmitter; and', 'a second layer comprising a second optical transmitter over the first layer, the first optical transmitter configured to transmit data from the first layer to the second layer and the second optical transmitter configured to transmit data from the second layer to the first layer., 'a three dimensional (3D) integrated circuit (IC) structure comprising2. The semiconductor arrangement of claim 1 , at least one of:the first layer comprising at least one of a first optical transceiver or a first optical receiver, the first optical transceiver comprising the first optical transmitter and the first optical receiver; orthe second layer comprising at least one of a second optical transceiver or a second optical receiver, the second optical transceiver comprising the second optical transmitter and the second optical receiver.3. The semiconductor arrangement of claim 2 , the first layer comprising at least one of a first serializer connected to the first optical transmitter or a first deserializer connected to the first optical receiver.4. The semiconductor arrangement of claim 3 , the second layer comprising at least one of a second ...

METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING

A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current. 1. A trimming method for setting a reference current used in operating a magneto-resistive random access memory (MRAM) module comprising a first MRAM cell coupled to a bit line , a plurality of reference MRAM cells coupled to a reference bit line , and a sense amplifier coupled to the bit line and the reference bit line , the method comprising:applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells;detecting the reference cell current;determining whether the detected reference cell current differs from a target reference cell current; andvarying one of the bit line reference voltage and a sensing ratio of the sense amplifier if it is determined that the detected reference cell current differs from the target reference cell current.2. The method of claim 1 , wherein the bit line reference voltage is varied by varying a control reference voltage at a first input of a first amplifier configured to control a switch claim 1 , wherein said switch is configured to selectively ...

Package with multiple plane i/o structure

A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.

Low-dropout regulator

A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.

NONVOLATILE MEMORY DEVICE AND METHOD OF SETTING A REFERENCE CURRENT IN A NONVOLATILE MEMORY DEVICE

A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell. 1. A nonvolatile memory device comprising:a cell array including a memory cell; anda reference signal generator configured to generate a reference current for reading data stored in the memory cell, the reference signal generator comprising:a first circuit coupled to a current summation node and including a reference cell, the reference cell having a floating gate and a control gate, wherein the first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell,a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current, andthe current summation node configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.2. The nonvolatile memory device of claim 1 , wherein a temperature slope of the reference current approximates that of the current flowing through the memory cell claim 1 , the temperature slope defining a rate of change of a respective current ...

Multiple-time programmable memory

A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.

LOW-DROPOUT REGULATOR

A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes. 1. A low-dropout (LDO) regulator , comprising:a first circuit operating as a closed loop control system configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage; anda second circuit operating as an open loop control system configured to increase the voltage at the first node when the voltage at the first node decreases below a first specified voltage.2. The LDO regulator of claim 1 , the first circuit comprising an operational amplifier.3. The LDO regulator of claim 2 , the specified regulator output voltage configured to be a function of a reference voltage at a non-inverting input of the operational amplifier.4. The LDO regulator of claim 1 , the first circuit comprising a first resistor with a first resistance and a second resistor with a second resistance.5. The LDO regulator of claim 4 , the specified regulator output voltage configured to be a function of the first resistance and the specified regulator output voltage configured to be a function of the second resistance.6. The LDO regulator of claim 1 , the second circuit comprising a switch connected to a voltage source.7. The LDO regulator of claim 6 , the switch configured to connect the voltage source to the first node when the voltage at the first node decreases below the first specified voltage claim 6 , for a ...

SYSTEMS, DEVICES AND METHODS FOR MEMORY OPERATIONS

Systems, devices and methods are provided for memory operations. An example system includes: a latch circuit shared by a plurality of memory blocks of a memory device and configured to provide one or more regulation signals for a memory operation; a source line circuit shared by the plurality of memory blocks and configured to provide a source line voltage to the plurality of memory blocks for the memory operation based at least in part on the one or more regulation signals; and a plurality of driver circuits configured to provide a plurality of drive signals to the plurality of memory blocks based at least in part on the one or more regulation signals. 1. A system for memory operations , the system comprising:a memory device including a plurality of memory blocks;a latch circuit shared by the plurality of memory blocks and configured to provide first and second regulation signals for a memory operation;a source line circuit shared by the plurality of memory blocks and configured to provide a source line voltage to the plurality of memory blocks for the memory operation based at least in part on the second regulation signal; anda plurality of driver circuits configured to provide a plurality of drive signals to the plurality of memory blocks based at least in part on the first regulation signal.2. The system of claim 1 , further comprising:a control signal generator configured to provide one or more control signals to the latch circuit;wherein the latch circuit is configured to provide the first and second regulation signals based at least in part on the one or more control signals.3. The system of claim 1 , further comprising:a control signal generator configured to provide a plurality of control signals to the plurality of driver circuits based at least in part on the memory operation.4. The system of claim 3 , wherein:the control signal generator is further configured to, in response to the memory operation corresponding to a read operation, provide same control ...

MEMORY WITH DYNAMIC FEEDBACK CONTROL CIRCUIT

A memory comprising a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is configured to boost the word line voltage to a predetermined voltage value greater than a target threshold voltage, change a clock frequency of a clock signal supplied to the charge pump from a non-zero frequency to a zero frequency if the word line voltage is above the predetermined voltage value, and change the clock frequency from the zero frequency to the non-zero frequency if the word line voltage is below the target threshold voltage. 1. A memory , comprising:a word line having a word line voltage;a charge pump coupled to the word line; anda dynamic feedback control circuit coupled to the charge pump, the dynamic feedback control circuit being configured to boost the word line voltage to a predetermined voltage value greater than a target threshold voltage, change a clock frequency of a clock signal supplied to the charge pump from a non-zero frequency to a zero frequency if the word line voltage is above the predetermined voltage value, and change the clock frequency from the zero frequency to the non-zero frequency if the word line voltage is below the target threshold voltage.2. The memory of claim 1 , further comprising:a clock generator coupled between the charge pump and the dynamic feedback control circuit, wherein the clock generator generates the clock signal.3. The memory of claim 2 , wherein the clock generator is a ring oscillator comprising an odd number of inverters.4. The memory of claim 2 , wherein the dynamic feedback control circuit comprises a memory cell and a current detection circuit claim 2 , wherein the current detection circuit is configured to detect a cell current of the memory cell.5. The memory of claim 4 , wherein the current detection circuit comprises a current minor circuit.6. The memory of claim 5 , wherein the current ...

CHARGE PUMP

In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of the first capacitive element. The second node is coupled with a first end of the second capacitive device. A first end of the first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive device and a first end of the second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element. 1. A charge pump circuit comprising:a first circuit configured to provide a first node with a first first-voltage level or a first second-voltage level;a second circuit configured to provide a second node with a second first-voltage level or a second second-voltage level;a charge transferring circuit coupled between the first node and the second node, and configured to transfer charge between the first node and the second node;a first capacitive element;a second capacitive element;a first voltage transfer element; anda second voltage transfer element, the first node is coupled with a first end of the first capacitive element;', 'the second node is coupled with a first end of the second capacitive device;', 'a first end of the first voltage transfer circuit is configured to receive an input voltage;', 'a second end of the first voltage transfer circuit is coupled with a second end of the first capacitive device, and a first end of the second voltage transfer circuit; and', 'a second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage., 'wherein'}2. The charge pump circuit of claim 1 , ...

STABILIZING CIRCUIT

A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V. 1. A memory structure , comprising:a first transistor and a second transistor, the first transistor connected to a node with a constant biased voltage, and the second transistor connected to the node; anda first circuit configured to inhibit a change in voltage of the constant biased voltage caused by parasitic capacitance within the memory structure, the first circuit comprising a third transistor.2. The memory structure of claim 1 , comprised within an integrated circuit using complementary metal-oxide semiconductor (CMOS) technology.3. The memory structure of claim 1 , the first transistor comprising an NMOS transistor.4. The memory structure of claim 3 , the second transistor comprising an NMOS transistor.5. The memory structure of claim 1 , the third transistor comprising an NMOS transistor.6. The memory structure of claim 4 , comprising a current mirror circuit connected to a drain of the first transistor and to a drain of the second transistor.7. The memory structure of claim 6 , the current mirror circuit comprising a fourth transistor claim 6 , a fifth transistor and a sixth transistor claim 6 , the current mirror circuit configured to induce a current to the drain of the first transistor that is equal to a current to the drain of the second transistor.8. The memory structure of claim 1 , a source of the ...

Selective Error Correction in a Data Storage Device

The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to detect a location one to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream. 1. An information encoder/decoder for a data storage device , comprising;an encoder configured to receive an input datastream having a first plurality of information bits and a first plurality of parity bits and to generate a second plurality of parity bits from the first plurality of information bits;an error checking circuitry configured to compare the first plurality of parity bits and the second plurality of parity bits to determine whether an error is present within the first plurality of information bits;an error correction circuitry configured to perform error correction on the first plurality of information bits in accordance with the first plurality of parity bits when the error is present within the first plurality of information bits to provide an error corrected datastream, the error correction circuitry being deactivated when the error is not present within the plurality of information bit: anda data selection circuitry configured to provide the first plurality of information bits as an output datastream when the error ...

MRAM SMART BIT WRITE ALGORITHM WITH ERROR CORRECTION PARITY BITS

Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location. 1. A system , comprising:write circuitry configured to attempt to write an expected multi-bit word to a memory location in a memory device;read circuitry configured to read an actual multi-bit word from the memory location; andcomparison circuitry configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word;wherein the write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.2. The system of claim 1 , wherein the write circuitry is further configured to re-write the number of erroneous bits to the memory location until the number of erroneous bits in the memory location is less than or equal to a pre-determined bitsize.3. The system of claim 2 , further comprising:error correction circuitry configured to correct the number of erroneous bits in the memory location using an error ...

MEMORY DEVICE

A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells. 1. A device comprising:a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array configured to record a corresponding relationship between a first storage cell and a second storage cell that is configured to be in place of the first storage cell.2. The device as claimed in claim 1 , wherein the RRAM-based non-volatile storage array is configured to provide a controller with a defect address corresponding to the first storage cell claim 1 , so that the controller accesses the second storage cell in a case that a received access address matches the defect address.3. The device as claimed in claim 2 , wherein the RRAM-based non-volatile storage array provides a repair address corresponding to the second storage cell to the controller claim 2 , so that the controller accesses the second storage cell according to the repair address.4. The device as claimed in claim 3 , wherein the RRAM-based non-volatile storage array is configured to record a corresponding relationship between the defect address and the repair address.5. The device as claimed in claim 1 , wherein the RRAM-based non-volatile storage array is configured to record a corresponding relationship between a defect address corresponding to the first storage cell claim 1 , and a repair address corresponding to the second storage cell claim 1 , and the second storage ...

MEMORY DEVICES WITH IMPROVED REFRESHING OPERATION

A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed. 1. A memory device , comprising:a first memory cell coupled to a bit line;a second memory cell coupled to the bit line; anda refresh module configured to read data in the second memory cell and then write the data back to the second memory cell in a condition that the first memory cell is programmed or erased.2. The memory device of claim 1 , wherein the refresh module is further configured to determine if a voltage level of the second memory cell is lower than a predetermined verifying voltage level claim 1 , or if a current level of the second memory cell is lower than a predetermined verifying current level.3. The memory device of claim 2 , wherein the refresh module is further configured to rewrite the data back to the second memory cell claim 2 , in a condition that the voltage level of the second memory cell is higher than or equal to the predetermined verifying voltage level claim 2 , or that the current level of the second memory cell is lower than the predetermined verifying current level.4. The memory device of claim 1 , wherein the refresh module is further configured to determine if a voltage level of the second memory cell is higher than or equal to a predetermined verifying voltage level claim 1 , or if a current level of the second memory cell is lower than a predetermined verifying current level.5. The memory device of claim 4 , wherein the refresh module is ...

Semiconductor device with split gate memory cell and fabrication method thereof

A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

Back-bias voltage regulator having temperature and process variation compensation and related method of regulating a back-bias voltage

Disclosed herein is a back-bias voltage regulator circuit for regulating a back-bias voltage used to control leakage current in at least one transistor within a primary circuit. In one embodiment, the back-bias voltage regulator circuit includes a voltage divider circuit configured to receive a back-bias voltage from a charge pump, and to generate a divided voltage signal by dividing the back-bias voltage based on a ratio of resistances of resistive elements within the voltage divider. In addition, the regulator circuit includes an output circuit configured to receive the back-bias voltage from the charge pump and having an output node for outputting the back-bias voltage, as well as a reference voltage circuit configured to generate a reference voltage signal based on a threshold voltage of the at least one transistor in the primary circuit. Also in such an embodiment, the regulator circuit includes a comparison circuit configured to compare the divided voltage signal to the reference voltage signal and to operate the output circuit to regulate the back-bias voltage level based on the comparison. Also disclosed is a related method of regulating a back-bias voltage to control leakage current in at least one transistor within a primary circuit.

Semiconductor device and method for manufacturing the same

Reading methods and reading architectures for reading magnetic random access memory cells

本發明提供一種讀取架構，用以讀取隨機存取記憶體(random access memory，RAM)記憶胞。此讀取架構包括多階感測側放大器、儲存模組、以及決定模組。多階感測側放大器包括複數感測放大器，且每一感測放大器具有各自之感測臨界值以及各自之感測輸出。儲存模組耦接多階感測放大器，用以儲存多階感測放大器之多個感測輸出。存模組儲存對應一RAM記憶胞之第一讀取的第一組感測輸出以及儲存對應此AM記憶胞之第二讀取的第二組感測輸出。決定模組比較第一組感測輸出以及第二組感測輸出，且根據比較結果來判斷RAM記憶胞之資料狀態。

Non-volatile memory device with a programming current control scheme

A non-volatile memory device includes at least one current source coupled to a bit line, along which at least two memory cells sharing a common source line are connected, for generating a programming current on the bit line when one of the memory cells is selected for programming operation. At least one voltage regulator is coupled to the bit line between the current source and the memory cells for allowing the programming current to flow between the current source and the selected memory cell when a voltage level on the bit line is higher than a predetermined reference voltage, and blocking the programming current flowing between the current source and the selected memory cell when the voltage level on the bit line is lower than the predetermined reference voltage, thereby preventing a punch-through across the unselected memory cell from occurring.

A digital memory, improved MRAM memory configuration, and a method for configuring an STT-MRAM

參考電路分辨磁阻記憶體元件如位元單元之高或低阻抗狀態。參考電路具有位於相反的高阻抗狀態RH以及低阻抗狀態RL之複數磁性穿隧接面元件，提供一電壓、電流或其他參數用以與需要分辨阻抗狀態之記憶體元件相比較。上述參數代表跨越RH以及RL之中間阻抗，如平均或兩相並聯之阻抗。參考MTJ元件以上述記憶體元件相同之讀取電流源偏壓，但其磁性層卻依物理上或偏壓電流路徑之相反的順序。偏壓參考MTJ元件以排除任何讀取干擾風險。上述記憶體位元單元沿著可比較的路徑耦接至相同偏壓極性源，可免除在其二可能邏輯狀態之一者時之讀取干擾風險。

Memory device

High voltage CMOS switch with reduced high voltage junction stresses

A high voltage switch circuit is disclosed for reducing high voltage junction stresses. The circuit contains a cascode device structure having one or more transistors of a same type connected in a series and being operable with a normal operating voltage and a high operating voltage. The cascode device structure comprises a high operating voltage coupled to a first end of the device structure, a low voltage coupled to a second end, and one or more control voltages controllably coupled to the gates of the transistors, wherein at least one of the control voltages coupled to the gate of at least one transistor is raised to a medium voltage level that is higher than a normal operating voltage when operating under the high operating voltage for tolerating stress imposed thereon by the high operating voltage.

An array of flash memory cells and an integrated circuit comprising an array of memory cells

Semiconductor device and method for manufacturing the same

本發明提供半導體元件與其形成方法。半導體元件包括基板，其包括金氧元件。金氧元件包括第一摻雜區與第二摻雜區於基板中，且第一摻雜區與第二摻雜區交界於通道區中。第一摻雜區與第二摻雜區摻雜有第一型的摻質。第一摻雜區與第二摻雜區之摻雜濃度不同。金氧元件更包含閘極結構，其橫越通道區與第一摻雜區及第二通道區之間的交界，並分隔源極區與汲極區。源極區係形成於第一摻雜區中，且汲極區係形成於第二摻雜區中。源極區與汲極區摻雜有第二型的摻質，且第一型的摻質與第二型的摻質之型態相反。

Memory devices with improved refreshing operation

A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.

Adaptive Control of Programming Currents for Memory Cells

A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation.

電阻式隨機存取記憶體之寫入緩衝器

本申請案提供包含電流產生器與電壓產生器的電路。在寫入操作過程中，該電流產生器係用於產生預定電流，經由節點流至記憶體陣列中所選擇的胞元。該電壓產生器係用於產生預定電壓。在該寫入操作過程中，當該所選擇的胞元在低電阻狀態與高電阻狀態之間切換時，該節點的電壓位準被箝制為與該預定電壓相關的預定值

Memory testing apparatus

The present invention discloses a memory testing apparatus. The testing apparatus can be embedded on a chip with embedded memory block or a memory chip to reduce the testing time of memory blocks or memory devices. Through the selection of testing modes and the data processing of the processing device, the correctness of the output data of a memory block can be represent with the data state of a verifying data. The data output can be pre-processed and simplified as the verifying data to reduce the test time. The apparatus for testing memories includes a memory block, a processing device, and a mode selecting device. An output data is read out from the memory block. The processing device is employed for processing the output data to generate a verifying data. The verifying data has a bit number less than a that of the output data. The mode selecting device is utilized for selecting testing modes of the processing device. In the case, the testing modes includes an all-high mode, an all-low mode, a data pattern verifying mode, and a by-pass mode.

多次可程式記憶體架構、互補金屬氧化物半導體多次可程式記憶體架構、以及操作多次可程式記憶體架構之方法

本發明揭露一種多次可程式記憶體(multiple-time programmable,MTP)架構。該多次可程式記憶體架構被提供以操作使用在具有1.5伏特至5.5伏特供應電壓之一供應電源。當供應電壓大於一第一電壓時，一第一電路被配置以在一第二電晶體之一汲極引發一第二常數電壓，以及在一第三電路中之一端點引發該第二常數電壓。在一些實施例中，該第三電路提供一第三電壓至一第三電晶體之一閘極。當該供應電壓低於該第一電壓，一第五電路被配置以在該第三電路中之一端點引發一第四常數電壓。該第四常數電壓等於該第二常數電壓。

Ｍｒａｍ感知基準トリミング方法とメモリ装置

【課題】ＭＲＡＭ感知基準トリミング方法とメモリ装置を提供する。 【解決手段】具体例において、ビットラインに結合される操作ＭＲＡＭセル、基準ビットラインに結合される複数の基準ＭＲＡＭセル、および、ビットラインと基準ビットラインに結合されるセンス増幅器を含むＭＲＡＭモジュールを操作するのに用いられる基準電流を設定するトリミングプロセスが開示される。プロセスは、ビットライン参照電圧を、基準ビットラインに加えて、複数の基準ＭＲＡＭセルにより、個別の電流の合計から生成される基準セル電流を提供する工程を含む。基準セル電流が検出される。検出された基準セル電流が、ターゲット基準セル電流と異なるか判断する。検出された基準セル電流が、ターゲット基準セル電流とは異なると判断する場合、ビットライン参照電圧が変化する、または、センス増幅器の検知比率が変化する。 【選択図】図１Ａ