УСТРОЙСТВО С ПАССИВНОЙ МАТРИЧНОЙ АДРЕСАЦИЕЙ И СПОСОБ СЧИТЫВАНИЯ ИНФОРМАЦИИ ИЗ ЭТОГО УСТРОЙСТВА

Изобретение относится к способу считывания информации из устройства с пассивной матричной адресацией и может быть применено в сенсорных устройствах с индивидуально адресуемыми ячейками на основе поляризуемого материала. Техническим результатом является устранение мешающих напряжений и токов утечки при деструктивном считывании ячеек и обеспечение параллельного считывания из нескольких ячеек. Устройство с пассивной матричной адресацией индивидуальных ячеек содержит электрически поляризуемый материал, обладающий гистерезисом, первый и второй наборы параллельных электродов, формирующих управляющие шины и шины данных, которые в зонах скрещивания в объеме поляризуемого материала образуют ячейки, содержащие структуры типа конденсатора, а также содержит средства управления и средства детектирования. Способ описывает процесс считывания данных из указанного устройства. 2 н. и 3 з.п. ф-лы, 4 ил.

ГИБРИДНОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО

Изобретение относится к гибридным запоминающим устройствам. Технический результат заключается в повышении быстродействия памяти при том же размере и емкости памяти. Описываются запоминающие устройства, контроллеры и электронные устройства, содержащие запоминающие устройства. В одном варианте осуществления изобретения запоминающее устройство содержит энергозависимую память, энергонезависимую память и контроллер, содержащий буфер памяти и логический блок для передачи данных между энергонезависимой памятью и энергозависимой памятью через буфер памяти в ответ на запросы от приложения, при этом данные в буфере памяти являются доступными для приложения. Также раскрываются и заявляются другие варианты осуществления изобретения. 3 н. и 14 з.п. ф-лы, 11 ил.

УСТРОЙСТВО ПОЛУПРОВОДНИКОВОЙ ПАМЯТИ ДЛЯ ДОСТИЖЕНИЯ ВЫСОКОЙ ПРОИЗВОДИТЕЛЬНОСТИ И СПОСОБ РАСПОЛОЖЕНИЯ В НЕМ СИГНАЛЬНЫХ ШИН

Изобретение относится к устройству полупроводниковой памяти. Техническим результатом является высокая производительность указанного устройства без использования отдельной локальной шины ввода-вывода для соединения битовой шины и главных шин ввода-вывода. Устройство содержит банки памяти, множество битовых шин, шин ввода-вывода данных (сигнальных шин), шин выбора столбца (сигнальных шин), словных шин, главную шину ввода-вывода данных, транзисторы считывания, транзисторы для записи, мультиплексор. Способ описывает расположение в нем сигнальных шин. 2 с. и 1 з.п. ф-лы, 13 ил.

ТВЕРДОТЕЛЬНОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО ДЛЯ ХРАНЕНИЯ ДАННЫХ, БЕСПРОВОДНЫМ ОБРАЗОМ ПЕРЕДАВАЕМЫХ С ХОСТА, И ДЛЯ БЕСПРОВОДНОЙ ПЕРЕДАЧИ ДАННЫХ НА ХОСТ

... 1. Твердотельное запоминающее устройство для хранения данных, беспроводным образом переданных с хоста, и для беспроводной передачи данных на хост, включающее:радиочастотный модуль (РЧ-модуль), который демодулирует сверхширокополосный сигнал записи, беспроводным образом полученный с хоста, и выдает сигнал записи беспроводного протокола;контроллер беспроводного протокола, имеющий уровень преобразования протокола, который преобразовывает сигнал записи беспроводного протокола в сигнал записи USB-протокола;микроконтроллер, имеющий уровень извлечения функции для извлечения команды записи из сигнала записи USB-протокола и в ответ на эту команду записи управляющий записью данных, извлеченных из сигнала записи USB-протокола, на твердотельную память для сохранения этих данных на твердотельной памяти;причеммикроконтроллер также считывает данные, хранящиеся в твердотельной памяти, в ответ на команду чтения, полученную с хоста, и выводит сигнал чтения USB-протокола на контроллер беспроводного протокола ...

СХЕМА ДВОЙНОГО ПИТАНИЯ В СХЕМЕ ПАМЯТИ

... 1. Полупроводниковое устройство памяти с двойным напряжением, содержащее: ! множество формирователей записи, принимающих входные сигналы данных низкого напряжения и, в ответ, записывающих значения данных в сердечник памяти; ! схему отслеживания синхронизации, функционирующую для обеспечения задержки сигнала числовой шины высокого напряжения в соответствии со временем, связанным с множеством формирователей записи, записывающих данные в сердечник памяти; и ! множество ячеек памяти, реагирующих на сигнал числовой шины высокого напряжения и на формирователи записи, записывающие значения данных, для сохранения в них данных. ! 2. Полупроводниковое устройство памяти с двойным напряжением по п.1, дополнительно содержащее множество разрядных шин, подключенных к формирователям записи, чтобы принимать значения данных. ! 3. Полупроводниковое устройство памяти с двойным напряжением по п.1, дополнительно содержащее: ! множество схем сдвига уровня адресного сигнала, сконфигурированных с возможностью преобразования ...

ПСЕВДОДВУХПОРТОВАЯ ПАМЯТЬ С СИНХРОНИЗАЦИЕЙ ДЛЯ КАЖДОГО ПОРТА

... 1. Псевдодвухпортовая память, содержащая: ! массив ячеек памяти, при этом каждая ячейка памяти массива представляет собой ячейку памяти с шестью транзисторами; ! первый порт, содержащий первое множество линий ввода адреса и линий ввода синхронизирующих импульсов, при этом первый переход от низкого уровня к высокому первого входного синхронизирующего сигнала на линии ввода синхронизирующих импульсов первого порта вызывает защелкивание адреса в первом множестве линий ввода адреса в псевдодвухпортовой памяти и инициирует первое обращение к памяти массива ячеек памяти; и ! второй порт, содержащий второе множество линий ввода адреса и линию ввода синхронизирующих импульсов, при этом: ! в первом случае: переход от низкого уровня к высокому второго входного синхронизирующего сигнала на линии ввода синхронизирующих импульсов второго порта в течение первого периода времени должен вызвать защелкивание адреса по второму множеству линий ввода адреса в псевдодвухпортовой памяти и должен вызывать инициирование ...

ФОТОЭЛЕКТРИЧЕСКОЕ ИЛИ ЭЛЕКТРЕТНОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО И СПОСОБ УПРАВЛЕНИЯ ПОДОБНЫМ УСТРОЙСТВОМ

... 1. Способ управления ферроэлектрическим или электретным запоминающим устройством, содержащим ячейки памяти на основе тонкопленочного поляризуемого ферроэлектрического или электретного материала, обладающего гистерезисом, например, на основе тонкой ферроэлектрической или электретной полимерной пленки, и первый и второй наборы электродов, взаимно параллельных в пределах одного набора, причем электроды первого и второго наборов расположены, по существу, ортогонально по отношению к электродам другого набора и находятся в прямом или непрямом контакте с тонкопленочным материалом, образующим ячейки памяти, а поляризационное состояние индивидуальных ячеек памяти можно считывать, обновлять или записывать путем подачи соответствующих напряжений на индивидуальные электроды первого и второго наборов, причем способ реализует протокол подачи импульсов напряжения заданной амплитуды и длительности, включающий циклы считывания и записи/обновления, состоящие из временных последовательностей импульсов напряжения ...

Halbleiterspeichervorrichtung

Halbleiterspeichervorrichtung, umfassend: ein Speicherfeld (100) mit einem ersten, zweiten, dritten und vierten Feldblock (10–40), wobei die Feldblöcke in Form einer 2×2-Matrix angeordnet sind und dadurch zwei Zeilen und zwei Spalten von Feldblöcken bilden; eine Vielzahl von zwischen den Zeilen der Feldblöcke angeordneten Anschlußflächen; einen in einem Zentrumsbereich (70) des Speicherfelds angeordneten Datenpfadschaltkreis (50, 112, 114, 122, 124, 212, 214, 222, 224): eine Vielzahl von Datenleitungen (DL), die die Anschlußflächen mit dem Datenpfadschaltkreis verbinden; und eine Vielzahl von Haupteingangs/Ausgangsleitungen (MIO), die die Feldblöcke mit dem Datenpfadschaltkreis verbinden, dadurch gekennzeichnet, daß die Halbleiterspeichervorrichtung ferner einen zwischen den Spalten der Feldblöcke angeordneten Datenpfadsteuerschaltkreis (60) umfaßt; und die Vielzahl der Haupteingangs/Ausgangsleitungen lediglich zwischen den Zeilen der Feldblöcke angeordnet sind.

Halbleiterspeicheranordnung

Boundary Scan-Kette für gestapelten Speicher

Eine Boundary Scan-Kette für gestapelten Speicher. Eine Ausführungsform eines Speichergeräts umfasst ein Systemelement und einen Speicherblock, der eine oder mehrere Speicherchiplagenschichten umfasst, wobei jede Speicherchiplagenschicht Eingabe-Ausgabe-(I/O)-Zellen und eine Boundary Scan-Kette für die I/O-Zellen umfasst. Eine Boundary Scan-Kette einer Speicherchiplagenschicht umfasst einen Scankettenteil für jede der I/O-Zellen, wobei der Scankettenteil für eine I/O-Zelle einen ersten Scanlogik-Multiplexer umfasst, einen Scanlogik-Latch, wobei ein Eingang des Scanlogik-Latches mit einem Ausgang des ersten Scanlogik-Multiplexers gekoppelt ist, und einen Decoder, um Befehlssignale an die Boundary Scan-Kette bereitzustellen.

Speicherbaustein

Speicherbaustein (700), aufweisend: mehrere industriestandardisierte integrierte dynamische Direktzugriffsspeicher(DRAM)-Schaltkreise (720), die in einer vertikalen Richtung gestapelt sind, wobei die mehreren integrierten DRAM-Schaltkreise einen Arbeitspool (885, 886) von integrierten DRAM-Schaltkreisen und einen Ersatzpool (895) von integrierten DRAM-Schaltkreisen aufweisen; und einen integrierten Pufferschaltkreis (710) zum Bilden einer Schnittstelle zwischen den integrierten DRAM-Schaltkreisen und einem Speicherbus (730) durch Puffer von Adress- und/oder Steuer- und/oder Datensignalen, um elektrische Lasten der integrierten DRAM-Schaltkreise von dem Speicherbus elektrisch zu isolieren, wobei der integrierte Pufferschaltkreis konfiguriert ist, um zumindest einen integrierten DRAM-Schaltkreis von dem Arbeitspool von integrierten DRAM-Schaltkreisen durch zumindest einen integrierten DRAM-Schaltkreis von dem Ersatzpool von integrierten DRAM-Schaltkreisen zu ersetzen.

AKTIVABSCHLUSSSCHALTUNG UND VERFAHREN ZUR STEUERUNERTEN SCHALTUNGEN

Signalübertragungssystem

Integrierte Schaltung umfassend Speichermodul mit einer Mehrzahl von Speicherbänken

Eine integrierte Schaltung umfassend ein Speichermodul mit einer geraden Anzahl von Speicherbänken, die mindestens vier ist. Jede Speicherbank weist eine Mehrzahl von Speicherzellen auf, wobei jeweils zwei Speicherbänke einen Speicherbankbereich bilden und wechselweise mit einem m-Bit-Datenbus verbunden sind. Die Speicherbänke sind in zwei Gruppen unterteilt, wobei jede Gruppe eine Speicherbank jedes Speicherbankbereichs umfasst. Das Speichermodul umfasst weiterhin eine Auswahleinheit, die mit den Speicherbänken verbunden ist und die auf Auswahlbits reagiert. Die Auswahleinheit wählt eine der zwei Speicherbankgruppen und eine Gruppe von i-Speicherzellen innerhalb der Speicherbank der ausgewählten Speicherbankgruppe aus, um über die zugehörigen m-Bit-Datenbusse der Speichergruppen, die die ausgewählten Speicherbänke umfassen, auf die ausgewählten i-Speicherzellen pro Takt zuzugreifen, wobei m gleich einem ganzzahligen Vielfachen von i ist.

Hierarchische Spaltenleitungsauswahl für Multi-Bank-DRAM-Speicher und Verfahren dazu

Semiconductor memory element, has multiple inlet or outlet ports for entering command signals for mode revitalization operation, and memory field, which has divided storage area that is accessible over multiple inlet or outlet ports

The semiconductor memory element has multiple inlet or outlet ports for entering command signals for a mode revitalization operation, and a memory field (190), which has a divided storage area that is accessible over multiple inlet or outlet ports. The memory field is divided into different storage areas. A distribution control block (300) assigns a right of access in reaction to an external command signal, where the distribution control block produces distribution control signals. Independent claims are also included for the following: (1) a method for assigning a right of access, which involves assigning a right of access, over a divided storage area (2) a method for refreshing storage areas in a semiconductor memory element, which involves refreshing two storage area in two mode.

HALBLEITERSPEICHERVORRICHTUNG

Verfahren und Vorrichtung zum Betreiben von maskierbaren Speicherzellen

Verfahren zum Betreiben einer Mehrzahl von maskierten Speicherzellen, die in zumindest zwei Spalten organisiert sind, wobei jede Spalte ein einzelnes Maskensignal verwendet, wobei das Verfahren folgende Schritte umfasst:Bereitstellen zumindest eines logisch gültigen Maskensignals an zumindest einer Speicherzelle zumindest einer ausgewählten Spalte einer durch ein Wortleitungssignal ausgewählten Zeile, wobei auf die Speicherzelle zugegriffen werden soll; undBereitstellen eines logisch ungültigen Maskensignals an Speicherzellen aller anderen Spalten der durch das Wortleitungssignal ausgewählten Zeile außer der zumindest einen ausgewählten Spalte.

Continuous read burst support at high clock rates

Storage device with multi tiered caches for increasing transmission speeds between system and a solid state memory

A storage device comprises a controller having an external interface (104), an interface (106) to a solid state memory (20) and a plurality of data stores or buffers (110,112) disposed between the interfaces. The data stores or buffers are in tiers such when data is being written to the first store (110), data can be transferred to the memory interface (106) from the second store in a first cycle (Fig 4A). In a second cycle data is transferred from the first store to the memory whilst data is written to the second store (Fig 4B). The continuing alternation of the read/write stages allows transmission throughput between the system and memory to be increased. In a further embodiment (Fig 5) two sets of data buffers may be used either side of a compression module such that the speed of compressing data is increased.

Memory system for a multi threaded processor

A multi threaded processor has a memory system 900 in which there is a plurality of entries 920. Each entry has a plurality of active cells 901E-904E for storing data corresponding to each of the threads or tasks of the processor. A shared read cell 930 is connected to the active cells to combine their output into a single read bit line 910. The active cells may be connected using a thread select circuit. The read cell may be a gate, the inputs of which are connected to the outputs of the active cells. The active cell may be connected to a number of base cells 901-904 to which the contents of the active cell may be saved and restored. The memory system may be incorporated in the processor as a register file.

Digital memory device

A digital circuit is disclosed which includes a micro processor 10 having one input port I1 and a plurality of output ports O1 - O3. The output ports are connectable to the input port via respective links 1a - 1c, which may be selectively removed. The micro processor then establishes the pattern of connected or removed links 1a - 1c by supplying signals to the output ports O1 - O3 and measuring the response to these signals at the input port I1. The effective memory capacity of one input port compared to the input port being tied to the low or high logic level is thus increased. More elaborate embodiments with further input ports, and with resistors in the connection paths, are disclosed (Figs. 2-5). ...

Per byte lane dynamic on-die termination

Non-volatile memory error mitigation

DRAM WITH HALF ONE AND FULL ONE DENSITY ENTERPRISE

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

PROCEDURE FOR THE ENTERPRISE OF AN FERROUSELECTRICAL OR ELEKTRET OF MEMORY MODULE AND COMPONENT OF THIS KIND

PSEUDO DOUBLE HAVEN MEMORY WITH A CLOCK PULSE FOR EACH HAVEN

STORAGE CONTROL WITH ALTERNATING CURRENT PHOTOGRAPH DECREASE BY NON TRAINING RUN RETURN OF ADDRESS AND CONTROL SIGNALS

INTEGRATED CIRCUIT AND PROCEDURE FOR THE TRANSACTION CANCELLATION

MULTI-LEVEL CELL ENTRANCE BUFFER WITH DOUBLE FUNCTION

DYNAMIC ONE PERIPHERIEFUNKTIONSUMABBILDUNG ON EXTERNAL ENTRANCE PARENT COMPOUNDS OF AN INTEGRATED SWITCHING CONFIGURATION

SWITCHING CONFIGURATION TO WOULD DRIVE THROUGH AN ON CHIP TIME NESTING OF THE ACCESS TO DYNAMIC RAM COMPONENTS.

SEMICONDUCTOR MEMORY.

COMMUNICATION PROTOCOL FOR DYNAMIC MEMORY

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SOLID MEMORY MODULE FOR WIRELESS STORING OF DATA SENT FROM A HOST AND FOR WIRELESS SENDING OF THE DATA TO THE HOST

SYSTEM AND METHOD FOR TRANSLATION OF SDRAM AND DDR SIGNALS

MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF CONTROLLING READ VOLTAGE OF THE MEMORY DEVICE

A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation MEMORY CONTROLLER MEMORY DEVICE 711 CTRL z21 ECC PROCESSING MEMORY UNIT CMD CELL ARRAY 1112 -F 22 READ VOLTAGE ADDR [ PAGE BUFFER DETERMINING UNI T j UNIT COUNTING UNIT VOLTAGE VWL ROW WL MEMORY GENERATOR DECODER CELL ARRAY ZCL ,'BL z22 CTRL PAGE BUFFER CONTROL LOGIC UNIT CMD ADDR 23 COUNTING UNIT 1 TO 10A ...

Low latency multi-level communication interface

SYSTEM FOR READING AND WRITING INFORMATION

SYSTEM FOR READING AND WRITING INFORMATION First binary bits are read synchronously relative to clock signals (e.g. 125 MHz) from first memory positions and second binary bits are read from, or written in, second memory positions asynchronously relative to the clock signals without affecting the reading of the first memory bits. For synchronously reading the first bits, a plurality of channels are sequentially activated at a suitable frequency (e.g. 25 megahertz). Information from pairs of data lines are introduced into a pair of buses at the clock frequency. The information in the buses is sampled upon the occurrence of the first polarity in synchronizing signals having frequency (e.g. 62.5 MH3) derived from the clock signals and is prolonged and evaluated in a first pair of output lines upon the occurrence of the second polarity in the synchronizing signals. The information being evaluated is introduced to such output lines during the occurrence of the first polarity in the synchronizing ...

SEMICONDUCTOR MEMORY DEVICE HAVING A THREE-DIMENSIONAL STRUCTURE

A three-dimensional memory device includes a stack of semiconductor layers. Phase change memory (PCM) cell arrays are formed on each layer. Each PCM cell includes a variable resistor as storage element, the resistance of which varies. On one layer, formed is peripheral circuitry which includes row and column decoders, sense amplifiers and global column selectors to control operation of the memory. Local bitlines and worldliness are connected to the memory cells. The global column selectors select global bitlines to be connected to local bit lines. The row decoder selects wordlines. Applied current flows through the memory cell connected to the selected local bitline and wordline. In write operation, set current or reset current is applied and the variable resistor of the selected PCM cell stores "data". In read operation, read current is applied and voltage developed across the variable resistor is compared to a reference voltage to provide as read data.

MASS STORAGE DEVICES PACKAGES AND SOFTWARE-DEFINED ARRAYS OF SUCH PACKAGES

Semiconductor Devices Having Initialization Circuits And Semiconductor Systems Including The Same

Sensing circuit

In the PLC for the MPU and memory between the method of transmitting and receiving data

SEMICONDUCTOR MEMORY DEVICE

PROCEEDED OF READING ANTICIPEE OF MEMORY HAS ACCESS SERIES AND MEMORY REFERRING ITSELF TO it

L'invention propose un procédé de lecture d'une mémoire (1) à accès série tel qu'on commence le décodage d'adresse alors que les bits d'adresse n'ont pas encore tous été reçus. On extrait alors toutes les informations correspondant à l'adresse partiellement décodée, et on sélectionne, quand on a reçu les derniers bits d'adresse, l'information correspondant à l'adresse complète. On augmente ainsi de manière interne le délai maximal admissible pour extraire une information, ce délai restant identique vu de l'extérieur de la mémoire, pour une fréquence donnée. L'invention concerne également une mémoire mettant en oeuvre ce procédé.

Semiconductor memory device and method for layout of the same

TRIMMING CIRCUIT AND METHOD FOR DRIVING TRIMMING CIRCUIT

MEMORY DEVICE

A memory device includes: multiple first lines; multiple second lines; multiple bank groups including one or more banks; and a column signal transfer unit configured to transfer one or more column command signals and one or more column address signals in an odd column command through first lines, and the column command signals and the column address signals in an even column command through second lines. Thereby, the present invention minimizes the number of lines to transfer the command signal and the address signal and secures a margin which transfers the command signal and the address signal by each band group. COPYRIGHT KIPO 2016 (210) Mode setting unit (220) Column signal transfer unit ...

SEMICONDUCTOR MODULE WITHOUT TIE BAR IN TAB PIN

According to the present invention, a semiconductor module without a tie bar in a tab pin is disclosed. The semiconductor module comprises: a printed circuit board having an integrated circuit chip loaded thereon; connecting terminals arranged at an edge part of the printed circuit board; via holes arranged in signal lines which correspondingly connect electrical connection pads of the integrated circuit chip to the connecting terminals; and plating lines connected to the via holes. The connecting terminals are plated by using the via holes of the printed circuit board connected to the plating lines. COPYRIGHT KIPO 2016 ...

감지 회로를 사용한 패리티 결정을 위한 장치들 및 방법들

... 본 개시는 감지 회로를 사용한 패리티 결정들에 관련된 장치들 및 방법들을 포함한다. 예시적인 방법은 감지 회로를 사용하여, 입력/출력 라인을 통해 어레이로부터 데이터를 전송하지 않고 다수의 데이터 값들에 대응하는 패리티 값을 결정함으로써 어레이의 감지 라인에 결합된 각각의 수의 메모리 셀들에 저장된 다수의 데이터 값들을 보호하는 단계를 포함할 수 있다. 패리티 값은 예를 들어, 다수의 XOR 연산들에 의해 결정될 수 있다. 방법은 감지 라인에 결합된 또 다른 메모리 셀에 패리티 값을 저장하는 단계를 포함할 수 있다.

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE

SEMICONDUCTOR MEMORY DEVICE

The present invention relates to a semiconductor memory device which normally stores data and enables a test to be conducted on whether the data, which has been stored, is normally output. The semiconductor memory device comprises: a first comparison unit which, in response to a plurality of channel selection signals, compares a plurality of pieces of channel data with each other to generate a first comparison signal, or outputs one of the pieces of channel data as the first comparison signal; a second comparison unit which compares the pieces of channel data to generate a second comparison signal based on the channel selection signals and a channel detection signal; a channel selection detection unit which enables the channel detection signal when only one channel selection signal among the channel selection signals is enabled; and a combined output unit which enables a test result signal when at least one of the first and second comparison signals is enabled. COPYRIGHT KIPO 2016 (100) ...

PROGRAMMING DATA INTO A MULTI-PLANE FLASH MEMORY

SEMICONDUCTOR MEMORY DEVICE HAVING A DATA INPUT/OUTPUT PORT, AND A MEMORY MODULE AND A MEMORY SYSTEM USING THE SAME, DETERMINING ENABLE OF A DATA INPUT/OUTPUT PORT SELECTIVELY FOR REPEAT-TRANSMISSION OF WRITE DATA

PURPOSE: A semiconductor memory device having a data input/output port, and a memory module and a memory system using the same are provided to reduce power consumption of the memory system requiring repeat-transmission of data by connecting a number of memories in a daisy chain method. CONSTITUTION: A packet decoder(208) decodes a packet command including device ID information and generates a first signal if the decoded device ID information is different from stored ID information and the packet command is a read command. A data input port(212) and a data output port(218) are enabled in response to the first signal. A register(206) stores the device ID information. The packet decoder generates a second signal if the decoded device ID information coincides with the ID information stored in the register and the packet command is a read command, and the data output port is enabled in response to the second signal. © KIPO 2008 ...

POST DRIVER

A post driver comprises a source follower and a first sub-unit. The source follower comprises an input unit to receive a first voltage from a pad, and an output unit to provide a second voltage. The first sub-unit comprises a first transistor and a second transistor. The first transistor is coupled between the pad and a first power rail, and is configured to operate in a sub-threshold region in response to the second voltage and a first range of the first voltage. The second transistor is coupled in parallel with the first transistor between the pad and the first power rail, and is configured to electrically connect the pad to the first power rail in response to a second range of the first voltage. COPYRIGHT KIPO 2016 (110) Core circuit (120) Level shifter (130) Pre driver (241) Pull-up unit (242) Pull down ...

Storage apparatuses and method of operating the same

System and method of operating a memory device

A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.

Path isolation in a memory device

Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation ...

Data output circuit and method for driving the same

A data output circuit includes a data driving unit suitable for driving a data transmission line with a driving voltage corresponding to data during a data transmission operation, and a charging/discharging unit suitable for storing charges on the data transmission line and reuse the stored charges as the driving voltage.

Mass data storage system with non-volatile memory modules

A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain.

Access circuit

An access circuit is provided to properly decrease the time demanded for accessing a buffer memory according to an outside command. In a control unit, a data-unit-specifying signal is regarded as an address signal and is output to the address-decoder. The data-unit-specifying signal specifies data among one byte, one word and two words to be the access amount of a SDRAM in one period of the operation clock of the access circuit. A request-generation part outputs a request signal for commanding an access in this data amount according to data-accessing amount decoded by an address decoder. The memory interface accesses the SDRAM in the access amount corresponding to the request signal from the specified address when the head of the data for accessing the SDRAM is specified by an outside command.

Memory system having two-way ring topology and memory device and memory module for ring-topology memory system

A memory system, memory module and memory device are described. The memory system includes a plurality of the memory modules connected in a series configuration on a first signal path. The first signal path and a second signal path carry memory control and data signals between the memory modules and a memory controller. The memory controller transmits and receives the control signals and data signals on the first and second signal paths. The first and second signal paths are connected together such that the memory modules are connected in a ring configuration. The control signals and data signals travel in opposite directions on the first and second signal paths. The first and second signal paths are shared by both the data signals and the control signals. The memory modules include multi-functional ports, each of which can receive both the control signals and the data signals and re-drive the signals onto the connected signal paths. The memory device in accordance with the invention can ...

Apparatuses and methods for in-memory operations

The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The apparatus also includes a controller configured to direct a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset and performance of a sequential plurality of operations in-memory on the number of data values by the first sensing circuitry coupled to the first subset.

Memory cell and memory array

Memory device capable of changing data output mode

Disclosed herein is a memory device capable of changing data output modes. According to the present invention, an address that is input to a circuit, which is designed in 8-bit output mode, is internally modified, to operate in 16-bit output mode, and a test operation is performed in 8-bit output mode. As such, two kinds of output mode circuits can be tested in one test equipment. Accordingly, test efficiency can be enhanced and costs can be saved.

Memory system and method with serial and parallel modes

Semiconductor device and driving method thereof

Memory device and semiconductor device including the memory device

SYSTEM HAVING ONE OR MORE MEMORY DEVICES

A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

APPARATUS AND METHOD FOR STORAGE DEVICE READING

According to an example, a method for storage device reading may include receiving an input signal indicative of a period of oscillation of a ring oscillator coupled to a storage device of a plurality of storage devices, and measuring the period of oscillation of the ring oscillator by a time-to-digital circuit. The method for storage device reading may further include determining a value of data stored in the storage device based on the measurement.

APPARATUS AND METHOD FOR SELECTIVELY CONFIGURING A MEMORY DEVICE USING A BI-STABLE RELAY

The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system includes input, output, and data storage devices, a processor coupled to the devices, a memory device coupled to the processor, and a configuration circuit interposed between the processor and the memory device to selectively couple lines in the address, control and data busses of the processor to lines in the address, control and data busses of the memory device. In another embodiment, a memory device includes an array coupleable to one or more busses of an external device and a configuration circuit between the array and the busses of the external device to selectively couple the busses to the memory cell array. In a particular embodiment, the configuration circuit includes one or more bi-stable relays, such as Micro-Electrical-Mechanical System (MEMS) relays.

APPARATUSES AND METHODS FOR STORING A DATA VALUE IN A SENSING CIRCUITRY ELEMENT

The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

Method for reducing output data noise of semiconductor apparatus and semiconductor apparatus implementing the same

Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.

Apparatus for data recovery in a synchronous chip-to-chip system

An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Memory for a voltage regulator circuit

A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Protocol for communication with dynamic memory

A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be perform ed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than ...

Memory with improved write mode to read mode transition

A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.

Column selecting circuit in semiconductor memory device

Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

Data transfer apparatus with large noise margin and reduced power dissipation

In a data transfer apparatus powered by first and second power supply voltages, a data output circuit generates first complementary output signals, a data transfer circuit having a large load capacitance transfers the first complementary output signals to generate second complementary output signals, and an amplifier circuit amplifies the second complementary output signals to generate third complementary output signals. A first transfer gate circuit is connected between the data output circuit and the data transfer circuit. A second transfer gate circuit is connected between the data transfer circuit and the amplifier circuit. The first, second and third complementary output signals are caused to be approximately at an intermediate level between the first and second voltages.

Memory device having data paths with multiple speeds

A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. The memory device has different modes. Depending on a certain mode, the memory device uses different combinations of the multiple bi-directional data paths to transfer data either at a single speed or at multiple speeds. In some cases, the data represents data information to be stored in memory cells of the memory device. In other cases, the data represents control information and feedback information to be transferred to and from internal circuits, besides the memory cells, of the memory device.

Semiconductor memory device and method for operating the same

A semiconductor device includes a plurality of input units configured to receive a plurality of data, a plurality of latching units configured to latch output signals of the plurality of input units in response to a plurality of synchronization clock signals, and a synchronization clock generating unit configured to delay a source clock signal by a time corresponding to each of signal transmission times taken between the plurality of input units and the plurality of latching units, thereby generating the plurality of synchronization clock signals.

Method and apparatus for read bitline clamping for gain cell DRAM devices

A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.

Semiconductor memory

A semiconductor memory, such as a static random access memory (SRAM), utilizes short data buses to improve operation speed. The semiconductor memory includes a first group of output ports for receiving data through a first set of bit line pairs, a first data fetching gate and a first data bus for the first set of bit line pairs, disposed along a first long side, a second group of output ports for receiving data through a second set of bit line pairs, and a second data fetching gate and a second data bus for the second set of bit line pairs, disposed along a second long side.

Nonvolatile memory apparatus

A nonvolatile memory device includes: a data transmission line configured to transmit internal configuration data; a data path control unit configured to control a data transmission path direction of the data transmission line according to control of a test signal; and a configuration data latch unit configured to latch a signal transmitted through the data transmission line or drive a latched signal to the data transmission line, according to control of the test signal.

Output enable signal generation circuit of semiconductor memory

An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).

Отказоустойчивый цифровой преобразователь информации для управления дискретными процессами

Полезная модель относится к отказоустойчивым цифровым преобразователям информации для управления дискретными процессами. Технический результат заключается в повышении надежности преобразователя. Указанный результат достигается за счет применения отказоустойчивого цифрового преобразователя информации для управления дискретными процессами, который содержит мажорирующий блок, и конечный автомат с памятью, включающий входную комбинационную схему, блок памяти, выходную комбинационную схему и цепь обратной связи, подключенную ко входу входной комбинационной схемы. В качестве блока памяти установлен троированный блок, и выходы каждого экземпляра троированного блока подключены к входам мажорирующего блока, выходы которого подключены ко входам входной комбинационной схемы и по цепи обратной связи со входами входной комбинационной схемы, мажорирующий блок содержит два элемента задержки, выходы которых подключены к двум экземплярам троированного блока памяти, а их входы подключены к внешнему входу синхронизации, мультиплексор, входы которого подключены к выходам входной комбинационной схемы и к выходам мажорирующего блока, а выход подключен к входам блоков памяти, и блок регистрации ошибок, входы которого подключены к выходам мажорирующего блока и внешнему входу синхронизации. Ц 1 174640 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ > © а х& < р. — = о) >= „> 2 272 р... И 2%. ее п РЦ ‘’ (50) МПК СОбЕ 11007 (2006.01) (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2017120753, 14.06.2017 (24) Дата начала отсчета срока действия патента: 14.06.2017 Дата регистрации: 24.10.2017 Приоритет(ы): (22) Дата подачи заявки: 14.06.2017 (45) Опубликовано: 24.10.2017 Бюл. № 30 Адрес для переписки: 195251, Санкт-Петербург, ул. Политехническая, 29, Центр интеллектуальной собственности ФГАОУ ВО "СПбПУ" (72) Автор(ы): Егоров Игорь Валерьевич (КП), Мелехин Виктор Федорович (КП) (73) Патентообладатель(и): федеральное государственное автономное ...

Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction

One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the original data groups. The semiconductor memory device also includes data decoding logic for generating the original data groups from the converted data groups and the inverted flag data. A peripheral circuit may be enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells. A control logic may be enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit.

Precharging circuit and semiconductor memory device including the same

A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.

Dynamic impedance control for input/output buffers

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Managed hybrid memory with adaptive power supply

Subject matter disclosed herein relates to a memory device, and more particularly to a managed hybrid memory that includes a power supply.

Level shifter for use with memory arrays

In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from the first voltage domain to the second voltage domain; and (4) isolation circuitry that selectively isolates the first voltage domain from the second voltage domain so as to selectively prevent current flow between the first voltage domain and the second voltage domain. Numerous other aspects are provided.

Apparatus and methods for optically-coupled memory systems

Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.

Scatter-Gather Intelligent Memory Architecture For Unstructured Streaming Data On Multiprocessor Systems

A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Memory systems and memory modules

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Sampling phase correcting host controller, semiconductor device and method

One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

Synchronous semiconductor memory device

A synchronous semiconductor memory device includes a data alignment reference pulse generation unit configured to generate a data alignment reference pulse in response to a data strobe signal, a data alignment suspension signal generation unit configured to generate a data alignment suspension signal in response to the data alignment reference pulse, a data strobe termination signal, and a write pulse, and a data alignment unit configured to align input data in response to the data alignment reference pulse and stop aligning the input data in response to the data alignment suspension signal.

Memory Device Having Multiple Power Modes

A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

Digital frequency locked delay line

A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.

Apparatus and method for read preamble disable

A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.

System and method of page buffer operation for memory devices

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

Apparatus and method for programmable read preamble

A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.

Different types of memory integrated in one chip by using a novel protocol

A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I 2 C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

Delay locked loop circuit of semiconductor memory apparatus

Various embodiments of a delay locked loop circuit of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the delay locked loop circuit may include an input correction unit configured to correct a duty ratio of an input clock based on a duty control signal and generate a reference clock; a delay line configured to delay the reference clock by a delay time and generate a delay locked clock; an output correction unit configured to correct a duty ratio of the delay locked clock based on the duty control signal and generate a corrected clock; and a control signal generation unit configured to generate the duty control signal when a correction activation signal is enabled.

Data output buffer and memory device

A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

Memory module with memory stack and interface with enhanced capabilities

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

System and Method for Simulating an Aspect of a Memory Circuit

A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.

Data signal mirroring

Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.

Data paths using a first signal to capture data and a second signal to output data and methods for providing data

Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Semiconductor memory device and driving method of semiconductor memory device

A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.

Semiconductor device having pull-up circuit and pull-down circuit

To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

Memory instruction including parameter to affect operating condition of memory

Subject matter disclosed herein relates to techniques to operate memory.

Memory Modules and Devices Supporting Configurable Core Organizations

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

Charge pump control scheme using frequency modulation for memory word line

A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage.

Semiconductor device and method of controlling the same

A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word line; a second signal unit outputting a second signal for activating or inactivating a bit line and the sense circuit; a third signal unit outputting a third signal for starting or stopping a supply of an overdrive voltage to the sense circuit; and a fourth signal unit outputting a fourth signal for inactivating the word line. The period during which the third signal remains activated is determined in accordance with the magnitude of an external voltage. In the fourth signal unit, the timing to generate the fourth signal is determined independently of the magnitude of the external voltage.

Write circuitry for hierarchical memory architectures

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Programming memory cells with additional data for increased threshold voltage resolution

Methods for programming memory and memory devices are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.

Semiconductor integrated circuit

A semiconductor memory apparatus includes a buffer control unit configured to deactivate a buffer control signal in response to an auto-refresh start pulse, and activate the buffer control signal in response to an auto-refresh end pulse, a command buffer configured to buffer an external command and output an internal command when the buffer control signal is activated, an address buffer configured to buffer an external address and output an internal address when the buffer control signal is activated, and a clock buffer configured to buffer an external clock and output an internal clock when the buffer control signal is activated.

Memory Module With Reduced Access Granularity

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Auto-precharge signal generator

An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set signal generator is configured to generating a set signal in response to receiving the control signal and the precharge control signal. The auto-precharge signal generator is configured to generate an auto-precharge signal in response to receiving the set signal and a period set signal.

Internal voltage generation circuit and semiconductor integrated circuit

A semiconductor integrated circuit includes first and second bank groups, a first internal voltage control unit configured to generate a first enable pulse which is enabled when a first read operation or a first write operation is performed for banks included in the first bank group, and a first internal voltage generation unit configured to generate and supply a first internal voltage to the first bank group in response to the first enable pulse, wherein an enable period of the first enable pulse is set to be longer in the first write operation than in the first read operation.

Column address counter circuit of semiconductor memory device

The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most significant counter unit configured to generate the most significant bit of the column address in response to a mask clock, where the mask clock is toggled when the internal clock is toggled by a set number of times.

Semiconductor memory device, test circuit, and test operation method thereof

A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Memory module cutting off dm pad leakage current

A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.

Memory System with Multi-Level Status Signaling and Method for Operating the Same

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

Memory channel having deskew separate from redrive

A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.

Timing adjustment circuit for a memory interface and method of adjusting timing for memory interface

According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.

Integrated circuit with staggered signal output

A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Ddr flash implementation with direct register access to legacy flash functions

A Double Data Rate (DDR) nonvolatile memory for use with a wireless device. A host processor transfers commands and data through a DDR interface of the nonvolatile memory. The DDR nonvolatile memory implements legacy flash functions while maintaining DDR behavior.

Semiconductor device

A semiconductor device according to the present invention includes plural controlled chips CC 0 to CC 7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A 13 to A 15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A 13 to A 15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A 13 to A 15 reach the controlled chips earlier than the command signal ICMD.

Circuit

An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Memory System with Calibrated Data Communication

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Write control circuit and semiconductor device

In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.

Write bandwidth in a memory characterized by a variable write time

A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

Integrated circuit

An integrated circuit includes a plurality of data lines on which data aligned by a plurality of pulse signals are loaded, a plurality of transfer lines, a data transfer unit configured to transfer the data of the plurality of data lines to the plurality of transfer lines in response to a correlation signal, a data output unit configured to output the data of the transfer line corresponding to a transmission signal activated among a plurality of transmission signals, a correlation signal generation unit configured to generate the correlation signal using a latency value and a logic value of one of the plurality of transmission signals when a command is inputted to the correlation signal generation unit, and a pulse signal generation unit configured to sequentially activate the plurality of pulse signals when the command is inputted.

Utilizing two algorithms to determine a delay value for training ddr3 memory

A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

Semiconductor memory apparatus

A semiconductor memory apparatus includes a memory cell array including a plurality of chips, a control circuit configured to control an internal operation of the memory cell array, a power circuit configured to supply power to the control circuit, and a mode setting circuit configured to output a flag signal for power supply control based on a mode register set command and data received through a data input/output pad, in response to a clock enable signal.

Three dimensional memory system with intelligent select circuit

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

Semiconductor device

The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

Semiconductor memory device and methods thereof

According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.

Method for compensating a timing signal, an integrated circuit and electronic device

A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

Synchronous data processing system and method

A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

Signal receiving circuit, memory controller, processor, computer, and phase control method

A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.

Non-Sequential Encoding Scheme for Multi-Level Cell (MLC) Memory Cells

Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.

Semiconductor memory device and method of setting operation environment therein

A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.

Neighborhood operations for parallel processing

A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.

Semiconductor memory and semiconductor memory control method

According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.

Data input device for semiconductor memory device

A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs internal data to the flip-flop unit. The combinational logic circuit receives an external data strobe signal to generate a first data strobe signal and a second data strobe signal. The flip-flop unit stores the data in synchronization with the first data strobe signal and outputs the stored data in synchronization with the second data strobe signal. A last rising edge of the second data strobe signal is generated prior to onset of the postamble ringing on the external data strobe signal, so that a data transferred path in the flip-flop unit is closed prior to onset of the postamble ringing.

Delay circuit and latency control circuit of memory, and signal delay method thereof

A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.

Memory controller and operating method of memory controller

A controller to control a memory system including a memory device. The controlling the memory system may include calculating an error location polynomial in a received read vector with a key equation solving unit of the memory system to read data from the memory device, estimating the number of errors in the received read vector with a control unit of the memory system according to at least one of the calculated error location polynomial and information on the error location polynomial, searching error locations of the received read vector according to the calculated error location polynomial with a chien search unit of the memory system with the control unit. A cycle-per power consumption of the chien search unit may be adjusted with the control unit. A maximum correction time may be adjusted according to the number of errors of the read vector.

Semiconductor Device

As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a first capacitor and a second capacitor. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region.

Memory device and signal processing circuit

A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. A memory device includes a logic circuit including a first node and a second node, a first memory circuit connected to the first node, a second memory circuit connected to the second node, and a precharge circuit connected to the first node, the second node, the first memory circuit, and the second memory circuit. When reading data is performed, the precharge circuit outputs a precharge potential to the first node and the second node. The first memory circuit and the second memory circuit each include a transistor in which a channel is formed in an oxide semiconductor film.

Integrated circuit memory device

A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2̂K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

Advanced memory device having improved performance, reduced power and increased reliability

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Isolated resistive current sensor

An isolated current-sensing system for use with a resistive current sense element includes an analog front-end configured to receive a voltage from the resistive current sense element, and to provide an analog output. A processing circuit receives the analog output, and provides a measurement signal indicative of the sensed current. An isolation circuit provides an isolation barrier, and is configured to pass the measurement signal. A programmable over-current protection alarm may be included, and configured to generate an alarm signal when the analog output exceeds a programmable threshold. The processing circuit may include a voltage-to-PWM converter.

Apparatus including memory system controllers and related methods

Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria.

Infrastructure for performance based chip-to-chip stacking

A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.

Semiconductor memory device and method of driving semiconductor memory device

A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.

Asynchronous/synchronous interface

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Semiconductor memory device, information processing system including the same, and controller

A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.

Low voltage sensing scheme having reduced active power down standby current

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Random Access Memory Controller Having Common Column Multiplexer and Sense Amplifier Hardware

Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry is shared between the column multiplexer and the sense amplifier so that the memory controller includes a single instance of the common circuitry for the column multiplexer and sense amplifier pair. The common circuitry includes a common pre-charge circuit, a common equalizer, or a common keeper circuit.

Programming of phase-change memory cells

A method and apparatus for programming a phase-change memory cell. A bias voltage signal (V BL ) is applied to the cell. A measurement portion (m) of this bias voltage signal has a profile which varies with time. A measurement (T M ), which is dependent on a predetermined condition being satisfied, is then made. The predetermined condition is dependent on cell current during the measurement portion (m) of the bias voltage signal. A programming signal is generated in dependence on the measurement (T M ), and the programming signal is applied to program the cell.

Digit line comparison circuits

A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Semiconductor device, adjustment method thereof and data processing system

A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips.

Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system

A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.

Multi-core processor system, memory controller control method, and computer product

A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.

Frequency-agile strobe window generation

The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.

On-chip memory (ocm) physical bank parallelism

According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.

Memory device for managing timing parameters

A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

Input buffer circuit, semiconductor memory device and memory system

An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.

Processor with memory delayed bit line precharging

A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.

High speed multiple memory interface i/o cell

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

Semiconductor apparatus

A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

Semiconductor memory device and method of operating the same

A semiconductor memory device includes memory blocks that each include memory cells coupled to bit lines, a column masking circuit configured to output data change signals in response to an address signal indicating bit lines of selected columns among a plurality of columns, and an operation circuit configured to store data of the memory cells transferred through the bit lines and simultaneously change data transferred through the bit lines of the selected columns into operation pass data in response to the data change signals.

Floating addressing of an eeprom memory page

A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row i is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

Network-capable raid controller for a semiconductor storage device

Embodiments of the present invention provide a network-capable RAID controller for a storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type that supports a low-speed data processing speed for a host. Specifically, embodiments of this invention provide a network-capable RAID controller coupled to one or more (i.e., a set of) semiconductor storage devices (SSDs). Among other components, the network-capable RAID controller comprises an input/output (I/O) controller coupled to a network interface. The network interface allows the network-capable RAID controller to communicate with an external network.

Method and apparatus for multiple access of plural memory banks

A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to different physical memory banks, among the plurality of memory banks, and scheduling the selected subset of access requests, each over a separate access port.

Semiconductor device operates on external and internal power supply voltages and data processing system including the same

The semiconductor device including an output terminal; and an output unit coupled to the output terminal. The output unit includes an output buffer coupled to the output terminal and operating on a first power supply voltage, a first control circuit operating on a second power supply voltage, receiving an impedance adjustment signal and a data signal and making the output buffer drive the output terminal to a first logic level designated by the data signal with impedance designated by the impedance adjustment signal, and a level shifter coupled between the output buffer and the first control circuit. The second power supply voltage is smaller in level than the first power supply voltage. The level shifter includes a first circuit portion operating on the second power supply voltage and a second circuit portion operating on the first power supply voltage.

Electronic Control Unit for Vehicle and Method of Writing Data

An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory.

Semiconductor device

A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code, and an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code.

Setting data storage for semiconductor devices including memory devices and systems

A setting data storage circuit includes a setting data storage block configured to store setting data; an access unit configured to access the setting data of the setting data storage block; an error detection unit configured to detect an error in the setting data; and an error recovery unit configured to recover an error in the setting data storage block when the error detection unit detects an error.