감지 회로를 사용한 패리티 결정을 위한 장치들 및 방법들
The disclosure is generally semiconductor memory and method relate to and, more particularly sensing using the parity crystals (e.g., are calculated) related to device and method are disclosed to. Memory device are typically of computers or other in electronic systems, semiconductor, encoded ball number as an integrated circuit. Many different types of memory including volatile and non - volatile memory flow tides. Volatile memory is data TX (e.g., host, such as error data) may require power for holding another among, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM) without using a tool. Non - volatile memory is supplied with power when they are not permanent by number data stored in another data retention under public affairs among, NAND flash memory, NOR flash memory, phase change random access memory (PCRAM), resistance random access memory (RRAM), and spinning magnetoresistive random access memory (MRAM) such as torque transfer random access memory (STT RAM) such as, can be variable resistance memory. Electronic systems often a plurality of processing resources (e.g., one or more processors) which, this searching and indications of which results in proper location for storing instructions can be executed. For example processor, arithmetic logic unit (ALU) circuit, floating-point unit (FPU) circuit, and/or combinatorial logic block (the application clock functions in the covalently (FUC)) including a plurality of functional units such as can be, this allows for (for example, one or more operands) AND, OR, NOT, NAND, NOR, and XOR logic operation by performing logical operations such as performing orders can be used. For example, the operands FUC for adding, subtracting unit, multiplication, division and/or can be used for performing such as arithmetic operations. Many electronic system components of the FUC under public affairs for execution when the number indications can be involved. Indications, for example, violations of the number and/or host processor such as can be generated by the processing resources. Data (e.g., execute instruction operands to be added) can be stored in the memory array accessible by the FUC. Indication and/or data and instructing the FUC to the data retrieved from the memory array to implement and/or may be buffered prior to beginning be ordered. Furthermore, one or more clock cycles through different types of operation can be run in the FUC are formed, indicating and/or data and/or may be buffered in addition be ordered are interim results of the calculation. Stored in a Hamming code or BCH error correction code (ECC) data (Bose Chaudhuri Hocquenghem) such as using error detection and/or error correction data protection techniques include various through can be protected. These codes can be stored together with the data they protect data errors (for example, erroneous bits values) for detecting whether a including when data are read out and capable of being tested disclosed. In addition these codes is detected in order to correct a specific number of errors can be used. However, in order to ECC code, ECC protected data array is read out and engine number ball should be substrate (for example, input/output (I/O) line by data transmission via a). Figure 1 shows a plurality of disclosure in the embodiment according to the invention in the form of a computation system including an block device are disclosed. Figure 2 shows a plurality of disclosure in the embodiment according to the invention a portion of the schematic diagram of the sensing circuit coupled to the memory array example as follows. In the embodiment according to the disclosure are also 3a and 3b also includes a plurality of sense circuit for determining method for performing operations using parity associated with schematic degrees example as follows. Figure 4 shows a plurality of disclosure in the embodiment according to the invention a portion of the schematic diagram of the sensing circuit coupled to the memory array for example as follows. In the embodiment according to the disclosure are 5a also includes a plurality of sense circuit performing logical operations associated with multiple timing degree example as follows. In the embodiment according to the disclosure are also 5ba 5bb is also and a plurality of sense circuit performing logical operations associated with multiple timing mobilities is exemplified substrate. In the embodiment according to the disclosure is also 5ca 5cb and a plurality of sense circuit performing logical operations are associated with multiple timing mobilities is exemplified substrate. Figure 6 shows a schematic diagram of a portion of a plurality of disclosure in the embodiment example according to sensing circuit are therefore as follows. In the embodiment according to the disclosure are also 7a and 7b also includes a plurality of schematic of portions of the memory array to example as follows. In the embodiment according to the disclosure are also 8a and 8b also includes a plurality of sense circuit performing logical operations associated with multiple timing mobilities is exemplified substrate. Figure 9 shows a plurality of disclosure in the embodiment according to invention are selectable with the illustrated schematic logic value selection logic configured to sense circuit are disclosed. Figure 10 the disclosure in the embodiment are implemented by a plurality of selectable according to sensing circuit logic value to exemplify the logic table results are disclosed. The disclosure includes a sensing device and method for using the parity decisions comprising the. Input/output (I/O) line array exemplary method for transmitting data from a plurality of data values a corresponding parity value determined without sensing array coupled to a number of memory cells through each protecting stored data values; and sensing line coupled to another memory cell comprising said parity values can be. The disclosure in the embodiment in a plurality of, for protecting a plurality of data values stored in a plurality of exclusive OR (XOR) parity value is used for the memory can be determined by model (for example, sensing line address access it leads and such as I/O line array out data and/or column decode line enable (enable) without without). As used in the application, parity value is the particular data (e.g., number of bits) or odd-is a particular data value (e.g., an odd or even number of "1 are" or "are 0") including a data value indicating whether the battery can exhibit. A plurality of memory cells corresponding to the data stored specific data protected wrong parity value is made (for example, data including the one or more erroneous bits) for determining can be examined. For example, a plurality of protected data values a corresponding parity value is calculated subsequent examination can be parity value indicating values of different parity if, protection data can be including errors. Protection data including errors (for example, a wrong one that protected data values) can be determined, can be calibration actions are taken (e.g., erroneous data value in order to correct). For example, erroneous data value its detection, correction parity value is erroneous data value to determine a plurality of XOR operation can be carried out with respect to integrated into protected data values. For example, specific sensing line (for example, digit line) in addition specific sensing coupled to another memory coupled to a protected by storing data values stored in the parity value considering defect/deficiency group of cells. Data stored in said memory cell group upon determination that particular access line coupled to, a plurality of XOR operation are parity with the value of the group of other memory cells (e.g., protected by parity value as all other data stored in memory cells) can be carried out with respect to data stored values. A plurality of memory cells to store data values correct XOR operations result from specific access lines coupled to memory cells can be recorded. A further application as described, in a plurality of in the embodiment, memory cells coupled to an array of sensing circuit comprises a plurality of data values stored in particular digit line of memory cells including, "N" operands corresponding to parity values, simultaneously, can be operative to determine a, said N exhibits array corresponding to quantity of digit lines. A further application as described, in a plurality of in the embodiment, input/output (I/O) line (are) parity value (for example, sensing line address access in relation to local I/O line) can be accomplished without transmitting data from the memory array. For example, sensing circuit (for example, in Figure 4 and also 2 described sensing circuit) address access requests the data through a sense line (e.g., column and does not decode signal) with respect to the parity value of the plurality of logical operations (e.g., AND, OR, NAND, NOR, NOT) can be operative to perform. Rather than external to the sensing circuit having processing resources (e.g., associated with ALU circuit such as a processor and/or, by other processing circuits), using sensing circuit performing gain among other such logical operations, such as gains can be under public affairs number system to reduce power consumption. The disclosure of the following detailed description, reference is made to drawing and forming portions thereof are judged, the disclosure in the embodiment as shown for example in application one or more wonder what can be embodiment are exhibited. In the embodiment of the disclosure are described in the embodiment are in the field of these skilled machine operators are fully detailed embodiment to which, in the embodiment can be employed other process, electrical, and/or structural variations in the disclosure can be accomplished without deviates from the range of will be appreciated that the will. As used in the application, in particular drawing reference number in ("N", "T", such as "U") against specifier are so designated is a particular feature may be included can be losing the number of blocks. As used in the application, "a plurality of" can exhibit one or more of the these specified (for example, a plurality of memory arrays are one or more memory arrays can exhibit). The application data units or data units that correspond to a number drawing number 1 in drawing are the remaining data units in a drawing element or components along the numbering which said identifying. Among different drawing similar elements or components are identified by the use of similar data units can be. For example, the 130 in Figure 1 element ("30") can be similar elements is in Figure 4 430 can be referenced as reference. As it will be, in the embodiment shown in the disclosure in the application various elements are added to the number in the embodiment and a plurality of additional under public affairs, and exchanged, and/or number of special 1308. In addition, as will be, in the embodiment of the present invention presents a number ratio of and relative scale is drawing elements in particular are is exemplified are substituted, but number taken sense should not be disclosed. Figure 1 shows a plurality of disclosure are therefore in the embodiment according to memory device (120) including computing system (100) in the form of block device are disclosed. As used in the application, memory device (120), memory array (130), and/or sensing circuit (150) is individually "device" can be considering in addition. System (100) includes a memory device (120) request (110) which, this memory array (130) having a predetermined wavelength. Host (110) in different other types of host among, citation two laptop computer, desktop computer, digital camera, mobile phone, or memory card reader such as be a host system. Host (110) or backplane has a motherboard and/include third processing resources (e.g., one or more processors, microprocessors, or some other type of number the circuit) can be comprising. System (100) is separate integrated circuits or may host (110) and memory device (120) both thereof can on the same integrated circuit. System (100) is, for example, high performance computing (HPC) server system and/or system and/or can be a part of. An example is also shown in a von Neumann (Von Neumann) architecture 1 equipped with the is exemplified but, in the embodiment of the disclosure are phone - neumann architectures (e.g., [thyu[thyu] ring machine) can be implemented in, this often associated with a von Neumann architecture does not include one or more components (e.g., CPU, such as ALU) thereof can. Toward the clear, system (100) having the features specific to the relevance to the disclosure in order to focus has been simplified. Memory array (130) is for example, DRAM array, SRAM arrays, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or be a NOR flash array. Array (130) includes access lines (the application low lines, word lines, or selection lines can be covalently) coupled by rows and sense lines (the application in bit lines, digit lines, or data lines can be covalently) by coupled columns can be arranged into memory cells. Single array (130) is shown but also 1, so number one in the embodiment are not. For example, memory device (120) includes a plurality of arrays (130) comprising (e.g., number of banks DRAM cells) can be. Also described in relation to an exemplary DRAM array 2 and also 4. Memory device (120) includes a I/O circuit (144) through I/O bus (156) (for example, data bus) presents a number address signals over latching for address circuitry (142) having a predetermined wavelength. Address signals are memory array (130) for accessing the row decoder (146) and column decoder (152) by received and decoded. Data sensing circuit (150) of the fluidic line voltages and/or current sense changes on by memory array (130) can be read from. Sensing circuit (150) the memory array (130) reads the [lay[lay] it will name be pages of data from (e.g., low). I/O circuit (144) is I/O bus (156) host (110) can be used for communication orientation data amount with -. Recording circuit (148) the memory array (130) are used for recording data. The circuit number (140) host (110) from bus number (154) presents a number by decodes signals. These signals are data reading, data recording, and standing erase operations used including, memory array (130) number used for operations performed on the chip enable signals, write enable signals, and address latch signals can be. In various in the embodiment, the circuit number (140) host (110) the pin is performing orders from CPE. The circuit number (140) includes a state machine, sequencer, or some other type of number (for example, on - die number violations) violations of the implementation being. Sensing circuit (150) further described hereinafter in connection with the examples of 2 to 6 also also. For example, in a plurality of in the embodiment, sensing circuit (150) includes a plurality of sense amplifiers (e.g., 2 also shown in sense amplifiers (206 - 1, .. , 206-U) 또는 도 4에 도시된 감지 증폭기(406)) 및 다수의 계산 구성요소들(예로서, 도 2에 도시된 계산 구성요소들(231-1 내지 231-X) 및 도 4에 도시된 계산 구성요소(431))을 포함할 수 있다.As also illustrated 4, data latch components are calculated can be act as a number of logical operations (e.g., AND, NOT, NOR, NAND, XOR or the like) used for performing other sensing circuit can be coupled transistors cross - can be combined. In a plurality of in the embodiment, sensing circuit (e.g., 150) and then transferring it address access data through a sense line (e.g., column and does not decode signal), the application are described in the embodiment according to with respect to the parity calculation for performing logical operations can be used. The, logic operations are performed by processing resources outside of the sensing circuit rather than a sensing circuit (150) using array (130) can be carried out in (for example, device (120) on (for example, number the circuit (140) or elsewhere on) located, host (110) associated with the processor and/or ALU circuit such as, by other processing circuits). Figure 2 shows a sensing circuit coupled to the memory array in the embodiment according to the invention a plurality of disclosure (201) a portion of the schematic diagram of the example as follows. Memory array (201) side of a circuit board (203 - 1 to 203 a-T) (generally memory cells (203) the covalently) access lines (e.g., word lines) (204 - 1, 204 - 2, 204 - 3, 204 - 4, and 204 - 5) coupled to the rows and sense lines (for example, digit lines) (205 - 1, 205 - 2, 205 - 3, 205 - 4, 205 - 5, .. , 205 a-S) into the coupled columns are prevented. For example, access lines (204 - 1) cells (203 - 1, 203 - 2, 203 - 3, 203 - 4, 203 - 5, .. , 203 a-T) comprises. Memory array (201) has a plane orientation number of access lines and/number lines are sensed or not, terms ("rows" and "columns") access lines and/or the use of a particular physical structure and/or orientation sensing line does not intended. Picture is visible but not, memory cells each column corresponding pairs complementary (complementary) sensing lines (for example, described 4 also can be associated with complementary sensing lines (D405-a 1 and D_405-a 2). Memory cells each column is a sensing circuit (for example, 1 also shown in sensing circuit (150)) can be coupled to. In one embodiment, sensing circuit coupled to a plurality of sense amplifiers each detection lines (206 - 1, 206 - 2, 206 - 3, 206 - 4, 206 - 5, .. , 206 a-U) comprises. Sense amplifiers (206 - 1 to 206 a-U) the transistors (208 - 1, 208 - 2, 208 - 3, 208 - 4, 208 - 5, .. , 208 a-V) input/output (I/O) through line (234) (for example, local I/O line) coupled to. In this example, each detection lines in addition sensing circuit coupled to a plurality of calculated components (231 - 1, 231 - 2, 231 - 3, 231 - 4, 231 - 5, .. , 231 a-X) comprises. Column decode lines (210 - 1 to 210 a-W) is transistors (208 - 1, 208 - 2, 208 - 3, 208 - 4, 208 - 5, .. , 208-V)의 게이트들에 결합되며 각각의 감지 앰프들(206-1 내지 206-U에 의해 감지되고 및/또는 각각의 계산 구성요소들(231-1 내지 231-X)에 저장된 데이터를 2차 감지 증폭기(214)로 전송하기 위해 선택적으로 인에이블될 수 있다. Figure 2 array (201) side of a circuit board (203) exhibits exemplary data values stored. In one embodiment, sensing line (205 - 1) coupled to the cells (203 - 1, 203 - 6, and 203 - 11) ("1", "1", and "0") respectively storing data values, in addition sensing line (205 - 1) coupled to the cell (203 - 21) cells (203 - 1, 203 - 6, and 203 - 11) stored data values (e.g., "1", "1", and "0") corresponding to store parity value "0". In this way, cell (203 - 11) cells stored parity value (203 - 1, 203 - 6, and 203 - 11) corresponding stored data value changing substrate (for example, secure causes). Sensing line (205 - 2) coupled to the cells (203 - 2, 203 - 7, and 203 - 12) includes data ("0", "0", and "1") stores the values, in addition sensing line (205 - 2) coupled to the cell (203 - 22) cells (203 - 2, 203 - 7, and 203 - 12) stored data values (e.g., "0", "0", and "1") corresponding to store parity value "1". Sensing line (205 - 3) coupled to the cells (203 - 3, 203 - 8, and 203 - 13) includes data ("0", "1", and "0") stores the values, in addition circuit senses (205 - 3) coupled to the cell (203 - 23) cells (203 - 3, 203 - 8, and 203 - 13) stored data values (e.g., "0", "1", and "0") corresponding to store parity value "1". Sensing line (205 - 4) coupled to the cells (203 - 4, 203 - 9, and 203 - 14) ("1", "0", and "1") respectively storing data values, in addition sensing line (205 - 4) coupled to the cell (203 - 24) cells (203 - 4, 203 - 9, and 203 - 14) stored data values (e.g., "1", "0", and "1") corresponding to store parity value "0". Sensing line (205 - 5) coupled to the cells (203 - 5, 203 - 10, and 203 - 15) includes data ("0", "0", and "0") stores the values, in addition sensing line (205 - 5) coupled to the cell (203 - 25) cells (203 - 5, 203 - 10, and 203 - 15) stored data values (e.g., "0", "0", and "0") corresponding to store parity value "0". In one example shown also 2, protecting parity values are noted in the same data as the data stored in memory cells coupled to a sense line, each sense line corresponding to parity values are the same access line (for example, in one embodiment access lines (204 - 5)) of memory cells overnight. In this way, in a plurality of in the embodiment, each specific sensing line cells storing parity value protecting stored data values, stored data values of adjacent rows of memory cells (e.g., ROW 5) is for protecting the entire array (or sub - array) can be used. Storing data protected by parity value and is connected to the cells in the "protection" application access lines having rows can be covalently. Thus, protected by parity value which does not store data values having cells and is connected to the access lines are "unprotected" rows can be covalently. In one example shown in Figure 2, access lines (204 - 1, 204 - 2, 204 - 3 and) exhibit protective rows, access lines (204 - 4 and 204 - 5) is unprotected rows are disclosed. Access line (204 - 5) the access lines (204 - 5) cells coupled to each detection of protected data values a corresponding parity values can be covalently judges the "parity row". In addition, in this example, unprotected access lines (204 - 4) cells coupled to the application described in the embodiment in accordance with the parity values for protecting associated with intermediate result can be used. In a plurality of in the embodiment, includes a diode and a plurality of unprotected access lines (e.g., 204 - 4, and 204 - 5) host and/or user-accessible that are addressable not may not disclosed. For example, in a plurality of in the embodiment, parity calculation associated with cells for storing intermediate results used the unprotected access lines are addressable WIPO. Each detection lines of memory cells stored data I/O line array parity values are preliminary data out of the plurality of requests can be determined by model. A plurality of operations are performed to parity values specific sensing line coupled to memory cells exclusive OR (XOR) operation data stored values can be a. Example, parity value is conducting these memory cells data values (e.g., respectively, bit values ("1", "1", and "0")) by performing XOR operations to memory cells (203 - 1, 203 - 6, and 203 - 11) can be determined for the data stored. For example, number 1 XOR operation is memory cells (203 - 1 and 203 - 6) stored data values (for example, each bit values ("1" and "1")) can be performed. Number 1 XOR operation is "0" bit value of (for example, the "0" "1" "1" XOR are disclosed) tolerant. The result of an operation (for example, bit value ("0")) number 1 XOR has a plane orientation sensing line coupled to another memory cell (e.g., memory cell (203 - 16)) can be stored. Number 2 XOR operation is the result of an operation (for example, bit value ("0")) and memory cell number 1 XOR (203 - 11) (for example, bit value ("0")) data stored value can be performed. Number 2 XOR operation is "0" (bit values ("0" and "0") to) bit value of (for example, "0" "0" "0" is the XOR) tolerant. (For example, bit value ("0")) is the result of an operation number 2 XOR cells (203 - 1, 203 - 6, and 203 - 11) preliminary data stored parity value represents the memory cell (203 - 21) can be stored. As described further hereinafter, the disclosure in a plurality of in the embodiment, I/O operations are XOR array line out without transmitting data (e.g., data transmission via a sensing line address access without) can be performed. In a plurality of in the embodiment, the XOR operation data values pairs is performing the NAND operation for a pair data values, performing the OR operation data values pairs, and then NAND OR AND operation result value and result values includes performing. In a plurality of in the embodiment, parity values according to sensing memory device array (e.g., 201) measuring noise of line basis (basis) data stored can be determined. For example, XOR operations are simultaneous manner each sense line corresponding to each individual sensing line determining dimensions in the parity values (205 - 1 to 205 a-S) memory cells (203) can be conducted simultaneously with data stored values. In one example shown, are provided to enhance lines (205 - 1 to 205 - 5) corresponding to parity values are cells (203 - 21 to 203 - 25) overnight. Each detection lines (203 - 2 to 203 - 5) memory cells coupled to data stored parity values are preliminary sensing line (205 - 1) coupled to the cells (203 - 1, 203 - 6, and 203 - 11) stored data values (e.g., "1", "1", and "0") (e.g., "0") and corresponding to the parity value can be determined in a similar manner (as described in said). As shown in this example, memory cell (203 - 22) stored, parity value is "1" each memory cells (203 - 2, 203 - 7, and 203 - 12) stored data values (e.g., bit values ("0", "0", and "1")) by performing the XOR operations determined. Memory cell (203 - 23) stored, parity value is "1" each memory cells (203 - 3, 203 - 8, and 203 - 13) stored data values (e.g., bit values ("0", "1", and "0")) by performing the XOR operations determined. Memory cell (203 - 24) parity value is "0" stored in each memory cells (203 - 4, 203 - 9, and 203 - 14) stored data values (e.g., bit values ("1", "0", and "1")) by performing the XOR operations determined. In addition, memory cell (203 - 25) stored, parity value is "0" each memory cells (203 - 5, 203 - 10, and 203 - 15) stored data values (e.g., bit values ("0", "0", and "0")) by performing the XOR operations determined. In a plurality of in the embodiment, specific sensing line of memory cells is initially parity value stored data corresponding to an initial parity value is protected by storing data values record can be updated in response to one or more cells. For example, memory cell (203 - 21) (e.g., "0") stored parity value "1" bit value of storing current in this example, memory cell (203 - 6) can be updated in response to data to be written to. Memory cell (203 - 6) data values stored in the memory cell (203 - 6) (for example, be written in memory cell) (e.g., "1") data stored value and a memory cell (203 - 21) (e.g., "0") an initial corresponding stored parity value XOR parity value for initial operation from crystals number can be volatile, this in this example 1 "updated parity value (e.g.," 1 "is" 1 "XOR" 0" are disclosed) tolerant. Updated parity value (e.g., "1") corresponding sensing line (205 - 1) coupled to an additional memory cell (for example, memory cell (203 - 16) or an additional memory cell (not clear to show)) can be stored (e.g., it can be recorded). In this example, memory cell (203 - 6) to be written to updated (e.g., new) data value is "0" (for example, cell (203 - 6) is replaced by "0" will currently stored "1") is assumed defect/deficiency. Cell (203 - 6) in response to the value of the write new data to, new data value (e.g., "0") XOR operation (for example, "1") and updated parity value for signal is received by the, newly updated parity value of "1" tolerant. Therefore, in this example, "0" bit value of "1" bit value of data stored in protected memory cell is "0" "1" (e.g., switching) varies in protected 2n. parity value corresponding to the data. Calculating transaction data recording can be performed after array of memory cells. Calculating transaction includes an array of memory cells can be changed data stored in a plurality of operations and/or can be calculated including. Calculating positions of operations and/or calculation of intermediate results array of memory cells can be temporarily stored (e.g., rows of memory cells can be stored temporary register array). Calculating positions of memory cells make the calculated operation performed and/or recorded records are on hold until the end of the transaction so that it can be calculated, each protection in addition to the row parity determining previous transaction calculated previously calculated transaction preserve the data stored in memory cells. Intermediate results are stored in a memory cell of the array recorded, memory cell a corresponding parity value can be updated. In a plurality of in the embodiment, the application described in the embodiment in accordance with the determined parity value is erroneous data value (for example, erroneous bits value) for the repair of correct data value storing memory cell can be used. A plurality of XOR recovered data value can be determined by model. For example, when determined that the memory cell is in an erroneous store data values (for example, memory cell (203 - 6) is "1" bit value of "0" is determined to be stored but if storing), these data values are erroneous data value and a plurality of XOR operation on the protective parity value (for example, memory cell (203 - 21) ("0") stored parity value) coupled to memory cell sensing line (e.g., 205 - 1) storing other data stored in memory cells (for example, memory cells (203 - 1 and 203 - 11)) values can be performed. In one embodiment, cell (203 - 6) is in an erroneous store data values in response to a determination that a, number 1 XOR operation memory cells (203 - 1 and 203 - 11) stored data values (for example, each bit values ("1" and "0")) with respect to carried out. Number 1 XOR number 2 XOR operation is the result of an operation (e.g., "1") value (e.g., "1" "0" "1" the XOR are disclosed) and the same sensing line (e.g., 205 - 1) (for example, "0") coupled to the parity value can be performed. The result of an operation value is bit value ("1") and number 2 XOR, this wrong store data values determining memory cell (for example, memory cell (203 - 6)) can be stored. In the embodiment according to the disclosure are also 3a is a plurality of sensing method using the parity calculation associated with schematic degree for example as follows. In the embodiment according to the described application also 3a is a plurality of parity values associated with a plurality of operation steps (371 - 1 to 371 - 7) during specific sensing line (305 - 1) calculation component coupled to (331 - 1) stored in the particular data value is exemplified substrate. Sensing line (305 - 1) 2 also is shown in array (201) can be one such as array plurality of sensing lines. As such, sensing line (305 - 1) is coupled to a plurality of memory cells the same (303 - 1, 303 - 6, 303 - 11, 303 - 16, and 303 - 21) which, in addition cells are each access lines (304 - 1 to 304 - 5) coupled. Calculating component (331 - 1) also 4 is further described hereinafter in relation to the calculated component (431) component such as can be calculated. The, calculating component (331 - 1) the memory cells (303) and/or a corresponding sensing circuit having (for example, also 3a not shown other sensing circuit in also 2 shown such as sense amplifier (206 - 1), a sense amplifier shown in fig. 4 (406)) devices (e.g., transistors) having formed on a pitch can be. In this example, access lines (304 - 1 to 304 - 3) coupled to the cells (e.g., cells (303 - 1, 303 - 6, and 303 - 11)) the access lines (304 - 5) coupled to the cell (e.g., cell (303 - 21)) protected by parity value stored data values (e.g., each "1", "1", and "0") store. I.e., access lines (304 - 1 to 304 - 3) protective access lines are disclosed. Therefore, in this example, access lines (304 - 4 and 304 - 5) is unprotected access lines (for example, and is connected to the protected cells which do not have access lines) are disclosed. In this example, access lines (304 - 5) access lines are arranged are disclosed. For example DRAM array 3a also in array can be, but not shown, sensing line (305 - 1) each complementary sensing line pair (e.g., 4 also shown in complementary sensing lines (405 - 1/405 - 2)) can be comprising. Sensing line (305 - 1) coupled to the sensing circuit includes a plurality of XOR in the embodiment described application according to model protection memory cells (e.g., cells (303 - 1, 303 - 6, and 303 - 11)) corresponding to the data to determine stored parity value can be. XOR operations are for example, NAND, AND, OR, and/or inverter (invert) such as model number of logical operation circuit which senses can be carried out. 3a also shown in example includes memory cells (303 - 1, 303 - 6, and 303 - 11) (for example, sensing line (305 - 1) coupled to the protection cells) stored data parity calculation is exemplified substrate. Operation steps (371 - 1 to 371 - 3) are associated with the NAND operation is performed. Operation steps (371 - 4 to 371 - 5) OR are associated with the performed operation. Operation step (371 - 6) is the result of an operation for performing the NAND operation and OR AND values (for example, each NAND and resulting values OR "AND (ANDing) the") and are associated with the development. Operation steps (371 - 1 and 371 - 2) is protected by a parity value number 1 memory cell (e.g., 303 - 1) stores data to be stored data value and the parity value stores data to be protected by a number 2 memory cell (e.g., 303 - 6) AND data stored values associated with the performed operation. For example, operation step (371 - 1) is cell (303 - 1) (e.g., "1") data stored value sensing line (305 - 1) corresponding to the sensing circuit to comprise a loading (e.g., calculating component (331 - 1)). Memory cell (303 - 1) (e.g., "1") data stored value calculating component (331 - 1) loading to a corresponding sense amplifier (e.g., a sense amplifier shown in fig. 2 (206 - 1)) to a memory via a cell (303 - 1) and a plurality of number of sensing the signals via (also described further hereinafter in relation to 4 to 6 also as) calculating component (331 - 1) transmits the values (for example, copying) data perceived as a can. Thus, as shown in fig. 3a, operation step (371 - 1) computing components (331 - 1) cell (303 - 1) (e.g., "1") data stored value tolerant storage. Operation step (371 - 2) in, sensing circuit which calculates the components (331 - 1) data value stored in the cell (303 - 1) (e.g., "1") data stored value and a cell (303 - 6) (e.g., "1") stored in a data value of the results of an AND operable with each other. As further described hereinafter, for performing an operation circuit which AND is sensed so that the merged view number (0 are) accumulator effectively operates as calculating component (331 - 1) can be a. Thus, in this example, operation step (371 - 2) has a cell (303 - 6) (e.g., "1") and data stored value AND cell (303 - 1) (e.g., "1") is stored in data value "1" is "1" components calculated dimensions (331 - 1) tolerant stored. Operation step (371 - 3) computing components (331 - 1) activating data stored value invert the sensing circuit comprise a (e.g., calculating component (331 - 1) is cells (303 - 1 and 303 - 6) adapted to store result data stored price NAND). Calculating component (331 - 1) step is computed (371 - 2) after cell (303 - 1) stored data value and cell (303 - 6) result data stored value AND starts, operation step (371 - 3) calculated for components (331 - 1) reversed value data stored in the calculated component (331 - 1) is cells (303 - 1 and 303 - 6) NAND data values stored in the result storing tolerant. Thus, in this example, calculating component (331 - 1) is "0" stored data value is generated (for example, cell (303 - 6) stored "1" cell (303 - 1) is "0" "1" stored in a NAND result of the) calculated components (331 - 1) tolerant stored (for example, the "0" stored "1" is inverted substrate). Calculating components stored data to inverter operation (for example, "0" to "1" and vice versa as well as inverted to a water-in addition are disclosed) examples of performing further described hereinafter. As shown in 3a also sensing circuit includes memory cell (303 - 16) can be operative to store the result of an operation to NAND (e.g., calculating the same components (331 - 1) by copying data stored value). Operation steps (371 - 4 and 371 - 5) are arranged value number 1 memory cell (e.g., 303 - 1) stores data to be protected by a parity value stored data value and stores data to be protected by a number 2 memory cell (e.g., 303 - 6) OR data stored values associated with the performed operation. For example, operation step (371 - 4) is cell (303 - 1) (e.g., "1") data stored value calculating component (331 - 1) loading the substrate. Memory cell (303 - 1) (e.g., "1") data stored value calculating component (331 - 1) loading to a corresponding sense amplifier (e.g., a sense amplifier shown in fig. 2 (206 - 1)) to a memory via a cell (303 - 1) and a plurality of number of sensing a signal of operation (hereinafter also as further described in relation to the 4 to 6 also) calculated through component (331 - 1) transmits the values (for example, copying) data perceived as a can. Thus, as shown in fig. 3a, operation step (371 - 4) the computing component (331 - 1) cell (303 - 1) (e.g., "1") data stored value tolerant storage. Operation step (371 - 5) in, sensing circuit which calculates the components (331 - 1) data value stored in the cell (303 - 1) (e.g., "1") data stored value and a cell (303 - 6) (e.g., "1") of the results of an OR a stored data value operable with each other. As further described hereinafter, are sensed so that OR operation circuit which won't (are 1) an effectively functioning as accumulator calculating component (331) can be a. Thus, in this example, operational phase (371 - 5) is cell (303 - 6) (e.g., "1") and data stored value OR cell (303 - 1) (e.g., "1") is stored in data value "1" is "1" components calculated dimensions (331 - 1) tolerant stored. Operation step (371 - 6) from NAND operation result value (for example, "0") is essentially OR operation result value (e.g., "1") and for performing calculation operations from AND sensed so that circuit by operating the cells (303 - 1 and 303 - 6) carried out with respect to the result of an operation data stored values and its OR NAND combination substrate. The result of an operation result of an operation result and NAND OR AND values test carried out with respect to the result of an operation to XOR value disclosed. As shown in 3a also, operation step (371 - 6) in, protection cells (303 - 1 and 303 - 6) were performed before the NAND operation result value from data stored values (e.g., "0") is unprotected cell (303 - 16) overnight. In addition, calculation step (371 - 6) in, calculating component (331 - 1) includes cells (303 - 1 and 303 - 6) were performed before data stored values (e.g., "0") OR operation result value from store. In this way, cell (303 - 16) stored data value and calculating component (331 - 1) AND data stored value to sensing line (305 - 1) coupled to the sensing circuit activating computational component (331 - 1) is, protection cells (303 - 1 and 303 - 6) XOR operation result value data stored values (e.g., the "0" "1" "1" XOR are disclosed) corresponding to, "0" (for example, the "0" "0" "0" AND are disclosed) tolerant storage. The result of an operation value (for example, the instance in time, "0") XOR protective cells a corresponding parity value. Operation step (371 - 7) in, sensing circuit which calculates the components (331 - 1) value (for example, parity value ("0")) data stored in the parity cell (303 - 21) so as to store operation with each other (for example, calculation component (331 - 1) stored data value ("0") as town, cell (303 - 21) is copied into the substrate). Number 1 XOR operation from the resulting data value (e.g., said described as "0" protective cells (303 - 1 and 303 - 6) carried out with respect to data stored values attributed to XOR) coupled to particular sensing line (for example, sensing line (305 - 1)) with different protection memory cells (for example, memory cell (303 - 11)) carried out with respect to data stored values can be used in subsequent XOR operation. For example, sensing line (305 - 1) coupled to the sensing circuit detects the result of an operation number 1 XOR value (for example, "0" memory cells (303 - 1 and 303 - 6) XOR operation carried out with respect to data stored values attributed) and another memory cell data value (for example, also 3a shown as cell (303 - 11) ("0") data stored value) to number 2 (for example, subsequent) can be enabled to perform the XOR operation. In this example, number 2 XOR operation is "0" "0" "0" "0" since the XOR parity value calculated step (371 - 7) in parity cell (303 - 21) a specific relationship to storage are disclosed. In this way, cells (303 - 1, 303 - 6, and 303 - 11) for protecting data stored parity value is "0" and, this protected data is an even number of "1 are" (for example, the instance in time, each cells (303 - 1, 303 - 6, and 303 - 11) stored data values ("1", "1", and "0") comprises an even number of "1 s" in the two "1 are") comprising indicating that the substrate. Sensing line (305 - 1) coupled to its additional protection cells if so, protected data on a corresponding parity value corresponding sensing circuit to determine, said described similar manner, each number of additional XOR operations can be operative to perform. In this example, NAND operation is two data values (e.g., "1" and "1") previously OR operation performed for a NAND (for example, "0") to the result of an operation is an additional memory cell (for example, memory cell (303 - 16)) OR (" 1) is stored in the result of an operation is stored AND operation calculated components but, in the embodiment are not so number one. In some in the embodiment, the operations are NAND operations can be carried out prior to OR. In these in the embodiment, the result of an operation OR additional NAND memory cell can be the result of an operation performed AND operation calculated when the stored components can be stored. In the embodiment according to the disclosure are also 3b includes a plurality of sensing method using the parity calculation associated with schematic degree for example as follows. In the embodiment according to the described application 3b also includes determining a value of a plurality of parity associated with a plurality of operation steps (373 - 1 to 373 - 7) during specific sensing line (305 - 2) calculation component coupled to (331 - 2) stored in the particular data value is exemplified substrate. Sensing line (305 - 2) 2 also is shown in array (201) can be one such as array plurality of sensing lines. As such, sensing line (305 - 2) structure is coupled to a plurality of memory cells (303 - 2, 303 - 7, 303 - 12, 303 - 17, and 303 - 22) which, in addition cells are each access lines (304 - 1 to 304 - 5) coupled. Calculating component (331 - 2) is further described hereinafter in relation to also 4 is that component (431) component such as can be calculated. The, calculating component (331 - 2) the memory cells (303) and/or a corresponding sensing circuit having (for example, also 3b not shown other sensing circuit in also 2 shown such as sense amplifier (206 - 2), a sense amplifier shown in fig. 4 (406)) devices (e.g., transistors) having formed on a pitch can be. In this example, access lines (304 - 1 to 304 - 3) coupled to cells (e.g., cells (303 - 2, 303 - 7, and 303 - 12) the access lines (304 - 5) coupled to the cell (e.g., cell (303 - 22)) protected by parity value stored data values (e.g., each "0", "0", and "1") store. I.e., access lines (304 - 1 to 304 - 3) protective access lines are disclosed. Therefore, in this example, access lines (304 - 4 and 304 - 5) is unprotected access lines (for example, and is connected to the protective cells which do not have access lines) are disclosed. In this example, access lines (304 - 5) access lines are arranged are disclosed. For example DRAM array also 3b in array can be, but not shown, sensing line (305 - 1) each complementary sensing line pair (e.g., 4 also shown in complementary sensing lines (405 - 1/405 - 2)) can be comprising. Sensing line (305 - 2) described in the embodiment are coupled to the sensing circuit includes a plurality of model according to XOR application protection memory cells (e.g., cells (303 - 2, 303 - 7, and 303 - 12)) corresponding to the data to determine stored parity value can be. XOR operations are for example NAND, AND, OR, and/or sensed so that inverter operation such as model number of logical circuit which can be carried out. Example 3b also shown in memory cells (303 - 2, 303 - 7, and 303 - 12) (for example, sensing line (305 - 1) coupled to the protection cells) stored data parity calculation is exemplified substrate. Operation steps (373 - 1 to 373 - 3) are associated with the NAND operation is performed. Operation steps (373 - 4 to 373 - 5) OR are associated with the performed operation. Operation step (373 - 6) is the result of an operation values AND OR calculation and NAND operation (for example, each NAND and resulting values OR "AND the") are associated with the development and performing. Operation steps (373 - 1 and 373 - 2) are arranged value number 1 memory cell (e.g., 303 - 2) stores data to be protected by a parity value stored data value and stores data to be protected by a number 2 memory cell (e.g., 303 - 7) AND data stored values associated with the performed operation. For example, operation step (373 - 1) is cell (303 - 2) (e.g., "0") data stored value sensing line (305 - 2) corresponding to the sensing circuit to comprise a loading (e.g., calculating component (331 - 2)). Memory cell (303 - 2) (e.g., "0") data stored value calculating component (331 - 2) loading to a corresponding sense amplifier (e.g., a sense amplifier shown in fig. 2 (206 - 2)) to a memory via a cell (303 - 2) and a plurality of number of sensing the signals (also as described further hereinafter in relation to the 4 to 6 also) calculated through operation of components (331 - 2) transmitting a data value (e.g., radiation) perceived as a can. Thus, as shown in also 3b, operation step (373 - 1) computing components (331 - 2) cell (303 - 2) (e.g., "0") data stored value tolerant storage. Operation step (373 - 2) in, sensing circuit which calculates the components (331 - 2) data value stored in the cell (303 - 2) (e.g., "0") data stored value and a cell (303 - 7) (e.g., "0") of the results of an AND a stored data value operable with each other. As further described hereinafter, for performing an operation circuit which AND is sensed so that the merged view number (0 are) accumulator effectively operates as calculating component (331 - 2) can be a. Thus, in this example, operation step (373 - 2) has a cell (303 - 7) (e.g., "0") and data stored value AND cell (303 - 2) (e.g., "0") is "0" data stored value "0" is calculated component dimensions (331 - 2) tolerant stored. Operation step (373 - 3) computing components (331 - 2) reverse the value stored in the sensed so that circuit comprises activating (e.g., calculating component (331 - 2) is cells (303 - 2 and 303 - 7) NAND adapted to store result data stored values). Operation step (373 - 2) after calculating component (331 - 2) cell (303 - 2) stored data value and cell (303 - 7) starts AND result data stored value, operation step (373 - 3) calculated for components (331 - 2) reversed value data stored in the calculated component (331 - 2) is cells (303 - 2 and 303 - 7) NAND data values stored in the result storing tolerant. Thus, in this example, calculating component (331 - 2) reversed data stored value is "1" (for example, cell (303 - 7) stored "0" cell (303 - 2) "0" "1" is stored in the NAND result are disclosed) calculated components (331 - 2) tolerant stored (for example, "0" "1" is stored is the one substrate). Stored data according to a predetermined inverter calculated components (e.g., a "0" to "1" or vice versa as well as reversing in addition are disclosed) in examples hereinafter further described. As shown in 3b also sensing circuit includes memory cell (303 - 17) can be operative to store the result of an operation to NAND (e.g., calculating the same components (331 - 2) by copying data stored value). Operation steps (373 - 4 and 373 - 5) are arranged value number 1 memory cell (e.g., 303 - 2) stores data to be protected by a parity value stored data value and stores data to be protected by a number 2 memory cell (e.g., 303 - 7) OR data stored values associated with the performed operation. For example, operation step (373 - 4) is cell (303 - 2) (e.g., "0") data stored value calculating component (331 - 2) loading the substrate. Memory cell (303 - 2) (e.g., "0") data stored value calculating component (331 - 2) loading to a corresponding sense amplifier (e.g., a sense amplifier shown in fig. 2 (206 - 2)) to a memory via a cell (303 - 2) and a plurality of number of sensing the signals (also as described further hereinafter in relation to the 4 to 6 also) calculated through operation of components (331 - 2) transmitting a data value (e.g., radiation) perceived as a can. Thus, as shown in also 3b, operation step (373 - 4) the computing component (331 - 2) cell (303 - 2) (e.g., "0") data stored value tolerant storage. Operation step (373 - 5) in, sensing circuit which calculates the components (331 - 2) data value stored in the cell (303 - 2) (e.g., "0") data stored value and a cell (303 - 7) (e.g., "0") data stored value to the results of an OR operable with each other. As further described hereinafter, are sensed so that OR operation circuit which won't (are 1) an effectively functioning as accumulator calculating component (331 - 2) can be a. Thus, in this example, operation step (373 - 5) is cell (303 - 7) (e.g., "0") and the stored data value OR (303 - 2) (e.g., "0") is "0" data stored value "0" is calculated component dimensions (331 - 2) tolerant stored. Operation step (373 - 6) from NAND operation result value (e.g., "1") and essentially OR operation (for example, "0") AND operation result value from the sensed so that circuit by operating the cells (303 - 2 and 303 - 7) carried out with respect to the result of an operation data stored values and its OR NAND combination substrate. The result of an operation result of an operation result and NAND OR AND values test carried out with respect to the result of an operation to XOR value disclosed. Also as shown in 3b, operation step (373 - 6) in, protection cells (303 - 2 and 303 - 7) data stored values (e.g., "1") is performed before the NAND operation result value from unprotected cell (303 - 17) overnight. In addition, calculation step (373 - 6) in, calculating component (331 - 2) includes cells (303 - 2 and 303 - 7) were performed before data stored values (e.g., "0") OR operation result value from store. The, cell (303 - 17) stored data value and calculating component (331 - 2) AND data stored value to sensing line (305 - 2) coupled to the sensing circuit activating computational component (331 - 2) protected cells (303 - 2 and 303 - 7) XOR operation result value data stored values (e.g., "0" "0" "0" is the XOR) corresponding to, "0" (for example, the "0" "1" "0" AND are disclosed) tolerant storage. The result of an operation value (for example, the instance in time, "0") XOR protective cells a corresponding parity value. Operation step (373 - 7) in, sensing circuit includes a parity cell (303 - 22) calculated in component (331 - 2) (for example, parity value ("0")) a stored data value operative to store with each other (for example, calculation component (331 - 2) stored data value ("0") as town, cell (303 - 22) is copied into the substrate). Number 1 XOR operation from the resulting data value (e.g., said described as "0" protective cells (303 - 2 and 303 - 7) carried out with respect to data stored values in XOR attributed) coupled to particular sensing line (for example, sensing line (305 - 2)) with different protection memory cells (for example, memory cell (303 - 12)) carried out with respect to data stored values can be used in subsequent XOR operation. For example, sensing line (305 - 2) coupled to the sensing circuit detects the result of an operation number 1 XOR value (for example, "0" memory cells (303 - 2 and 303 - 7) XOR operation carried out with respect to data stored values attributed) and another memory cell data value (for example, also 3b shown as cell (303 - 12) ("1") data stored value) to number 2 (for example, subsequent) can be enabled to perform the XOR operation. In this example, number 2 XOR operation is "0" "1" "1" "1" since the XOR parity value calculated step (373 - 7) in parity cell (303 - 22) a specific relationship to storage are disclosed. In this way, cells (303 - 2, 303 - 7, and 303 - 12) for protecting data stored parity value is "1" and, this odd-protected data is "1 are" (for example, the instance in time, each cells (303 - 2, 303 - 7, and 303 - 12) stored data values ("0", "0", and "1") is odd in one "1" "1 are" comprises) comprising indicating that the substrate. Sensing line (305 - 2) coupled to its additional protection cells if so, protected data on a corresponding parity value corresponding sensing circuit to determine, said described similar manner, each number of additional XOR operations can be operative to perform. Figure 4 shows a plurality of disclosure are therefore in the embodiment according to sensing circuit coupled to the memory array (430) a portion of the schematic diagram of the example as follows. In one embodiment, memory array (430) from each other are access device (402) (e.g., transistor) and storage element (403) a (for example, capacitor) including 1T 1C (1 transistor 1 capacitor) DRAM array memory cells are disclosed. In the embodiment are, however, not one number to this example process from other array types (e.g., etc. intersection arrays PCRAM memory elements). Array (430) cells comprise access lines coupled to respective rows (404 - 0 (Row0), (Row1) 404 - 1, 404 - 2 (Row2), 404 - 3 (Row3), .. , 404 a-N (RowN)) and sense lines are coupled columns by (e.g., digit lines) to (305 - 1 (D) and 405 - 2 (D_)) are prevented. In this example, cells each column complementary sensing lines are associated with the pair of (405 - 1 (D) and 405 - 2 (D_)). In a plurality of in the embodiment, a sense amplifier (e.g., 406) calculating component (e.g., 431) of transistors and/or arrays of memory cells (e.g., 430) having a plurality of transistors can be formed on pitch, this particular feature size (e.g., 4F2 , 6F2 Or the like) can follow a disclosed. As described further hereinafter, calculation component (431) a sense amplifier (406) with, and then transferring it through sensing line address access (e.g., data local I/O lines (for example, also 2 shown in I/O line (466) and/or I/O line (234)) installed in circuit and array external to the circuit and does not decode signal are sent at column) of a change in the parity value associated with can be operative to perform various operations. Also illustrated 4 in one example, component (431) to corresponding circuit for sensing lines (D and D_) transistor coupled to 5 but; in the embodiment are not one number to this example. Transistors (407 - 1 and 407 - 2) coupled to the source/drain regions respectively sensing lines (D and D_) number 1, and cross-coupled latch coupled to (e.g., cross-coupled NMOS transistors (408 - 1 and 408 - 2) and cross-coupled PMOS transistors (409 - 1 and 409 - 2) such as, cross-coupled pair of transistors coupled to gates) number 2 has a source/drain region. The application as further described, transistors (408 - 1, 408 - 2, 409 - 1, 409 - 2 and) 2 difference can be covalently cross-coupled latch comprising a latch, this accumulator acts as the application can be referred in accumulators (sensing amplifier (406) corresponding to the cross-coupled latch the latch 1 difference in application can be covalently). Transistors (407 - 1 and 407 - 2) comprise transistors can be covalently, this provides the sensing lines (D and D_) on voltages or currents transistors (408 - 1, 408 - 2, 409 - 1, 409 - 2 and) comprising cross-coupled latch inputs (for example, an input of the latch 2 difference) for transferring each signals (411 - 1 (Passd) and 411 - 2 (Passdb)) through enabled disclosed. In this example, transistor (407 - 1) number 2 of source/drain regions are transistors (408 - 2 and 409 - 2) gates as well as transistors (408 - 1 and 409 - 1) coupled to a source/drain region of number 1. Similarly, transistor (407 - 2) number 2 of source/drain regions are transistors (408 - 2 and 409 - 2) as well as source/drain regions of transistors number 1 (408 - 1 and 409 - 1) coupled to gates. Transistors (408 - 1 and 408 - 2) source/drain region is generally part of number 2 (negative) number signals (412 - 1) coupled to (Accumb). Transistors (409 - 1 and 409 - 2) number 2 of source/drain regions are generally positive (positive) number signals (412 - 2) coupled to (Accum). Activated Accum signal (412 - 2) the supply voltage (e.g., Vcc) can have a reference voltage (e.g., ground) signal is activated Accumb implementation being. Signals (412 - 1 and 412 - 2) for activating the corresponding transistors latch 2 difference (408 - 1, 408 - 2, 409 - 1, 409 - 2 and) cross-coupled latch comprising frequencies. Enabled cross-coupled latch node (417 - 1) is one of the signal voltage (e.g., Vcc and ground one) Accumb Accum signal voltage and drive, node (417 - 2) Accumb Accum signal voltage and another of the signal voltage is installed to the common node (417 - 1) and a common node (417 - 2) amplifying differential voltages between operable to each other. As described further hereinafter, signals (412 - 1 and 412 - 2) 2 for performing a logic operation to latch the difference (for example, AND operation) to act as an accumulator during use because "Accum" and "Accumb" labeled. In a plurality of in the embodiment, an accumulator can collect pass transistors (407 - 1 and 408 - 2) as well as cross-linked transistors 2 difference latch (408 - 1, 408 - 2, 409 - 1, 409 - 2 and) comprises. In this example, calculation component (431) is in addition each digit lines coupled to the source/drain region transistors (D and D_) number 1 (414 - 1 and 414 - 2) is generated comprising substrate. Transistors (414 - 1 and 414 - 2) of number 2 source/drain areas each have a transistors (416 - 1 and 416 - 2) coupled to a source/drain region of number 1. Transistors (416 - 1 and 416 - 2) can be coupled to a ground source/drain region is of number 2. Transistors (414 - 1 and 314 - 2) signal gates (413) coupled to (InvD). Transistor (416 - 1) the gate of the transistor (408 - 2) gate, transistor (409 - 2) gate, and transistor (408 - 1) number 1 of source/drain area is in addition coupled to a common node (417 - 1) coupled to. Complementary manner, transistor (416 - 2) the gate of the transistor (408 - 1) gate, transistor (409 - 1) gate, and transistor (408 - 2) number 1 of source/drain area is in addition coupled to a common node (417 - 2) coupled to. In this way, inverter operation is signal (InvD) can be performed by activating an, this latch 2 difference data value (for example, stored data value calculated components) and reverse the inverted value sensing lines (405 - 1 and 405 - 2) into conformal substrate. In a plurality of in the embodiment, and also in relation to the 2 and 3 also as said display, parity value calculating component for calculating regarding for example, NAND, AND, OR, and inverter model can be used. For example, sense amplifier specific values enabled (406) can be sensed by. Data values are then Passd (411 - 1) and Passdb (411 - 2) signal as well as Accumb (412 - 1) and Accum signals (412 - 2) activate calculated by component (431) latch data can be transmitted. The same sensing coupled to a different specific data stored value stored in the data value and calculation component for AND, enabled access line be different specific cells are disposed. Sensing amplifier (406) can be enabled (e.g., operating), this sensing lines (405 - 1 and 405 - 2) on differential signal of the substrate. Only Passd (411 - 1) activating only the (e.g., Passdb (411 - 2) while maintaining a non-activated) sensing line (405 - 1) on voltage signals (e.g., logic "1" or logical "0" corresponding to Vcc corresponding to ground) tolerant data corresponding to the accumulation value. Accumb AND Accum signals are activated during calculation operations and remain disclosed. Therefore, different specific (and sense amplifier (406) sensed by) stored in the logic "0" data value back, 2 difference calculating component to latch (low) for example, such as ground voltage 0V) to which asserted (assert), the logical "0" and store. However, different specific stored in (and sense amplifier (406) sensed by) value the logical "0" is not, its old value difference calculating component holds the latch 2. Therefore, logical "1" only if it previously calculated components store storing logic "1" logic "1" in addition different specific cells which store. Therefore, calculating component (431) logical AND operation is enabled to perform the other. Said as known, inversion signal (413) is for example, which can be synchronized using the NAND operation, calculating component (431) reversing the data value stored by the can be activated (e.g., by the watermark to be the result of an operation AND). In the embodiment according to the disclosure are using multiple 5a also includes a plurality of sense circuit to perform an operation performing logic operations associated with timing is also (585 - 1) for example as follows. Timing is also (585 - 1) is carried out (for example, R - input logic operation) number 1 operation of logic value associated with signals (e.g., voltage signals) is exemplified substrate. Also described number 1 operation step 5a for example, AND, NAND, OR, or NOR operation be a number 1 of an operation step. As described further hereinafter, operations carried out previous processing approaches also illustrated 5a is considerably less than the energy (for example, about one half) can be consuming involves, this perform a logic operation between the voltage rails (for example, between the supply and ground) can be under public affairs number involves full swing. In one example illustrated 5a also, complementary logic values (for example, "1" and "0") to a supply voltage corresponding to the voltage rails (574) (VDD) and ground voltage (572) (Gnd) are disclosed. Prior to perform a logic operation, complementary sensing lines (D and D_) is balanced voltage (525) (VDD/2) to short together at equilibrium can be generated. 6 also is further described hereinafter in relation to equilibrium. t1 In, balanced signal (equilibration signal) (526) is deactivated and, then selected access line (e.g., row) is enabled (e.g., data value is detected and used as an input number 1 memory cell row). Signal (504 - 0) is the selected row (e.g., row in Figure 4 (404 - 0)) exhibits voltage applied to the signal. Low signal (504 - 0) a corresponding access transistor (e.g., 402) is selected cell when it reaches the threshold voltage of (Vt), access transistors in the sensing line (D) turning on the selected memory cell (e.g., cell back 1T 1C DRAM cell capacitor (403) to) joins the, this times (t2 T and3 ) Between the differential voltage signal sensed between lines (D and D_) (e.g., each signals (505 - 1 and 505 - 2) as indicated by) generate musical sound. Are cell voltage signal (503) represented. Due to conserve energy, and generating the D_ D between differential signals (for example, by the engagement of a cell sensing line (D)), low signal (504) is activated/associated with that deactivates the plurality of memory cells is coupled to a low-energy across can be redeemed, not a switch. Time (t3 ) In, sensing amplifier (e.g., 406) is enable is (for example, positive (positive) number signals (531) (for example, also 6 shown in PSA (631)) is pulled high and as, part (negative) number signals (528) (for example, RNL_ (628)) is (low) to go to other), this apparatus for differential signal of the D D_ in between and, logic 1 voltage (e.g., VDD) line (D) corresponding to sensed or detected on driver logic 0 (e.g., ground) (and a complementary sensing line (D_) on different voltages) and dimensions, the sensed data values are then sensing amplifier (406) of latch 1 difference overnight. 1 difference energy consumption are balanced voltage (VDD/2) from rail voltage (VDD) sensing line (D) (505 - 1) can be occur when filling. Time (t4 ) In, pass transistors (407 - 1 and 407 - 2) is enabled (for example, in Figure 4, each number through the other side of (411 - 1 and 411 - 2) and applied through signals over each Passd Passdb number). The number signals (411 - 1 and 411 - 2) to the number all the signals (511) covalently substrate. As used in the application, such as Passd and Passdb, various signals are combined at the other side of the applied reference the number number can be referred to. For example, number Passd signal is a signal (411 - 1) can be covalently. Time (t5 ) In, the accumulator number signals (Accum Accumb and) the other side of the each number (412 - 1 and 412 - 2) through activated substrate. As described hereinafter, the accumulator number signals (for example, the accumulator number signals (512 - 1 and 512 - 2)) corresponding to a activated toward subsequent operation steps thereof can. Thus, in this example, the number signals (512 - 2 and 512 - 1) activating a computational component (e.g., 431) of latch 2 difference frequencies. Sensing amplifier (406) stored sensed data value is calculated components (431) of 2 difference (for example, copying) a latch transmission are disclosed. Time (t6 ) In, pass transistor (407 - 1 and 407 - 2) capabilities but is (for example, turn-off); the accumulator number signals (512 - 1 and 512 - 2) is activated corresponding to a, cumulative results calculated components (431) of storage (e.g., latch) latch 2 difference with each other. Time (t7 ) In, low signal (504 - 0) is is deactivated and, array sensing amplifier NID (t8 ) In disabled (for example, the sensing amplifier number signals (528 and 531) is deactivated with each other). Time (t9 ) In, is capable of sensing lines (D and D_) respective rails values balanced voltage (525) (VDD/2) movement of the sensing line voltage signals (505 - 1 and 505 - 2) as to that, balanced with each other (for example, balanced signal (526) is activated with each other). The first conductive type is a switch S. equilibrium conserve energy laws. As described hereinafter in relation to 6 also, equilibrium is in this example, VDD/2 in, balanced voltage with current power involves complementary sensing lines (D and D_) can be. Equilibrium is, for example, memory cell can be generated before sense operation. In the embodiment according to the disclosure are also 5ba 5bb is also and a plurality of sense circuit performing logical operations associated with multiple, timing mobilities (585 - 2 and 585 - 3) is exemplified substrate. Timing mobilities (585 - 2 and 585 - 3) logical operation (for example, R - input logic operation) of a plurality of intermediate operation steps (e.g., voltage signals) is exemplified therein associated with the signals. For example, timing is also (585 - 2) is input NAND operations or R - R - input AND of an operation that corresponds to a plurality of intermediate operation step, timing is also (585 - 3) input NOR operations or R - R - a plurality of intermediate operation steps OR of an operation is input into the slide groove. For example, AND or NAND operation also is such as 1 or more times and then initial operation described 5a shown in operation can be carried out also 5ba comprising. Similarly, the NOR OR or a predetermined initial operation such as 1 or more times and then also described 5a shown in drain hose carried out can be also 5bb comprising. Timing mobilities (585 - 2 and 585 - 3) as shown in, time (t1 ) In, equilibrium is disabled (e.g., balanced signal (526) is deactivated substrate), then the selected row is disabled (e.g., data value is detected and number 2 input, such as the memory cells used as inputs input number 3 row). Signal (504 - 1) is the selected row (e.g., row in Figure 4 (404 - 1)) exhibits voltage applied to the signal. Low signal (504 - 1) a corresponding access transistor (e.g., 402) is selected cell when it reaches the threshold voltage of (Vt), access transistors in turning on the selected memory cell (e.g., cell back 1T 1C DRAM cell capacitor (403) to) and combining sensing line (D), this times (t2 T and3 ) Between the differential voltage signal sensed between lines (D and D_) (e.g., each signals (505 - 1 and 505 - 2) as indicated by a) generate musical sound. Are cell voltage signal (503) represented. Due to conserve energy, and generating the D_ D between differential signals (for example, by the engagement of a cell in sensing line (D)), low signal (504) is activated/associated with that deactivates the plurality of memory cells is coupled to a low-energy across can be redeemed, not a switch. Time (t3 ) In, sensing amplifier (e.g., 406) is enabled (e.g., positive number signals (531) (for example, also 6 shown in PSA (631)) is pulled high and as, part number signals (528) (for example, RNL_ (628)) is (low) to go to other), this apparatus for differential signal of the D D_ in between and, logic 1 voltage (e.g., VDD) line (D) corresponding to sensed or detected on driver logic 0 (e.g., ground) (and a complementary sensing line (D_) on different voltages) and dimensions, the sensing amplifier (for example, sensing amplifier (406)) sensed data value is stored in latch difference of 1. 1 difference energy consumption are balanced voltage (VDD/2) from rail voltage (VDD) sensing line (D) (405 - 1) can be occur when filling. Timing mobilities (585 - 2 and 585 - 3) as seen, time (t4 ) (For example, the cell is formed after an) in, the number signals (411 - 1 (Passd) and 411 - 2 (Passdb)) only one of the control, in dependence on the particular logical operation, activated substrate (for example, pass transistors (407 - 1 and 407 - 2) only one of the enabled). For example, timing is also (585 - 2) is in accordance with the NAND or AND the intermediate of an operation, a signal number (411 - 1) is time (t4 ) In number signal and a signal (411 - 2) has is deactivated remain disclosed. On the contrary, timing is also (585 - 3) corresponding to the intermediate steps of an operation is NOR or OR, a signal number (411 - 2) is time (t4 ) In number signal and a signal (411 - 1) is is deactivated remain disclosed. The signals from said accumulator number (512 - 1 (Accumb) and 512 - 2 (Accum)) have been activated during initial operation step described 5a auditory canal, they (are) remains activated during intermediate operation step that said defect/deficiency. Components enable it became calculated previously, only Passd (411 - 1) activating only the voltage signal (505 - 1) tolerant data corresponding to the accumulation value. Similarly, only Passdb (411 - 2) activating only the voltage signal (505 - 2) tolerant data corresponding to the accumulation value. For example, only Passd (411 - 1) activated only in an exemplary AND/NAND operation (for example, timing is also (585 - 2)), the selected memory cell (for example, in one embodiment, Row1 memory cell) data value logic 0 stored in back, 2 difference value is logic 0 to 2 difference associated with latch configured to store encoded asserted to latch (low). Row1 logic stored in the data value is not 0, 2 difference (for example, logical 1 or logical 0) stored Row0 its latch holds the data value. Thus, in such AND/NAND operation, the merged view 2 difference latch number (0 are) accumulator such as ease. Similarly, only Passdb activated only in an exemplary OR/NOR operation (for example, timing is also (585 - 3)), the selected memory cell (for example, in one embodiment Row1 memory cell) logic 1 data stored value back, accumulated value is logic 1 2 2 difference associated with latch to store the encoded difference latch asserted pulled high. Row1 logic stored in the data value is not 1, 2 difference (for example, logical 1 or logical 0) stored Row0 its latch holds the data value. Thus, in this OR/NOR operation, D_ latch on 2 difference voltage signals (405 - 2) setting the value data is calculated component chamber because the number one are (1 are) effectively 4. calculated as components. Also 5ba shown in intermediate operation in step such as concrete and also 5bb, Passd signal (for example, for AND/NAND) or Passdb signal (for example, for OR/NOR) (for example, in time (t5)) and is deactivated, the selected row is disabled (e.g., in time (t6)), and has a sensing is disabled (e.g., in time (t7)), equilibrium occurs (for example, in time (t8)). 5ba or also a plurality of additional steps such as exemplified in also 5bb intermediate operation can be repeated for brought results from a row. For example, timing is also (585 - 2 or 585 - 3) Row2 sequence of subsequent memory cell (for example, number 2) time, a subsequent memory cell (for example, number 3) Row3 object in real time can be performed. For example, 10 - input NOR of arithmetic, number 10 - input logic value shown in intermediate step also 5bb for generating under public affairs 9 inputs can be 9 times, number 10 input during initial operation step (for example, as also described 5a) determined. Said logic operations (e.g., AND, OR, NAND NOR) described in the embodiment of the disclosure regarding parity according to yield can be performed. In the embodiment according to the disclosure are also 5ca 5cb sense circuit is also and a plurality of channels associated with performing logical operations, timing mobilities (585 - 4 and 585 - 5) is exemplified substrate. Timing mobilities (585 - 4 and 585 - 5) logic operation is carried out (for example, R - input logic operation) the last operation associated with signals (e.g., voltage signals) is exemplified substrate. For example, timing is also (585 - 4) is the last operation in accordance with the operation input NAND operations or R - R - input NOR and, timing is also (585 - 5) is the last operation in accordance with the operation input OR AND operations or R - input R - 2000. For example, NAND is described in relation to a predetermined number of iterations after the intermediate operation step also 5ba shown in operation can be carried out also 5ca comprising, NOR 5bb is also described in relation to a predetermined number of iterations after the intermediate operation step shown in operation can be carried out also 5ca comprising, AND 5ba is described in relation to a predetermined number of iterations after the intermediate operation step also shown in operation can be carried out also 5cb comprising, OR 5bb is also described in relation to a predetermined number of iterations after the intermediate operation step shown in operation can be carried out also 5cb comprising. In the embodiment shown in table 1 hereinafter described application according to a plurality of the plurality of R - input logical operations associated with performing a sequence of operational steps corresponding drawing indicating other. Table 1 Also 5ca last operation steps are array (e.g., array (430)) and also 5cb R - rows storing described regarding input logic value. However, in a plurality of in the embodiment, the total array again not result an appropriate location (e.g., I/O line through, number go back and/or host processor external register, different memory device into a memory array or the like) can be stored. Timing mobilities (585 - 4 and 585 - 5) as shown in, time (t1 ) In, sensing lines (D and D_) equilibrium floating so that the disabled (e.g., balanced signal (526) is deactivated substrate). In time (t2), InvD signal (513) or Passd and Passdb signals (511) depending on whether any logic operation is performed, activated substrate. In this example, InvD signal (513) is NAND or NOR operation and be activated toward (also 5ca reference), Passd and Passdb signals (511) are activated toward the AND or OR operation (also 5cb reference). In InvD signal time (t2) (513) (for example, NAND or NOR operation in relation to) a activating the transistors (414 - 1/414 - 2) wherein the sensing line (D) enables the lead to pulling (pull) (low) (D_) sensed or detected line components (e.g., 431) of 2 difference calculated to prevent latch data value inverse tolerant. In this way, signal (513) leading to the activation of the invert the accumulated output. Therefore, NAND of arithmetic, previous operation steps (e.g., steps and at least one middle operation initial operation step) is detected in any of the logical 0 if storing memory cells (e.g., any of the logical 0 point R - input NAND back), sensing line (D_) driver may convey the logical 0 (e.g., ground voltage) which sensing line (D) corresponding to logical 1 voltage (for example, such as supply voltage VDD) may convey are disclosed. This NAND for example, memory cells storing logic 1 if both sensed previous operation steps (for example, command inputs NAND logic 1 R - both back), sensing line (D_) driver may convey a logical 1 which may convey a logical 0 (D) sensing line driver are disclosed. In time (t3), sensing amplifier (406) (for example, sensing amplifier is activated substrate) of 1 difference latch is then is enabled, which leads to an appropriate rails and D_ D, sensing line (D) is determined from this number detecting previous operation steps as NAND memory cells each input data values are made of liquid crystal cell. As such, sensing line (D) back to any of the logical 0 VDD input data values which may both logic 1 input data values back ground sensing line (D) it will rain. NOR of arithmetic, previous operation steps (e.g., steps and at least one middle operation initial operation step) is detected in any of the logical 1 if storing memory cells (e.g., any of the logical 1 input point R - NOR back), a logical 1 (e.g., VDD) sensing line (D_) driver may convey a logical 0 which sensing line (D) driver may convey (e.g., ground) are disclosed. This NOR for example, memory cells storing logic 0 if both sensed previous operation steps (for example, R - NOR logic 0 inputs both point back), sensing line (D_) corresponding to a logical 0 voltage which may convey the sensing line (D) driver may convey the logical 1 are disclosed. In time (t3), sensing amplifier (406) of this number is 1 difference sensing line (D) latch is then enable detecting the memory cells as determined from previous operation steps each input data values comprises NOR result. As such, sensing line (D) will prevent any of the logical 1 input data values back ground sensing line (D) logic 0 input data values both in back VDD are disclosed. The reference also 5cb, Passd and Passdb signals (511) (for example, AND or OR operation in relation to) activating a computational component (431) of latch 2 difference stored accumulated output sensing amplifier (406) of components in the primary latch 1. For example, AND of arithmetic, previous operation steps (e.g., one or more iterations of number 1 and intermediate operation step also 5ba operation also 5a) if any of the logical 0 is detected in memory cells storing (e.g., any of the logical 0 point R - inputs AND back), a logical 1 (e.g., VDD) sensing line (D_) driver may convey a logical 0 which sensing line (D) driver may convey (e.g., ground) are disclosed. This AND for example, memory cells storing logic 1 if both sensed previous operation steps (for example, R - AND logic 1 inputs both point back), sensing line (D_) corresponding to a logical 0 voltage which may convey the sensing line (D) driver may convey the logical 1 are disclosed. In time (t3), sensing amplifier (206) of this number is 1 difference sensing line (D) latch is then enable detecting the memory cells as determined from previous operation steps each input data values AND result to a liquid crystal cell. As such, sensing line (D) will prevent any of the logical 0 input data values back ground sensing line (D) logic 1 input data values both in back VDD are disclosed. OR of arithmetic, previous operation steps (e.g., also 5a of number 1 and one or more intermediate operation step shown in operation also 5bb iterations) is detected in any of the logical 1 if storing memory cells (e.g., any of the logical 1 input point R - OR back), sensing line (D_) (e.g., ground) voltage corresponding to a logical 0 which may convey the sensing line (D) driver (e.g., VDD) may convey the logical 1 are disclosed. This OR for example, memory cells storing logic 0 if both sensed previous operation steps (for example, R - OR of an operation logic 0 inputs both back), sensing line (D) corresponding to a logical 0 voltage which may convey the sensing line (D_) driver may convey the logical 1 are disclosed. In time (t3), sensing amplifier (for example, sensing amplifier (406)) of this number is 1 difference sensing line (D) latch is then enable detecting the memory cells as determined from previous operation steps each input data values OR result to a liquid crystal cell. As such, sensing line (D) any of the logical 1 input data values back to VDD which may sense line (D) both logic 0 input data values back ground it will rain. R - input AND, OR, NAND, and NOR operations (e.g., array (430)) memory cell of their again in the array can be stored. Examples include also 5cb 5ca and also seen, R - the result of the logic operation RowN input coupled to memory cell (for example, in Figure 4 404 provided N) to overnight. Memory cell storing a logic value by enabling RowN simply RowN RowN access transistor (402) enable involve other. RowN memory cell capacitor (403) a sense line (D) data in value (e.g., logic 1 or logical 0) driving method corresponding to be at the predetermined level, this essentially any data value previously stored in the grand overlapping RowN anyway. RowN memory cell used as inputs for a logic operation is that store data values equal memory one which it will count attention thereto. For example, a memory cell or memory cell can be re-Row1 Row0 logic value. Timing mobilities (585 - 4 and 585 - 5) in time (t3), sensing amplifier (406) rendered inert by means of has a positive number to enable a signal (531) and different number signals (528) (for example, signal (531) is pulled high and as signal (528) is (low) to go to other) for example as follows. In time (t4), time (t2) of each signal activated (e.g., 511 or 513) is deactivated substrate. In the embodiment are not one number to this example. For example, in a plurality of in the embodiment, sensing amplifier (406) is time (t4) then (for example, signal (513) or signals (511) inactive after) enabled disclosed. As seen also 5cb 5ca and also, in time (t5), RowR (404 a-R) is enabled, this is cell capacitor (403) corresponding to the stored logic value voltage calculating components leads to the other. In time (t6), the Row R is disabled, in time (t7), sensing amplifier (406) is disabled (e.g., signals (528 and 531) inactive with each other), in time (t8), equilibrium occurs (for example, signal (526) is activated and complementary sensing lines (405 - 1/405 - 2) voltages on equilibrium voltage applied to the substrate). In a plurality of in the embodiment, also described 4 such as sensing circuit (e.g., pitch and having memory cells formed on a circuit) of the plurality of logical operations can be performed simultaneously is possible. For example, columns with array 16K, 16K logic operations can, through I/O lines (for example, via bus) array and without transmitting data from a sensing circuit, can be carried out simultaneously. As such, sensing circuit in a plurality of in the embodiment, a plurality of (e.g., 16K) (e.g., XOR operations) are parity calculation can be operative to perform. The disclosure of specific sensing circuit configuration in the embodiment are also illustrated 4 not one number. For example, in the embodiment according to a plurality of different calculation component architectures the described application for performing logical operations are can be used. For example, computation component architecture also 7 alternative illustrated substrate. Also illustrated but not 4, in a plurality of in the embodiment, the circuit number (for example, number 1 also shown in the circuit (140)) array (430), sensing amplifier (406), and/or calculated components (431) can be coupled to. The circuit number such for example, array and control circuitry and the same chip on and/or external processor can be implemented on the outer processing resources, the array and sensing circuitry for performing logical operations described application as various signals corresponding to the number be activated/de-activating [e[e] it will do. Figure 6 shows a schematic diagram of a portion of a plurality of disclosure in the embodiment example according to sensing circuit are therefore as follows. In one embodiment, sensing circuit portion of the sense amplifier (306) having a predetermined wavelength. In a plurality of in the embodiment, one sense amplifier (606) (e.g., "sensing amplifier") array (e.g., array (130)) encoded ball number for each column column memory cells. Sensing amplifier (606) is for example, be a DRAM array sense amplifier. In one embodiment, sensing amplifier (606) performs data reading circuit senses (605 - 1 ("D") and ("D_") 305 - 2) coupled to the pair of floating. As such, sensing amplifier (606) a sense lines (D and D_) via column column memory cells coupled to both. Sense amplifier (606) are each part number signals (628) (RNL_) coupled to each of the sources and sensing lines (D and D_) and coupled to the cross-coupled n - channel transistors having their drains (for example, NMOS transistors) (627 - 1 and 627 - 2) alignment of the substrate. Sense amplifier (606) is in addition each, positive number signals (631) (PSA) coupled to each of the sources and sensing lines coupled to it (D and D_) having their drains cross-coupled p - channel transistors (for example, PMOS transistors) (629 - 1 and 629 - 2) alignment of the substrate. Sensing amplifier (606) (D and D_) sensing lines each coupled to separate transistors (isolation transistors) (621 - 1 and 621 - 2) alignment of the substrate. Separating transistors (621 - 1 and 621 - 2) is activated when, column of a memory cell sense amplifier (306) to transistors for connecting (621 - 1 and 621 - 2) enables a number (for example, turn-on) a signal (622) coupled to (ISO). 6 also illustrated but not, sensing amplifier (606) is number 1 and number 2 memory number can be coupled to an array of complementary signals (e.g., ISO_) can be coupled to another pair of isolation transistors, this sensing amplifier (606) is number 2 when coupled to an array of sensing amplifier (606) is separated from the ISO number 1 array is deactivated and vice versa in addition is deactivated when it is disclosed. Sensing amplifier (606) in addition is configured to comprise a fixed sensing lines (D and D_) circuit. In this example, equilibration circuit such as VDD/2 can be, balanced voltage (625) coupled to the source/drain regions (dvc2) number 1 transistor (624) wherein, the application associated with the supply voltage VDD in array are disclosed. Transistor (624) number 2 of source/drain regions are transistors (623 - 1 and 623 - 2) pairs of source/drain regions coupled to a common number 1. Transistors (623 - 1 and 623 - 2) of number 2 source drain areas each, coupled to sensing lines (D and D_). Transistors (624, 623 - 1, 623 - 2) number of gates is a signal (626) coupled to (EQ). In this way, leading to the activation of the transistors EQ (624, 623 - 1, and 623 - 2) wherein the enable, this circuit senses (D and D_) is balanced voltage (dvc2) balanced sensed so that line (D) effectively short sensing line (D_) higher. Sensing amplifier (606) is in addition signal gates (633) (COLDEC) coupled to transistors (632 - 1 and 632 - 2) comprises. Signal (633) is column decode signal or column select signal can be covalently. Sensing lines (D and D_) signal (633) in response to each local I/O lines activating ((IO) 634 - 1 and 334 - 2 (IO_)) coupled with each other (for example, reading with respect to motion sensing line access such as for performing the). In this way, signal (633) is I/O lines (634 - 1 and 634 - 2) out of the accessed memory cell array at on state (e.g., logic 0 or logic 1 such as logical data value) corresponding to signal can be activated. In operation, when memory cell sensing (e.g., reading), sensing lines (D, D_) on one on the other during the supply voltage of the circuit senses (D, D_) slightly larger than the voltage at will. Sense amplifier (606) to high (high) for enabling a PSA signals are then brought into conformal and furnace (low) RNL_ signal reduction of vehicle from the outside. The PMOS transistor having a lower voltage sensing line (D, D_) (629 - 1, 629 - 2) to a greater degree than the other of the PMOS transistor (629 - 1, 629 - 2) be at the turning on one, thereby sensing line (D, D_) other than this high to be brought into conformal to a greater degree with a higher voltage than a high reduction with sensing line (D, D_) 2000. Similarly, the NMOS transistor having a higher voltage than a sense line (D, D_) (627 - 1, 627 - 2) to a greater degree than the other of the NMOS transistor (627 - 1, 627 - 2) be at the turning on one, thereby converting other sensing line (D, D_) (low) to be brought into conformal to a greater degree than with a lower voltage (low) to a sensing line (D, D_) into conformal substrate. As a result, after a short delay, the slightly larger voltage sensing line (D, D_) voltage (supply voltage (VDD) may be a) which leads to the PSA, the RNL_ other sensing line (D, D_) voltage (reference potential such as ground potential which may be) leads to the vehicle from the outside. Therefore, cross-coupled NMOS transistors (627 - 1, 627 - 2) and PMOS transistors (629 - 1, 629 - 2) comprises a sense amplifier pair acts as, this circuit senses (D and D_) differential voltages sensed from memory cells on the selected amplification factor viii. to latching data values. As used in the application, sensing amplifier (306) 1 latch includes at least one of cross-linking can be covalently latch difference. On the contrary, as described in association with said and also 4, calculated components (for example, 4 also shown in calculation component (431)) 2 difference can be covalently associated with the cross-coupled latch includes at least one latch. In the embodiment according to the disclosure are sense circuit 7a also has a plurality of the illustrated a schematic among others. Memory cell storage element (for example, capacitor) and access devices (e.g., transistor) having a predetermined wavelength. For example, transistor (702 - 1) and capacitor (703 - 1) the memory cells, transistor (702 - 2) and capacitor (703 - 2) memory cell etc.. In one embodiment, memory array (730) is 1T 1C (1 transistor 1 capacitor) DRAM array memory cells are disclosed. In a plurality of in the embodiment, memory cells are destructive read memory cells than the disclosed (for example, stored in the data reading the cell after refreshing to read the data stored original data positions by artillery). Memory array (730) cells comprise word lines are bound by a rows (704 a-X(Row X), such as 704 a-Y (Row Y)), and a complementary data lines (digit (n 1)/digit (n 1) _, digit (n)/digit (n) _, _ (n + 1)/(n + 1) digit digit) by a pair of into coupled columns are prevented. In addition each individual data lines are complementary data lines corresponding to a respective pair of the data lines (705 - 1 (D) and 705 - 2 (D_) can be vestibular. A pair of complementary data lines 3 are shown in the 7a but also only, so are not one number in the embodiment of the disclosure, an array of memory cells and/or data lines of memory cells (e.g., such as 4,096, 8,192, 16,384) comprising additional columns can be. Memory cells are coupled to different data lines and/or word lines can be. For example, transistor (702 - 1) number 1 of source/drain regions are data line ((D) 705 - 1) can be coupled to, transistor (702 - 1) number 2 of source/drain regions are capacitor (703 - 1) can be coupled to, transistor (702 - 1) the gate of the word line (704 a-X) can be coupled to. Transistor (702 - 2) data line of source/drain region is number 1 ((D_) 705 - 2) can be coupled to, transistor (702 - 2) number 2 of source/drain regions are capacitor (703 - 2) can be coupled to, transistor (702 - 2) the gate of the word line (704 a-Y) can be coupled to. Also as shown in 7a, cell plate from the capacitors (703 - 1 and 703 - 2) can be coupled to. A reference voltage (e.g., ground) cell plate in various memory array configurations which can be applied to be a common node. Memory array (730) is a plurality of in the embodiment according to the disclosure are sensing circuit (750) coupled to. In one embodiment, sensing circuit (750) columns corresponding to the memory cells (for example, coupled to a respective pair of complementary data lines a) sense amplifier (706) and calculating component (731) without using a tool. Sense amplifier (706) is cross-coupled latch can be, this difference can be latch vestibular 1 in the application. Sense amplifier (706) is, for example, as also described for 7b, can be configured. Also illustrated 7a in one example, calculating component (731) corresponding to static latch circuit (764) and other among, for implementing additional 10 comprising the dynamic latch transistor. Calculating component (731) all dynamic latch and/or the static latch the latch vestibular 2 can be difference in application, this can act as an accumulator. Thus, calculating component (731) and/or the accumulator in the accumulator acts as a application can be covalently. Calculating component (731) is also shown in 7a output data lines (D (705 - 1) and D_ (705 - 2)) can be coupled to. However, in the embodiment are not one number to this example. Calculating component (731) transistors may be e.g. an n - channel transistors (for example, NMOS transistors) both implementation being. In this example, the transistors data line (D (705 - 1)) (716 - 1 and 739 - 1) number 1 of source/drain regions, as well as rod/pass transistor (718 - 1) number 1 of source/drain regions can be. Data line (D_) (705 - 2) the transistors (716 - 2 and 739 - 2) number 1 of source/drain regions, as well as rod/pass transistor (718 - 2) number 1 of source/drain regions can be. Rod/pass transistor (718 - 1 and 718 - 2) the gates as discussed further hereinafter, generally LOAD number or may be coupled to a signal, or a signal can be coupled to each PASSD/PASSDB number. Rod/pass transistor (718 - 1) number 2 of source/drain regions are transistors (716 - 1 and 739 - 2) can be coupled directly to the gates. Rod/pass transistor (718 - 2) number 2 of source/drain regions are transistors (716 - 2 and 739 - 1) can be coupled directly to the gates. Transistor (716 - 1) pull down transistor source/drain region is of number 2 - (714 - 1) can be coupled directly to the source/drain region of number 1. Transistor (739 - 1) pull down transistor source/drain region is of number 2 - (707 - 1) can be coupled directly to the source/drain region of number 1. Transistor (716 - 2) pull down transistor source/drain region is of number 2 - (714 - 2) can be coupled directly to the source/drain region of number 1. Transistor (739 - 2) pull down transistor source/drain region is of number 2 - (707 - 2) can be coupled directly to the source/drain region of number 1. Pull - down transistors (707 - 1, 707 - 2, 714 - 1, and 714 - 2) each source/drain region is number 2 generally reference voltage (791 - 1) (for example, ground (GND)) can be joined together. Pull - down transistor (707 - 1) can be coupled to the gate of the data signal line AND number, pull - down transistor (714 - 1) the gate of the data signal line ANDinv number (713 - 1) can be coupled to, pull - down transistor (714 - 2) the gate of the data signal line ORinv number (713 - 2) can be coupled to, pull - down transistor (707 - 2) can be coupled to the gate of the data signal line OR number. Transistor (739 - 1) has its gate node (S1) can be vestibular, transistor (739 - 2) the gate of the node (S2) can be vestibular. 7a (S1 and S2) also shown in circuit nodes dynamically on accumulator data for sparse subtrees. Activating the signal LOAD number load - pass transistors (718 - 1 and 718 - 2) which operate, (S1 and S2) complementary data nodes by loading or other. A signal LOAD number total VDD S1/S2 level V for deliveringDD Voltage greater than can be increased. However, the V signal LOAD numberDD Is optional and greater than voltage increases, the function of the circuit shown in V also 7aDD A signal into the LOAD number increased voltage greater than a closing uninhabitable. Also shown in 7a calculation component (731) the configuration of the pull - down transistors (707 - 1, 707 - 2, 714 - 1, and 714 - 2) sense amplifier (706) before operation (e.g., sense amplifier (706) during pre-seeding -) sense amplifier has a gain balance when operating function. As used in the application, sense amplifier (706) the latch operating 1 difference in order to sense amplifier (706) over and then line 1 in order to maintain a set difference latch sense amplifier (706) exhibits non-disabled. Balanced after performing logical operations disable but (in sensing amplifier), sense amplifier before operation, sense amplifier latch the entire rail voltage (for example, VDD , GND) using "flip (flip)" since the gate can power the need. Transistors is reversed when performing a particular logical operations can be each data line pull - down. For example, transistor (714 - 1) (ANDinv number data signal line (713 - 1) coupled to the gated) in series with a transistor (716 - 1) (S2 of dynamic latch coupled to the gated) causes the line (705 - 1) (D) equation solver - down can be operable to, transistor (714 - 2) (ANDinv number data signal line (713 - 2) coupled to the gated) in series with a transistor (716 - 2) (S1 of dynamic latch coupled to the gated) causes the line (705 - 2) (D_) equation solver - down can be operable. Latch (764) on a high voltage and VDD Rather than activity by binding to continue to number portion configured for data signal line (712 - 1) (ACCUMB) and active and switching data signal line number (712 - 2) by binding to number (ACCUM) as soon as possible following the enabled disclosed. In various in the embodiment, rod/pass transistors (708 - 1 and 708 - 2) each may have a signal or a signal coupled to one LOAD number PASSD/PASSDB number data. According to some in the embodiment, rod/pass transistors (718 - 1 and 718 - 2) can be coupled to a signal gate are generally LOAD number. Rod/pass transistors (718 - 1 and 718 - 2) are generally LOAD number configuration including a signal coupled to gate, transistors (718 - 1 and 718 - 2) be a load transistors. Activating the signal LOAD number load transistors which operate, (S1 and S2) complementary data nodes by loading or other. A signal LOAD number total VDD S1/S2 level V for deliveringDD Voltage greater than can be increased. However, the signal V LOAD numberDD Voltage need not be increased and greater than selectively, the function of the circuit shown in V also 7aDD A signal into the LOAD number increased voltage greater than a closing uninhabitable. According to some in the embodiment, rod/pass transistor (718 - 1) can be coupled to the gate of the a signal PASSD number, rod/pass transistor (718 - 2) can be coupled to the gate of the a signal PASSDb number. Transistors (718 - 1 and 718 - 2) each coupled to one of the and gates PASSD PASSDb number configuration including, transistors (718 - 1 and 718 - 2) comprise can be transistors. Pass transistors hereinafter on the load transistors (for example, are used to a different voltage/current conditions and/or different time) can be operated. As such, the configuration of the pass transistors of compositional load transistor may differ. For example load transistors, (S1 and S2) that combine local dynamic nodes associated with data line consists of handle the loading. Pass transistors associated with data line adjacent in accumulator combine more loading handle the consists of (for example, as shown in also 7a, shift circuit (723) through). According to some in the embodiment, rod/pass transistors (718 - 1 and 718 - 2) corresponding to the pass transistor configured to receive more than loading but can be combined as load transistor which is operated. Pass transistors configured as load/pass transistors (718 - 1 and 718 - 2) can be used as the load transistor in addition. However, load/load transistors configured as pass transistors (718 - 1 and 718 - 2) is utilized as transistors comprise thereof can not possible. In a plurality of in the embodiment, latch (764) including, calculating component (731) with its are formed array (e.g., array shown in also 7a (730)) corresponding transistor memory cells have a plurality of transistors can be formed on pitch, this particular feature size (e.g., 4F2 , 6F2 Or the like) can be along. In the embodiment according to various, latch (764) comprises a load/pass transistors (718 - 1 and 718 - 2) through complementary data lines (D (705 - 1) and D_ (705 - 2)) 4 coupled to the pair of access transistors (708 - 1, 708 - 2, 709 - 1, and 709 - 2) comprises. However, in the embodiment are this number is not one. Latch (764) is be a cross-coupled latch (e.g., n - channel transistors (for example, NMOS transistors) (709 - 1 and 709 - 2) such as, include the first gates is p - channel transistors (for example, PMOS transistors) (708 - 1 and 708 - 2) such as, a pair of transistor gates of coupled to another crossing). The application as further described, cross-coupled latch (764) can be static latch is covalently. Each data lines on voltages or currents are cross-coupled latch (D and D_) (764) of each latch inputs (717 - 1 and 717 - 2) (for example, an input of the latch 2 difference) to 1308. ball number. In one embodiment, latch input (717 - 1) the transistors (708 - 2 and 709 - 2) gates as well as transistors (708 - 1 and 709 - 1) coupled to a source/drain region of number 1. Similarly, latch input (717 - 2) the transistors (708 - 1 and 709 - 1) gates as well as transistors (708 - 2 and 709 - 2) number 1 of source/drain regions can be. In this example, transistor (709 - 1 and 709 - 2) number 2 of source/drain regions are generally part number data signal line (712 - 1) (for example, 1 difference latch fig. 7b shown in (RnIF) similar to a ground (GND) a signal number ACCUMB number or a signal) coupled to. Transistors (708 - 1 and 708 - 2) number 2 of source/drain regions are generally positive number data signal line (712 - 2) (e.g., a signal number 1 difference latch shown in fig. 7b (ACT) similar to a VDD ACCUM number or a signal) coupled to. Positive number signals (712 - 2) variable resistors (for example, VDD ) Part number can be a number under public affairs signals (712 - 1) is cross-coupled latch (764) for enabling a reference voltage (e.g., ground) implementation being. According to some in the embodiment, transistors (708 - 1 and 708 - 2) number 2 of source/drain regions are generally supply voltage (e.g., VDD ) Coupled directly, transistor (709 - 1 and 709 - 2) number 2 of source/drain regions are generally latch (764) reference voltage (e.g., ground) continue to enable directly coupled. Enabled cross-coupled latch (764) includes a latch input (717 - 1) mechanical number activated a signal voltage (for example, VDD ) Or activated part number and the signal voltage (e.g., ground) driven, latch input (717 - 2) mechanical number activated a signal voltage (for example, VDD ) Or activated part number (e.g., ground) of the signal voltage driven another latch input (717 - 1) (for example, common node number 1) and latch input (717 - 2) (for example, common node number 2) amplifying differential voltages between operable to each other. Also as shown in 7a, sense amplifier (706) and calculating component (731) is shift circuit (723) through array (730) can be coupled to. In one embodiment, shift circuit (723) data lines each coupled to (705 - 1 (D) and (D_) 705 - 2) separation devices (for example, separation transistors (721 - 1 and 721 - 2)) alignment of the substrate. Separating transistors (721 - 1 and 721 - 2) is activated when, memory cells corresponding column (for example, complementary data lines (705 - 1 (D) and (D_) 705 - 2) corresponding pair) corresponding sense amplifier (706) and calculating component (731) are separated for coupling transistors (721 - 1 and 721 - 2) enables a number (for example, turn-on) a signal (722) coupled to (NORM). In the embodiment according to various, separation transistors (721 - 1 and 721 - 2) behaves in shift circuit (723) of "normal" bellows can be referred. Also illustrated 7a in one example, shift circuit (723) is for example, when inactive NORM, can be activated, complementary number signals (719) (SHIFT) separation devices (for example, separation transistors (721 - 3 and 721 - 4)) coupled to another (for example, number 2) comprise a pair. Separating transistors (721 - 3 and 721 - 4) are specific sense amplifier (706) and calculating component (731) different pair of complementary data lines (for example, separation transistors (721 - 1 and 721 - 2) specific sense amplifier (706) and calculating component (731) complementary data line pair of combining different pair of complementary data lines) or may be configured to be coupled to operation (e.g., a signal number (719) through), or another memory array specific sense amplifier (706) and calculating component (731) can be combining (and number 1 from the memory array specific sense amplifier (706) and calculating component (731) component-a higher). In the embodiment according to various, shift circuit (723) is for example, sense amplifier (706) of (in) can be arranged as a portion. 7a also shown in shift circuit (723) a particular pair of complementary data lines (705 - 1 (D) and (D_) 705 - 2) (e.g., digit (n) (n)_ and digit) specific sensing circuit (750) (for example, particular sense amplifier (706) and corresponding calculation component (731)) used for combining separate transistors (721 - 1 and 721 - 2) which separation transistors (721 - 3 and 721 - 4) particular direction adjacent pair of complementary data lines (for example, also shown in 7a right adjacent data lines (digit (n + 1) and (n + 1) digit _) specific sensing circuit (750) arranged but combining, the one in the embodiment are not so number of 99900 06763999. For example, shift circuit particular pair of complementary data lines (for example, digit (n) (n)_ and digit) specific sensing circuit used for combining separate transistors (721 - 1 and 721 - 2) and in another specific direction adjacent pair of complementary data lines (also shown in example 7a left adjacent data lines (digit (n 1) (n 1)_ and digit) specific to a sensing circuit arranged to be used for combining separate transistors (721 - 3 and 721 - 4) can be comprising. In the embodiment of the disclosure also 7a are shown in shift circuit (723) not one configuration of number. In a plurality of in the embodiment, also shown in 7a such as shift circuit (723) is for example, I/O line (for example, local I/O line (IO/IO_)) through sensing circuit (750) transmitting data out without performing computational functions such as sorter functions can be condition (e.g., sense amplifiers (706) and calculating components (731) with). Not shown but also 7a, local I/O line memory cells each column, corresponding sense amplifier (706) and/or calculated components (731) from external processing resource (e.g., host processor and/or other functional unit circuit) outside of the bran component number such as array data which can be enabled for a data column decode can be coupled to a first line. Column decode line is coupled to the column decoder (for example, column decoder) can be. However, the described application as, in a plurality of in the embodiment, in the embodiment according to the disclosure of data to be transmitted through such I/O line for performing logical operations do not need to be disclosed. In a plurality of in the embodiment, shift circuit (723) is for example, array data outside of the bran component number and then transferring it sorter function calculated for performing functions such as sense amplifiers (706) and calculating component (731) can be operating in conjunction with a. In the embodiment according to the disclosure also 7b are a portion of the sensing circuit is a plurality of the illustrated a schematic among others. In the embodiment according to various, sense amplifier (706) is can be cross-coupled latch. However, sense amplifier (706) in the embodiment are not one number of cross-coupled latch. For example, sense amplifier (706) includes a current - mode sense amplifier and/or single - ended sense amplifier (for example, one data line coupled to the sense amplifier) implementation being. In addition, the disclosure in the embodiment are not one number of folding data line architecture. In a plurality of in the embodiment, sense amplifier (e.g., 706) holds the corresponding calculated components (731) of transistors and/or are formed array of memory cells (e.g., 730 also shown in 7a) pitch having a plurality of transistors can be formed on, this particular feature size (e.g., 4F2 , 6F2 Or the like) can follow a disclosed. Sense amplifier (706) performs data reading data lines (D (705 - 1) and D_ (705 - 2)) of transistors coupled to the pair of latch 4 (715) without using a tool. Latch (715) is - be a cross coupled latch (e.g., n - channel transistors (for example, NMOS transistors) (727 - 1 and 727 - 2) such as, include the first gates are p - channel transistors (for example, PMOS transistors) (729 - 1 and 729 - 2) such as, another aspect of transistors coupled to a pair of gates crossing). The application as further described, transistors (727 - 1, 727 - 2, 729 - 1, 729 - 2 and) including latch (715) can be covalently latch difference is 1. However, in the embodiment are not one number to this example. Each data lines on voltages or currents are cross-coupled latch (D and D_) (715) of each latch inputs (733 - 1 and 733 - 2) (for example, an input of the latch 2 difference) to 1308. ball number. In one embodiment, latch input (733 - 1) the transistors (727 - 2 and 729 - 2) gates as well as transistors (727 - 1 and 729 - 1) coupled to a source/drain region of number 1. Similarly, latch input (733 - 2) the transistors (727 - 1 and 729 - 1) gates as well as transistors (727 - 2 and 729 - 2) number 1 of source/drain regions can be. Calculating component (733) (for example, accumulator) as shown includes a cross-coupled latch (715) latch inputs (733 - 1 and 733 - 2) coupled to but, in the embodiment shown in example 7b also are not one number. In this example, transistor (727 - 1 and 727 - 2) source/drain region is generally activity unit number number 2 of a signal (728) coupled to (RnIF). Transistors (729 - 1 and 729 - 2) number 2 of source/drain regions are generally active and switching a signal number (790) coupled to (ACT). ACT signal (790) variable resistors (for example, VDD ) And can have a reference voltage (e.g., ground) RnIF signal implementation being. Signals (728 and 790) to activate the cross-coupled latch (715) frequencies. Enabled cross-coupled latch (715) has a latch input (733 - 1) one RnIF ACT signal voltage and the signal voltage (for example, VDD And ground one) driven, latch input (733 - 2) RnIF ACT signal voltage and the signal voltage to another of the driven latch input (733 - 1) (for example, common node number 1) and latch input (733 - 2) (for example, common node number 2) amplifying differential voltages between operable to each other. Sense amplifier (706) is in addition comprises a circuit configured to data lines (D and D_) can be fixed (e.g., sensitive operation in the sense amplifier for preparing regarding). In this example, data line equilibration circuit (D) (705 - 1) and transistor (725 - 1) number 1 source/drain regions coupled to source/drain regions of transistor number 1 (724) without using a tool. Transistor (724) number 2 of source/drain regions are data line (D_) (705 - 2) and transistor (725 - 2) number 1 of source/drain regions can be. Transistor (724) the gate of the transistors (725 - 1 and 725 - 2) can be coupled to the gates. Transistors (725 - 1 and 725 - 2) number 2 of source drain regions balanced voltage (738) (for example, VDD /2) is coupled to, this VDD Such as/2 may be, the application in VDD Supply voltage associated with array are disclosed. Transistors (724, 725 - 1, and 725 - 2) number of gates is a signal (725) can be coupled to (EQ). In this way, leading to the activation of the transistors EQ (724, 725 - 1, and 725 - 2) wherein the enable, this allows lines (D and D_) is balanced voltage (VDD /2) balanced line data so that the data line (D) (D_) effectively short sleeve. In the embodiment according to the disclosure are various, carried out by a sense amplifier sensing a plurality of logical operator, result storing components (e.g., accumulator) can be calculated. Sensing circuit (750) is logic value are initially sense amplifier (706) stored number 1 mode, and logic value are initially calculated components (731) to stored number 2 mode, performing logical operations can be operated in several modes. Number 1 mode sensing circuit (750) 8a and 8b of operation is also described hereinafter and also to, number 2 mode sensing circuit (750) of operation is also described hereinafter with respect to the also 5cb 5a to in. Additionally number 1 on the mode of operation, sensing circuit (750) is is first sense amplifier (706) having stored logic value pre - sensing (e.g., active sensing amplifier are operated logic value before a signal number) and post - sensing (e.g., a signal activated after the sense amplifier are active logic value number) both can be operated. As described further hereinafter, sense amplifier (706) is, calculated components (731) with, using the data array as input from various logical operations can be operative to perform. In a plurality of in the embodiment, logic value without data transmission via a data line address access (e.g., local I/O line installed in circuit and array from outside the circuit data is transmitted without operating to column decode signal) can be re-array. As such, the disclosure in the embodiment are less than previous approaches a plurality of various logical operations and associated with it using the power handling instruction that specifies the be performing computation functions. Additionally, in the embodiment are calculated in order to perform a plurality of functions (for example, memory and between discrete processor) I/O lines for transmitting the request number data across a stand-alone, compared to previous approaches in the embodiment are a plurality of enabling parallel processing capability can be increased. Also 7a sensing circuit (750) performing the function of the logical operations and initially sense amplifier (706) storing in the table of 1 hereinafter described hereinafter with respect to result in abstract with each other. Initially sense amplifier (706) latch storing logic value 1 difference of specific example, components are initially calculated result (731) of 2 (for example, accumulator) present in the secondary latch, then then sense amplifier (706) that can be sent to a number under public affairs improved compared to previous approaches can be pluripotent. Table 1 Initially sense amplifier (706) storing the result of an operation is specified (for example, result calculated components (731) (for example, accumulator) from sense amplifier (706) without the need for moving incrementally by sending additional performs) for example, result is low (the array of memory cells) or without performing precharge cycle (for example, complementary data line (705 - 1 (D) and/or 705 - 2 (D_)) on) accumulators can be written again since WIPO. In the embodiment according to the disclosure are 8a also includes a plurality of sense circuit performing logical operations associated with multiple timing degree example as follows. Number 1 and number 2 for an operand AND disclosure a logic operation is also 8a operand associated with timing degree example as follows. In this example, the operand access line coupled to memory cell number 1 number 1 (for example, ROW X) stored in the operand access line coupled to memory cell number 2 number 2 (e.g., ROW Y) overnight. Examples particular column corresponding cells stored data indicative but performing AND, so number one in the embodiment are not. For example, entire rows are data values data values different rows and, simultaneously, can be AND. For example, array 2,048 power to two columns, can be 2,048 AND operation are performed simultaneously. AND perform a logic operation circuit (for example, 750) 8a is also sensed so that associated with operating a plurality of number signals over example as follows. ". ". "". "EQ" a sense amplifier (706) applied to correspond to equilibrium, "ROW X" is access line (704 a-X) corresponding to the applied activation signal, access line is "ROW Y" (704 a-Y) corresponding to the applied activation signal, "Act" and "RnIF" a sense amplifier (706) positive and part number applied to each activity to the low-speed signal, the load number "LOAD" signals (e.g., also shown in 7a LOAD/PASSD and LOAD/PASSDb) corresponds to, "AND" 7a AND number is also shown in a signal into the slide groove. In addition Row X and various data values for the data values is also 8a Row Y combination logic operation AND sense amplifier (706) (D and D_) corresponding to digit lines on and calculating component (731) (S1 and S2) (e.g., Accum) corresponding to nodes (e.g., voltage signals) signals in shown on waveform diagrams is exemplified substrate (for example, each data value combinations diagrams (00, 10, 01, 11) into the slide groove). A circuit associated with a particular timing is also waveforms are shown in pseudo code AND operation also 7a to hereinafter discussed in the other. Low (704 a-X) coupled to the data value stored in the accumulators associated with number 1 loading (e.g., radiation) can be abstract example of pseudo code as follows: A Row X accumulators copies: EQ deactivated Heat Row X Sensing amplifier are operating (Row X data is sensed to amplifier then present) LOAD activation (sense amplifier data (Row X) is (S1 and S2) at which the accumulator nodes sent to dynamically present) LOAD deactivated Row X close Precharge Said pseudo code, "EQ deactivated" is a sense amplifier (706) corresponding to the balanced signal (also shown in 8a EQ signal) is also 8a as shown in t1 The washing predefinition phenoxyethanol (for example, complementary data lines (e.g., 705 - 2 and 705 - 1 (D) (D_)) V longerDD Ofan circuited/2). After a disabled equilibrium, low (for example, ROW X) selected physician code "ROW X heat" also are indicated by 8a t for signal (Row X)2 As seen enabled (for example, a particular row selecting signal to select with it is bitter and and selected, open substrate). ROW X signal is selected cell voltage applied to the corresponding access transistor (e.g., 702 - 2) when it reaches the threshold voltage of (Vt), access transistors in differential voltage signal between data lines and turning on the selected cell (for example, capacitor (703 - 2) to) bind to a data line (e.g., 705 - 2 (D_)). After Row X is enabled, said pseudo code, "sensing amplifier are operating" in the sense amplifier (706) is enabled for setting latch 1 difference is then disable the washing phenoxyethanol. For example, in t 8a also3 As seen, a signal (for example, 7b also seen 790) is positive number ACT pulled high RnIF part number and as a signal (e.g., seen also 7b 728) is (low) to go to, this D_ 705 - 1 (D) and (705 - 2) in between differential signal of the, gate driver logic 1 (e.g., VDD ) Or data line (705 - 1) (D) logic 0 on driver (e.g., GND) (and a complementary data line (705 - 2) (D_) driver on the other logic state) tolerant. Sensed data value is sense amplifier (706) of latch 1 difference overnight. 1 difference energy consumption are balanced voltage (VDD /2) in rail voltage (VDD ) Data lines (e.g., 705 - 1 (D) or (D_) 705 - 2) occurs when filling. 4 8a also illustrated a two sets of possible sense amplifier and accumulator signals (e.g., one for each combination Row X and Row Y data values) on behavior of signals in data lines (D and D_) shown substrate. Row X data value is stored in latch 1 difference sensing amplifier. Row X is also 7a corresponding to, storage element (702 - 2) including memory cells coupled to the complementary data line (D_) while, Row Y corresponding to the storage element (702 - 1) including memory cell is coupled to a data line (D) are shown as follows. However, as also seen in 7a, "0" data values that correspond to the memory cell (702 - 2) (corresponding to row X) the charge stored on the data line (D_) (memory cell (702 - 2) combined) and pulled high voltage toward the "1" data on values that correspond to the memory cell (702 - 2) data line (D_) charge stored on voltage (low) and to a water baffle immersion seal, this allows States and coupled to data line (D), corresponding to Row Y, memory cell (702 - 2) between the charge stored on the corresponding opposite are disclosed. Different data lines coupled to memory cells each store charge differences when writing data values of memory cells they properly taken into account other. After sensing bit lines between the operating, said pseudo code, "LOAD activation" is in the signal is also 8a t LOAD number4 As seen go pulled high, rod/pass transistors (718 - 1 and 718 - 2) making it possible to operate at a display substrate. In this way, activating the signal LOAD number computational component (731) of accumulator 2 difference in frequencies latch. Sense amplifier (706) 2 difference sensed data value is stored in a latch transmission (for example, copy) with each other. 4 8a also illustrated a two sets of possible sense amplifier and accumulator signal each of the as shown, an input of the latch 2 is loaded into the latch 2 difference accumulator movements in Row X data value difference indicating other. As shown in fig. 8a, the dynamic latch latch 2 difference accumulator depending flip or previously stored data (e.g., Row X="0" and Row Y="0" to "1" and "0" and Row X=Row Y=reference signals for accumulator defect/deficiency), or flip not be (e.g., Row X="0" and Row Y="1" to "1" and "1" for reference defect/deficiency Row X=Row Y=accumulator signals). Sense amplifier stored (and data lines (705 - 1 (D) and (D_) 705 - 2) present on) 2 difference data values after setting latch, said pseudo code, "LOAD deactivated" comprises a load/pass transistors (718 - 1 and 718 - 2) complementary data lines which operate at a stop by separating the signal is also 8a t in order LOAD number from the dynamic latch5 As seen again (low) at the inside of the display substrate. However, data value is 2 difference are stored dynamically accumulator latch remains disclosed. 2 difference latch on after store data values, the selected row (e.g., ROW X) is indicated by "close ROW X" and 8a also in t6 As displayed is disabled (e.g., specific row selection signal and deactivating the selected number with it is bitter and, closed other), this combination selected cells from corresponding data line access transistor is turned on and off the number can be accomplished by a. Once the selected row closed the memory cells separated from the data lines, data lines are said pseudo code "precharge" as indicated by the pre-charge can be disclosed. T for precharging the data lines7 In EQ 8a also that as displayed on then go to a clock, can be accomplished by a balanced operation. t7 4 illustrated 8a also in a two sets of possible sense amplifier and accumulator signals as shown each, balanced operations include lines on each voltage V (D and D_)DD S./ 2 to be returned to. Equilibrium is, for example, memory cell sensing operation or logical operations (described hereinafter) can be generated before. Number 1 data value (the number calculated components (731) of 2 difference latch and sense amplifier (706) stored) data value and number 2 (Row Y (704 a-Y) coupled to memory cell (702 - 1) stored) for subsequent operation step for performing an operation associated with AND or OR AND or OR is performed depending on whether or perform certain steps comprising. The presence in accumulator a data value (e.g., Row X (704 a-X) coupled to memory cell (702 - 2) data value stored number 1) and number 2 data value (e.g., Row Y (704 a-Y) coupled to memory cell (702 - 1) data stored value) associated with a "AND the" and "OR the" pseudo code are abstract in examples hereinafter. Data values associated with exemplary pseudo code "AND the" can be involving: EQ deactivated Heat Row Y Sensing amplifier are operating (Row Y data is sensed to amplifier then present) Close Row Y In the next operation, the result of the logic operation, located on a sensing amplifier which, this activity will optional low piece. Row Y even when closed, sense amplifier comprising still Row Y data value. AND activation This sense amplifier is function value (for example, Row X AND Row Y) to record 2n. Accumulators "0" (i.e., node (S2) on "0" driver and node (S1) "1" on driver) power to, sense amplifier data "0" into the slot Accumulators "1" (i.e., node (S2) on "1" corresponding to "0" (S1) voltage and node on driver) contains the, sense amplifier data remain disclosed (Row Y data) may be identified. The operations are not be modified data in causes accumulator AND deactivated Precharge Said pseudo code, "EQ deactivated" is a sense amplifier (706) by asserting a signal corresponding to the washing is disabled the display (for example, complementary data lines longer V (705 - 1 (D) and (D_) 705 - 2)DD Ofan circuited/2), this t8 In 8a also illustrated substrate. After a disabled equilibrium, is low (e.g., ROW Y) selected to said pseudo code are indicated t "Row Y heat"9 As shown in 8a also enabled. ROW Y signal is selected cell voltage applied to the corresponding access transistor (e.g., 702 - 1) when it reaches the threshold voltage of (Vt), access transistors in differential voltage signal between data lines and turning on the selected cell (e.g., capacitor (703 - 1) bind to a data line (for example, D_ (705 - 1)). After Row Y is enabled, said pseudo code, "sensing amplifier are operating" in the sense amplifier (706) is 705 - 1 (D) and 705 - 2 is enabled for amplifying a differential signal between (D_), logic 1 driver (for example, VDD ) Or data line (705 - 1) (D) logic 0 on driver (e.g., GND) (for example, complementary data line (705 - 2) (D_) on the other logic state is voltage) that indicates that the other dimensions. T 8a also in10 As seen, a signal (for example, 790 as also seen 7b) positive number ACT is pulled high RnIF part number and as a signal (for example, as seen also 7b 728) is admitted to the furnace for operating a sense bit lines between the (low). Memory cell (702 - 1) from a sensed data value as previously described, sense amplifier (706) of latch 1 difference overnight. The dynamic latch latch 2 difference not changed still memory cell (702 - 2) from data value into the slide groove. Row Y coupled to memory cell (702 - 1) number 2 data value sensed from the sense amplifier (706) of 1 difference after storage latch, said pseudo code, "Row Y close" is the selected row (e.g., ROW Y) corresponding to the memory cells again AND Row Y it is required to ensure that the stored logic value if not disabled disclosed. However, the memory cells corresponding to the result of an operation is also 8a Row Y Row Y logic is re-enabled to remain negative shown substrate. Row Y memory cell corresponding to a separate data line (705 - 1) (D) selected from the cell (702 - 1) number in order to access transistor turned off can be achieved thereby. After a second or selected Row Y (for example, memory cell separates cells avoid separating or memory), said pseudo code "AND activation" is the signal is t AND number11 As seen also in 8a pulled high go, pass transistor (707 - 1) phenoxyethanol not the cooking operation. In this way, leading to the activation of a signal AND number (for example, Row X AND Row Y) written sensed amplifier causes the function value. Accumulator (731) of the dynamic latch stored number 1 data values (e.g., Row X) and sense amplifier (706) having stored data values (e.g., Row Y) number 2, calculating component (731) of the dynamic latch is "0" (i.e., node (S2) on "0" driver and node (S1) "1" on driver) power to, sense amplifier data node (S1) on "1" corresponding to the DC voltage (709 - 1) and in operation causes the submitted (709 - 1), pass transistor (707 - 1) and data lines (705 - 1) through (D) to ground sense amplifier (706) the protrusion of a "0" signal received by an antenna (sensing amplifier regardless of previously stored data value). AND when "0" data value of an operation, the result is "0". In the application, when "0" is number 2 (dynamic latches) data value, the data value "0" and regardless of the result of an operation state of number 1 AND, "0" is written when the result of the configuration of the sensing circuit initially sense amplifier (706) causes stored. This operation is not be modified data value in accumulator causes (for example, from Row X). Power to "1" (for example, from Row X) 2 difference accumulator latch, the result of an operation AND sense amplifier (706) depending substrate (for example, from Row Y) data stored. The result of an operation AND sense amplifier (706) is "1" stored data value "1" (for example, from Row Y) back then but in addition, sense amplifier (706) is "0" (for example, from Row Y) in addition data stored value "0" then the back AND should the result of an operation. Sensing circuit (750) is "1" the dynamic latch accumulator (i.e., node (S2) on "1" corresponding to "0" (S1) voltage and node on driver) power to, transistor (709 - 1) and not operate, does not sense amplifier is coupled to ground (as described said), sense amplifier (706) remains unchanged data stored previously recorded value is changed (for example, AND the operation results are Row Y data value "1" back "1" and AND the operation results are "0" data value "0" is Row Y back to Row Y data value) consists of to. This operation is not be modified data value in accumulator causes (for example, from Row X). The result of an operation AND are initially sense amplifier (706) after stored, said pseudo code "AND deactivated" is in the signal is also 8a t AND number12 As seen to had a (low), pass transistor (707 - 1) sense amplifier from ground (706) (and data line (705 - 1) (D)) operative for separating a main body and easily stopped beating bar. Previously not be carried out but, can be Row Y is closed (8a also in t13 As shown) sense amplifier disabled disclosed (positive number (low) to the clock signal is phase and as part number ACT RnIF 8a also that in t to go to14 As shown in). Data separating line have, said pseudo code "precharge" is as previously described (e.g., 8a also seen t14 Starts at the), balanced by the operation of a data line precharge specific relationship disclosed. 8a also includes alternative, sense amplifier (e.g., also shown in 7a 706) coupled to data lines (for example, shown in (D) (D_) 705 - 2 and also 7a 705 - 1) voltage signals on possible combination of behavior and operands (for example, data values Row X/Row Y (00, 10, 01, and 11)) for each of the logical operation result AND computation component (for example, also shown in 7a 731) (S1 and S1) of 2 difference latch nodes on behavior of voltage signals shown substrate. Said pseudo code number 2 described and illustrated 8a also timing mobilities operand to load sensing amplifier (e.g., Row Y data value) indicating that the logic operation after starting AND disclosure but, 7a also shown in circuit number 2 operands (for example, Row Y data value) before starting to load the logic operation by sensing amplifier AND disclosure can be successfully operated. In the embodiment according to the disclosure are 8b also includes a plurality of sense circuit performing logical operations associated with multiple timing degree example as follows. 8b also includes a sensing amplifier operand number 2 (e.g., Row Y data value) to load the logic operation after starting OR disclosure associated with timing degree example as follows. Number 1 and number 2 is also 8b operand data values for various combinations of memory accumulator signals example as follows. Specific timing is also signals are shown in pseudo code associated with a logic operation circuit AND 7a also hereinafter discussed in the other. Subsequent operation step alternatively number 1 data value (the number sense amplifier (706) and calculating component (731) of latch 2 difference stored) data value and number 2 (Row Y (704 a-Y) coupled to memory cell (702 - 1) stored) OR for performing calculation operations can be associated with. Also shown in 8a times (t1 T to7 ) Row X data to previously described for loading operations are repeated to sense amplifier and accumulators 8b also does not. "ORing" data values associated with exemplary pseudo code can be involving: EQ deactivated Heat Row Y Sensing amplifier are operating (Row Y data sensing amplifier to then present) Close Row Y When Row Y is closed, sense amplifier comprising still Row Y data value. OR activation This sense amplifier is function value (for example, Row X OR Row Y) which cause the record, this sense amplifier as follows from previously stored Row Y data value can be written: Accumulators "0" (i.e., node (S2) on "0" driver and node (S1) "1" on driver) power to, sense amplifier data remain disclosed (Row Y data) may be identified. Accumulators "1" (i.e., node (S2) on "1" corresponding to "0" (S1) voltage and node on driver) power to, sense amplifier data "1" is recorded in the This operation is accumulator data in unmodified causes. OR deactivated Precharge Said shown in pseudo code, "EQ deactivated" (8b also in t8 Shown), "Row Y heat" (8b also in t9 Shown), "sensing amplifier are operating" (8b also in t10 Shown), and "close Row Y" (8b also in t13 Is shown, this signal can occur before the disclosure to a particular logic function number) is pseudo code AND operation are the same as previously described functions on the basis of substrate. Of the selected Row Y consists of appropriately (for example, calculation is Row Y corresponding to the memory cells storing if enable or calculation is Row Y corresponding to the memory cell to the word line for separating unless closed substrate), said pseudo code in the signal is also 8b t OR number is "activated OR"11 As shown in high at the inside of the display, this pass transistor (707 - 2) causes operation of the device. In this way, leading to the activation of a signal OR number (for example, Row X OR Row Y) written sensed amplifier causes the function value. Calculating component (731) latch data value stored number 1 of 2 difference (e.g., Row X) and sense amplifier (706) having stored data values (e.g., Row Y) number 2, dynamic latch is "0" accumulator (i.e., node (S2) on "0" driver and node (S1) "1" on driver) power to, the result of an operation OR sense amplifier (706) depending substrate (for example, from Row Y) data stored. The result of an operation OR sense amplifier (706) is "1" (for example, from Row Y) data stored value "1" but then back, the result of an operation OR sense amplifier (706) is "0" (for example, from Row Y) in addition data stored value should then back "0". Sensing circuit (750) is "0" power to the dynamic latch accumulator, node (S2) "0" corresponding to the on voltage is, sense amplifier (706) coupled to ground (with either side) to transistor (709 - 2) is in an off state and not operate (AND number and the signal is asserted does not pass transistor (707 - 1) is off in addition to) being, sense amplifier (706) may be identified previously stored data values are then remain disclosed (for example, Row Y data value "1" back OR and the operation results are "1" and Row Y data value "0" to "0" and the operation results are back OR is Row Y data value). Dynamic latch is "1" accumulator (i.e., node (S2) on "1" corresponding to "0" (S1) voltage and node on driver) power to, transistor (709 - 2) is the operating frequency (OR number the signal is asserted so that pass transistor (707 - 2) as is allowed), data line (705 - 2) coupled to a sense amplifier (D_) (706) on "1" corresponding to the DC voltage input node (S2) (709 - 2) causes the pass transistor (707 - 2) operating in conjunction with and as such (in addition OR number so that the asserted signal and operate) coupled to ground. In this way, "1" initially includes the previously stored data value "1" latch 2 difference sensing amplifier comprising the result of an operation when OR accumulator regardless as sense amplifier (706) overnight. This operation is accumulator data in unmodified causes. 8b is also, alternatively, sense amplifier (e.g., also shown in 7a 706) coupled to data lines (for example, shown in (D) (D_) 705 - 2 and also 7a 705 - 1) voltage signals on possible combination of behavior and operands (for example, data values Row X/Row Y (00, 10, 01, and 11)) for each of the logical operation result in the OR calculation component (731) (S1 and S2) of 2 difference latch nodes on behavior of voltage signals are shown as follows. The result of an operation OR are initially sense amplifier (706) after stored, said pseudo code "OR deactivated" is in the signal is also 8b t OR number12 As shown in the (low) had a, pass transistor (707 - 2) from ground allows sense amplifier (706) (and data line (D) (705 - 2)) at the other side is stopped not to decouple a phenoxyethanol. Not be carried out prior to each item, can be Row Y is closed (also in t 8b13 As shown), sense amplifier disabled disclosed (positive number (low) to the clock signal is phase and as part number ACT RnIF 8b also that in t to go to14 As shown in). Data separating line have, said pseudo code is in "precharge" previously described and also 8b t14 As shown, balanced operation is effected by the predetermined data lines may cause disclosed. Also illustrated 7a sensing circuit (750) additional flexibility can be under public affairs number logic value is as follows. Said AND and OR operation signals of operation described in the previous word replacing ANDinv number AND number, and/or signals of operation by replacing the OR number ORinv number computing, logic operations are {- Row X AND Row Y} in {Row X AND Row Y} can be changed (the application "- Row X" in Row X data value is opposite, for example NOT Row X phenoxyethanol), {- Row X OR Row Y} in {Row X OR Row Y} can be changed. For example, AND during calculation operations result in the inverted data values, the signal is the inverted data values can be asserted instead of ANDinv number AND number accompanying OR during calculation operations, the signal is asserted 1308. ORinv number OR number instead. A signal activating an ORinv number allows transistor (714 - 1) a signal for activating the cooking operation ANDinv number which allows transistor (714 - 2) causes operation of the device. In each case, the appropriate sense amplifier wherein the asserted signal inverted number permits the sense amplifier flip (706) and when the result is related to using data values stored inverted Row X and seal number Row Y AND operation of inverted Row X and seal number Row Y using data values or of being OR operation causes. One of the data value repair version number of threads for example, first and second data value to be inverted is the one data value not by loading, for performing a logic operation (for example, AND, OR) can be used in the accumulator. Said AND and OR described against similar sample in the left at an angle of said data values in one approach is described, the dynamic latch accumulator non - inverted data value shown in sensing circuit also 7a into the sense amplifier (706) to effect a reversal of said data in data value by NOT (e.g., inverter) can be performed. As removes, activate a signal ORinv number allows transistor (714 - 1) activate the cooking operation and a signal ANDinv number allows transistor (714 - 2) causes operation of the device. ORinv ANDinv number and/or the signals, as further described hereinafter, are used when implementing NOT function: A Row X accumulators copy EQ deactivated Heat Row X Sensing amplifier are operating (Row X data is sensed by amplifier then present) LOAD activation ((S1 and S2) is transmitted to the sense amplifier data (Row X) accumulator nodes dynamically which the present LOAD deactivated ANDinv and ORinv activation (data line data value on the output interface key generator) This sense amplifier in the inverted data value (e.g., sense amplifier latch are flip-encoded) tolerant The operations are not in data is causes accumulator ANDinv and ORinv deactivated Row X close Precharge Said pseudo code seen "EQ deactivated", "Row X heat", "sensing amplifier are operating", "LOAD activation", and "LOAD deactivated" is pseudo code AND calculation and OR operation described previously said initial operation step to the same pseudo code "Row X accumulators a copy" operation accorded equal functions on the basis of substrate. However, Row X data sense amplifier (706) is copied into the pre-charge and embraces description below compared to Row X after loading the dynamic latch, dynamic latch accumulator in data value located on the data line repair version enables the shift transistors (e.g., ANDinv and ORinv) (for example, transistor and) and by disabling sense amplifier (706) can be sent. This sense amplifier (706) is stored in a thread number stored data value from previous sense amplifier sensing amplifier maintenance data value (for example, an inverted data value) 2n. to flip over and over again. I.e., number of threads in data value accumulator activate and deactivating ORinv ANDinv version of the repair and can be sent to the sense amplifier. This operation is accumulator data in unmodified causes. 7a also shown in sensing circuit (750) are initially sense amplifier (706) to (e.g., sense amplifier nodes on) AND, OR, and judges the NOT logic operations result, these calculation are any enabled low, logic operation after completing the activated any rows, and/or calculated components (731) can be easily and quickly transmit latch difference of 2. Sense amplifier (706) and AND, OR, and/or NOT logic against ordering is in addition sense amplifier (706) before operation AND, OR, ANDinv, and/or the appropriate actuation signals ORinv number (and certain number having a signal gate coupled to corresponding the substrate) can be interchanged by. In this way when performing logical operations, sense amplifier (706) a sense amplifier are (706) adders function sense amplifier (706) is copied into the whole rail voltage (e.g., supply voltage or ground/reference voltage) are not used because the total current for reducing the dynamic latch having at least one free - 1308. accumulator data from seeding. Pre - seeded sense amplifier (706) with a sequence of operations for one data line to provide a reference voltage or (V complementary data lineDD Or using the sleep/2), or complementary data lines causes unmodified. Sense amplifier (706) is a sense amplifier (706) when each data line is wholly rails attract each other into substrate. Operations such sequence will low to data piece is enabled. Two techniques (ISO) of the existing method DRAM SHIFT operation is separating out complementary data line pair ("muxing (muxing)") can be otherwise achieved. In the embodiment according to the disclosure of, shift circuit (723) on different pair of complementary data lines in response to a driving circuit (750) (e.g., sense amplifier (706)) (e.g., left or right adjacent pair of complementary data lines corresponding to the sense amplifier (706) such as) a pair of complementary data lines coupled to memory cells in a particular stored data values can be used for shifting. As used in the application, sense amplifier (706) the separated transistors (721 - 1 and 721 - 2) when the sense amplifier is coupled to the pair of complementary data lines operate the slide groove. SHIFT operations (left or right) is pre - Row X accumulators does not copy data value. A right shift therebetween abstract Row X for operations are as follows: Norm (norm) deactivating and Shift activated (shift) EQ deactivated Heat Row X Sensing amplifier are operating (sense amplifier are then shifted Row X data applying) Norm Shift deactivated activation and Row X close Precharge Said pseudo code, is the signal (low) to "Norm deactivating and Shift activation" NORM number had a shift circuit (723) of discrete transistors (721 - 1 and 721 - 2) is not operating and other (e.g., complementary data lines separating corresponding sense amplifier from a pair) phenoxyethanol. The signal is pulled high SHIFT number go separating transistors (721 - 3 and 721 - 4) while operating, thereby sense amplifier (706) bind to an arm adjacent pair of complementary data lines (e.g., left adjacent pair of complementary data lines separating transistors non - operation (721 - 1 and 721 - 2) provided between the memory array of). Shift circuit (723) after does not, said pseudo code shown in "EQ deactivated", "Row X heat", and "sensing amplifier are operating" pseudo code previously described the AND OR operation and its said initial operation step to the same pseudo code "Row X accumulators a copy" operation accorded equal functions on the basis of substrate. After these operations, left adjacent pair of complementary data lines coupled to the memory cell sense amplifier is the right shift Row X data value (706) overnight. Said pseudo code, the signal is pulled high "activation and Norm Shift deactivated" is NORM number go shift circuit (723) of discrete transistors (721 - 1 and 721 - 2) which operate (e.g., sense amplifier corresponding to the pair of complementary data lines bind to), SHIFT number (low) to the signal had a separation transistors (721 - 3 and 721 - 4) not operate the left adjacent pair of complementary data lines from the sense amplifier (706) separation (e.g., left adjacent pair of complementary data lines separating transistors non - operation (721 - 1 and 721 - 2) provided between the memory array of) display substrate. The Row X is still active, the right shifted Row X data value is separated transistors (721 - 1 and 721 - 2) corresponding to pairs of complementary data lines through Row X transmitted. Row X pairs of complementary data lines corresponding data values shifted right after, the selected row (e.g., ROW X) is represented by the pseudo code is disabled as said "close Row X", this combination number selected cells from corresponding data line access terminal in response can be achieved thereby. The selected row and closed memory cell separated from the data lines, data lines are said pseudo code "precharge" as indicated by the pre-charge can be disclosed. The data lines for precharging said as described, can be accomplished by a balanced operation. Shift arm Row X can be abstract computation are as follows: Norm Shift deactivated activation and EQ deactivated Heat Row X Sensing amplifier are operating (Row X data is sensed by amplifier then present) Norm deactivating and Shift activation Sense amplifier data (left shifted Row X) Row X is sent by Row X close Precharge Said pseudo code, the signal is pulled high "activation and Norm Shift deactivated" is NORM number go shift circuit (723) of discrete transistors (721 - 1 and 721 - 2) while operating, SHIFT number (low) to the signal had a separation transistors (721 - 3 and 721 - 4) is not operating signals to the display substrate. The arrangement is such pairs of complementary data lines corresponding sense amplifier (706) which will bind to the complementary data line sense amplifier from a right adjacent pair of isolated each other. After a second or shift circuit, said pseudo code seen "EQ deactivated", "Row X heat", and "sensing amplifier are operating" pseudo code previously described the AND OR operation and its said initial operation step to the same pseudo code "Row X accumulators a copy" operation accorded equal functions on the basis of substrate. After these operations, sensing circuit (750) corresponding to a pair of complementary data lines coupled to the memory cell sense amplifier Row X data value (706) overnight. Said pseudo code, the signal (low) to "Norm deactivating and Shift activation" is NORM number had a shift circuit (723) of discrete transistors (721 - 1 and 721 - 2) which is not operating (e.g., pairs of complementary data lines corresponding sense amplifier from separating), the signal is pulled high SHIFT number go separating transistors (721 - 3 and 721 - 4) external power left adjacent pair of complementary data lines that sense amplifier coupled (e.g., left adjacent pair of complementary data lines separating transistors non - operation (721 - 1 and 721 - 2) provided between the memory array of) display substrate. The Row X is still active, left shifted Row X data value is left adjacent pair of complementary data lines to Row X transmitted. Row X data values left adjacent pair of complementary data lines after shifted left, the selected row (e.g., ROW X) is indicated by "close Row X" is disabled as, this combination number selected cells from corresponding data line access terminal in response can be achieved thereby. Once the selected row closed the memory cells separated from the data lines, data lines are said pseudo code "precharge" as represented by the pre-charge can be disclosed. The data lines for precharging said as described, can be accomplished by a balanced operation. Figure 9 shows a plurality of disclosure in the embodiment according to invention are selectable with the illustrated schematic logic value selection logic configured to sense circuit are disclosed. Figure 9 shows a pair of complementary sense lines also (905 - 1 and 905 - 2) coupled to a sense amplifier (906), and pass gates (907 - 1 and 907 - 2) through sense amplifier (906) calculation component coupled to (931) when a is etched. Pass gates (907 - 1 and 907 - 2) by the number of gates is selection logic signal (PASS) logic operation can be, this logic operation selection logic (913 - 5) can be outputted from. Figure 9 shows a also calculates a component (931) data value "A" data value stored in the sensing amplifier (906) auditory canal 10 data stored value shown on the example logic tables indicating the data value for calculated labeled "A" "B" component (931) and "B" to labeled sense amplifier (906) when a is etched. 9 also illustrated sensing circuit (950) is logic value selection logic (913 - 5) comprises. In this example, logic (913 - 5) a logic operation by the selection logic signal (PASS *) number it became [e[e] swab gates (942) comprises. The logic operation number logic (913 - 5) is in addition 4 logical selection transistor comprising the: swab transistors (942) number of gates and the TF signal line coupled between the logic selection transistor (962), pass gates (907 - 1 and 907 - 2) the number of gates and TT signal line coupled between the logic selection transistor (952), pass gates (907 - 1 and 907 - 2) the number of gates and FT signal line coupled between the logic selection transistor (954), and swab transistors (942) number of gates and the FF signal line coupled between the logic selection transistor (964). Logic selection transistors (962 and 952) of gates is separation transistor (950 - 1) (ISO number signal is coupled to a gate) coupled to the sensing line number (e.g., 905 - 1) through chamber, logic selection transistors (954 and 964) of gates is separation transistor (950 - 2) (in addition ISO number signal is coupled to a gated) coupled to complementary sensing line through (e.g., 905 - 2). Logic selection transistors (952 and 954) as also shown in the 7a, each transistor (707 - 1) (AND signal is coupled to a number) and transistor (707 - 2) (OR signal is coupled to a number) similarly are prevented. Logic selection transistors (952 and 954) on each operation of the ISO signal is asserted when data values and based on the status of selected signals FT TT complementary sensing lines and similar disclosed. Logic selection transistors (962 and 964) in addition the swab transistors (942) for continuity of the number and operate in a similar manner. I.e., swab transistors (942) (for example, turn-on) for a OPEN, TF number "1" in chamber number sensing memory device having the signal is activated or data value (e.g., high), or FF number "1" in the signal is complementary sensing memory device activating the substrate (e.g., high) data value. Corresponding sensing line (for example, specific logic selection gate of transistor is coupled sensing line) the or each data value if it is not a number on a clock, swab transistors (942) provides certain logic selection transistors will not be OPEN are disclosed. A signal that is complementary to a signal must be PASS number PASS * number are not disclosed. For example, PASS and both signals are simultaneously activated or deactivated or both PASS * number is more than. However, the activation of both signals simultaneously PASS PASS * number and a pair of short complementary sensing line read together, this can be avoided destruction configuration. 9 also illustrated a logic value transistor logic table also results illustrated 10 are abstract. Figure 10 shows a plurality of disclosure in the embodiment 9 according to the invention also implemented by a selection logic operation results it became at the time of sensing circuit to exemplify the logic table are disclosed. With particular data value present on the complementary sensing lines, of logic selection number 4 the signals (e.g., TF, TT, FT, and FF) in the sense amplifier (906) and calculating component (931) start data values stored in a logic operation involving selecting one of a plurality of implement can be used. With particular data value present on the complementary sensing lines, the number of 4 signals pass gates (907 - 1 and 907 - 2) and swab transistors (942) wherein the continuity of the number, this results in operating after/before calculating component (931) and/or sense amplifier (906) in data value affects the other. Swab transistors (942) for continuity of the selectably number among other things is also reverse data values (e.g., inverse operands and/or its inverse result) to implement logical operations result in the nephrophathy. Logic table is shown in column (A) 1044 also illustrated 10 calculation component (931) stored start data value, and a sense amplifier shown in column (B) 1045 (906) a start data value stored shown substrate. Another top column number 3 of Figure 10 logic table of necks (NOT OPEN, OPEN TRUE, and OPEN INVERT) comprise gates (907 - 1 and 907 - 2), and swab transistors (942) exhibits continuity of, this complementary circuit senses the signal is asserted when each ISO number (905 - 1 and 905 - 2) with the value of the particular data present on a pair of, 4 logical selection number depends on the state of the signals (e.g., TF, TT, FT, and FF) to OPEN or CLOSED to the number can be disclosed. ". ". "". "Not Open" column includes both the non - operating condition, pass gates (907 - 1 and 907 - 2) and swab transistors (942) corresponds to, "Open True" is the operating conditions of the pass gates (907 - 1 and 907 - 2) corresponds to, "Open Invert" is the operating conditions of the swab transistors (942) into the slide groove. Both operating conditions the pass gates (907 - 1 and 907 - 2) and swab transistors (942) a filter selected has a control sensing line together with the center of the reflected not cause logic table of Figure 10. Pass gates (907 - 1 and 907 - 2) and swab transistors (942) [e[e] through selective of the continuity of the number, of the upper portion of Figure 10 logic table number 1 3 of each of the set of two rows of columns, as indicated by various linking paths are shown in the 1075, 9 corresponding to two different logic operation, 3 × 3=9 different result set number 1 number 2 number under public affairs combinations for each of the set of two rows of column 3 of below can be combined with. Sensing circuit (950) 9 which can be implemented by two different selectable logic operations are illustrated 10 also abstract logic table are disclosed. The lower portion of the table 10 also illustrated logic state of a signal including number of the columns may have logic selection number neck (1080) are shown as follows. For example, signals of state number 1 logic selection number row (1076) and ball in number, number 2 logic selection number signals of low state (1077) and ball in number, number 3 logic selection number signals of low state (1078) is ball number in, signals of state number 4 logic selection number row (1079) encoded in ball number. Specific result corresponding to the low logic value (1047) in abstract with each other. Thus, as shown in fig. 10 also 9 shown in sensing circuit for performing various logical operations can be used. For example, sensing circuit (950) according to the disclosure in the embodiment includes a plurality of data in a removable memory pattern comparing regarding a variety of logical operations (e.g., AND and OR logic operations) can be operative to perform. In the embodiment exemplified and described but are the application specific, skilled in the art of which is calculated to achieve the results shown in the embodiment can be replaced specific alignment will understand. The disclosure is intended to cover the one or more adaptation or variations in the prior art disclosure in the embodiment are disclosed. Said description is but other than a number, will be appreciated that exemplary manner are disclosed. Combination of said in the embodiment, and the description in the embodiment are not described specifically in said other application regarding the user when it is apparent that skilled in the art will. The disclosure range used in the embodiment of one or more other applications comprising the structures and method. Therefore, the disclosure in the embodiment with one or more ranges of such claim with full range of entitlements are equivalent, determined reference should appended claim. In the aforementioned description, several features for simplifying disclosure a single groups together in the embodiment. The disclosure of these method in the embodiment of the disclosure the disclosure the respective claim unambiguously listed using less includes a number of features intended will not reflect that the interpreted are disclosed. Rather, as the following claim are reflecting, in the embodiment of the present invention disclosure has all the characteristics of the main number less than single of 2000. The, following description and claim are integrated into, each claim in the embodiment separate itself as established substrate. The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line. In method, input/output (I/O) line array for transmitting data from a plurality of data (parity value) determined without preliminary parity value through said array of memory cells each coupled to a plurality of data values stored sensing steps of protecting; and said sensing coupled to a parity value including said another memory cell storing, method. According to Claim 1, said plurality of data values protection step, using sensing circuit, said parity value in order to determine said number of said plurality of data values stored memory cells each exclusive OR (XOR) operations including performing, method. According to Claim 2, said array I/O line for transmitting data from a sensing line address access without performing said XOR operations without performing including performing said XOR operations, method. According to Claim 1, said updated data recorded a predetermined memory cell of the plurality of memory cells in response to the parity value or said further including, method. According to Claim 4, parity value or said step, said parity value from crystals, said stand including a data value stored in said specific number, method. According to Claim 5, said parity value from crystals, said specific number stored in the data value includes a stand-alone: said sensing a data value stored in said specific memory; to obtain said updated parity value stored in said data value and said specific memory parity values performing XOR operation; and said another memory cell including storing said updated parity value, method. According to Claim 6, said updated data in response to said recorded a predetermined memory cell, newly updated parity value to obtain said updated data and said updated parity values performs XOR; and said newly updated parity value by said another memory cell, said influence of said updated parity (effect) it is to include a further including, method. As described in claim either claim 1 to claim 7, said calculating positions of each completed transaction (compute transaction) until said calculated number of memory cells to thereby delay records including, method. As described in claim either claim 1 to claim 7, including a particular number of memory cells each said determined error recover data stored in the further including, method. According to Claim 9, recover data stored in said specific memory includes said parity value and said stored data values to a particular memory on the outside which it will count each number of said memory cells further including additional XOR model, method. According to Claim 10, recover data stored in said specific memory includes storing said result from said predetermined memory cell further including additional XOR operations, method. According to Claim 9, recover data stored in said specific memory calculated positions of said error detection step and before said calculating further including recovering the data transaction to restart said, method. According to Claim 2 or Claim 3, model number 1 of the plurality of memory cells includes XOR said access line coupled to memory modules stored in the memory cell of the plurality of memory cells coupled to the access line number 2 data value and said number 1 XOR operation including performing data stored values, method. According to Claim 13, the result of an operation of the plurality of memory cells includes said number 1 XOR XOR model number 3 and said access line coupled to memory cell number 2 XOR operation including performing data stored values, method. According to Claim 14, coupled to a subsequent data with previously stored in the XOR operation subsequent subsequent access from subsequent corresponding XOR operations on the result previously performing including, method. In device, a plurality of sensing lines as an array of memory cells, each containing the corresponding sensing circuit coupled to a plurality of memory cells coupled to the having therein, each of the plurality of memory cells each coupled to one of said number of access lines, said including an array of memory cells, and said sensing circuit includes:
According to sensing line on sensing line basis (basis), input/output (I/O) line and then transferring it data from said array, each of the plurality of sensing lines said stored parity data corresponding to the memory cells to determine said specific sensing said plurality of memory cells coupled to a plurality of exclusive OR (XOR) data stored values and model; and
Said each sense line coupled to an additional memory cells operable to store said determined parity values a, device. According to Claim 16, said device includes a plurality of XOR operations for performing said number number signals over said sensing circuit configured to under public affairs number including anxiety, device. According to Claim 17, said each of the plurality of sensing lines corresponding to each of the circuits and components and calculated sensing said sense amplifier, said sense amplifier and said corresponding each of the plurality of sense lines in addition said calculating component coupled to corresponding complementary sensing line having corresponding (complementary sense line), device. According to Claim 16, said each sense line coupled to said additional memory cells are coupled to the same access line, device. As described in claim either claim 16 to claim 19, said sensing circuit includes:
Number 1 AND performs said data values;
Said data values perform inverter operation (invert operation);
Said data values and OR operation; and
Performing an operation on the result from said number 1 AND operation from results and said OR operation number 2 AND enabled to, device. In device, sensing line coupled to a plurality of memory cells each storing data array; said sensing coupled to a sensing circuit as:
Number 1 stored in the data value and said sensing circuit corresponding to said plurality of memory cells enables decode line number 1 results without dimensions in the number 2 memory cell performs XOR data stored values; and
Said number 1 result value and said decode line number 2 dimensions in the memory cell of the plurality of memory cells results without enabling said number 3 operable to XOR operation data stored values, said sense circuit including, device. According to Claim 21, said sensing circuit enables said decode line without previous XOR operations result from values and said plurality of memory cells a plurality of subsequent values of data stored in the remaining memory cells operable to model XOR, device. According to Claim 21, each said sensing circuit sensing said XOR operation performed on said each of the plurality of memory cells coupled to a repeated until being operable to perform XOR operations; and said XOR operations from said stored data values corresponding to said plurality of memory cells output value is XOR parity value, device. As described in claim either claim 21 to claim 23, said device includes a plurality of memory cells when error is detected said stored data values configured to amplify said rollback (rollback) number including anxiety, device. In device, sensing line coupled to a plurality of memory cells each storing data in a memory cell of the array; and a sensing circuit coupled to an array of said:
Each of said plurality of memory cell decode signal without activating said stored data as XOR operation, said XOR operation is:
Said sensing coupled to a memory cell number 1 number 2 memory cell and performing NAND operation data stored values;
Performing said data values OR operation; and
Said NAND operation on the result of the result of an operation and said OR AND performing operations including, for performing said XOR operation;
The result of an operation based on said data corresponding to said AND determining parity value; and
Said sensing line coupled to said additional memory cell operable to store a value determined parity number 1, sense circuit including said, device. According to Claim 25, said number 1 memory cell and said number 2 said data values stored in said NAND operation is carried out with respect to: said number 1 said sensing said components coupled to a data value stored in the calculated loading; and said number 2 access line and pass transistor (pass transistor) memory cells are disposed is coupled to line number including an address pin, device. According to Claim 25, said sensing circuit includes said number 2 memory cell pass transistor is coupled to said access line coupled to said enabling signal and said specific number due to the output value shift (invert) operable to, device. According to Claim 25, said number 1 memory cell and said number 2 said data values stored in said OR operation is carried out with respect to: said number 1 said sensing said components coupled to a data value stored in the calculated loading; and said number 2 memory cells are disposed access line and an additional pass transistor is coupled to a signal line number including enabling, device. According to Claim 28, said loading is calculated components: said number 1 memory cells are disposed enabling access line; and said pass transistor is coupled said number data signal line and said additional pass transistors is coupled to a signal line including enabling said number, device. As described in claim either claim 25 to claim 29, said sense line is one of sensing line and said complementary sensing lines said one sense line is coupled to said pair of complementary sensing line and said pair of complementary pass transistor circuit senses another sense line is coupled to said additional pass transistors, device. According to Claim 27, said sensing said output value is coupled to a stored memory cell number 3, device. According to Claim 31, said AND operation is: storing said number 3 memory cells are disposed output value enabling said access line; and said pass transistor is coupled to a signal activating said number including, device. According to Claim 32, said AND access line number 4 is the result of an operation memory cells are disposed by enabling said number 4 recorded memory cell, said memory cell data value stored in said calculating component for copying said number 4, device. In method, memory cell of the array using a pair of complementary sensing line coupled to the sensing circuit, said input/output line pair of number 1 without using said sensing array for transmitting data from a plurality of memory cells coupled to a stored parity values for protecting data step, said step of determining parity value:
AND operation step, said AND operation is:
Sensing said number 1 number 1 number 1 data value and said number 1 to the word line coupled to a sensing coupled to a data value stored in the number 2 number 2 NAND carried out with respect to the result of an operation value; and
Said number 1 data value and the data value and said number 2 carried out with respect to the result of an operation performed OR value,
Said NAND operation is:
Said number 1 amount of said component calculated steps of loading a data value; and
Said number 2 memory cells are disposed said number 1 and number 2 component access line and said stored data values calculated AND operation carried out with respect to a data value corresponding to configure as enabling dimensions in the number 1, number 1 coupled to a source/drain area having said number 1 pass transistor is included in sensing said number 1, said enabling; and,
Said stored data value as said calculated components turned, said said NAND inverted data value is the result of an operation value, said shift step;
The result of an operation value recording said NAND memory cell coupled to a sensing said number 1 number 3;
Said OR operation is:
Calculating said number 1 component steps of loading said data value; and
The result of an operation value calculated said access line and said OR said number 2 memory cell coupled to said sensing circuit senses said complementary pairs of number 2 is stored component number 1 coupled to a source/drain region to configure and enabling number 2;
The result of an operation value and said OR said NAND said AND operation is the result of an operation values:
Storing the result of an operation value said NAND access line enabling said number 3 memory cells are disposed; and
Said calculating component said NAND result value and result value stored in said OR carried out with respect to the result of an operation value and enabling said AND dimensions in the directions to said number 1, said result value is said number 1 and number 2 (parity value) in preliminary data parity value, method. According to Claim 34, said data value includes calculating said number 1 loading components enabling said number 1 and said number 2 pass transistors with said number 1 memory cells are disposed by enabling said number 1 access line from memory cells to said component calculated data value including transmitting said number 1, method. According to Claim 34, said calculating step calculating said data value stored components reversed component coupled to said inverted transistor including enabling cross-coupled latch (cross coupled latch), method. As described in claim either claim 34 to claim 36, said NAND the result of an operation result of an operation value and said OR said number 1 and number 2 said AND values a predetermined step being carried out with respect to number 1 XOR data values, said plurality of memory cells for protecting data on a parity value stored said said step of determining said number 1 number 3 data value and said number 1 and number 2 coupled to a sensing data values stored in the carried out with respect to said number 1 XOR operation on the result of number 2 XOR operation including performing, method. According to Claim 37, said parity value coupled to a parity memory writing to the cell wherein sensing said number 1, said parity memory cell the plurality of memory cells different memory with said first address, method. According to Claim 37, said determining is subsequently parity value, said data value to be protected by parity value storing each an additional memory cells, each data value and said predetermined values protected data XOR operation including performing XOR performed the result of an operation values, method. According to Claim 39, said step of determining said value in response to the parity parity value of each of said data values stored in said plurality of memory cells to be protected at it said XOR operations including repeating until the XOR operation performed, method.
