УСИЛИТЕЛЬ СЧИТЫВАНИЯ С ОДНИМ ВХОДОМ И ДВУМЯ ВЫХОДАМИ

Изобретение относится к устройствам для записи или считывания информации в цифровых запоминающих устройствах, а именно к усилителям считывания с одним входом и двумя выходами. Техническим результатом является повышение синхронности выходных сигналов и увеличение быстродействия за счет отсутствия генерации дополнительных дифференциальных сигналов. Устройство содержит защелку, состоящую из пары nMOSFET, в которой первый и второй nMOSFET перекрещены один с другим, и пары pMOSFET, в которой первый и второй pMOSFET перекрещены один с другим; первый ключ pMOSFET, соединенный с защелкой и состоящий из стока, истока, затвора; второй ключ pMOSFET, соединенный с защелкой и состоящий из стока, истока, затвора; два предзаряжающих транзистора nMOSFET, выполненных с возможностью обеспечения низкого импеданса между нулевым уровнем и защелкой; pMOSFET, выполненный с возможностью обеспечения низкого импеданса между Vcc и истоками pMOSFET защелки; инвертор с цепью предзаряда, который состоит из включенных ...

ПРОГРАММАТОР ЗАПОМИНАЮЩИХ УСТРОЙСТВ

Относится к вычислительной технике и предназначен для записи информации в микросхемы программируемых запоминающих устройств. Содержит задатчик микрокоманд управления записью информации, блок регулируемых источников питания, блок согласования, регистр адреса, регистр данных и ЭВМ. Блок согласования необходим для включения источников питания и выбора режима работы программатора. Адресы программируемых ячеек памяти ПЗУ и коды записываемой информации считываются из ЭВМ в регистры. Микропрограмма управления записью информации предварительно загружается в блок оперативной памяти задатчика и по командам ЭВМ циклически считывается в регистры регулируемых источников питания. Программатор повышает эффективность использования ЭВМ и позволяет уменьшить объем памяти, отводимой для программирования запоминающих устройств, поскольку в функции ЭВМ входит лишь выборка адресов программируемых ячеек памяти ПЗУ и задание кода записываемой информации с последующим контролем достоверности программирования, а ...

Усилитель считывания на МДП-транзисторах

Изобретение относится к вычислительной технике и может быть использовано в запоминающих устройствах на МДП-тран- зисторах для усиления сигналов считываемой информации. Целью изобретения является повышение надежности усилителя считывания. Для этого в усилитель введены пятый и шестой ключевые транзисторы 12, 14 и второй, третий и четвертый установочные транзисторы 17, 18, 15 с соответствующими связями. Затворы транзисторов 12,11 являются парафазным входом усилителя, а стоки транзисторов 13, 14 - парафазным выходом. Усиление парафазного сигнала обеспечивает большую чувствительность усилителя. 1 ил.

Усилитель считывания

Усилитель считывания (его варианты)

... 1. Усилитель считывания, содержа-. щий ключбвые транзисторы с первого по девятый и нагрузочные транзисторы с первого по шестой, причем затвор и исток первого нагрузочного транзистора подключен к стоку первого.и затвору второго ключевых транзисторов, стоки первого, третьего, четвертого, пятого и шестого нагрузочных транзисторов подключены к первой шине питания , исток первого ключевого транзис- тора подключен к шине нулевого потенциала , затвор и исток второго нагрузочного транзистора подключен к стоку третьего ключевого транзистора, затвор четвертого ключевого транзистора подключен к стоку третьего ключевого .транзистора и затвору пятого ключевого транзистора, затвор третьего ключевого транзистора и исток пятого ключевого транзистора являются первым входом усилителя, сток пятого ключевого тран.зистора подключен к истоку третьего , нагрузочного транзистора и затвору шестого ключевого транзистора, сток которого подключен к истоку.четвертого нагрузочного транзистора и затвору седьмого ключевого ...

Усилитель считывания на КМОП-транзисторах

УСИЛИТЕЛЬ СЧИТЫВАНИЯ НА КМОП-ТРАНЗИСТОРАХ, содержащий элемент предварительной установки на р-канальных транзисторах, истоки которых соединены с шиной питания, затворы - с шиной стробирования, стоки - с входами соответствуюш .их выходных инверторов, ключевые элементы на р-канальных транзисторах , соединенных перекрестными связями, истоки которых соединены с шиной питания, стоки - с входами соответствующих выходных инверторов, элементы сравнения на п-канальных транзисторах, затворы которых являются входами усилителя, отличающийся тем, что, с целью повышения надежности усилителя, он содержит элемент стробирования на п-канальных транзисторах, дополнительные инверторы, каждый из которых состоит из р-канального ключевого и п-канального нагрузочного транзисторов, затворы каждого из которых объединены и подключены к входам соответствуюших выходных инверторов, сток нагрузочного и сток ключевого транзисторов каждого дополнительного инвертора объединены и подключены к истокам соответствующих п-канальных ...

Усилитель считывания для интегрального запоминающего устройства

Балансный усилитель

Импульсный усилитель

Усилитель считывания на полевых транзисторах с барьерным переходом

УСИЛИТЕЛЬ СЧИТЫВАНИЯ НА ПОЛЕВЫХ ТРАНЗИСТОРАХ С БАРЬЕРНЫМ ПЕРЕХОДОМ, содержащий триггер , первый и второй выводы питания которого подключены к шине питания и общей шине соответственно, отличающийся тем, что, с целью повышения быстродействия усилителя, в него введены первый и второй инверторы, первый и второй выводы питания которых подключены к шине питания и обшей шине соответственно, а входы - к прямому и инверсному выходам триггера соответственно , а также первый и второй нагрузочные элементы, выводы питания которых .подключены к шине питания, входы - к выходам соответствующих инверторов, а выходы - соответственно к первой и второй разрядны.м шинам, которые подключены соответственно к входам установки нуля и единицы триггера.

Усилитель считывания на дополняющих МДП-транзисторах

Усилитель считывания для запоминающего устройства на цилиндрических магнитных доменах

УСИЛИТЕЛЬ СЧИТЫВАНИЯ ДЛЯ ЗАПОМИНАЮЩЕГО УСТРОЙСТВА НА ЦИЛИНДРИЧЕСКИХ МАГНИТНЫХ ДОМЕНАХ, содержащий дифференциальны каскад и пороговый элемент, связанный с входами дифференшшльного каскада индуктивно-емкостной связью, а входы дифференциального каскада явлшотся входами усилителя, отличающийс я тем, что, с цепью повышения надежности усилителя за счет повышения отношения сигнал/помеха, в него введены счетчик, тифро- налогювый преобразователь и элемент И, первый вход которого соединен с выходом дифференциального каскада, второй вход -. с управляющим входом усишггеля, а ылход - со счетным входом счетчика, выходы которого с входом цифро-аналогового преобразователя, выход которого соединен с входом установки порога срабатьшания дифференциального каскада.

Усилитель считывания

Усилитель считывания

Усилитель считывания

Усилитель воспроизведения

Усилитель для считывания информации

Усилитель считывания

Усилитель считывания для оптоэлектронногозАпОМиНАющЕгО уСТРОйСТВА

Усилитель считывания для запоминающего устройства с n-секционной обмоткой считывания

Prüfverfahren für programmierbare nicht flüchtige Halbleiterspeichervorrichtung

Leseverstärkertreiberschaltung für einen Halbleiterspeicher

Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften

Halbleiterspeicher mit verbesserter Leseanordnung

Leseverstärkerschaltung

Nichtflüchtige Speicheranordnung, fähig zum Liefern richtiger Lesedaten zu einem bestimmten Zeitpunkt.

LESEVERSTAERKER FUER EINEN NICHTFLUECHTIGEN SPEICHER.

Halbleiterspeichervorrichtung.

Speichervorrichtung mit dynamisch betriebenen Bezugsschaltungen

Diese Erfindung betrifft eine Halbleiterspeichervorrichtung, die umfasst: zumindest eine Leseverstärkerschaltung (SAi) zum Lesen von Daten, die aus ausgewählten Speicherzellen in einem Speicherarray erfasst werden, zumindest eine Bezugsschaltung (RSAj), wobei jede Bezugsschaltung (RSAj) eine Nachbildung der Leseverstärkerschaltung (SAi) ist und einen Ausgang (OUTj) aufweist, durch den die Bezugsschaltung (RSAj) eine physikalische Ausgangsgröße liefert, ein Regelnetzwerk, das jede Leseverstärkerschaltung (SAi) und jede Bezugsschaltung (RSAj) mit einem Regelsignal (REG) versorgt, wobei das Regelsignal (REG) aus einer Durchschnittswertbildung der physikalischen Ausgangsgröße über die Zeit und/oder den Raum abgeleitet ist, wobei das Regelnetzwerk eine Steuereinheit (CU) umfasst, die ausgebildet ist, die physikalischen Größen jedes Ausgangs (OUTj) der Bezugsschaltung (RSAj) und einen Zielmittelwert zu summieren, wobei die Steuereinheit ein Regelsignal (REG) basierend auf der Summe liefert, wobei ...

Signalübertragungssystem

Speichereinheit unter Verwendung eines Speicherelements mit variablem Widerstand und Verfahren zum Bestimmen des Referenzwiderstandes davon

HALBLEITERSPEICHERANORDNUNG.

Ausleseschaltung für wieder beschreibbare Speicher und Ausleseverfahren für dieselben

Ausleseschaltung für wiederbeschreibbare Speicher umfassend: eine Steuerlogik (SL) mit einem Eingang zum Zuführen eines Startsignals (START) und mit mehreren Ausgängen zum Bereitstellen jeweils eines Steuersignals in Abhängigkeit des Startsignals (START), einen ersten Anschluss (21) zum schaltbaren Verbinden mittels eines ersten Schalters (S1) mit einer ersten Speicherzelle (140) und einen zweiten Anschluss (22) zum schaltbaren Verbinden mittels eines zweiten Schalters (S2) mit einer zweiten Speicherzelle (130), eine mit der Steuerlogik (SL), sowie mit dem ersten und dem zweiten Anschluss (21, 22) gekoppelte Ausleseeinheit (ENT, AV), mit einem Ausgang (23) zum Bereitstellen eines Ausgangssignals (Out) in Abhängigkeit eines Zustands der ersten und/oder der zweiten Speicherzelle (140, 130) und in Abhängigkeit der Steuersignale, wobei die Ausleseschaltung jeweils zum selbstterminierten Betrieb in einer Lesebetriebsart und in einer Testbetriebsart ausgelegt ist, und wobei die Ausleseschaltung ...

DETEKTIONSSCHALTUNG ZUR LADUNGSVERTEILUNG IN ANTISICHERUNGEN

Strombegrenzung während des Blockschreibens in Speicherschaltungen

Halbleiteranordnung

Halbleiteranordnung mit: einem Abtastverstärker (44), welcher auf den Empfang eines Lesefreigabesignals ein Signal verstärkt; einer Verzögerungseinheit (52, 54), welche eine Mehrzahl von Übertragungspfaden mit unterschiedlichen Verzögerungszeiten bereitstellen kann und das Lesefreigabesignal durch einen Übertragungspfad entsprechend einem Wahlsignal aus der Mehrzahl von Übertragungspfaden überträgt; gekennzeichnet durch eine Befehlssignalerzeugungsschaltung (122, 124), welche der Verzögerungseinheit (52, 54) als Befehlssignal ein ODER-Ergebnis einer Verknüpfung eines vorbestimmten Maximalverzögerungsbefehlssignals, welches zum Zwecke der Aufnahme eines Übertragungspfads mit der maximalen Verzögerungszeit als Übertragungspfad für das Lesefreigabesignal ausgegeben wird, und eines willkürlichen Wahlsignals zuführt, welches zum Zwecke der Wahl eines willkürlichen Übertragungspfads als Übertragungspfad für das Lesefreigabesignal ausgegeben wird.

Nichtflüchtiger ferroelektrischer Speicher

Nichtflüchtiger ferroelektrischer Speicher mit - einem Hauptzellenarray (71) mit: - einer Anzahl von Unterzellenarrays (71_1, 71_2, ...), - einer Anzahl globaler Hauptbitleitungen (BLG_n, BLG_n+1, ...) und mindestens einem Paar globaler Bezugsbitleitungen (BLRG_1, BLRG_2), die über die Unterzellenarrays (71_1, 71_2, ...) hinweg ausgebildet sind, - lokalen Hauptbitleitungen (BLLn_n, BLLn_n+1, ...) und lokalen Bezugsbitleitungen (BLLR_1, BLLR_2), die entsprechend den globalen Hauptbitleitungen (BLG_n, BLG_n+1, ...) und den globalen Bezugsbitleitungen (BLRG_1, BLRG_2) ausgebildet sind, und - Schaltern (SW11, SW12, SW21, SW22), die zwischen lokalen Bitleitungen (BLLn_n, BLLn_n+1, ...; BLLR_1, BLLR_2) und entsprechenden globalen Bitleitungen (BLG_n, BLG_n+1, ...; BLLR_1, BLLR_2) vorhanden sind, - einer über oder unter den Hauptzellenarray (71) ausgebildeten Bezugsbitleitungssteuerung (77) mit einem Bezugsleseverstärker (77a), der mit einer Bezugsbitleitung (BLRG_2) des Paars globaler Bezugsbitleitungen ...

Verfahren zum Betreiben eines Strom-Leseverstärkers

Die Erfindung betrifft ein Verfahren zum Betreiben eines Current Sense Amps, bei dem zur Verbesserung des Signal-Rauschverhältnisses die Versorgungsspannung (VBB) der Latchkonfiguration (P0, P1, N0, N1) größer als die am Eingang (MDQ, bMDQ) liegende Spannung eingestellt wird.

Halbleiterspeichervorrichtung mit übersteuertem Leseverstärker und Halbleitervorrichtung

Schaltungsanordnung zur Steuerung eines Referenzknotens in einem Leseverstärker

Method and circuit arrangement for shortening the read access time in an ECL memory.

The high capacitive loading on the outputs of the word selection decoder in an ECL memory having storage cells arranged in the manner of a matrix causes relatively long transit times between the binary values of the word selection signals on the word lines, and thus also long transit times of the read signals on the bit lines when the content of storage cells called up in succession differs. To shorten the read access time, it is proposed to make the response threshold of the read amplifiers connected to the bit lines variable in such a manner that the response already occurs at less than half the signal deviation depending on the direction of the signal change on the bit lines. A read amplifier with signal-edge-dependent response threshold is presented. ...

Speicherleseschaltung

Verfahren zur Leserverstärkersteuerung

SPEICHERBLOCKAUSWAHL UNTER VERWENDUNG VON MEHREREN WORTLEITUNGEN ZUR ADRESSIERUNG EINER EINZIGEN SPEICHERZELLENZEILE

Verschachtelte Bewerterschaltung mit einseitiger Vorladungsschaltung

Halbleiterspeicheranordnung

Einseitiger Übereinstimmungsleseverstärker

Abfühlverstärker für nichtflüchtigen Speicher mit niedriger Spannung

Read-out device for dynamic magnetic stores

... 1,084,758. Magnetic recording heads; local circuits. SOCIETE D'ELECTRONIQUE ET D'AUTOMATISME. Aug. 20, 1965 [Oct. 8, 1964], No. 35902/65. Heading G5R. To improve the realizable packing density of binary digital signals on a magnetic tape, the respective outputs of a balanced playback head 1 are fed to a pair of delay lines 6-9, 10-13 terminated by their characteristic impedances 19, 20, whose length is a fraction (preferably a half) of the characteristic period of the shortest recorded digital period. The delay elements are balanced symmetric. ally about the mid-point 11-12 of one of them and appropriate fractions of the tapping points are summed by resistors 14-18, whose output is fed to known reconstitution circuitry. Additional delay elements 2, 3, adjustable by varying-direct currents I c in their secondary windings may be used to balance lack of symmetry in the head outputs and to set a desired overall phase delay for the playback system.

A SEMICONDUCTOR INTERGRATED CIRCUIT MEMORY

Sense amplifier

A sense amplifier 14 for a memory comprises a data refresh amplifier 13 for supplying voltages to true and complementary bit lines BL, /BL in response to a first control signal SAP. A first transistor N1 amplifies current of the true data on BL, in response to a second control signal SAN, to a true input/output line DB. A second transistor N2 amplifies current of the complementary data on /BL, in response to the second control signal SAN, to a complementary input/output line /DB. A first switch N10 selectively forms a current path between the true input/output line and the true bit line BL, and a second switch N11 selectively forms a current path between the complementary input/output line and the complementary bit line /BL. Embodiments of the data refresh amplifier 13 are described (Figs 5 and 6). In a further aspect a sense amplifier has a third current amplifier (MP7 - MP10, Fig 7). A further aspect relates to a sense amplifier having first and further amplifiers for amplifying current ...

Flash memory device

High-speed sense amplifier for semiconductor memory device

A sense amplifier in a semiconductor device

Bitline level insensitive sense amplifier

A sense amplifier (221) for detecting the difference in voltage between two bitlines (113, 115) of a momory circuit. The sense amplifier is comprised of a differential amplifier (201, 203) which is coupled to the two bitlines (113, 115) and generates an output signal based on voltage levels sensed in the bitlines (113, 115). The differential amplifier (201, 203) is coupled to Vcc and ground through an active load (205, 207) and a current source (209) respectively. To address the problem of increased common mode voltage levels found in the bitlines (113, 115), a pair of transistors (223, 225) are connected in parallel across the active load (205, 207) to Vcc and the differential amplifier (202, 203). The gate of one of the transistors is coupled to one of the bitlines (113, 115) and the gate of the other one of the transistors is coupled to the other one of the bitlines (113, 115). With these two transistors (223, 225) coupled in parallel across the load (205, 207) as described, the differential ...

Differential current sensing circuit

A current sensing circuit comprises a differential current input stage in which a current from a sensing device 14 is compared with a reference current generated by current source or dummy sensor 16. The differential current input stage is made up from matched transistors T1, T2 acting as a current mirror. A switch SW1 may be provided between nodes N1 and N2 of the current mirror to equalize the output voltages Vout2 and Vout1 when the sensing device is not in use. The difference in currents IIN and IREF is converted to a voltage difference Vout1 - Vout2, which can then be supplied to differential voltage output stage. The differential voltage output stage comprises two transistors T8, T9 configured as a current mirror which acts as a differential amplifier. The output from the differential voltage output stage may then be provided to a buffering stage. The current sensing circuit is fabricated as an integrated circuit, for example using thin film transistors (TFTs). The reference current ...

Sense amplifier

Flash memory with redundancy

The present invention relates to a flash memory cell device having a repair circuit for replacing a fail cell of main memory cell arrays with a spare cell. The flash memory device according to the present invention comprises a main memory cell array, a redundancy cell block, a redundancy row decoder, a row decoder, a column decoder, a flag bit cell block, a flag cell transfer gate, a main sense amplifier and a flag sense amplifier.

Sense amplifier circuit

Latch type sense amplifier circuit

Current-mode sense amplifier and reference current circuitry

Electronic circuit comprising a current sense amplifier 103 and static memory cells 115. The current sense amplifier comprises a reference current input terminal 109, a sense current input terminal 108, and an output terminal 106, the static memory cells being coupled in parallel each via a respective associated n-FET stack 116 (i.e n-type MOSFET devices connected in series) to the sense current input terminal, the reference current input terminal being coupled to ground via two reference n-FET stacks 127 connected in series, the amplifier being configured to: generate a first logical value at the output terminal, in response to a reference current of the reference current input being higher than a sense current of the sense current input terminal, and generate a second logical value at the output terminal, in response to a reference current of the reference current input terminal being lower than a sense current of the sense current input terminal. A voltage generator 129 (or Vdd supply ...

Matchline sense circuit and method

CURRENT SENSING AMPLIFIER FOR A MEMORY

Sense amplifier for reading logic device

Sense amplification in data memories

RANDOM ACCESS SEMICONDUCTOR MEMORIES

... 1502925 Data store INTERNATIONAL BUSINESS MACHINES CORP 23 May 1975 [19 June 1974] 22913/75 Heading G4C A monolithic data store includes a matrix array of bi-stable memory cells producing output signals indicative of stored data, the signals having a voltage range whose midpoint shifts with respect to an absolute value as a function of temperature, and a bias circuit, Fig. 3, arranged to provide a reference voltage VREF equal to the midpoint of the cell voltage range which tracks the midpoint as it shifts due to temperature effects. The memory, Fig. 2, is conventional, each cell includes a bi-stable circuit formed of two double emitter transistors T21, T22 connected as shown to a pair of bit lines 301, 302 which are connected to a sense amplifier SA1 which acts to write into and read the storage cells. The cell transistor T21 combines with transistors T41, and T31 in the sense amplifier to form a current switch. When not used for read or write operations the cells are quiescent, a small ...

VOLTAGE SENSING CIRCUITS

... 1535237 Transistor bistable circuits TELETYPE CORP 25 Feb 1976 [5 March 1975] 07526/76 Heading H3T In a bistable sense amplifier comprising FET's Q3, Q4 a first control FET Ql fed with the signal being sensed is coupled in parallel with Q3, a second control FET Q2 fed with a reference potential is coupled in parallel with Q4, and means are provided for equalizing the potentials at the gates of the two control FET's during one period of a sensing cycle. The circuit is used as a read/write amplifier for a matrix of capacitive storage elements e.g. C M-1 , C M-2 . Before reading or writing, ° 1 is brought to - V volts turning on transistors Q5, Q6, Q7 to equalize the voltages at points A, B, C, D to - V R which is midway between 0 and - V c volts, this turning transistors Q1 . . . Q4 partially on to act as resistance elements. At the end of this preset period ° 1 goes to 0 volts, to turn off Q5, Q6, Q7, and the required cell is selected by energizing the appropriate Y conductor and X decoder ...

DOUBLE LOOPS READ PATTERN FOR RESISTANCE MEMORY CELLS

READ AMPLIFIER FOR NON VOLATILE INTEGRATED MULTI-LEVEL MEMORY MODULES

NON VOLATILE MEMORY AND SELECTION PROCEDURE

DEVICE FOR CURRENT MEASUREMENT DURING THE READING OF A MEMORY CELL

CURRENT MEASURING AMPLIFIER WITH FEEDBACK LOOP

ALTERNATING CURRENT MEASUREMENT FOR A RESISTIVEN A MEMORY

DIFFERENTIAL BOLTING DEVICE THRUST REVERSER AND DIRECT ACCESS STORAGE USING THE SAME DEVICE.

DETECTION CIRCUIT FOR CHARGE PATTERN IN ANTI-SAFETY DEVICES

Sense amplifier with offset autonulling

CASCODE SENSE AMP AND COLUMN SELECT CIRCUIT AND METHOD OF OPERATION

Matchline sense circuit and method

Sense amplifier with improved latching

LOW LEAKAGE ASYMMETRIC SRAM CELL DEVICES

DIFFERENTIAL LATCHING INVERTER AND RANDOM ACCESS MEMORY USING SAME

Synchronous integrated circuit device

COMPOSITIONS AND METHODS FOR PREPARING OLIGONUCLEOTIDE SOLUTIONS

The present invention is directed to methods and compositions for generating a pool of oligonucleotides. The invention finds use in preparing a population or subpopulations of oligonucleotides in solution. The pool of oligonucleotides finds use in a variety of nucleic acid detection and/or amplification assays.

SYSTEM EMPLOYING NEGATIVE FEEDBACK FOR DECREASING THE RESPONSE TIME OF A CELL

SYSTEM EMPLOYING NEGATIVE FEEDBACK FOR DECREASING THE RESPONSE TIME OF A CELL First and second lines respectively receive first and second complementary input signals representing a binary bit. Each of the input signals has first and second logic levels respectively corresponding to a binary "1" and a binary "0". The input signals produce a current through a load in accordance with the relative logic levels of the first and second input signals. The difference between the logic levels of the input signals is amplified and introduced as a negative feedback to a particular one of the first and second lines in accordance with the relative logic levels of the signals on the lines. The feedback causes a current to be produced in the load with a polarity opposite to the polarity of the current produced in the load by the input signals and with a magnitude less than the magnitude of the current produced in the load by the input signals. The negative feedback is effective in minimizing the time ...

PROGRAMMABLE SENSE AMPLIFIER FOR READ ONLY MEMORY

PROGRAMMABLE SENSE AMPLIFIER FOR READ ONLY MEMORY A programmable sense amplifier in accordance with the present invention includes an input multiplexer which receives a plurality of data input signals from the column lines of a ROM and provides a selected one of a data input signals as a data output signal based on control signals provided to the input multiplexer. The voltage level of the data output signal corresponds to the number of 1's contained in the selected column line. A sensing stage receives the data output signal and amplifies its The amplified signal is then provided to an XOR gate which either does or does not invert the amplified signal, based upon the state of the select node to which one of the XOR gate inputs is connected. The state of the select node is determined by a programmable internal multiplexer. The internal multiplexer comprises a number of FET switching transistors corresponding to the number of data input signals. Each of the switching transistors has one ...

MOS SENSE AMPLIFIER

MOS SENSE AMPLIFIER A comparator circuit suitably configured and synchronously operated to distinguish between the levels of two input signals and to provide the relative standing of the levels in binary format. In one form, a symmetrically organized circuit having the fundamental structure of a bistable multivibrator is initially operated in a differential mode and subsequently transitioned to a latch mode. Appropriate constant current source biasing shifts the differential mode operation to optimize amplifier element gain characteristics for the levels of input signals received. The amplified difference between the two input signals is stored within various capacitive elements of the circuit output stages. During the differential mode, the bistable multivibrator crosscoupling elements are disabled. At the termination of the differential mode, the amplified difference between the two input signals provides the initial conditions for the regenerative dynamics associated with the onset of ...

SINGLE-ENDED CURRENT SENSE AMPLIFIER

A single-ended sense amplifier (Fig. 1) having a precharge circuit (20) for maintaining a stable voltage on a bitline (19), a sensing circuit (30) coupled to the bitline (19) for sensing an amount of current flowing into the bitline (19), a direct current amplification circuit (40) electrically coupled to the sensing circuit (30) for amplifying the current sensed on the bitline (19), a current-to-voltage conversion circuit (50) for converting the sensed current to a voltage and a voltage amplification circuit (60) for amplifying the voltage at the sense amp output (80). The sense amplifier can be implemented using standard CMOS components (Fig. 2) and provides improved access time at low power supply voltage, high robustness to process variations, and the ability to sense very low currents.

C-MOS DIFFERENTIAL SENSE AMPLIFIER

A C-MOS sense amplifier detects voltage differences between the signals applied to its inputs in correspondence with transitions of a clock signal. It comprises a level converter, a sense circuit and a feedback circuit, which are inactive in a first inactive phase of the clock signal, while in a second active phase, immediately following a clock signal transition, the sense amplifier reaches an operating point necessary to activate the level converter and the sense circuit, and hence a high positive feedback is set up which switches the sense circuit. Finally, following the corresponding level transition of a delayed clock signal, the feedback signal generated by the feedback block reduces the dissipation of the entire differential sense amplifier to zero.

CIRCUIT AND METHOD FOR MULTIPLE MATCH DETECTION IN CONTENT ADDRESSABLE MEMORIES

The invention detects multiple matches between search and stored data in hi gh high-density content addressable memories. An input signal is derived from t he matchlines, such that the input signal starts discharging form a predetermined precharge level towards a discharge level determined by the number of match conditions. A reference signal is generated such that it starts to discharge at the same time from the same precharge level towards a reference level which falls between the two discharge levels corresponding to single and double match condition. A latching differential amplifier is activated shortly thereafter to compare the input signal with the reference signal and thereby provide an indication whether a multiple single or no match occurs on the matchlines, after which the amplifier is deactivated. The disclosed circuit features a relatively fast detection with low current consumption.

Elektromechanischer, insbesondere elektroakustischer Wandler

Magnetisches Wiedergabesystem

Schaltungsanordnung für das Ablesen von binären magnetischen Registrierungen

Schaltungsanordnung zur Verstärkung und Verriegelung binärer Datensignale

Reference cell for huigh speed sensing in non-volatile memories

Comparator with improved time constant

The invention provides a comparator with an improved time constant and an apparatus used for comparing input of differential input signals. The apparatus comprises a CMOS read amplifier (which is provided with a first input terminal, a second input terminal, a first output terminal and a second output terminal), a first output circuit (which is provided with a first load capacitor), a second output circuit (which is provided with a second load capacitor) and an isolation circuit. The isolation circuit is connected with and arranged between the first output terminal of the CMOS read amplifier and the first output circuit and connected with and arranged between the second output terminal of the CMOS read amplifier and the second output circuit. The isolation circuit isolates the first and second load capacitors from the CMOS read amplifier.

Sense amplifier with configurable voltage swing control

Method for improving writability of sram memory

A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Memory and method for sensing data in a memory using complementary sensing scheme

In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

Phase change memory device

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

Complementary read-only memory (rom) cell and method for manufacturing the same

A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Method for writing data in semiconductor storage device and semiconductor storage device

A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other.

Differential data sensing

A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Semiconductor memory device for minimizing mismatch of sense amplifier

A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized.

Maintenance of amplified signals using high-voltage-threshold transistors

Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

Low voltage sensing scheme having reduced active power down standby current

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Amplifiers using gated diodes

A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal is coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.

Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits. 1. A method of complementary pairing of memory cells comprising:providing a set of at least two reference cells per erase block wherein a first reference cell has a value of ‘1’ and a second reference cell has a value of ‘0’; andcomparing a selected memory cell in said erase block to said two reference cells to determine whether said memory cell has a value of ‘0’ or ‘1’.2. The method according to wherein said comparing is performed by a sense amplifier wherein said sense amplifier performs a subtraction-like function in order to determine whether said selected memory cell's signal is closer to said first or second reference signal.3. The method according to wherein said comparing is performed by a data latch wherein said data latch performs a subtraction-like function in order to determine whether said selected memory cell's signal is closer to said first or second reference signal.4. The method according to wherein said subtraction-like function is performed by a voltage subtractor circuit.5. The method according to wherein:a first sense amplifier compares said selected memory cell to said first reference cell;a second sense amplifier compares said selected memory cell to said second reference cell; anda third sense amplifier compares outputs from said first and second sense amplifiers to each other to find the output with the largest delta voltage or current.6. The method according to wherein said first claim 5 , second claim 5 , and third sense amplifiers are voltage sense amplifiers or current sense amplifiers.7. The method according to wherein:a first voltage subtractor compares said selected memory cell to said first reference cell;a second voltage subtractor compares said selected memory cell to said ...

NANO-SENSE AMPLIFIER

A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. 1. A sense amplifier (nSA) of a series of cells (Ci , Cj) of a memory , including:{'b': 1', '2, 'a writing stage comprising a CMOS inverter (T-T), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, and'}{'b': '3', 'a reading stage comprising a sense transistor (T), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter,'}wherein one or more of the transistors are multigate transistors.2. The sense amplifier according to claim 1 , wherein at least one multigate transistor is a FinFET.3. The sense amplifier according to claim 1 , wherein the input of the writing stage is directly connected to the input terminal of the inverter claim 1 , said input terminal being intended to be connected to a main bitline (MBL) which will address a plurality of sense amplifiers in parallel.44. The sense amplifier according to claim 1 , wherein the reading stage comprises an additional transistor (T) complementary to the sense transistor claim 1 , the additional transistor and the sense transistor forming a CMOS inverter claim 1 , the input of which is connected to the output of the reading stage and the output of which is connected to the input of the inverter of ...

Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths

A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation. 1. An apparatus , comprising:an array of memory cells; a first discharge node coupled to discharge a charge on said at least one bit line; and', 'a second discharge node coupled to discharge a charge on said at least one bit line, the first discharge node and the second discharge nodes at different locations along said at least one bit line; and, 'a plurality of bit lines accessing the array of memory cells, at least one bit line of the plurality of bit lines each havingdischarge circuitry electrically connected to the first discharge node and the second discharge node of the at least one bit line coupled to provide multiple discharge paths, wherein the discharge circuitry coupled to the first discharge node and the discharge circuitry coupled to the second discharge node are controlled by different signals.2. The apparatus of claim 1 , further comprising:control circuitry providing the different signals for the at least one bit line of the plurality of bit lines at a same time.3. The apparatus of claim 1 , a first plurality of discharge transistors electrically connected to the first discharge nodes of the plurality of bit lines, such that different bit lines of the plurality of bit lines discharge the charge through different discharge transistors of the first plurality of discharge transistors, and', 'a second plurality of discharge transistors electrically connected to the second discharge nodes of the plurality of bit lines, such that different bit lines of the plurality of bit lines discharge the charge through different discharge transistors of the second plurality of discharge transistors., 'wherein the discharge circuitry includes4. The apparatus of claim 1 ,wherein the discharge path of the ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier that is disposed above or below the memory cell array to be overlapped with the memory cell array in a planar fashion, connected to at least one bit line connected to the at least one cell bit line, and at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell; a decompression unit for decompressing a signal having a lower voltage level from among a signal of the at least one bit line and a signal of the at least one complementary bit line; a boosting unit for boosting a signal having a higher voltage level from among the signal of the at least one bit line and the signal of the at least one complementary bit line; and an equalizing unit for equalizing the signal of the at least one bit line and the signal of the at least one complementary bit line. 1. A semiconductor memory device comprising:a memory cell array that is disposed at a first layer and comprises at least one word line, at least one cell bit line, and at least one memory cell which is disposed in a region where the at least one word line and the at least one cell bit line cross each other;at least one sense amplifier configured to sense data stored in the at least one memory cell, the at least one sense amplifier being disposed at a second layer different from the first layer and connected to at least one bit line and at least one complementary bit line, the at least one bit line being connected to the at least one cell bit line,output device that is connected to the at least one cell bit line,wherein the bit line is connected to the output device via the cell bit line.2. (canceled)3. The semiconductor memory device of claim 1 , wherein ...

INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY

An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier. 1. A apparatus comprising:a first plurality of sense amplifiers, a first sense amplifier of the first plurality of sense amplifiers configured to provide a first output signal based on a first sensed state, wherein the first sense amplifier has a first output current drive setting;a second plurality of sense amplifiers, a second sense amplifier of the plurality of sense amplifiers configured to provide a second output signal based on a second sensed state, wherein the second sense amplifier has a second output drive setting, the second output current drive setting different than the first output current drive setting; anda data output circuit coupled to the first plurality of sense amplifiers and to the second plurality of sense amplifiers, the data output circuit configured to receive the first output signal and the second output signal and to provide output signals based on at least one of the first output signal or the second output signal.2. The apparatus of claim 1 , wherein the first sense amplifier comprises a first current driver configured to provide the first output signal having the first output current drive setting claim 1 , and wherein the second sense amplifier comprises a second current driver configured to provide the second output signal having the second output current drive setting.3. The apparatus of claim 2 , wherein the first current driver comprises a source follower stage comprising a plurality of transistors claim 2 , wherein each transistor of the plurality of transistors is coupled to a respective switch pair claim 2 , wherein the respective switch pair is configured to activate an associated transistor of the ...

Sense amplifier with offset current injection

A sense amplifier includes a sense input node, a current mirror circuit to mirror the current on the sense input node, and a result output node. A current source supplies an offset current. The sense amplifier increases the current on the sense input node by the offset current and reduces the offset current from the mirrored current at the result output node.

STORAGE DEVICE

Noise attributed to signals of a word line, in first and second bit lines which are overlapped with the same word line in memory cells stacked in a three-dimensional manner is reduced in a storage device with a folded bit-line architecture. The storage device includes a driver circuit including a sense amplifier, and first and second memory cell arrays which are stacked each other. The first memory cell array includes a first memory cell electrically connected to the first bit line and a first word line, and the second memory cell array includes a second memory cell electrically connected to the second bit line and a second word line. The first and second bit lines are electrically connected to the sense amplifier in the folded bit-line architecture. The first word line, first bit line, second bit line, and second word line are disposed in this manner over the driver circuit. 1. A semiconductor device comprising:a driver circuit comprising a sense amplifier, the sense amplifier being electrically connected to a first bit line and a second bit line;a first memory cell array comprising a first memory cell, the first memory cell being electrically connected to the first bit line and a first word line; anda second memory cell array comprising a second memory cell over the first memory cell array, the second memory cell being electrically connected to the second bit line and a second word line,wherein the first bit line is provided over the first word line,wherein the second word line is provided over the second bit line, andwherein the first memory cell overlaps with the second memory cell.2. The semiconductor device according to claim 1 , wherein the first memory cell array is provided over the driver circuit.3. The semiconductor device according to claim 2 , wherein the driver circuit comprises a transistor comprising a channel formation region in a single-crystal semiconductor substrate.4. The semiconductor device according to claim 1 , wherein each of the first ...

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. 1. A semiconductor device comprising:a first local bit line coupled to a plurality of memory cells arranged in a first area;a second local bit line coupled to a plurality of memory cells arranged in a second area;a local sense amplifier of a differential type amplifying a voltage difference between the first and second local bit lines;a global bit line arranged in an extending direction of the first and second local bit lines;a first switch controlling an electrical connection between the first local bit line and the global bit line; anda second switch controlling an electrical connection between the second local bit line and the global bit line.2. The semiconductor device according to claim 1 , further comprising a global sense amplifier of a single-ended type connected to one end of the global bit line.3. The semiconductor device according to claim 1 , further comprising a control circuit controlling the first and second switches claim 1 ,wherein in response to a selected memory cell of the memory cells, the control circuit renders one of the first and second switches conductive and renders the other thereof non-conductive.4. The semiconductor device according to claim 3 , wherein the control circuit renders the first switch conductive when the selected memory cell is in the first area claim 3 , and renders the second switch conductive when the selected memory cell is in the second area.5. The semiconductor device according to claim 4 , ...

SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES

Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. 18.-. (canceled)9. A sensing circuit comprising:a data column including an output voltage node, a memory cell, a first PMOS transistor that is diode-connected, and a first differential threshold NMOS transistor having a drain connected to a drain of the first PMOS transistor to form the output voltage node and a source connected to a first node; anda first memory column comprising a second differential threshold NMOS transistor having a drain connected to the first node; anda second memory column connected to the first node in parallel with the first memory column, wherein each memory column includes a differential threshold MOS transistor;wherein one or more of the differential threshold transistors are transistors that each have a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage.10. The sensing circuit of further comprising one or more additional memory columns.11. A sensing circuit or differential sense amplifier comprising:a reference column including a reference voltage node, a reference memory cell, a first differential threshold PMOS transistor that is diode-connected and has a drain connected to the reference voltage node, and a first differential threshold NMOS transistor having a drain connected to the reference ...

Sense-amplifier circuit of memory and calibrating method thereof

A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided.

SYSTEM AND METHOD OF REFERENCE CELL TESTING

Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. 1. A method comprising:coupling a first reference cell of a first reference cell pair of the a memory array to a first input of a first sense amplifier of the memory array; andproviding a reference signal to a second input of the first sense amplifier, wherein the reference signal is associated with a second reference cell pair of the memory array.2. The method of claim 1 , wherein the first sense amplifier includes comparator circuitry configured to output a comparator output value that is dependent upon a first signal received at the first input of the first sense amplifier and upon a second signal received at the second input of the first sense amplifier.3. The method of claim 1 , further comprising after coupling the first reference cell to the first input of the first sense amplifier and providing the reference signal to the second input of the first sense amplifier claim 1 , determining whether the first reference cell is functional by comparing an output of the first sense amplifier to a first predetermined threshold.4. The method of claim 3 , further comprising when the first reference cell is determined to be non-functional claim 3 , replacing use of the first reference cell in the memory array with use of a redundant reference cell of the memory array.5. The method of claim 3 , further comprising:coupling a second reference cell of the first reference cell pair to a first input of a second sense amplifier of the memory array;providing a second reference signal to a second input of the second sense ...

SYSTEM AND METHOD FOR MODIFYING ACTIVATION OF A SENSE AMPLIFIER

Systems, methods, and other embodiments associated with controlling a sense amplifier in a memory device are described. According to one embodiment, an apparatus includes a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device. The apparatus includes a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation. The apparatus also includes a controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit. The plurality of semiconductor gates are connected in parallel. 1. An apparatus , comprising:a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device;a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation; anda controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit, where the plurality of semiconductor gates are connected in parallel.2. The apparatus of claim 1 , wherein the memory device is a static random access memory (SRAM) and the apparatus is integrated with the SRAM.3. The apparatus of claim 1 , wherein the controller is configured to modify the timing of the sense enable signal to advance when the sense enable signal occurs.4. The apparatus of claim 3 , wherein the controller is configured to advance when the sense enable signal occurs by an amount based on a number of the plurality of semiconductor ...

SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal. 1. An apparatus , comprising:a first transistor configured to receive an input signal and adjust a resistance of a second transistor based, at least in part, on the input signal, the first transistor configured to provide an output signal based, at least in part, on the input signal,wherein a rate at which the output signal is provided is based, at least in part, on a magnitude of the resistance of the second transistor.2. The apparatus of claim 1 , wherein the resistance is an ON-resistance.3. The apparatus of claim 1 , wherein the input signal comprises an analog signal and the output signal comprises a digital signal.4. The apparatus of claim 3 , wherein the first transistor is configured to provide the output signal having a first state when the input signal has a voltage less than a reference voltage and to provide the output signal having a second state when the input signal has a voltage greater than the reference voltage.5. The apparatus of claim 1 , wherein a terminal of the first transistor and a terminal of the second transistor are capacitively coupled.6. The apparatus of claim 1 , ...

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. 1. A method of operation within a memory component , the method comprising:receiving, during a first command reception interval, a row command and a row address, the row address indicating a row of storage cells within the memory component;decoding the row address upon receiving the row command to select a row of storage cells within the memory component;receiving, during a second command reception interval and after decoding the row address has commenced, a first column command and a first column address, the first column address indicating a first column of data within a first subrow of storage cells included within the row of storage cells, and the first column command indicating a memory access operation to be carried out with respect to the first column of data; andtransferring a first subrow of data, including the first column of data, from the first subrow of storage cells to a first set of sense amplifiers in response to the first column command.2. The method of further comprising executing the memory access operation indicated by the first column command with respect to the first column of data after transferring the first subrow of data from the first subrow of storage cells to the first set of sense amplifiers.3. The method of wherein executing the memory access operation comprises transferring the first column of data from the first set of sense amplifiers to an output driver of the memory component in a memory read operation claim 2 , the output driver to output the first column of data from the memory component claim 2 , wherein an elapsed time between receipt of the first column ...

Spin-transfer torque memory self-reference read method

A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE

To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground. 1. A sense amplifier circuit comprising:a sensing transistor that is connected between a first power supply and a second power supply through a memory cell connection line that extends to a memory cell;a resistance element that is connected between the first power supply and a control terminal of the sensing transistor; anda capacitance element that is connected between the second power supply and the control terminal of the sensing transistor.2. The sense amplifier circuit according to claim 1 , wherein a first capacity from the sensing transistor to the second power supply through the capacitance element is equal to a second capacity from the sensing transistor to the second power supply through the memory cell connection line.3. The sense amplifier circuit according to claim 1 , comprising a current-mirror circuit that mirrors a current flowing through the sensing transistor claim 1 ,wherein a first capacity from the sensing transistor to the second power supply through the capacitance element is based on a second capacity from the sensing transistor to the second power supply through the memory cell connection line and a third capacity of a circuit in an output side of the current-mirror circuit.4. The sense amplifier circuit according to claim 3 , wherein the third capacity is a capacity in which a parasitic capacity of an output-side transistor of the current-mirror circuit claim 3 , a whole parasitic capacity of an output line from the output-side transistor to an output inverter which is an output ...

Systems, memories, and methods for repair in open digit memory architectures

A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.

SEMICONDUCTOR MEMORY DEVICE

In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced. 2. The semiconductor memory device of claim 1 , whereinthe first and second signal lines are local bit lines,the third and fourth signal lines are global bit lines,the local and global bit lines form a hierarchical bit line architecture.3. The semiconductor memory device of claim 1 , wherein a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,', 'a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,', 'a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,', 'a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,', 'a fifth cell transistor of the second conductivity type ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells, and a column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches. One of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled. 1. A semiconductor memory device comprising:a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells; anda column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches,one of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled.2. The semiconductor memory device according to claim 1 ,wherein, when a set of the sense amplifiers capable of handling one of the cell columns is set as a sense amplifier set, a set of the data latches capable of handling one of the cell columns is set as a data latch set, and a set of the one of the sense amplifier sets and the one of the data latch sets is set as a column set,the sense amplifier-data latch unit includes a common control circuit that is used in common for controlling a ...

Bipolar primary sense amplifier

A sense amplifier for a memory includes two bipolar transistors and isolation switches for selectively coupling and decoupling the base of the bipolar transistors to bit lines during portions of a read cycle. The sense amplifier has a feedback circuit that couples the collector of one of the bi polar transistors to the base of the other bipolar transistor and vice versa.

Redundant memory array for replacing memory sections of main memory

Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.

SINGLE-ENDED READ RANDOM ACCESS MEMORY

A single-ended read random access memory including a plurality of memory units, a clock generator, a bit line load circuit, a control processing unit, and a sensing unit is revealed. The memory units are coupled to a bit line and the clock generator is for generating a clock signal. The bit line load circuit charges the memory units to an operating voltage according to the clock signal. The control processing unit controls at least one of the memory units according to the clock signal to make the memory unit store a stored voltage according to the operating voltage. The sensing unit generates a sensing threshold according to the clock signal and a data dependency, and outputs a data signal according to the sensing threshold and the stored voltage. The operating voltage includes a noise whose ratio to the operating voltage is inversely proportional to the operating voltage. 1. A single-ended read random access memory comprising:a plurality of memory units coupled to a bit line;a clock generator that generates a clock signal;a bit line load circuit that charges the memory units to an operating voltage according to the clock signal;a control processing unit that controls at least one of the memory units according to the clock signal so as to make the memory unit stores a stored voltage in accordance with the operating voltage; anda sensing unit that generates a sensing threshold according to the clock signal and the stored voltage, and outputs a data signal according to the sensing threshold and the stored voltage;wherein the operating voltage includes a noise and a ratio of the noise to the operating voltage is inversely proportional to the operating voltage.2. The device as claimed in claim 1 , wherein the sensing unit outputs an amplified voltage according to the stored voltage.3. The device as claimed in claim 2 , wherein the sensing unit outputs the amplified voltage according to the noise so as to output the data signal.4. The device as claimed in claim 1 , ...

SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER

In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. 1. A semiconductor memory device , comprising:a plurality of sense amplifiers driving bit lines to which memory cells are connected;a plurality of sense amplifier drivers supplying a power supply to the sense amplifiers, each of sense amplifier drivers having first and second driver transistors, and the first driver transistor having a first diffusion regions in a first well region and the second driver transistor having a second diffusion region in a second well region which is different conductivity type from the first well region, andan element separation region formed between the first and second well region,wherein the first and second driver transistors are arranged in parallel with a first direction so as to be arranged one of second driver transistors between two of the first driver transistors,wherein the first diffusion region comprises first and second sides, the first side is parallel to the first direction and the second side is perpendicular to the first direction,wherein the second diffusion region comprises third and fourth sides, the third side is parallel to the first direction and the fourth side is ...

CIRCUITS AND METHODS FOR CALIBRATING OFFSET IN AN AMPLIFIER

In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset cancels a least a portion of the offset of the amplifier. In one implementation, the amplifier is a sense amplifier in a memory. 120-. (canceled)21. A method for determining offset in an amplifier , the method comprising:generating, using offset generation circuitry, an offset value at an input of an amplifier;determining, using offset detection circuitry, whether an output of the amplifier is greater than an output threshold; andsetting, using control circuitry, an offset inject value which indicates that an offset should be generated at the input of the amplifier if the output is determined to be greater than the output threshold.22. The method of claim 21 , further comprising:generating an incremented offset value by incrementing the offset by an offset increment value if the output is determined to be greater than the output threshold;determining, using offset detection circuitry, whether the output of the amplifier is greater than a output threshold; andstoring, using offset value storage circuitry, the incremented offset value if the output is less than or equal to the output threshold.23. The method of claim 22 , wherein the offset value and incremented offset value is determined by successive approximation.24. The method of claim 21 , wherein the input of the amplifier is a first polarity input of the amplifier and the output of the amplifier is associated with the first polarity of the input.25. The method of claim 21 , further comprising storing the generated ...

SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME

A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed; a sink unit configured to provide a sense voltage in response to the enable signal; and a sense unit configured to generate an output signal in response to the sense voltage and the input signals. 1. A sense amplifier circuit , comprising:an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed;a sink unit configured to provide a sense voltage in response to the enable signal; anda sense unit configured to generate an output signal in response to the sense voltage and the input signals.2. The sense amplifier circuit according to claim 1 , wherein the enable signal generation unit receives a sense control signal and supplies the sense control signal as the enable signal when the change in the voltage level of the input signals is sensed.3. The sense amplifier circuit according to claim 2 , further comprising a cut-off unit configured to prevent the sense voltage from being supplied to the sense unit when the sense control signal is disabled.4. The sense amplifier circuit according to claim 2 , wherein:the input signals are a pair of input signals, andthe enable signal generation unit provides the sense control signal as the enable signal when a voltage level of one of the pair of input signals shifts to a specific voltage level.5. The sense amplifier circuit according to claim 1 , wherein the enable signal generation unit further comprises a first PMOS transistor operably coupled in parallel with a second PMOS transistor.6. The sense amplifier circuit according to claim 5 , wherein the enable signal generation unit receives input signals through a gate of the first PMOS transistor and a gate of the second PMOS transistor.7. A sense amplifier circuit claim 5 , comprising:an enable signal generation unit configured to generate ...

Apparatuses and methods for coupling load current to a common source

Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.

SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT

Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation. 1. A semiconductor device comprising:a first line;a second line;a first node;a second node supplied with a first power supply potential;a first control element that controls an amount of current flowing between the second line and the first node according to a potential of the first line;a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line;a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential;a second control circuit that performs a second operation to connect the first node to the second node; anda third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation.2. The semiconductor device as claimed in claim 1 , wherein the first potential and the second potential are substantially the same potential.3. The semiconductor device as claimed in claim 1 , further comprising first and second memory cells claim 1 ,wherein the first line receives data read from the first memory cell, and the ...

SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE

A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. 1. A semiconductor device comprising:a first conductive line;a second conductive line;a first transistor coupled between the first conductive line and a first power supply line, the first transistor including a control terminal coupled to a first control line;a second transistor coupled between a second power supply line and a first node, the second transistor including a control terminal coupled to a second control line different from the first control line;a third transistor coupled between the first conductive line and the first node, the first transistor including a control terminal coupled to a third control line; anda fourth transistor coupled between the second conductive line and a third power supply line, the fourth transistor including a control terminal connected to the first node;wherein the first power supply line is able to be supplied an intermediate voltage which is intermediate between a voltage of the second power supply line and a voltage of the second power supply line.2. The semiconductor device according to claim 1 , further comprising a memory cell coupled ...

SEMICONDUCTOR DEVICE, METHOD OF RETRIEVING DATA, AND MICROCOMPUTER

A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing inverted data of the reference data; a sense amplifier unit; and a data output unit. In a first retrieving process, the sense amplifier unit differentially amplifies the data and the reference data, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference. In a second retrieving process, the sense amplifier unit differentially amplifies the data and the inverted data, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the predetermined retrievable voltage difference. The data output unit determines and outputs the data according to a result of the first retrieving process and the second retrieving process. 1. A semiconductor device comprising:a data memory cell for storing data;a reference data memory cell for storing reference data to be compared with the data;an inverted data memory cell for storing inverted data of the reference data;a sense amplifier unit; anda data output unit,wherein said sense amplifier unit is configured to perform a first retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the reference data stored in the reference data memory cell, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference,said sense amplifier unit is configured to perform a second retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the inverted data stored in the inverted data memory cell, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the ...

Bitline for Memory

Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.

SEMICONDUCTOR DEVICE HAVING OPEN BITLINE STRUCTURE

Disclosed herein is a semiconductor device that includes: a plurality of memory arrays disposed in a first direction and a second direction that crosses the first direction; a plurality of row decoders disposed along a first side of the memory arrays; a plurality of first column decoders each disposed along a second side that does not face the first side of an associated one of the memory arrays; and a plurality of second column decoders each disposed along a third side that faces the second side of an associated one of the memory arrays. Each of the memory arrays is sandwiched between a corresponding one of the first column decoders and a corresponding one of the second column decoders. 1. A semiconductor device comprising:a plurality of memory mats arranged in a first direction and selected based on a mat address, the plurality of memory mats including a first memory mat disposed in one end portion of the first direction, a second memory mat disposed in the other end portion of the first direction, and a third memory mat positioned between the first and second memory mats; anda plurality of sense amplifier areas each arranged between two of the memory mats that are adjacent to each other in the first direction, each of the sense amplifier areas including a plurality of sense amplifiers, whereineach of the memory mats includes a plurality of bit lines extending in the first direction, a plurality of word lines extending in a second direction that crosses the first direction, and a plurality of memory cells disposed at intersections of the bit lines and word lines,each of the sense amplifiers is connected to an associated one of the bit lines included in an adjacent one of the memory mats on one side of the first direction, and to an associated one of the bit lines included in an adjacent one of the memory mats on the other side of the first direction,the first and third memory mats are selected when the mat address indicates a first value, andthe second and third ...

SEMICONDUCTOR STORAGE DEVICE

According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part. 1. A semiconductor storage device , comprising:a plurality of peripheral circuits on a semiconductor substrate;a memory cell array having a plurality of semiconductor layers above the peripheral circuits, the memory cell array including two or more regions;a plurality of upper bit lines disposed in one or more layers above the memory cell array and extending in a first direction, each of the upper bit lines electrically connected to at least one of the peripheral circuits;a plurality of lower bit lines disposed in one or more layers below the memory cell array and extending in the first direction, each of the lower bit lines corresponding to a respective upper bit line; anda plurality of connection parts including contact plugs connecting upper bit lines to corresponding lower bit lines,wherein a first group of the upper bit lines are connected to the peripheral circuits via a first connecting part and respective lower bit lines, the first connecting part disposed between two regions of the memory cell array, and a second group of the upper bit lines are connected to the peripheral circuits via a second connecting part and respective lower bit ...

Memory Device, System Having the Same, and Method for Manufacturing the Same

A memory device includes a memory cell array including normal memory cells arranged in a form of matrix, and a sense amplifier array including sense amplifiers each amplifying a signal output from each of the normal memory cells. Some of the sense amplifiers have different sizes so that they may have different sense capabilities depending on a layout location. The size is determined according to at least one of a channel length and a channel width of a MOS transistor included in each of the some sense amplifiers. 1. A memory device , comprising:a memory cell array including memory cells arranged in a matrix; anda sense amplifier array including a plurality of sense amplifiers, each sense amplifier configured to amplify a signal output from each cell of a set of memory cells;wherein each sense amplifier of the sense amplifier array is formed of a plurality of transistors, andwherein an average size among the plurality of transistors that form a first sense amplifier of the sense amplifier array is larger than an average size among the plurality of transistors that form a second sense amplifier of the sense amplifier array.2. The memory device of claim 1 , wherein the first sense amplifier is an edge sense amplifier claim 1 , and the second sense amplifier is an inner sense amplifier.3. The memory device of claim 1 , wherein an average channel length among the plurality of transistors that form the first sense amplifier of the sense amplifier array is larger than an average channel length among the plurality of transistors that form the second sense amplifier of the sense amplifier array.4. The memory device of claim 1 , wherein an average channel width among the plurality of transistors that form the first sense amplifier of the sense amplifier array is larger than an average channel width among the plurality of transistors that form the second sense amplifier of the sense amplifier array.5. (canceled)6. (canceled)7. The memory device of claim 1 , wherein an average ...

MEMORY WITH REDUNDANT SENSE AMPLIFIER

Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state. 1. An apparatus , comprising:a plurality of data storage cells;a decoder circuit configured to select a data storage cell from the plurality of data storage cells;a control circuit configured to store test data in the selected data storage cell;a first sense amplifier configured to amplify the stored test data in the selected data storage cell using a first gain level;wherein the control circuit is further configured to compare test data to the stored data amplified using the first gain level; anda second sense amplifier configured to amplify the stored test data in the selected data storage cell using a second gain level responsive to a determination that the stored test data amplified using the first gain level does not match the test data, wherein the second gain level is greater than the first gain level; and compare the test data to the stored test data amplified using the second gain level; and', 'store information indicative of the strength of the selected data storage cell dependent upon the comparison of the test data to the stored data amplified using the second gain level., 'wherein the control circuit is further configured to2. The apparatus of claim 1 , ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption. 1. A semiconductor memory device comprising:a first core region and a second core region disposed along a first reference line substantially parallel to a major axis, the first reference line connecting an input pad and an output pad;first and second cell blocks disposed in the first core region along the first reference line;third and fourth cell blocks disposed in the second core region along the first reference line; anda repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, through a first global input/output line in a read operation for the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line.2. The semiconductor memory device according to claim 1 , further comprising:a data output unit configured to receive the data amplified by the repeater, through the second global input/output line, and output the received data to a third global input/output line.3. The semiconductor memory ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a sense amplifier circuit region including first wells disposed in a first direction, a driving circuit region including second wells disposed in a second direction, and a conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region. 1. A semiconductor memory device , comprising:a sense amplifier circuit region including first wells disposed in a first direction;a driving circuit region including second wells disposed in a second direction; anda conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region.2. The semiconductor memory device as claimed in claim 1 , wherein the part of each of the first wells in the conjunction region includes first and second partial wells extending from the sense amplifier circuit region at both sides of the conjunction region into the conjunction region claim 1 , the first and second partial wells being spaced apart from each other.3. The semiconductor memory device as claimed in claim 2 , wherein a length of the first partial well or the second partial well in the first direction is greater than about 5% of a width of the conjunction region in the first direction.4. The semiconductor memory device as claimed in claim 2 , wherein lengths of the first partial well and the second partial well in the first direction are substantially identical to each other.5. The semiconductor memory device as claimed in claim 2 , further comprising a third well in the conjunction region claim 2 , the third well connecting the first partial well ...

SEMICONDUCTOR DEVICE

A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed. 1. A semiconductor device , comprising:a first memory cell;a second memory cell;a first bit line extending in a first direction and being connected to the first memory cell;a second bit line extending in the first direction and being connected to the second memory cell;a first power line; anda sense amplifier circuit comprising a first transistor and a second transistor, the first transistor including a first gate electrode that is formed over a first channel region and connected to the first bit line, a first diffusion region that is connected to the second bit line and includes a first side edge defining the first channel region and a second diffusion region that is connected to the first power line and includes a second side edge defining the first channel region, and the second transistor including a second gate electrode that is formed over a second channel region and connected to the second bit line, a third diffusion region that is connected to the first bit line and includes a third side edge defining the second channel region and a fourth diffusion region that is ...

SENSE AMPLIFIER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

A sense amplifier circuit includes a first pull-up transistor configured to pull-up drive a data bar line in response to a voltage of a data line, a first pull-down transistor configured to pull-down drive the data bar line in response to the voltage of the data line, and to receive the voltage of the data line through a back gate of the first pull-down transistor, a second pull-up transistor configured to pull-up drive the data line in response to a voltage of the data bar line, and a second pull-down transistor configured to pull-down drive the data line in response to the voltage of the data bar line, and to receive the voltage of the data bar line through a back gate of the second pull-down transistor. 1. A sense amplifier circuit comprising:a first pull-up transistor configured to pull-up drive a data bar line in response to a voltage of a data line;a first pull-down transistor configured to pull-down drive the data bar line in response to the voltage of the data line, and to receive the voltage of the data line through a back gate of the first pull-down transistor;a second pull-up transistor configured to pull-up drive the data line in response to a voltage of the data bar line; anda second pull-down transistor configured to pull-down drive the data line in response to the voltage of the data bar line, and to receive the voltage of the data bar line through a back gate of the second pull-down transistor.2. The sense amplifier circuit of claim 1 , wherein each of the first pull-down transistor and the second pull-down transistor includes a fully depleted silicon on insulator (FDSOI) NMOS transistor.3. The sense amplifier circuit of claim 2 , wherein each of the first pull-up transistor and the second pull-up transistor includes a PMOS transistor.4. A memory device comprising:one or more cell arrays,a bit line and a bit bar line connected to the one or more cell arrays;a first pull-up transistor configured to pull-up drive the bit bar line in response to a ...

Sense Amplifier Circuit for Nonvolatile Memory

A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal.

SEMICONDUCTOR MEMORY DEVICES

A semiconductor memory device includes a memory bank having a first cell block including a plurality of memory cells coupled to a first word line which can be activated in response to a row address signal, a second cell block including a plurality of memory cells coupled to a second word line, and a dummy cell block including a plurality of memory cells coupled to a third word line which can be activated in response to the row address signal. The first and second cell blocks share a first sense amplifier. The second cell block and the dummy cell block share a second sense amplifier. The first cell block is disposed adjacent to a first edge of the memory bank, and the dummy cell block is disposed adjacent to a second edge of the memory bank opposing the first edge. 1. A semiconductor memory device comprising:a first cell block including a first plurality of memory cells coupled to a first word line;a second cell block including a second plurality of memory cells coupled to a second word line; anda dummy cell block including a third plurality of memory cells coupled to a third word line,wherein the first and second cell blocks share a first sense amplifier, the second cell block and the dummy cell block share a second sense amplifier, the first cell block is disposed adjacent to a first edge of the semiconductor memory device where a row address signal is inputted, and the dummy cell block is disposed adjacent to a second edge of the semiconductor memory device opposing the first edge.2. The semiconductor memory device of :wherein when the row address signal indicates the first cell block is being accessed and no failed memory cells exists in the first cell block, the first and third word lines are simultaneously activated; andwherein when the row address signal indicates the first cell block is being accessed and at least one failed memory cell exists in the first cell block, the first and third redundancy word lines are simultaneously activated.3. The semiconductor ...

Bit line sense amplifier and layout method therefor

A bit line sense amplifier and a layout method therefor which can reduce coupling capacitance. The bit line sense amplifier is disposed between a first memory cell block and a second memory cell block adjacent to the first memory cell block and configured to include first and third switching elements substantially symmetrically formed in a first direction so that the drain terminals of the first and third switching elements face each other, second and fourth switching elements substantially symmetrically formed in the first direction so that the drain terminals of the second and fourth switching elements face each other, a first line configured to electrically couple the gate terminal of the first switching element and the drain terminal of the second switching element, and a second line configured to electrically couple the gate terminal of the third switching element and the drain terminal of the fourth switching element.

SENSE AMPLIFIERS, MEMORIES, AND APPARATUSES AND METHODS FOR SENSING A DATA STATE OF A MEMORY CELL

Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances. 1. An apparatus , comprising:a data line and a reference line;a precharge circuit configured to precharge the data line and the reference line during a precharge phase;a switch block having a data line input coupled to the data line, a reference data line input coupled to the reference line, a reference input, and a feedback input, the switch block further including a data line output, a reference data line output, a reference output, and a feedback output, during the precharge phase the switch block configured to couple the reference input to the data line output, the reference data line output, and the reference output, and further couple the feedback input to the feedback output, during an evaluation phase the switch block configured to couple the data line input to the data line output and further couple the reference data line input to the reference data line output;a first capacitance coupled to the data line output;a second capacitance coupled to the reference data line output; anda differential amplifier coupled to the first and second capacitances and configured to ...

DATA VERIFICATION DEVICE AND A SEMICONDUCTOR DEVICE INCLUDING THE SAME

A semiconductor device includes a data verification device. The data verification device includes a data storage unit for storing data to be input to a memory region in response to a first or second control signal, an input data verifier for deactivating an output of a sense amplifier in response to the first control signal and transmitting the input data stored in the data storage unit to an external pad, and a sense-amplifier verifier for transmitting the input data stored in the data storage unit to the sense amplifier upon in response to the second control signal. 1. A data verification device comprising:a data storage unit configured to store input data in response to a first or second control signal generated in a test mode;an input data verifier configured to deactivate an output of a sense amplifier in response to the first control signal, and transmit the input data provided by the data storage unit to an external pad; anda sense-amplifier verifier configured to transmit the input data provided by the data storage unit to the sense amplifier in response to the second control signal, wherein the sense amplifier senses the input data transmitted thereto and transmits sensed data to the external pad.2. The data verification device according to claim 1 , wherein the data storage unit includes a latch that stores the input data in response to the first or second control signal.3. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the input data verifier in response to the first control signal.4. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the sense-amplifier verifier in response to the second control signal.5. The data verification device according to claim 1 , wherein the data storage unit is coupled to a data input buffer claim 1 , and receives the input data through the data input buffer and stores the input data.6. The data verification device ...

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started. 1. A semiconductor apparatus comprising:a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started; anda switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started.2. The semiconductor apparatus according to claim 1 , further comprising a control unit configured to generate the control signal and the second read enable signal in response to the first read enable signal and a second select signal.3. The semiconductor apparatus according to claim 2 , wherein the control unit generates the second read enable signal by delaying the first read enable signal.4. The semiconductor apparatus according to claim 3 , wherein the first select signal comprises a signal enabled during a write operation.5. The semiconductor apparatus according to claim 4 , wherein the second select signal comprises a signal enabled during a read operation.6. The ...

SEMICONDUCTOR DEVICE AND DATA OUTPUT CIRCUIT THEREFOR

A semiconductor device includes a memory cell array configured to include a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines, a bit line sense amplifier connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment I/O line, a control signal generator configured to determine a level of an I/O switch control signal in response to a level of a power source voltage, and a local sense amplifier connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line. 1. A semiconductor device , comprising:a memory cell array configured to comprise a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines;a bit line sense amplifier (BLSA) connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment input/output (I/O) line;a control signal generator configured to determine a level of an I/O switch control signal in response to a level of a power source voltage; anda local sense amplifier (LSA) connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line.2. The semiconductor device according to claim 1 , wherein the control signal generator outputs the I/O switch control signal in response to a pre-switching control signal and a level detection signal determined by the level of the power source voltage.3. The semiconductor device according to claim 2 , wherein ...

SEMICONDUCTOR DEVICE INCLUDING BURIED GATE, MODULE AND SYSTEM, AND METHOD FOR MANUFACTURING

An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device. 1. A semiconductor device comprising:a recess formed in an active region;a gate buried in a lower part of the recess;a first capping insulation film formed over the gate;a second capping insulation film formed over the first capping insulation film; anda third capping insulation film formed over the second capping insulation film so as to fill the recess.2. The semiconductor device according to claim 1 , wherein the first capping insulation film comprises a silicon nitride film having a higher nitrogen ratio than a SiNmaterial.3. The semiconductor device according to claim 1 , wherein the first capping insulation film is formed over a sidewall of the recess and over the gate.4. The semiconductor device according to claim 1 , wherein the second capping insulation film includes an oxide film in which the first capping insulation film is partially oxidized.5. The semiconductor device according to claim 1 , wherein the third capping insulation film comprises a silicon nitride film having a higher nitrogen ratio than a SiNmaterial.6. The semiconductor device according to claim 1 , wherein the third capping insulation film includes an oxide film.7. The semiconductor device according to claim 6 , wherein the third capping insulation ...

JUNCTIONLESS SEMICONDUCTOR DEVICE HAVING BURIED GATE, APPARATUS INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current. 1. A junctionless semiconductor device comprising:an active region disposed over an underlying substrate and defined by a device isolation film over the underlying substrate;an insulation layer disposed between the active region and the underlying substrate; anda plurality of buried gates formed in the device isolation film and the active region,wherein source and drain regions and a body in the active region around a buried gate are doped with the same-type impurities.2. The junctionless semiconductor device according to claim 1 , wherein the impurities are implanted into the active region with substantially uniform density.3. The junctionless semiconductor device according to claim 1 , wherein the active region is formed of a silicon layer claim 1 , and the impurities are N-type impurities.4. The junctionless semiconductor device according to claim 1 , wherein the active region is formed using any of a silicon germanium (SiGe) substrate claim 1 , a germanium (Ge) substrate claim 1 , and a group 3 compound semiconductor substrate or a group 5 compound semiconductor substrate claim 1 , and the impurities are P-type impurities.5. The junctionless semiconductor device according to claim 1 , wherein the active region is isolated from the underlying substrate by the insulation layer.6. The junctionless semiconductor ...

SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DIFFERENTIAL SIGNAL TRANSMISSION STRUCTURE AND METHOD FOR DRIVING THE SAME

A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal. 1. A semiconductor integrated circuit , comprising:an input data line pair;a sense amplifier configured to sense and amplify data loaded on the input data line pair and output the amplified data to an output data line pair, in response to a control signal; anda sense amplification controller configured to detect an amplification level on the output data line pair, and output the control signal for controlling the sense amplifier based on a sense amplification enable signal and the detected amplification level.2. The semiconductor integrated circuit of claim 1 , wherein the sense amplification enable signal is activated during a predetermined period in response to a command.3. The semiconductor integrated circuit of claim 1 , wherein the sense amplification controller comprises:a reset unit configured to reset a sensing node in response to the sense amplification enable signal;a sensing driving unit configured to sense voltage levels of the output data line pair and drive the sensing node to a predetermined voltage level; andan output unit configured to output the control signal in response to the sense amplification enable signal and a voltage on the sensing node.4. The semiconductor integrated circuit of claim 3 , wherein the reset unit comprises an NMOS transistor having a source coupled to a ground voltage terminal claim 3 , a drain coupled to the sensing node claim 3 , and a gate to receive an inverted sense amplification enable signal.5. The semiconductor integrated circuit of claim 3 , ...

MEMORY DEVICE AND METHOD OF PERFORMING A READ OPERATION WITHIN SUCH A MEMORY DEVICE

A memory device is provided comprising an array of memory cells. During a read operation, voltage on a read bit line will transition towards a second voltage level if a data value stored in that activated memory cell has a first value, and sense amplifier circuitry will then detect this situation. If that situation is not detected, the sense amplifier circuitry determines that the activated memory cell stores a second value. Bit line keeper circuitry is coupled to each read bit line and is responsive to an asserted keeper pulse signal to pull the voltage on each read bit line towards the first voltage level. Keeper pulse signal generation circuitry asserts the keeper pulse signal at a selected time. The selected time is such that the voltage on the associated read bit line will have transitioned to the trip voltage level before the keeper pulse signal is asserted. 1. A memory device comprising:an array of memory cells arranged as a plurality of rows and columns, each row of memory cells being coupled to an associated read word line, each column of memory cells forming at least one column group, and the memory cells of each column group being coupled to an associated read bit line;word line driver circuitry configured, during a read operation, to issue an asserted read word line pulse signal on the read word line coupled to an addressed row of the array so as to activate the memory cells within that addressed row whilst the read word line pulse signal is asserted;precharge circuitry configured, prior to the read operation, to precharge each read bit line to a first voltage level;during the read operation the voltage on the read bit line associated with any column group containing one of the activated memory cells being arranged to transition towards a second voltage level if a data value stored in that activated memory cell has a first value;sense amplifier circuitry connected to the associated read bit line of each column group, and configured for each activated ...

TRANSISTOR VOLTAGE THRESHOLD MISMATCH COMPENSATED SENSE AMPLIFIERS AND METHODS FOR PRECHARGING SENSE AMPLIFIERS

Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored. 1. An apparatus , comprising:first and second field-effect transistors (FETs), the first and second FETs having a respective drain configured to receive a respective input signal; anda capacitance coupled between sources of the first and second FETs, the capacitance configured to store a voltage difference between the sources of the first and second FETs to compensate for threshold voltage differences between the first and second FETs.2. The apparatus of claim 1 , further comprising:an equilibration transistor coupled to the drain of the first FET and the drain of the second FET and configured to receive an equilibration signal, the equilibration transistor configured to couple the drain of the first FET to the drain of the second FET responsive to the equilibration signal.3. The apparatus of claim 1 , further comprising third and fourth FETs claim 1 , the third FET having a drain coupled to the drain of the first FET and the fourth FET having a drain coupled to the drain of the second FET.4. The apparatus of claim 1 , wherein the capacitance is configured to store the voltage difference during each of a plurality of precharge cycles.5. The apparatus of claim 1 , wherein the ...

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line. 1. A method comprising:accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line;transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; andrestoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line.2. The method as claimed in claim 1 , further comprising restoring claim 1 , in response to the data read mode claim 1 , the data into the memory cell through the global and local bit lines.3. The method as claimed in claim 2 , wherein the restoring responsive to the data read mode is carried out by a global sense amplifier connected to the global bit line and the restoring responsive to the refresh mode is carried out a restoring circuit connected to the local bit line.4. A method comprising:accessing a plurality of memory cells to all the memory cells to output data stored therein onto a plurality of local bit lines, respectively; and designating one of the local bit lines as a selected local bit line and remaining one of the local bit lines respectively as non-selected local bit lines;', 'transferring a data signal on the selected local bit line to a global bit line;', 'restoring the data into the memory cell connected to the selected bit line through the global bit line and the selected bit line; and', 'restoring the data into the memory cells connected respectively to the non-selected local bit lines while keeping each of the non-selected local bit lines electrically isolated ...

Circuits and Methods of a Self-Timed High Speed SRAM

Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power. 1. A SRAM memory , comprising:a plurality of SRAM cells having a bitlines (BL) and wordline (WL) that can be selected for access;at least one reference cell having a reference bitline in (BLin) and a reference bitline (RBL) that can be selected from one of a plurality of wordlines or from at least one reference wordline, the reference cell being selectable not earlier than any selected SRAM cells and the RBL being activatable not later than any selected SRAM cells to activate the selected BL;at least one sense amplifier to sense signals coupled to the selected BL from the at least one selected SRAM cell and convert the signals into digital data; andwherein the sense amplifier can be activated by the RBL signal to track the wordline and BL propagating delay.2. A SRAM memory as recited in claim 1 , wherein the at least one reference cell is placed near the far end of a driver to drive a selected wordline or a reference wordline.3. A SRAM memory as recited in claim 1 , wherein the reference cell has at least one inverter with an input coupled to BLin and an output NB coupled to RBL claim 1 , and wherein the RBL is activated by setting BLin at a voltage close to a supply voltage once the wordline or reference wordline is selected.4. A SRAM memory as ...

SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials. 1. (canceled)2. A semiconductor device comprising:a source line;a first bit line;a first word line;a memory cell connected to the source line, the first bit line and the first word line, wherein the memory cell comprises a first transistor and a gate of the first transistor is configured to hold a written potential in accordance with data to be held in the memory cell;a driver circuit configured to drive the first word line so as to select the memory cell specified by an address signal;a reading circuit comprising a plurality of comparing circuits; anda potential generating circuit configured to generate a plurality of reading potentials to supply to the reading circuit,wherein each of the plurality of comparing circuits is configured to compare a potential of the first bit line and one of the plurality of reading potentials, andwherein the reading circuit is configured to decide a potential range of the potential of the first bit line by comparing the potential of the first bit line with the plurality of reading potentials.3. The semiconductor device according to claim 2 , further comprising a control circuit configured to select one of a plurality of voltages for correction on a basis of comparison results between the potential of the first bit line and the plurality of reading potentials.4. The semiconductor device ...

SEMICONDUCTOR MEMORY DEVICE WITH DATA PATH OPTION FUNCTION

A semiconductor memory device may include a memory cell, a bit line connected to the memory cell, a bit line data latch circuit configured to sense-amplify data stored in the memory cell connected to the bit line and to store write data in the memory cell via the bit line; an input/output driver configured to output read data on the bit line to an external device or to drive the write data provided from the external device; and a selection unit configured to select whether the read data and the write data are communicated between the input/output driver and the memory cell with or without use of the bit line data latch circuit. 1. A semiconductor memory device comprising:a memory cell;a bit line connected to the memory cell;a bit line data latch configured to sense-amplify read data stored in the memory cell connected with the bit line and to store write data to be written in the memory cell through the bit line;an input/output driver configured to output the read data on the bit line to an external device and to drive the write data provided from the external device; anda selection circuit configured to select whether the bit line data latch is bypassed or is used or bypassed to sense-amplify read data stored in the memory cell and to store the write data to be written in the memory cell .2. The semiconductor memory device of claim 1 , wherein the selection circuit is configured to select whether data stored in the memory cell is transferred directly to the input/output driver or to the input/output driver via the bit line data latch at a read operation claim 1 , and to select whether the write data is transferred directly to the memory cell or to the memory cell via the bit line data latch at a write operation.3. The semiconductor memory device of claim 1 , wherein the memory cell is a magneto-resistive random access memory type of memory cell.4. The semiconductor memory device of claim 3 , wherein the magneto-resistive random access memory type of memory cell is ...

GENERATING AND EXECUTING A CONTROL FLOW

Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array. 120-. (canceled)21. An apparatus comprising:a central processing unit (CPU), configured to generate control flow instructions; and an array of memory cells;', 'an execution unit, coupled to the array, to execute the control flow instructions; and', 'a controller configured to control an execution of the control flow instructions on data stored in the array., 'a memory device, including22. The apparatus of wherein the CPU is further configured to generate the control flow instructions including instructions and an execution order associated with the instructions.23. The apparatus of claim 21 , wherein the CPU is further configured to:request data associated with a program from the memory device;store the data associated with the program in cache; andgenerate the control flow instructions from the data stored in the cache.24. The apparatus of claim 23 , wherein the CPU is further configured to:request data associated with a program from the memory device;cause an arithmetic logic unit (ALU) to generate the control flow instructions, andwherein the apparatus further comprises the ALU configured to generate the control flow instructions.25. The apparatus of claim 21 , wherein the memory device is further configured to receive the control flow instructions via at least one of a buffer claim 21 , the memory array claim 21 , and shift circuitry.26. An apparatus comprising:a system on a chip (SoC) configured to generate control flow instructions; and an array of memory cells;', 'an execution unit, coupled to the array, to execute the ...

LATCHING SENSE AMPLIFIER

A latching sense amplifier includes an input stage and an output stage. The output stage is coupled to the input stage. The output stage includes a first output node, a second output node, a pull-up circuit, and a pull-down circuit. The pull-up circuit includes a first transistor, a second transistor, and a latch circuit. The first transistor is configured to pull up the first output node. The second transistor is configured to pull up the second output node. The latch circuit is configured to control the first transistor and the second transistor. The pull-down circuit includes a latch circuit configured to pull-down the first output node based on a voltage of the second output node. 1. A latching sense amplifier , comprising:an input stage comprising a clocked differential amplifier; and a first output node;', 'a second output node;', a first transistor;', 'a second transistor cross-coupled with the first transistor;', 'a third transistor, controlled by the first transistor, and configured to pull up the first output node;', 'a fourth transistor, controlled by the second transistor, and configured to pull up the second output node; and, 'a pull-up circuit, comprising, a fifth transistor configured to pull down the first output node; and', 'a sixth transistor configured to pull down the second output node;', 'wherein the fifth transistor and the sixth transistor are cross-coupled., 'a pull-down circuit, comprising], 'an output stage comprising2. The latching sense amplifier of claim 1 , wherein the pull-up circuit further comprises:a seventh transistor coupled to a first output node of the input stage, and configured to control the first transistor; andan eighth transistor coupled to a second output node of the input stage, and configured to control the second transistor.3. The latching sense amplifier of claim 1 , wherein the pull-down circuit further comprises:a seventh transistor coupled to a first output node of the input stage, and configured to pull-down the ...

SEMICONDUCTOR MEMORY DEVICE WITH MULTIPLE SUB-MEMORY CELL ARRAYS AND MEMORY SYSTEM INCLUDING SAME

A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array. 1. A semiconductor memory device comprising:a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic;a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array; anda second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.2. The semiconductor memory device of claim 1 , wherein each one of the first and second characteristics indicates one of relative importance of the corresponding data claim 1 , reliability of the corresponding data claim 1 , and type of the corresponding data.3. The semiconductor memory device of claim 1 , further comprising:a first sense amplifier accessing the first data stored in the first sub-memory cell array during the read operation using a first data access approach; anda second sense amplifier accessing the ...

APPARATUSES AND METHODS TO CONTROL OPERATIONS PERFORMED ON RESISTIVE MEMORY CELLS

Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device. 1. An apparatus comprising:a first conductive line;a second conductive line;a resistive memory cell coupled between the first and second conductive lines; anda control unit to:cause a voltage at the first conductive line during a first time interval and a second time interval of an operation of changing a resistance of the resistive memory cell to have a first voltage value during the first time interval and a second voltage value during the second time interval, the second voltage value being greater than the first voltage value, and to cause a current flowing through the resistive memory cell during the first and second time intervals to remain unchanged at a first current value; andcause a voltage at the first conductive line during a third time interval and a fourth time interval of the operation to have a third voltage value during the third time interval and a fourth voltage value during the fourth time interval, the fourth voltage value being greater than the third voltage value, and to cause a current flowing through the resistive memory cell during the third and fourth time intervals to remain unchanged at a second current value, the second current value being greater than the first current value.2. The apparatus of claim 1 , wherein the resistive memory cell has a first resistance before the first time interval and a second resistance after the ...

READ OPERATIONS BASED ON A DYNAMIC REFERENCE

Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing. 1. (canceled)2. An apparatus , comprising:a memory cell;a capacitive circuit configured to selectively couple with the memory cell and configured to develop a signal of the memory cell during an access operation;a bus configured to selectively couple with the capacitive circuit during the access operation; anda sense component configured to compare a charge stored by the capacitive circuit with a voltage on the bus.3. The apparatus of claim 2 , further comprising:a switching component configured to selectively couple the capacitive circuit with the bus to transfer a second voltage to the bus, wherein the voltage on the bus is based at least in part on transferring the second voltage to the bus from the capacitive circuit.4. The apparatus of claim 2 , further comprising:a circuit coupled with the capacitive circuit and the memory cell and configured to selectively isolate the memory cell from the capacitive circuit during the access operation based at least in part on a voltage associated with the memory cell.5. The apparatus of claim 4 , wherein the circuit is configured to ...

MEMORY DEVICE AND OPERATION METHOD THEREOF

A memory device and an operating method thereof are provided. The memory device includes a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data, a transmission circuit configured to output the read data stored in the latch through a page bus line in response to a transmission signal, a cache latch configured to receive the read data through the page bus line and temporarily store the read data, and a pump voltage output circuit coupled to the transmission circuit through a transmission line and configured to apply a second voltage greater than a first voltage after applying the first voltage to the transmission line for a set time. 1. A memory device , comprising:a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data;a transmission circuit configured to output the read data stored in the latch through a page bus line in response to a transmission signal;a cache latch configured to receive the read data through the page bus line and temporarily store the read data; anda pump voltage output circuit coupled to the transmission circuit through a transmission line and configured to apply a second voltage greater than a first voltage after applying the first voltage to the transmission line for a set time.2. The memory device of claim 1 , wherein the cache latch is configured to transfer data input from an external device to the latch through the page bus line during a program operation.3. The memory device of claim 1 , wherein the transmission circuit includes a switch electrically coupling or decoupling the latch and the transmission line in response to the transmission signal.4. The memory device of claim 3 , wherein the switch is configured to turn-on in response to the transmission signal.5. The memory device of claim 1 , wherein the pump voltage output circuit comprises:a first voltage output circuit configured to output the first voltage in response to a ...

Apparatuses and methods for comparing a current representative of a number of failing memory cells

Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current butler configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

SENSE AMPLIFIER STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region. 1. A semiconductor integrated circuit device , comprising:a first signal line and a second signal line; anda sense amplifier that includes a plurality of NMOS transistors and a plurality of PMOS transistors, and is configured to sense-amplify a potential difference between the first signal line and the second signal line,wherein junction regions of the PMOS and NMOS transistors having the same conductivity type to which a same signal is applied are integrated to share a portion of one active region, andthe sense amplifier includes a latch block,wherein the latch block includes:a first gate line arranged to partition one portion of the integrated active region; anda second gate line arranged to partition another portion of the integrated active region.2. The semiconductor integrated circuit device of claim 1 , wherein the latch block includes:an N latch block including a pair of the NMOS transistors connected in series between the first signal line and the second signal line by their sources; anda P latch block including a pair of the PMOS transistors connected in series between the first signal line and the second signal line by their sources, wherein the pair of PMOS transistors and the pair of NMOS transistors are configured as an inverter latch; andand the sense amplifier further includes an equalization block connected between the first signal line and the second signal line.3. The semiconductor integrated circuit device of claim 2 , wherein the pair of NMOS ...

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access. 120.-. (canceled)21. An apparatus , comprising:sensing circuitry comprising a sense amplifier and a compute component coupled to a column of an array of memory cells, the column comprising a sense line; anda controller configured to use the sensing circuitry to perform a logical operation by using a first data value on the sense line at a first point in time as a first input and a second data value on the sense line at a second point in time as a second input.22. The apparatus of claim 21 , wherein the sense amplifier comprises a first latch and the compute component comprises a second latch.23. The apparatus of claim 21 , wherein the controller is configured to use the sensing circuitry to perform the logical operation without activating a column decode signal.24. The apparatus of claim 21 , wherein the controller is further configured to cause the sensing circuitry to store a result of the logical operation in a memory cell coupled to the sense line.25. The apparatus of claim 21 , wherein the controller is further configured to cause a result of the logical operation to be transferred from the sense amplifier and/or the compute component external to the sensing circuitry and the array.26. The apparatus of claim 21 , wherein the logical operation is a Boolean operation.27. The apparatus of claim 21 , wherein the logical operation is a non-Boolean operation.28. The apparatus of ...

BIT-LINE SENSE AMPLIFIER CAPABLE OF COMPENSATING MISMATCH BETWEEN TRANSISTORS, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

A bit-line sense amplifier may include a pull-up driving circuit, a pull-down driving circuit and a latch-type sense amplifier. The pull-up driving circuit including a plurality of PMOS transistors connected between a power supply voltage line and a first driving power supply line, and may be configured to provide a first driving current on the first driving power supply line in response to an up control signal. The pull-down driving circuit may be configured to provide a second driving current on a second driving power supply line in response to a down control signal. The latch-type sense amplifier may be connected between the first driving power supply line and the second driving power supply line, and may be configured to sense and amplify a voltage difference between a bit line and a complementary bit line. 1. A bit-line sense amplifier , comprising:a pull-up driving circuit including a plurality of PMOS transistors connected between a power supply voltage line and a first driving power supply line, and configured to provide a first driving current on the first driving power supply line in response to an up control signal;a pull-down driving circuit configured to provide a second driving current on a second driving power supply line in response to a down control signal; anda latch-type sense amplifier connected between the first driving power supply line and the second driving power supply line, and configured to sense and amplify a voltage difference between a bit line and a complementary bit line.2. The bit-line sense amplifier of claim 1 , wherein the latch-type sense amplifier comprises:a first inverter including a first PMOS transistor and a first NMOS transistor, wherein a gate of each of the first PMOS transistor and the first NMOS transistor is connected to the complementary bit line; anda second inverter including a second PMOS transistor and a second NMOS transistor, wherein a gate of each of the second PMOS transistor and the second NMOS transistor is ...

STATIC MEMORY APPARATUS AND DATA READING METHOD THEREOF

A static memory apparatus and a data reading method thereof are provided. The static memory apparatus includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster. The dummy memory cells respectively include a plurality discharge ends for discharging charges on a dummy bit line. The sense amplifier is enabled for a sensing and amplifying operation according to a signal on the dummy bit line, and the sense amplifier generates readout data accordingly. The discharge current adjuster adjusts at least one discharge current on at least one controlled discharge end according to an operating voltage of the memory cells. 1. A static memory apparatus , comprising:a plurality of memory cells arranged to form a memory array coupled to a plurality of bit lines;a plurality of dummy memory cells coupled to a dummy bit line and respectively comprising a plurality of discharge ends to discharge charges on the dummy bit line;a sense amplifier coupled to the bit lines and the dummy bit line and performing a sensing and amplifying operation on signals on the bit lines according to a signal on the dummy bit line to generate readout data; anda discharge current adjuster coupled to at least one controlled discharge end of the discharge ends and adjusting a discharge current on the at least one controlled discharge end according to an operating voltage received by the memory cells.2. The static memory apparatus according to claim 1 , wherein the discharge ends not coupled to the discharge current adjuster are coupled to a reference ground voltage.3. The static memory apparatus according to claim 1 , wherein the discharge current adjuster comprises:a variable resistor coupled between the at least one controlled discharge end and a reference ground voltage, wherein a resistance value of the variable resistor varies according to a variation of a bias voltage; anda bias voltage adjuster coupled to the variable resistor and ...

Sense amplifier layout for finfet technology

A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.

SELF-REFERENCING SENSING SCHEMES WITH COUPLING CAPACITANCE

Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes. 1. (canceled)2. An apparatus , comprising:a sense component in electronic communication with a memory cell via a first access line;a capacitance between a first node of the sense component and a second node of the sense component; and generate a first sense signal at the first node of the sense component while the memory cell is coupled with the first node of the sense component;', 'generate a second sense signal at the second node of the sense component while the memory cell is coupled with the second node of the sense component, wherein the second sense signal is based at least in part on the generated first sense signal and the capacitance between the first node of the sense component and the second node of the sense component; and', 'determine a logic state stored by the memory cell based at least in part on generating the first sense signal and generating the second sense signal., 'a controller in electronic communication with the sense component and the memory cell, wherein the controller is operable to cause the apparatus to3. The apparatus of claim 2 , wherein the memory cell comprises a capacitive memory element.4. The apparatus of claim 2 , ...

SENSE AMPLIFIER WITH TRANSISTOR THRESHOLD COMPENSATION

One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors. The method also includes applying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier. 1. In a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell , a method to store the logic state , comprising:poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors; andapplying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier.2. The method of further comprising storing the offset voltage levels of the first and second transistors on first and second capacitors coupled claim 1 , respectively claim 1 , to source terminals of the first and second transistors.3. The method of wherein storing the offset voltage levels includes connecting a drain and gate of each transistor to a common voltage level and allowing the source voltages of each transistor to increase until each transistor stops passing current.4. The method of wherein the offset voltage levels of the first and second transistors are stored anew prior to every read operation of the sense amplifier.5. The method of wherein each threshold voltage is a gate-to-source threshold voltage below which ...

BITLINE SENSEAMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME

A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal. 1. A memory apparatus comprising:a bit line sense-amplifier coupled to first and second bit lines, the bit line sense-amplifier including a first power node and a second power node;a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal;a sense-amplifier power control unit suitable for providing a plurality of powers to each of the first and second power nodes in response to a power control signal; anda second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.2. The memory apparatus of claim 1 ,wherein the power control signal includes first and second power control signals, andwherein the sense-amplifier power control unit provides one of either an internal voltage or a first precharge voltage to the second power node in response to the first power control signal, and provides a ground voltage to the second power node in response to the second power control signal.3. The memory apparatus of claim 2 , wherein the sense-amplifier power control unit provides one of either the internal voltage or the first precharge voltage to the first power node in response to the second power control signal.4. The memory apparatus of claim 2 , wherein the sense-amplifier power control unit provides the first precharge voltage to the second power node in response to the bit line equalization signal.5. The memory ...

APPARATUS AND METHOD FOR REPAIRING RESISTIVE MEMORIES AND INCREASING OVERALL READ SENSITIVITY OF SENSE AMPLIFIERS

A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch. 1. A memory comprising: monitor outputs of a plurality of sense amplifiers, wherein each of the outputs of the plurality of sense amplifiers is configured to be in a first state or a second state,', 'determine that a plurality of the outputs of the plurality of sense amplifiers are in a same state, wherein the same state is the first state or the second state, and', 'output the state of the plurality of the outputs of the plurality of sense amplifiers; and, 'a module configured to'}a demultiplexer configured to provide the state of the plurality of the outputs of the plurality of sense amplifiers to a latch.2. The memory of claim 1 , wherein:the module is configured to determine that a majority of the outputs of the plurality of sense amplifiers is in the same state; andthe demultiplexer is configured to provide the same state of the majority of the outputs of the plurality of sense amplifiers to the latch.3. The memory of claim 1 , further comprising:an array of memory cells comprising a plurality of bit lines;a plurality of multiplexers, wherein each of the plurality of multiplexers is configured to receive outputs from two or more of the plurality of bit lines; andthe plurality of sense amplifiers configured to amplify respective outputs of the plurality of multiplexers.4. The memory of claim 3 , further comprising a second module configured to generate one or more selection ...

MEMORY WITH HIGH-SPEED AND AREA-EFFICIENT READ PATH

A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter. 1. A read path for a memory , comprising:a sense amplifier configured to sense a bit decision signal responsive to a read operation; anda level-shifting data latch configured to latch the bit decision signal to form a latched bit decision signal and to level shift the latched bit decision signal from a memory domain power supply voltage to an external domain power supply voltage.2. The read path of claim 1 , further comprising an output data driver configured to drive the latched bit decision signal from the memory.3. The read path of claim 1 , further comprising;a first transistor coupled between an output node of the sense amplifier and an input node to the level-shifting data latch; anda first logic gate configured to assert a combined sense enable and redundancy shift-off signal in response to an assertion of both a sense enable signal and a redundancy shift-off signal, wherein the first transistor is configured to switch on in response to the assertion of the combined sense enable and redundancy shift-off signal to conduct the bit decision signal from the sense amplifier to the integrated data latch and level shifter.4. The read path of claim 3 , wherein the first logic gate comprises a NOR gate. The present application is a divisional application of U.S. Non-Provisional patent application Ser. No. 16/421,365, filed May 23, 2019, which is hereby incorporated by reference in its entirety.This application relates to memories, and more particularly to an improved memory read path.In a conventional memory such as a static random-access memory (SRAM), a sense amplifier makes a bit decision for an accessed bitcell during a read operation. But the output of the sense amplifier is only valid during a sense enable period, so the sense amplifier typically drives a ...

MEMORY DEVICE

A memory device includes memory elements and a controller. The memory controller executes a process including a first section and a second section in response to a refresh command, detects an error of data stored in the memory elements in the first section, and writes correct data in a memory element storing data with the detected error in a second section, the second section being variable in accordance with a time to write the correct data. 1. A memory device comprising:memory elements; anda controller which executes a process including a first section and a second section in response to a refresh command, detects an error of data stored in the memory elements in the first section, and writes correct data in a memory element storing data with the detected error in a second section, the second section being variable in accordance with a time to write the correct data.2. The device of claim 1 , wherein:the controller identifies a memory element storing data with the detected data and writes correct data in the identified memory element.3. The device of claim 1 , wherein:the controller detects an error in all predetermined sized segments of received data in units of the segments in the first section, and identifies a memory element storing data with the detected error and writes correct data in the identified memory element in the second section.4. The device of claim 3 , wherein:the controller comprises a register storing information for identifying memory elements of the memory elements storing an error-corrected segment.5. The device of claim 1 , wherein:the controller outputs no data stored in the memory elements to outside the memory device in the first section.6. The device of claim 1 , wherein:the memory device further comprises second memory elements different from the memory elements; andthe controller executes error detection and writing of correct data to the second memory elements in response to another refresh command.7. The device of claim 1 , ...

APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells. 120.-. (canceled)21. A method of performing a compare function , comprising:charging an input/output (IO) line of a memory array to a voltage;determining whether the voltage of the IO line changes in response to activation of a number of selected decode lines and a number of access lines corresponding to at least two memory cells of the memory array.22. The method of claim 21 , wherein charging an IO line includes precharging an IO line of the memory array to a precharge voltage.23. The method of claim 21 , wherein charging the IO line to the voltage includes charging the IO line to a supply voltage.24. The method of claim 23 , wherein the supply voltage corresponds to a data value of 1.25. The method of claim 21 , wherein charging the IO line to a voltage includes charging the IO line to a ground voltage.26. The method of claim 25 , wherein the ground voltage corresponds to a data value of 0.27. The method of claim 21 , wherein activating selected decode lines comprises activating a subset of the decode lines of the array.28. The method of claim 27 , including determining the subset of decode lines based on a set of criteria of the subset.29. An apparatus comprising:an array of memory cells; precharging of a local input/output (LIO) ...

IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY

An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. In an embodiment, a corresponding method includes the following steps: selecting at least one of the sectors, determining an indication of the number of memory cells in the programmed state and an indication of the number of memory cells in the erased state of the selected sector, and identifying the condition of the selected sector according to a comparison between the indication of the number of memory cells in the programmed state and the indication of the number of memory cells in the erased state. 110-. (canceled)11. A memory circuit , comprising:a sector including a memory location having a memory cell and a complementary memory cell; and to determine a value stored in the memory location during a first read mode, and', 'to determine a first state of the memory cell and a second state of the complementary memory cell during a second read mode., 'a sense-amplifier circuit configured'}12. The memory circuit of wherein:the memory cell includes a non-volatile memory cell; andthe complementary memory cell includes a complementary non-volatile memory cell.13. The memory circuit of wherein the sense amplifier is configured to determine the value stored in the memory location in response to a first state of the memory cell and a ...

APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Apparatuses and methods including memory and operation of same

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

SECURITY DEVICE INCLUDING PHYSICAL UNCLONABLE FUNCTION CELLS AND OPERATION METHOD THEREOF

A security device includes a physical unclonable function (PUF) cell array including PUF cells connected with word lines and bit lines; first decoder circuitry connecting a first bit line connected to a target PUF cell with a first data line and a second bit line connected with a reference PUF cell to a second data line; a digital-to-analog converter (DAC) control circuit outputting first and second digital codes; a first DAC between a power supply voltage and the first data line, the first DAC generating a first analog output in response to the first digital code; a second DAC between the power supply voltage and the second data line, the second DAC generating a second analog output in response to the second digital code; and a sense amplifier comparing the first analog output and the second analog output and outputting a comparison result. 1. A security device comprising:a physical unclonable function (PUF) cell array including a plurality of PUF cells, connected with a plurality of word lines and a plurality of bit lines;first decoder circuitry configured to connect, from the plurality of bit lines, a first bit line connected to a target PUF cell with a first data line and to connect a second bit line connected to a reference PUF cell with a second data line;a digital-to-analog converter (DAC) control circuit configured to output a first digital code and a second digital code;a first digital-to-analog converter between a power supply voltage and the first data line, the first digital-to-analog converter configured to generate a first analog output in response to the first digital code;a second digital-to-analog converter between the power supply voltage and the second data line, the second digital-to-analog converter configured to generate a second analog output in response to the second digital code; anda sense amplifier configured to compare the first analog output and the second analog output and output the comparison result.2. The security device of claim 1 , ...

MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT

A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor. 1. (canceled)2. A memory element comprising:a volatile memory circuit;a sense amplifier comprising an output terminal electrically connected to an input terminal of the volatile memory circuit; anda first circuit and a second circuit each comprising an input terminal electrically connected to an output terminal of the volatile memory circuit and an output terminal electrically connected to the sense amplifier,wherein the memory element is configured to hold data of the volatile memory circuit in the first circuit and the second circuit when power supply voltage to the memory element is stopped.3. A memory element comprising:a volatile memory circuit;a sense amplifier comprising an output terminal electrically connected to an input terminal of the volatile memory circuit;a first circuit and a second circuit each comprising an input terminal electrically connected to an output terminal of the volatile memory circuit and an output terminal electrically connected to the sense amplifier,wherein the memory element is configured so that the first circuit and the second circuit are controlled by a same control signal, ...

Memory system with uniform decoder and operating method of same

A memory system includes a memory array including a plurality of memory cells, and an encoder operatively coupled to the memory array, for encoding an original data element to be programmed into the memory cells into a uniform data element in which the number of “0”s approximately equals the number of “1”s.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an external command. The second semiconductor device provides a first supply voltage to a bit line sense amplifier. The first supply voltage is generated by using a precharge voltage in response to the external command during a first time period from a point in time when a precharge mode begins. The second semiconductor device also adjusts a voltage level of the first supply voltage during a second time period from a point in time when the first time period terminates to a point in time when an active mode begins. 1. A semiconductor system comprising:a first semiconductor device suitable for outputting an external command; anda second semiconductor device suitable for providing a first supply voltage to a bit line sense amplifier,wherein the first supply voltage is generated by using a precharge voltage in response to the external command during a first time period from a point in time when a precharge mode begins, andwherein a voltage level of the first supply voltage is adjusted during a second time period from a point in time when the first time period terminates to a point in time when an active mode enabling a word line begins.2. The system of claim 1 , wherein the second semiconductor device includes a command decoder suitable for decoding the external command to generate a precharge signal which is enabled in the precharge mode or an active signal which is enabled in the active mode.3. The system of claim 1 , wherein the second semiconductor device includes:a pre-pull-down control signal generation unit suitable for generating a first pre-pull-down control signal which is enabled during the first time period and a second pre-pull-down control signal which is enabled during the second time period; anda first supply voltage drive unit suitable for generating the first supply voltage by coupling an output node thereof to a ...

SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING A BIT LINE SENSE AMPLIFIER OF THE SAME

A semiconductor memory device includes a plurality of memory cells, a plurality of word lines and a plurality of bit lines, wherein each memory cell is coupled to a respective word line and bit line. The semiconductor memory device includes a plurality of sense amplifiers, wherein each sense amplifier is coupled to two bit lines. The semiconductor memory device is configured to receive a first positive supply voltage, a second positive supply voltage, and a negative supply voltage, and determine a low level of an amplified voltage based on the negative supply voltage in an operation of amplifying data in a memory cell. 1. A semiconductor memory device , comprising:a plurality of memory cells, a plurality of word lines and a plurality of bit lines, wherein each memory cell is coupled to a respective word line and bit line; anda plurality of sense amplifiers, wherein each sense amplifier is coupled to two bit lines,wherein the semiconductor memory device is configured to receive a first positive supply voltage, a second positive supply voltage, and a negative supply voltage, and determine a low level of an amplified voltage based on the negative supply voltage in an operation of amplifying data in a memory cell.2. The semiconductor memory device of claim 1 , wherein a ground voltage is used as a bit line precharge voltage.3. The semiconductor memory device of claim 1 , wherein the low level of the amplified voltage is a voltage level of the negative supply voltage.4. The semiconductor memory device of claim 1 , wherein a high level of the amplified voltage is half of a cell supply voltage.5. The semiconductor memory device of claim 1 , wherein when a word line is activated claim 1 , a voltage having a voltage level higher than half of a cell supply voltage added to a threshold voltage of a cell transistor is applied to a gate of the cell transistor included in each of the memory cells connected to the word line.6. The semiconductor memory device of claim 1 , wherein ...

EFFICIENT SENSE AMPLIFIER SHIFTING FOR MEMORY REDUNDANCY

A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column. 1. A memory , comprising:a plurality of columns arranged into a plurality of column bit groups ranging from a first column bit group to a last column bit group, each column bit group including at least a column for an even word and a column for an odd word, the plurality of columns being further arranged from a first column in the first column bit group to a last column in the last column bit group, wherein each column includes a sense amplifier and a read line, and wherein the sense amplifier is configured to drive the read line with a bit decision for the column;a redundant column following the last column, wherein the redundant column includes a redundant sense amplifier and a redundant read line, and wherein the redundant sense amplifier is configured to drive the redundant read line with a bit decision for the redundant column;a plurality of multiplexers corresponding to the plurality of columns, wherein the multiplexers are arranged from a first multiplexer corresponding to the first column through a last multiplexer corresponding to the last column, wherein the first multiplexer through a next-to-last multiplexer in the plurality of multiplexers is each configured to select between the read line from the multiplexer's corresponding column and a read line from an immediately-subsequent column to the multiplexer's corresponding column, and wherein the last multiplexer is configured to select between the read line from the last column and the redundant read line;a decoder configured to, responsive to a defect in a defective one of the columns, control the first multiplexer through a final multiplexer before the defective one of the ...

SEMICONDUCTOR STORAGE DEVICE

A memory includes a first and second cell storing first data and second or reference-data. A first and second bit-lines connected to the first and second cells respectively correspond to a first and second sense-nodes. A first transfer-gate is inserted/connected between the first bit-line and the first sense-node. A second transfer-gate is inserted/connected between the second bit-line and the second sense-node. A sense-amplifier is inserted or connected between the first and second sense-nodes. A preamplifier includes a first and second common-transistors. The first common-transistor applies a first power-supply voltage to either the first or the second sense-node according to the first and second data or according to the first and reference-data during a data-read-operation. The second common-transistor applies a second power-supply voltage to the other sense-node out of the first and second sense-nodes according to the first and second data or according to the first and reference data. 1. A semiconductor storage device comprising:a first memory cell storing first logical data;a second memory cell storing second logical data or reference data;a first bit line connected to the first memory cell;a second bit line connected to the second memory cell;a first sense node corresponding to the first bit line;a second sense node corresponding to the second bit line;a first transfer gate inserted or connected between the first bit line and the first sense node;a second transfer gate inserted or connected between the second bit line and the second sense node;a sense amplifier inserted or connected between the first sense node and the second sense node, the sense amplifier detecting a voltage difference between the first sense node and the second sense node, comparing a voltage of the first sense node with a voltage of the second sense node, or amplifying the voltage difference between the first sense node and the second sense node; anda preamplifier comprising a first common ...

Sensor amplifier, memory device comprising same, and related method of operation

A sense amplifier comprises a sense amplifying unit configured to be connected to a bitline and a complimentary bitline of a memory device, to sense a voltage change of the bitline in response to first and second control signals, and to control voltages of a sensing bitline and a complimentary sensing bitline based on the sensed voltage change. It further comprises a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal, a second isolation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the isolation signal, a first offset cancellation switch configured to connect the bitline with the sensing bitline in response to an offset cancellation signal, and a second offset cancellation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the offset cancellation signal.

SEMICONDUCTOR MEMORY INTEGRATED DEVICE HAVING A PRECHARGE CIRCUIT WITH THIN-FILM TRANSISTORS GATED BY A VOLTAGE HIGHER THAN A POWER SUPPLY VOLTAGE

Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage. 1. A semiconductor memory circuit comprising:a memory circuit region including:a pair of bit lines;a plurality of word lines;a plurality of memory cells, each of which is coupled to one of the bit lines and to one of the word lines, and including a first transistor having a first gate electrode and a first gate oxide film;a sense amplifier circuit coupled to the pair of bit lines to amplify a potential difference between the pair of bit lines so as to provide the pair of bit lines with a high-level potential and a low level-potential respectively, anda precharging circuit, including a second transistor having a second gate electrode and a second gate oxide film, and adapted to set the bit lines at an intermediate level when the plurality of memory cells are in a non-selected state, wherein the intermediate level is between the high-level potential and the low-level potential; anda peripheral circuit region including a third transistor having a third gate electrode and third gate oxide film,wherein the first gate oxide film has a first thickness which is thicker than that of the second gate oxide film,wherein the second gate oxide film and the third gate oxide film have substantially the same thickness,wherein a first voltage is applied ...

VALIDATION OF DRAM CONTENT USING INTERNAL DATA SIGNATURE

Systems, methods, and apparatus related to validating data stored in a memory system. In one approach, a DRAM stores data for a host device. A controller that manages the DRAM receives a command from the host device to generate a signature. The controller also receives data from the host device that indicates a region of the DRAM. In response to receiving the command, the controller reads data from the indicated region. A signature is generated by the controller based on the data read from the indicated region. The generated signature is sent to the host device in response to the command. 1. A system comprising:a dynamic random access memory (DRAM) configured to store data for a host device; and{'claim-text': ['receive, from the host device, a command to generate a signature, and data indicating a region of the DRAM for which the signature is to be generated;', 'in response to receiving the command, read data from the indicated region of the DRAM;', 'generate, based on the data read from the indicated region of the DRAM, the signature; and', 'store the signature in a first register;', 'in response to generating the signature, update a value stored in a second register from a first value to a second value, wherein the first value indicates that the signature has not been generated, and the second value indicates that the signature has been generated.'], '#text': 'a controller configured to:'}2. The system of claim 1 , wherein the second value further indicates that the signature is stored in the first register.3. The system of claim 1 , further comprising an address register configured to receive an address from the host device claim 1 , wherein the address includes at least a portion of the data indicating the region of the DRAM.4. The system of claim 1 , wherein:the DRAM comprises banks of memory arrays;the data indicating the region of the DRAM comprises a range for a first bank including a starting row and an ending row; andreading the data comprises reading data ...

APPARATUSES AND METHODS FOR COMPARING A CURRENT REPRESENTATIVE OF A NUMBER OF FAILING MEMORY CELLS

Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison. 1. An apparatus , comprising:an amplifier including an output stage and a plurality of transistors coupled to the output stage;a first buffer circuit coupled to the amplifier and configured to provide a buffered first current to the output stage; anda second buffer circuit coupled to the amplifier and configured to provide a buffered second current to the output stage,wherein the amplifier is further configured to amplify a difference between the buffered first current and the buffered second current and to provide an output signal responsive to the amplified difference.2. The apparatus of claim 1 , wherein the buffered first current is a buffered sense current claim 1 , and the buffered second current is a buffered reference current.3. The apparatus of claim 2 , wherein each of the first buffer circuit and the second buffer circuit include at least one current mirror.4. The apparatus of claim 1 , wherein the buffered first current is provided by the first buffer circuit based on a first current received and buffered by the first buffer circuit.5. The apparatus of claim 4 , wherein the first buffer circuit includes a current mirror configured to receive the first current and mirror the first current to another current mirror.6. The apparatus of claim 5 , wherein the current mirror includes two gate coupled p-channel field effect transistors claim 5 , and the other current mirror includes two gate coupled n- ...

MEMORY DEVICE WITH CONTROL AND TEST CIRCUIT, AND METHOD FOR TEST READING AND WRITING USING BIT LINE PRECHARGE VOLTAGE LEVELS

A memory device and a method for test reading and writing thereof are provided. A precharge voltage control circuit is based on the precharge reference voltage to provide a first precharge voltage and a second precharge voltage. A sense amplifier circuit is coupled between a bit line and a complementary bit line and configured to sense data of a memory cell coupled to the bit line, and also coupled to the precharge voltage control circuit to make the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage respectively, the first precharge voltage and the second precharge voltage are on the same voltage level during the precharge operation, but during a test write sensing period and a test read sensing period after the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are different. 1. A memory device , comprising:a precharge voltage control circuit, generating a first precharge voltage and a second precharge voltage based on a precharge reference voltage;a sense amplifier circuit, coupled between a bit line and a complementary bit line and configured to sense a data of a memory cell coupled to the bit line, and the sense amplifier circuit is coupled to the precharge voltage control circuit for the bit line and the complementary bit line respectively receiving the first precharge voltage and the second precharge voltage,wherein in a precharge operation, a voltage level of the first precharge voltage and a voltage level of the second precharge voltage are the same, and during a test write sensing period and a test read sensing period after the precharge operation, the voltage level of the first precharge voltage and the voltage level of the second precharge voltage provided by the precharge voltage control circuit to the bit line and the complementary bit line are different; anda test comparison circuit, coupled to the precharge voltage control circuit and ...

Offset compensation for ferroelectric memory cell sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

SEMICONDUCTOR MEMORY APPARATUS

A semiconductor memory apparatus includes a first memory cell electrically coupled to a word line and a bit line; a second memory cell electrically coupled to the word line and a bit line bar; a sense amplifier electrically coupled to the bit line and the bit line bar; and a switching unit configured to electrically couple the bit line and the bit line bar to an input/output line and an input/output line bar in response to a column select signal. 1. A semiconductor memory apparatus comprising:a first memory cell electrically coupled to a word line and a bit line;a second memory cell electrically coupled to the word line and a bit line bar;a sense amplifier electrically coupled to the bit line and the bit line bar; anda switching unit configured to electrically couple the bit line and the bit line bar to an input/output line and an input/output line bar in response to a column select signal.2. The semiconductor memory apparatus according to claim 1 , wherein the sense amplifier senses and amplifies a voltage difference of the bit line and the bit line bar.3. The semiconductor memory apparatus according to claim 1 , wherein the switching unit electrically couples the bit line to the input/output line and electrically couples the bit line bar to the input/output line bar when the column select signal is enabled.4. The semiconductor memory apparatus according to claim 1 ,wherein the first memory cell is transferred with charges of the bit line or transfers its charges to the bit line when the word line is enabled, andwherein the second memory cell is transferred with charges of the bit line bar or transfers its charges to the bit line bar when the word line is enabled.5. The semiconductor memory apparatus according to claim 2 , wherein claim 2 , when the sense amplifier senses and amplifies the voltage difference of the bit line and the bit line bar claim 2 , raises a voltage level of one of the bit line and the bit line bar claim 2 , and lowers a voltage level of the ...