MEMORY DEVICE WORD LINE DRIVERS AND METHODS

Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed. 1. A memory subsystem , comprising:semiconductor material of a first type;an array of memory cells;a set of local word line drivers formed using the semiconductor material of the first type, each of the local word line drivers in the set being coupled to a word line extending through the array of memory cells, each of the local word line drivers including at least one transistor, each of the at least one transistor of each of the local word line drivers being a transistor of a second type;a well of semiconductor material of a second type formed in the semiconductor material of the first type; anda global word line driver coupled to the word line extending through the array of memory cells, the global word line driver including a transistor of a first type formed using the well of the semiconductor material of the second type.2. The memory subsystem of wherein the material of the first type comprises a p-type substrate claim 1 , the transistor of the second type comprises an NMOS transistor claim 1 , the material of the second type comprises a n-type material claim 1 , and the transistor of the first type comprises a PMOS transistor and further wherein:the at least one NMOS transistor of each of the ...

DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME

A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin. 1. A semiconductor device comprising:a first fin and a second fin separated by a trench;a first conductor disposed in the trench and extending substantially parallel to a sidewall of the first fin and a sidewall of the second fin to form a first gate; anda second conductor disposed in the trench above the first conductor and extending substantially parallel the sidewall of the first fin and the sidewall of the second fin to form a second gate, wherein the second conductor is electrically isolated from the first conductor.2. The semiconductor device of claim 1 , comprising a first oxide disposed on a bottom surface of the trench and on the sidewalls of the first fin and second fin.3. The semiconductor device of claim 2 , comprising a second oxide disposed on the second gate and on the sidewalls of the first fin and second fin.4. The semiconductor device of claim 3 , comprising a first liner disposed on the first oxide and a second liner disposed on the second oxide.5. The semiconductor device of claim 4 , wherein the first liner and the second liner comprise tin nitride.6. The semiconductor device of claim 1 , wherein the first conductor and the second conductor comprising tin or tungsten.7. A method of fabricating a semiconductor device claim 1 , comprising:forming a first sidewall of a first fin, the first sidewall extending in a first direction;forming a second sidewall of a second fin, the second sidewall extending ...

Line driver circuits, methods, and apparatuses

Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers

Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

APPARATUSES AND METHODS FOR ADJUSTING DEACTIVATION VOLTAGES

Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage. 1. An apparatus , comprising:a voltage control circuit configured to receive an address and adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address,wherein the first voltage is a lower voltage than the second voltage.2. The apparatus of claim 1 , wherein the voltage control circuit is further configured to provide a deactivation voltage to an access line physically adjacent the access line associated with the target group of memory cells at the second voltage for at least a portion of an access of the target group of memory cells.3. The apparatus of claim 1 , wherein the voltage control circuit is further configured to adjust the deactivation voltage of the access line associated with the target group of memory cells from the second voltage to the first voltage a period of time after adjusting the deactivation voltage of the access line associated with the target group of memory cells from the first voltage to the second voltage.4. The apparatus of claim 1 , wherein the voltage control circuit is further configured to provide the second voltage to a bus while the access line associated with the target group of memory cells is activated.5. The apparatus of claim 1 , wherein the access line associated with the target group of memory cells claim 1 , a first access line physically adjacent the access line associated with the target group of memory cells claim 1 , and a second access line ...

APPARATUSES AND METHODS FOR REDUCING CURRENT LEAKAGE IN A MEMORY

Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. During an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value of the charge stored by the memory cell. After the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value of the charge stored by the memory cell. 1. An apparatus comprising:a memory including a memory cell, the memory including circuits having a floating body architecture; anda sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value stored by a memory cell coupled to the digit line, wherein, during an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value stored by the memory cell, and wherein, after the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value stored by the memory cell.2. The apparatus of claim 1 , wherein the sense amplifier circuit comprises a compensation circuit configured to select a first input voltage to be provided as the first voltage during the initial time period claim 1 , and wherein the compensation circuit is further configured to select a second input voltage to be provided as the second voltage ...

Double gated 4f2 dram chc cell and methods of fabricating the same

A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

MEMORY DEVICE WORD LINE DRIVERS AND METHODS

Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed. 1. A memory subsystem , comprising:a semiconductor material of a first type;a plurality of arrays of memory cells formed over semiconductor material of the first type and comprising a first array of memory cells and a last array of memory cells;a plurality of sets of local word line drivers formed using the semiconductor material of the first type, each of the local word line drivers being formed between respective adjacent ones of the plurality of arrays of memory cells, each of the local word line drivers in each set being coupled to a respective one of a plurality of word lines extending through the plurality of arrays of memory cells, each of the local word line drivers including at least one transistor, all of the transistors in the local word line drivers being of a first type;a well of semiconductor material of the second type formed in the semiconductor material of the first type; anda plurality of global word line drivers formed using the well of semiconductor material of the second type, each of the plurality of global word line drivers being coupled to a respective one of the plurality of word lines extending through the plurality of arrays of memory cells, each of the plurality of global ...

Method for planarizing a layer of material

A method for forming a planarized layer of material starts by providing a substrate (12). An integrated circuit layer (14) is formed overlying the substrate (12). A first layer of material (16) is formed overlying the integrated circuit layer (14). An etch stop layer (18) is formed overlying the layer of material (16) and etched to form sidewall formations or spacers. A second layer of material (20) is formed overlying the layer of material (16) and the etch stop layer (18). Planarization, polishing, or etch-back processing is performed using the etch stop layer (18) to endpoint. The resulting planarized layer has a thickness which is determined accurately by the etch stop layer (18).

Dynamic sense-refresh detector amplifier

A dynamic sense-refresh detector amplifier consists essentially of a cross coupled MOS transistor pair and two sets of load-refresh circuits which each include a capacitor and three MOS transistors. The load-refresh circuits eliminate the negative effect of threshold voltage losses on noise margin by allowing the memory cell from which information is read out and sensed to be refreshed to full 1 and 0 levels. A control terminal of a transistor of each load-refresh circuit is coupled to the transistor of cross coupled pair not associated with that load-refresh circuit. In addition, a voltage clamping transistor is used with each load device to further increase operating noise margins. The dynamic operation of the amplifier allows for relatively low power dissipation.

Local word line decoder for memory with 2 MOS devices

A method and a circuit are disclosed by which the semiconductor area is reduced that a local word line decoder for a memory array requires. This reduction in area size has been achieved by eliminating one transistor of a three transistor local wordline decoder and by reducing the number of inputs to the decoder from three to two. The reduction in inputs is made possible by the method of applying to one of the inputs, when low, a voltage signal v b which is at least one threshold lower than the voltage signal to the other input, when low. This voltage v b can be derived from the p-substrate bias voltage.

Clock circuit

CLOCK CIRCUIT ABSTRACT A clock generator circuit (10) receives an input signal PPC0 and generates a delayed clock output signal PC0. The circut (10) is set to an initial condition by a precharge signal PC0R prior to a transition of the input signal PPC0. A time delay signal is produced at a node (26) by operation of transistors (18, 28). The transition of the input signal PPC0 produces a bootstrapped voltage at a capacitor (68). The delay signal activates a transistor (80) to couple the bootstrapped voltage to the gate terminal of an output transistor (88). The gate terminal of the output transistor (88) is driven directly from a low voltage state to a boosted high voltage state. This causes the output signal PC0 to be driven from an initial low voltage state to the power supply voltage Vcc without intervening steps. The output transistors (88, 90) of circuit (10) are never activated at the same time, thereby preventing any current spike from being propagated through the circuit (10).

Trench buried bit line memory devices and methods thereof

A memory device such as a 6F 2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

Method and system for accelerating coupling of digital signals

A system and method for coupling read data signals and write data signals through I/O lines of a memory array. Precharge circuits precharge alternating signal lines to high and low precharge voltages. An accelerate high circuit coupled to each of the I/O lines that has been precharged low detects an increase in the voltage of the I/O line above the precharge low voltage. The accelerate high circuit then drives the I/O line toward a high voltage, such as V CC . Similarly, an accelerate low circuit coupled to each of the I/O lines that has been precharged high detects a decrease in the voltage of the I/O line below the precharge high voltage. The accelerate low circuit then drives the I/O line to a low voltage, such as ground.

Delay-locked loop circuit and method using a ring oscillator and counter-based delay

A delay-locked loop includes a ring oscillator that generates a plurality of tap clock signals, with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. The oscillator clock signal clocks a coarse delay counter to develop a coarse delay count that determines a coarse delay of a delayed clock signal. A fine delay of the delayed clock signal is determined by selecting one of the tap clock signals of the ring oscillator. The phase between an in put clock signal and the delayed clock signal is determined and the coarse and fine delays adjusted in response to this phase to synchronize the delayed and input clock signals. The delay-locked loop may also monitor rising and falling edges of the input clock signal and develop corresponding rising-edge and falling-edge fine delays to synchronize rising and failing edges of the input clock signal.

Synchronous mirror delay (smd) circuit and method including a counter and reduced size bi-directional delay line

A synchronous mirror delay (SMD)includes a model delay line that is coupled to a bi-directional delay line. In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The SMD thereafter operates in a forward delay mode to alternately operate the bi-directional delay line in a forward mode and a backward mode to propagate the initial edge of the input clock signal through the bi-directional delay line and delay the initial edge of the input clock signal by a forward delay. In response to a subsequent edge of the input clock signal, the SMD mirrors the propagation of the input clock signal through the bi-directional delay line during the forward mode and further delay the initial edge of the input clock signal by a backward delay that is substantially equal to the forward delay.

Integrated circuit having a variably boosted node

INTEGRATED CIRCUIT HAVING A VARIABLY BOOSTED NODE Abstract An integrated circuit comprises a node that is boosted by one or more boost capacitors depending on the level of the power supply voltage. When the level is below a given threshold, a first boost capacitor is activated. Additional boost capacitors may be provided for activation at still lower thresholds. The boost capacitors are deactivated when the power supply level exceeds the corresponding thresholds. In this manner, a more constant boosted voltage is obtained. This provides for an adequate boosted voltage at low power supply levels, while avoiding excessive boost at high power supply voltages that could damage devices. The technique may be used for boosted row conductors in dynamic random access memories, among other applications.

Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays

Apparatus and method for a current limiting bleeder device that is shared between columns of different memory arrays and limits a current load on a voltage supply to prevent failure of an otherwise repairable memory device. The memory device includes first and second memory arrays having memory cells arranged in rows and columns where each of the columns of the first and second memory arrays have a equilibration circuit to precharge the respective column. A bleeder device is coupled to a precharge voltage supply and further coupled to at least one equilibration circuit of a column in the first memory array and to at least one equilibration circuit of a column in the second memory array to limit the current drawn by the equilibration circuits from the precharge voltage supply.

Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line

A synchronous mirror delay (SMD)includes a model delay line that is coupled to a bi-directional delay line. In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The SMD thereafter operates in a forward delay mode to alternately operate the bi-directional delay line in a forward mode and a backward mode to propagate the initial edge of the input clock signal through the bi-directional delay line and delay the initial edge of the input clock signal by a forward delay. In response to a subsequent edge of the input clock signal, the SMD mirrors the propagation of the input clock signal through the bi-directional delay line during the forward mode and further delay the initial edge of the input clock signal by a backward delay that is substantially equal to the forward delay.

Synchronous mirror delay(smd) circuit and method including a counter and reduced size bi-directional delay line

Multiple-depth STI trenches in integrated circuit fabrication

Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.

Fast column access memory

A dynamic random access memory obtains improved access time for reading data from a multiplicity of memory cells along a given selected row. This is obtained by allowing the output data line to remain active between activations of a column enable signal. An increase in data valid time at the memory output is obtained, while allowing increased latitude in memory address setup time.

Methods of reducing coupling noise between wordlines

Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.

Method and system for accelerating coupling of digital signals

A system and method for coupling read data signals and write data signals through I/O lines of a memory array. Precharge circuits precharge alternating signal lines to high and low precharge voltages. An accelerate high circuit coupled to each of the I/O lines that has been precharged low detects an increase in the voltage of the I/O line above the precharge low voltage. The accelerate high circuit then drives the I/O line toward a high voltage, such as V CC . Similarly, an accelerate low circuit coupled to each of the I/O lines that has been precharged high detects a decrease in the voltage of the I/O line below the precharge high voltage. The accelerate low circuit then drives the I/O line to a low voltage, such as ground.

Interconnection structure for conductive layers

An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).

A double gated 4F2 DRAM CHC cell and methods of fabricating the same

Synchronous mirror delay (smd) circuit and method including a counter and reduced size bi-directional delay line

A synchronous mirror delay (600) includes a model delay line (610) that is coupled to a bi-directional delay line (602). In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The SMD thereafter operates in a forward delay mode to alternately operate the bi-directional delay line in a forward mode and a backward mode to propagate the initial edge of the input clock signal through the bi-directional delay line and delay the initial edge of the input clock signal by a forward delay. In response to a subsequent edge of the input clock signal, the SMD mirrors the propagation of the input clock signal through the bi-directional delay line during the forward mode and further delay the initial edge of the input clock signal by a backward delay that is substantially equal to the forward delay.

VOLTAGE GENERATOR CIRCUIT

L'invention concerne les générateurs de tension. Un circuit générateur de tension 10 fait apparaître sur une borne de sortie 28 une tension supérieure à la tension d'alimentation disponible VDD. Dans ce générateur, des transistors MOS Q1 et Q5 font fonction de condensateurs, et ils emmagasinent une charge qui permet d'élever la tension d'alimentation lorsqu'un signal à deux niveaux est appliqué sur la borne d'entrée 12. Application aux mémoires vives dynamiques en technologie MOS. The invention relates to voltage generators. A voltage generator circuit 10 causes a voltage greater than the available supply voltage VDD to appear on an output terminal 28. In this generator, MOS transistors Q1 and Q5 act as capacitors, and they store a charge which makes it possible to raise the supply voltage when a two-level signal is applied to the input terminal 12. Application to memories vibrant dynamics in MOS technology.

Synchronous mirror delay (smd) circuit and method including a counter and reduced size bi-directional delay line

A synchronous mirror delay (600) includes a model delay line (610) that is coupled to a bi-directional delay line (602). In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The SMD thereafter operates in a forward delay mode to alternately operate the bi-directional delay line in a forward mode and a backward mode to propagate the initial edge of the input clock signal through the bi-directional delay line and delay the initial edge of the input clock signal by a forward delay. In response to a subsequent edge of the input clock signal, the SMD mirrors the propagation of the input clock signal through the bi-directional delay line during the forward mode and further delay the initial edge of the input clock signal by a backward delay that is substantially equal to the forward delay.

Memory structure having volatile and non-volatile memory portions

Memory structure having volatile and non-volatile memory portions

A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non- volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non- volatile memory portions, transferring data from the non- volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.

BicMOS device having a bipolar transistor and a MOS triggering transistor

The present invention includes a BiMOS device having an MOS transistor that triggers a bipolar transistor, wherein the base and channel region are formed within a well region that electrically floats. The present invention also includes a BiMOS device having separate regions for the collector and drain regions and for the base and channel regions. The present invention further includes processes for forming the BiMOS devices. The BiMOS device may include a floating well region. The BiMOS device may include both low voltage MOS logic transistors and a high voltage or high power bipolar transistor. A low voltage or low power bipolar transistor may also be used. Separate drain, collector, base, and channel regions allow the bipolar transistor performance to be optimized independently of the MOS transistor, which may have its performance independently optimized, too. A plurality of MOS logic transistors, such as an AND or an OR gate may be used in the BiMOS device.

Input buffer of integrated circuit

Formation method for step-up node of boot strap circuit on a semiconductor substrate

具有揮發性及非揮發性記憶體部分之記憶體結構

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Switch level simulation with cross-coupled devices

Double gated 4F2 dram CHC cell and methods of fabricating the same

A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.