Umfangreiche Datenbusarchitektur

LESEVERSTÄRKER FÜR NICHT-FLÜCHTIGEN HALBLEITERSPEICHER

Speichervorrichtung mit dynamisch betriebenen Bezugsschaltungen

Diese Erfindung betrifft eine Halbleiterspeichervorrichtung, die umfasst: zumindest eine Leseverstärkerschaltung (SAi) zum Lesen von Daten, die aus ausgewählten Speicherzellen in einem Speicherarray erfasst werden, zumindest eine Bezugsschaltung (RSAj), wobei jede Bezugsschaltung (RSAj) eine Nachbildung der Leseverstärkerschaltung (SAi) ist und einen Ausgang (OUTj) aufweist, durch den die Bezugsschaltung (RSAj) eine physikalische Ausgangsgröße liefert, ein Regelnetzwerk, das jede Leseverstärkerschaltung (SAi) und jede Bezugsschaltung (RSAj) mit einem Regelsignal (REG) versorgt, wobei das Regelsignal (REG) aus einer Durchschnittswertbildung der physikalischen Ausgangsgröße über die Zeit und/oder den Raum abgeleitet ist, wobei das Regelnetzwerk eine Steuereinheit (CU) umfasst, die ausgebildet ist, die physikalischen Größen jedes Ausgangs (OUTj) der Bezugsschaltung (RSAj) und einen Zielmittelwert zu summieren, wobei die Steuereinheit ein Regelsignal (REG) basierend auf der Summe liefert, wobei ...

Speichereinheit unter Verwendung eines Speicherelements mit variablem Widerstand und Verfahren zum Bestimmen des Referenzwiderstandes davon

DETEKTIONSSCHALTUNG ZUR LADUNGSVERTEILUNG IN ANTISICHERUNGEN

Halbleiteranordnung

Halbleiteranordnung mit: einem Abtastverstärker (44), welcher auf den Empfang eines Lesefreigabesignals ein Signal verstärkt; einer Verzögerungseinheit (52, 54), welche eine Mehrzahl von Übertragungspfaden mit unterschiedlichen Verzögerungszeiten bereitstellen kann und das Lesefreigabesignal durch einen Übertragungspfad entsprechend einem Wahlsignal aus der Mehrzahl von Übertragungspfaden überträgt; gekennzeichnet durch eine Befehlssignalerzeugungsschaltung (122, 124), welche der Verzögerungseinheit (52, 54) als Befehlssignal ein ODER-Ergebnis einer Verknüpfung eines vorbestimmten Maximalverzögerungsbefehlssignals, welches zum Zwecke der Aufnahme eines Übertragungspfads mit der maximalen Verzögerungszeit als Übertragungspfad für das Lesefreigabesignal ausgegeben wird, und eines willkürlichen Wahlsignals zuführt, welches zum Zwecke der Wahl eines willkürlichen Übertragungspfads als Übertragungspfad für das Lesefreigabesignal ausgegeben wird.

Halbleiterspeichervorrichtung mit übersteuertem Leseverstärker und Halbleitervorrichtung

Verfahren zur Leserverstärkersteuerung

Verschachtelte Bewerterschaltung mit einseitiger Vorladungsschaltung

Dynamisches Multipegelspeicherbauelement und Verfahren zum Treiben eines dynamischen Multipegelspeicherbauelements

Die Erfindung bezieht sich auf ein dynamisches Multipegelspeicherbauelement, das eine offene Bitleitungsstruktur aufweist, und auf ein Verfahren zum Treiben desselben. Das dynamische Multipegelspeicherbauelement umfasst eine Mehrzahl von Wortleitungen (WL), eine Mehrzahl von Bitleitungen (BL), die in einer offenen Bitleitungsstruktur angeordnet sind, eine Mehrzahl von Speicherzellen, wobei jede Speicherzelle mit einer der Wortleitungen (WL) und mit einer der Bitleitungen (BL) verbunden ist und dazu konfiguriert ist, wenigstens zwei Daten-Bits zu speichern, und eine Mehrzahl von Abtastverstärkern (SA_M, SA_S), die jeweils eine Spannungsdifferenz zwischen den Bitleitungen (BL) verstärken, wobei die Bitleitungen (BL) auf gegenüberliegenden Seiten eines jeweiligen Abtastverstärkers der Mehrzahl von Abtastverstärkern (SA_M, SA_S) angeordnet sind. Verwendung z. B. in der Speichertechnologie.

Read-out device for dynamic magnetic stores

... 1,084,758. Magnetic recording heads; local circuits. SOCIETE D'ELECTRONIQUE ET D'AUTOMATISME. Aug. 20, 1965 [Oct. 8, 1964], No. 35902/65. Heading G5R. To improve the realizable packing density of binary digital signals on a magnetic tape, the respective outputs of a balanced playback head 1 are fed to a pair of delay lines 6-9, 10-13 terminated by their characteristic impedances 19, 20, whose length is a fraction (preferably a half) of the characteristic period of the shortest recorded digital period. The delay elements are balanced symmetric. ally about the mid-point 11-12 of one of them and appropriate fractions of the tapping points are summed by resistors 14-18, whose output is fed to known reconstitution circuitry. Additional delay elements 2, 3, adjustable by varying-direct currents I c in their secondary windings may be used to balance lack of symmetry in the head outputs and to set a desired overall phase delay for the playback system.

High-speed sense amplifier for semiconductor memory device

Bitline level insensitive sense amplifier

A sense amplifier (221) for detecting the difference in voltage between two bitlines (113, 115) of a momory circuit. The sense amplifier is comprised of a differential amplifier (201, 203) which is coupled to the two bitlines (113, 115) and generates an output signal based on voltage levels sensed in the bitlines (113, 115). The differential amplifier (201, 203) is coupled to Vcc and ground through an active load (205, 207) and a current source (209) respectively. To address the problem of increased common mode voltage levels found in the bitlines (113, 115), a pair of transistors (223, 225) are connected in parallel across the active load (205, 207) to Vcc and the differential amplifier (202, 203). The gate of one of the transistors is coupled to one of the bitlines (113, 115) and the gate of the other one of the transistors is coupled to the other one of the bitlines (113, 115). With these two transistors (223, 225) coupled in parallel across the load (205, 207) as described, the differential ...

Matchline sense circuit and method

Leakage-tolerant dynamic wide-nor circuit structure

Sense amplifiers with high voltage swing

Sense amplification in data memories

VOLTAGE SENSING CIRCUITS

... 1535237 Transistor bistable circuits TELETYPE CORP 25 Feb 1976 [5 March 1975] 07526/76 Heading H3T In a bistable sense amplifier comprising FET's Q3, Q4 a first control FET Ql fed with the signal being sensed is coupled in parallel with Q3, a second control FET Q2 fed with a reference potential is coupled in parallel with Q4, and means are provided for equalizing the potentials at the gates of the two control FET's during one period of a sensing cycle. The circuit is used as a read/write amplifier for a matrix of capacitive storage elements e.g. C M-1 , C M-2 . Before reading or writing, ° 1 is brought to - V volts turning on transistors Q5, Q6, Q7 to equalize the voltages at points A, B, C, D to - V R which is midway between 0 and - V c volts, this turning transistors Q1 . . . Q4 partially on to act as resistance elements. At the end of this preset period ° 1 goes to 0 volts, to turn off Q5, Q6, Q7, and the required cell is selected by energizing the appropriate Y conductor and X decoder ...

DRAM WITH HALF ONE AND FULL ONE DENSITY ENTERPRISE

DOUBLE LOOPS READ PATTERN FOR RESISTANCE MEMORY CELLS

READ AMPLIFIER FOR NON VOLATILE INTEGRATED MULTI-LEVEL MEMORY MODULES

MRAM ARCHITECTURE WITH A WITH MASS CONNECTION WRITE BIT ORGANIZATION AND AN ELECTRICALLY INSULATING READ BIT ORGANIZATION

NON VOLATILE MEMORY AND SELECTION PROCEDURE

DEVICE FOR CURRENT MEASUREMENT DURING THE READING OF A MEMORY CELL

NON VOLATILE MEMORY AND PROCEDURE WITH SOURCE LINE ERROR COMPENSATION

ALTERNATING CURRENT MEASUREMENT FOR A RESISTIVEN A MEMORY

DETECTION CIRCUIT FOR CHARGE PATTERN IN ANTI-SAFETY DEVICES

CASCODE SENSE AMP AND COLUMN SELECT CIRCUIT AND METHOD OF OPERATION

Matchline sense circuit and method

Sense amplifier with improved latching

Synchronous integrated circuit device

METHOD AND SYSTEM FOR POWER SIGNATURE SUPPRESSION IN MEMORY DEVICES

A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.

Elektromechanischer, insbesondere elektroakustischer Wandler

Magnetisches Wiedergabesystem

Schaltungsanordnung für das Ablesen von binären magnetischen Registrierungen

Dual loop sensing scheme for resistive memory elements

A method and apparatus for sensing a resistive state of a resistive memory element includes producing a first current related to a resistance of a memory cell. The first current is added to a second current during a first sensing time and subtracted from a third current during a second sensing time. The first, second and third currents are integrated over time using a capacitor, and a resulting voltage signal on the capacitor is timed using a clocked counter. A time average value of a digital output of the clocked counter is then related to the resistance of the memory cell, and hence to the resistive state of the resistive memory element.

Nano-sense amplifier for memory

DIFFERENTIAL AMPLIFIER HAVING A SHORT RESPONSE TIME

DEVICE SEMICONDUCTOR MEMORY

Integrated memory e.g. SRAM, circuit, has dummy path with reference column having two reference bit lines, where one bit line discharged by drain currents of access transistors in their off state controls activation of read amplifier

Le circuit intégré comprend un dispositif de mémoire comportant un plan mémoire et un chemin de référence destiné à auto-ajuster temporellement la délivrance d'un signal d'activation des amplificateurs de lecture respectivement disposés aux pieds des colonnes du plan mémoire. Le chemin de référence (CHR) comporte des cellules-mémoire de référence respectivement connectées entre deux lignes de bits de référence (bltdum, blfdum), des moyens de sélection (WLD) d'au moins une cellule de référence (CELR1) destinée à décharger une première ligne de bit de référence (bltdum), la deuxième ligne de bit de référence (blfdum) étant parcourue par un courant de fuite, et des moyens de commande (MC) connectés aux deux lignes de bits, et à délivrer ledit signal d'activation (SCA) lorsque la valeur absolue de la différence entre les valeurs des tensions sur les deux lignes de bits de référence dépasse un seuil prédéterminé.

Detection circuit without return to zero to only one way

READ CIRCUIT FOR RESISTIVE MEMORY

L'invention concerne un circuit de lecture pour lire un état résistif programmé d'éléments résistifs (102) d'une mémoire résistive (101), chaque élément résistif étant programmable pour prendre l'un d'un premier et d'un deuxième état résistif (Rmax, Rmin), le circuit comprenant un intégrateur de courant (122) adapté à intégrer une différence de courant entre un courant de lecture (IR) passant dans un premier des éléments résistifs et un courant de référence (IREF).

OUTPUT SENSE AMPLIFIER FOR A MULTIBIT MEMORY CELL

SEMICONDUCTOR MEMORY DEVICE

DIFFERENTIAL READ-ONLY MEMORY(ROM) DEVICE

SEMICONDUCTOR MEMORY APPARATUS AND ACTIVATION SIGNAL GENERATION METHOD FOR SENSE AMPLIFIER

FeRAM having differential data

SEMICONDUCTOR MEMORY DEVICE

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH INTERNAL VOLTAGE DROP CIRCUIT

SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MINIMIZING A WRITING CURRENT AND A WRITING TIME

PURPOSE: A semiconductor memory device is provided to increase a writing speed by minimizing the number of memory cells, which are activated during a writing process. CONSTITUTION: A memory cell array(10) includes a normal memory cell block and a flag memory cell block. The normal memory cell block includes plural unit memory cells and stores data. The memory cell block includes plural flag memory cells storing write flag states for the memory cells in the normal memory cell block. A verify read circuit(25) performs a data read process while referring to a flag state of the flag memory cell corresponding to the data stored in the normal memory cell block. A comparator(26) compares the write data to be stored in the normal memory cell block with the data obtained from the verify read circuit. A write circuit determines the state for minimizing the number of memory cells to be written according to a compared result from the comparator and performs the write process with the write data. © ...

METHOD FOR STORING INFORMATION ON A MEMORY CELL

DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER

SEMICONDUCTOR MEMORY DEVICE

The present invention relates to a semiconductor memory device. The semiconductor memory device may include a detection/amplification unit that detects and amplifies data carried in a pair of data lines by using a pull-up driving voltage and a pull-down driving voltage; a pull-up driving unit that supplies a first voltage as the pull-up driving voltage for a first active section in an active mode, supplies a second voltage that is lower than the first voltage as the pull-up driving voltage for a second active section, and supplies the first voltage as the pull-up driving voltage for a third active section; and a pull-down driving unit that supplies a third voltage as the pull-down driving voltage for an entire section of the active mode and an initial section of a pre-charge mode. Since a refresh period can be improved as data retention time is improved, a performance of the refresh operation can be improved. COPYRIGHT KIPO 2016 (470) Pulldown control unit ...

감지 회로를 사용한 패리티 결정을 위한 장치들 및 방법들

... 본 개시는 감지 회로를 사용한 패리티 결정들에 관련된 장치들 및 방법들을 포함한다. 예시적인 방법은 감지 회로를 사용하여, 입력/출력 라인을 통해 어레이로부터 데이터를 전송하지 않고 다수의 데이터 값들에 대응하는 패리티 값을 결정함으로써 어레이의 감지 라인에 결합된 각각의 수의 메모리 셀들에 저장된 다수의 데이터 값들을 보호하는 단계를 포함할 수 있다. 패리티 값은 예를 들어, 다수의 XOR 연산들에 의해 결정될 수 있다. 방법은 감지 라인에 결합된 또 다른 메모리 셀에 패리티 값을 저장하는 단계를 포함할 수 있다.

MEMORY DEVICE AND OPERATION METHOD THEREOF

A memory device includes: a cell array having multiple memory cells and a bit line connected to the same; a sense amplifier for amplifying voltage difference between a first line and a second line; and a separation unit for connecting the bit line and the first line and separating the bit line and the first line during initial operation section of the sense amplifier. COPYRIGHT KIPO 2016 ...

MEMORY DEVICE HAVING A DIRECT SENSE CIRCUIT

PURPOSE: The memory device having a direct sense circuit is provided to use commonness column decoder and sense buffer circuit in a plurality of memory block. CONSTITUTION: In the memory device having a direct sense circuit, when a memory block 0 is activated a direct sense activation circuit 20 which composed against sense circuit line 12A activate a direct sense operating line to answer an activated lead bus line of a control circuit. The plurality of memory block arrayed perpendicular to a sense circuit column. The plurality of memory block located between the column decoder 13 and the sense buffer circuit 15 and located a word decoder 11 at an edge side. COPYRIGHT 2000 KIPO ...

AC SENSING FOR A RESISTIVE MEMORY

Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array. The peripheral circuitry can include a clock/control circuit providing a control signal, which controls when a row of memory cells are sensed, a switching circuit for receiving a cellplate count signal and a bit count signal provided by the clock/control circuit, a cellplate line signal and a bit line signal from the memory cell, the switching circuit producing a first output signal and a second output signal, wherein one of the first output signal and the second output signal is at a supply voltage and the other of the first output signal and the second output signal alternates polarity with each sensing operation and a comparison circuit receiving the first output signal and the second output signal and outputting a signal corresponding ...

MEMORY DEVICE

PURPOSE: A memory device is provided to reduce a delay of a read operation start timing by a write operation although a write frequency is identical to a read frequency. CONSTITUTION: A memory device comprises a memory cell array(6), transfer gate(TG)s(7,8),amplifiers(9,10) having a data holding function, a data selector(11), and a precharge circuit(14). The memory cell array(6) consists of a plurality of memory cells(5). Each memory cell(5) is defined by a word line and a bit line. The precharge circuit(14) is controlled responsive to a precharge signal(15), and initializes a bit line pair(12) so as to have the same potential. The transfer gate(7) connects or isolates the bit line pair(12) and the amplifier(9) in response to a select signal(16), and the transfer gate(8) connects or isolates the bit line pair(12) and the amplifier(10) in response to a select signal(17). The amplifiers(9,10) amplifies and holds a potential difference of the bit line pair(12) in response to corresponding ...

Memory device, method of performing read or write operation and memory system including the same

Nonvolatile memory, memory system, computer system, and operating method of nonvolatile memory

System and method of operating a memory device

A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.

Dynamically adaptable memory

In an environment wherein a microprocessor can operate at several different voltage levels depending upon the instantaneous throughput of the microprocessor, a memory and memory adjustment circuit that permits operating the memory at a plurality of voltages in response to the microprocessor is disclosed. The memory and memory adjustment circuit sense the instantaneous operating voltage of the microprocessor and adjust the operating voltage of the memory in response thereto. The memory adjustment circuit more particularly increases or decreases the memory's bitline sense interval in response respectively to a decrease or increase in the memory's operating voltage.

Apparatuses and methods for in-memory operations

The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The apparatus also includes a controller configured to direct a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset and performance of a sequential plurality of operations in-memory on the number of data values by the first sensing circuitry coupled to the first subset.

Random number generator with antifuse differential cell and associated sensing method

A random number generator includes a cell array including a plurality of antifuse differential cells; and a sensing circuit having an input terminal and an inverted input terminal. When a first antifuse differential cell of the cell array is selected as a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit, and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read action, the sensing circuit is capable of determining a storing state of the selected cell and one bit of a random code according a first charging current flowing through the bit line and a second charging current flowing through the inverted bit line.

Apparatuses and methods including memory and operation of same

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Read assist circuitry

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include precharge circuitry for precharging bitlines to a source voltage level. The integrated circuit may include write assist circuitry having a charge storage element for providing a write assist signal to at least one of the bitlines. The integrated circuit may include read assist circuitry having a switching element for providing charge sharing between the bitlines, the precharge circuitry, and the charge storage element of the write assist circuitry.

PROGRAMMABLE DELAY CONTROL IN A MEMORY

Inductive amplifier

A kind of inductive amplifier which applies to a semiconductor memory component. When the active signal of inductive amplifier is "H", the NMOS is conducted and activate the inductive amplifier. When the data signal Sda is "H" and data signal Sdb is "L", node NA will be "H" and node NB will be "L". The sources of each NMOS, i.e. the level of node NC and ND, are independently alternating according to the data signal Sda and Sdb. Therefore, the voltage of node ND will be reduced to the grounding and the voltage of node NB will be lower and the voltage of node NA will be higher. The voltage of node NA is outputted from the inverter composed of PMOS and NMOS to an output port OUTa. Similarly, the voltage of node NB in outputted from the inverter composed of PMOS and NMOS to an output port OUTb.

Method for measuring offset voltage of sense amplifier and semiconductor memory device employing the method

A semiconductor memory device precisely measures offset voltage of bit line sense amplifier. The semiconductor memory device of the present invention includes: a bit line sense amplifier for amplifying a voltage difference between a bit line and an inversion bit line, which carry date written on a memory cell upon read of the data; a data input/output line and an inversion data input/output line within a core region coupled to the bit line and the inversion bit line via one or more switches; a first external voltage supply pad connected to the data input/output line; a second external voltage supply pad connected to the inversion data input/output line; and an external voltage supply controller for switching a connection of the data input/output line and the first external voltage supply pad and a connection of the inversion data input/output line and the second external voltage supply pad.

Reference sense amplifier and method for compensated sensing in non-volatile memory

Low voltage operation of static random access memory

An integrated circuit having a microprocessor core and a memory block that may operate at different voltages. A voltage regulator, either external to the integrated circuit or designed as part of the integrated circuit, generates the two voltages. The operating voltage for the microprocessor core is selected to satisfy power and performance criteria while the operating voltage for the memory block is set to provide acceptable noise margins and maintain stability of the memory cells within the memory block.

APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

MEMORY MODULE WITH HIERARCHICAL FUNCTIONALITY

A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n-1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle ...

HIGHLY COMPACT NON-VOLATILE MEMORY AND METHOD THEREOF

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.

REDUCING THE POWER CONSUMPTION OF MEMORY DEVICES

Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.

Control clocks generator and method thereof for a high speed sense amplifier

A control clocks generator and method thereof for a high speed sense amplifier generates control clocks by utilizing RC delay and gate delay, in combination with reference sensing delay induced from a reference sense amplifier, and thereby, is tracking well for the high speed sense amplifier with process, temperature and voltage variations.

Semiconductor memory device and method of controlling the same

In a semiconductor memory device including a bank equipped having a predetermined memory capacity, a sub amplifier block is disposed at a center of the bank divided into two sections. The sub amplifier block includes a plurality of sub amplifiers connected to sense amplifier sets disposed in the two memory regions through an LIO and a sub amplifier control circuit for controlling the sub amplifiers. If the sub amplifier control circuit selects a word line, a control operation is performed to activate only one side of the sub amplifiers positioned on both sides of the word line to thereby reducce the power consumed for activating the sub amplifiers.

Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier

An integrated memory contains a memory cell array, which has word lines and bit lines, and a read/write amplifier, which is connected to the bit lines for the assessing and amplifying data signals. A voltage generator circuit generates a voltage supply for application to the read/write amplifier. A potential difference is applied to the read/write amplifier using different supply potentials. The voltage generator circuit increases the potential difference applied to the read/write amplifier for a limited period of time during an assessment and amplification operation of the read/write amplifier. Charge-dependent control is implemented in the voltage generator circuit. An assessment and amplification operation can be carried out at a comparatively high switching speed and a low power consumption is possible.

Method for reading a memory array with neighbor effect cancellation

There is provided in accordance with embodiments of the present invention a method of reducing the neighbor effect in reading data in a non-volatile memory array by sensing adjacent memory cells in a virtual ground array of memory cells comprising sensing substantially simultaneously a state of adjacent memory cells, wherein a bit stored in a charge trapping region of each cell of the adjacent memory cells is in an identical state.

SYSTEMS AND METHODS FOR SENSING A MEMORY ELEMENT

Methods, systems, and programs for recalibrating a sense amplifier are disclosed. A representative method includes: measuring a physical property of a memory cell to produce a first measurement; comparing the first measurement to a first range, the first range being indicative of a short or open circuit in the memory cell; halting the sense of the selected memory cell if the first measurement exceeds the first range; comparing the first measurement to a second range, the second range being a predetermined range signifying a recalibration of the sense amplifier may be necessary; proceeding with the sense if the first measurement is within the first range and the second range; repeating the steps of measuring and comparing for a predetermined number of iterations, if after each iteration, the measurement exceeds the second range but is within the first range; and recalibrating the sense amplifier, if after the predetermined number of iterations, the measurement still exceeds the second range ...

Semiconductor memory device for reducing noise in operation of sense amplifier

The present invention provides a semiconductor memory device for reducing operation noise, as a sense amplifier in accordance with the present invention senses and amplifies a supplied data signal of a bit line pair on high speed. For this object, the semiconductor memory device includes a first cell array including a plurality of unit cells to be selected by an address signal; a sense amplifying unit for sensing and amplifying voltage level of a bit line connected to the plurality of the unit cells; a switching unit for connecting or disconnecting the sense amplifying unit to the bit line; and a sense amplifying connection unit for controlling the switching unit for connecting or disconnecting the sense amplifying unit to the first cell array by increasing or decreasing an amount of current throughout the switching unit in response to the address signal.

Asynchronously-resettable decoder with redundancy

A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type

To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG-Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed. The leak circuit has ...

Serially accessible semiconductor memory with multiple level storage cells

According to this invention, in a data bit array for storing data, a plurality of memory cells capable of storing 4-level data are arranged in column and row directions. A check bit array for storing check data has a number of bits smaller than that of the data bit array. In the check bit array, a plurality of memory cells capable of storing 4-level data are arranged in column and row directions. A row address decoder selects one row from the check bit array and the data bit array in accordance with address data. Three sense amplifiers are connected to one column of the check bit array and the data bit array. The three sense amplifiers detect levels of data read from a memory cell in accordance with different reference levels in data read access, receive a plurality of precharge levels corresponding to 4-level write data, and write one of the precharged levels in the corresponding memory cell in accordance with write data. A data converter converts levels of data detected by the sense amplifiers ...

Methods and circuits for single-memory dynamic cell multivalue data storage

A multivalue dynamic random access memory cell and method therefor are provided. Sense circuitry for sensing a most significant bit (MSB) and a least significant bit (LSB) of a binary data value are coupled to an unsegmented complementary bitline pair. The binary data is represented by a multilevel voltage stored on a storage element in the DRAM cell. A reference signal is provided to the sense circuitry, wherein the reference signal is independent of a precharge on the bitline pair. Cross-coupling elements offset the reference signal in response to the sensing of the MSB, whereby the voltage levels corresponding to the LSB are sensed. Following a read, the multilevel data value is restored on the storage element by a restore/write unit including a programmable voltage supply. The detected MSB/LSB pair are input to the restore/write unit which outputs the corresponding voltage level to the DRAM cell. A write is effected using the same restore/write unit with the binary datum to be stored ...

Method and circuit for sharing sense amplifier drivers

A sense amplifier driver activates a plurality of sense amplifiers coupled to respective digit lines in each of a plurality of memory-cell arrays. The sense amplifiers each have first and second activation nodes. The sense amplifier driver includes a plurality of drive circuits each coupled to the first and second activation nodes of the sense amplifiers in at least one of the memory-cell arrays. The first activation nodes of the sense amplifiers in at least one of the memory-cell arrays are coupled to a plurality of drive circuits so that the plurality of drive circuits drive the first activation nodes of the sense amplifiers in at least one of the memory-cell arrays in parallel.

Semiconductor memory device having pull-down function for non-selected bit lines

In a semiconductor memory device constructed a memory cell array including a plurality of read-only memory cells connected to a plurality of bit lines, a plurality of sense amplifiers each including a first MOS trnasistor connected to one of the bit lines, a reference voltage generating circuit for applying a reference voltage to a gate of the first MOS transistor, and a bit line selection circuit, for generating a plurality of bit line selection signals for selecting the bit lines respectively, a plurality of second MOS trnasistors, each of which is connected between one of the bit lines and the ground terminal, is provided. Also, a plurality of inverters, are connected between the bit line selection circuit and the second MOS transistors, so that the second MOS transistors are controlled by inverted signals of the bit line selection signals.

Semiconductor random access memory device having shared sense amplifiers serving as a cache memory

A random access memory device has memory cell blocks, row address decoders respectively associated with the memory cell blocks, sense amplifier circuit arrays each shared between two of the memory cell blocks, and a column selecting unit for transferring a data bit from one of the sense amplifier circuit arrays to an output data buffer circuit, a flag generating unit for producing flag signals indicative of memory cell blocks supplying the data bits presently stored in the sense amplifier circuit arrays, and an address discriminating unit operative to examine block and row addresses supplied from the outside thereof to see whether or not an accessed data bit has been already stored in the sense amplifier circuit arrays, thereby allowing the shared sense amplifier circuit arrays to serve as a cache memory.

Read amplifier circuit for high-speed reading and semiconductor memory device employing the read amplifier circuit

A read amplifier circuit includes an equalize start circuit. Based on a preamp enable signal PAE and an equalize signal IOEQ, the equalize start circuit generates an equalize start signal EQ for starting equalization at the timing when the preamp enable signal PAE is activated. Simultaneously with activation of a preamplifier by the preamp enable signal PAE, a pair of read lines GIOR and /GIOR is cut off from the preamplifier, and a P channel MOS transistor starts equalization of the pair of read lines GIOR and /GIOR. In this way, it is possible to start equalization of the paired read lines at the same time that the output signal is supplied to the preamplifier.

SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DIFFERENTIAL SIGNAL TRANSMISSION STRUCTURE AND METHOD FOR DRIVING THE SAME

A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal. 1. A semiconductor integrated circuit , comprising:an input data line pair;a sense amplifier configured to sense and amplify data loaded on the input data line pair and output the amplified data to an output data line pair, in response to a control signal; anda sense amplification controller configured to detect an amplification level on the output data line pair, and output the control signal for controlling the sense amplifier based on a sense amplification enable signal and the detected amplification level.2. The semiconductor integrated circuit of claim 1 , wherein the sense amplification enable signal is activated during a predetermined period in response to a command.3. The semiconductor integrated circuit of claim 1 , wherein the sense amplification controller comprises:a reset unit configured to reset a sensing node in response to the sense amplification enable signal;a sensing driving unit configured to sense voltage levels of the output data line pair and drive the sensing node to a predetermined voltage level; andan output unit configured to output the control signal in response to the sense amplification enable signal and a voltage on the sensing node.4. The semiconductor integrated circuit of claim 3 , wherein the reset unit comprises an NMOS transistor having a source coupled to a ground voltage terminal claim 3 , a drain coupled to the sensing node claim 3 , and a gate to receive an inverted sense amplification enable signal.5. The semiconductor integrated circuit of claim 3 , ...

SEMICONDUCTOR MEMORY DEVICE

The present disclosure relates to a semiconductor memory device. A charge recycling circuit is driven to raise a potential of a restore node and a sensing bar node to a given potential before a sensing operation is performed. After the sensing operation is performed, electric charges discharged from the restore node and from the sensing bar node are stored using the charge recycling circuit and can then be used when a next sensing operation is performed. Therefore, current consumed when the sensing operation is performed can be reduced and the power consumption can be thus reduced.

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Memory architecture with single-port cell and dual-port (read and write) functionality

A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e., the READ operation); globally selecting, the second memory location; concurrently with the globally selecting, globally sensing the first datum at the first memory location ...

Low voltage sense amplifier for operation under a reduced bit line bias voltage

A regulated charge pump, regulated by a plurality of capacitor boost stages and separate from the memory device supply voltage (Vcc), generates a regulated voltage (VSA) over a range of supply voltages. The regulated charge pump powers sense amplifier and differential amplifier circuits of the memory device to permit a low bit line bias voltage. The differential amplifier circuit generates a logical output to indicate a memory cell programmed state that is detected by the sense amplifier circuit.

Memory with low current consumption and method for reducing current consumption of a memory

A method for reducing current consumption of a memory is disclosed, wherein the memory includes a controller and a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. The method includes the controller enabling an activating command corresponding to a first row address and an address of a first bank of the plurality of banks; a word line switch of a segment of the first bank corresponding to the first row address being turned on according to the activating command; the controller enabling an access command corresponding to an address of the segment; a plurality of bit switches corresponding to the segment being turned on according to the access command; and the controller enabling a pre-charge command corresponding to an address of a following segment and the address of the first bank after the access command is disabled.

Semiconductor memory device

Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines: after signal voltages were read out by the selecting operations of the word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with their individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. The switch MOSFETs, as fed with the intermediate potential at their gates, are turned ON as a result that sense nodes are set to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned from the intermediate potential level to the select level in response to the selecting operation of the ...

Driving signal control circuit and driving apparatus

A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal.

Techniques for reducing disturbance in a semiconductor memory device

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

Semiconductor memory apparatus having sense amplifier

Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

Method for improving writability of sram memory

A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Memory and method for sensing data in a memory using complementary sensing scheme

In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

Phase change memory device

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

Sense amplifier structure for a semiconductor integrated circuit device

A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.

Complementary read-only memory (rom) cell and method for manufacturing the same

A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Method for writing data in semiconductor storage device and semiconductor storage device

A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other.

Differential data sensing

A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Semiconductor memory device for minimizing mismatch of sense amplifier

A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized.

Maintenance of amplified signals using high-voltage-threshold transistors

Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

Semiconductor memory having staggered sense amplifiers associated with a local column decoder

A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.

Current-Sense Amplifier With Low-Offset Adjustment and Method of Low-Offset Adjustment Thereof

A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.

Sense Amplifier Apparatus and Methods

Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed.

Low voltage sensing scheme having reduced active power down standby current

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Semiconductor memory with sense amplifier

In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Random Access Memory Controller Having Common Column Multiplexer and Sense Amplifier Hardware

Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry is shared between the column multiplexer and the sense amplifier so that the memory controller includes a single instance of the common circuitry for the column multiplexer and sense amplifier pair. The common circuitry includes a common pre-charge circuit, a common equalizer, or a common keeper circuit.

Semiconductor device and semiconductor memory device

A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor.

Processor with memory delayed bit line precharging

A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.

Semiconductor memory device

In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced.

Amplifiers using gated diodes

A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal is coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.

Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits. 1. A method of complementary pairing of memory cells comprising:providing a set of at least two reference cells per erase block wherein a first reference cell has a value of ‘1’ and a second reference cell has a value of ‘0’; andcomparing a selected memory cell in said erase block to said two reference cells to determine whether said memory cell has a value of ‘0’ or ‘1’.2. The method according to wherein said comparing is performed by a sense amplifier wherein said sense amplifier performs a subtraction-like function in order to determine whether said selected memory cell's signal is closer to said first or second reference signal.3. The method according to wherein said comparing is performed by a data latch wherein said data latch performs a subtraction-like function in order to determine whether said selected memory cell's signal is closer to said first or second reference signal.4. The method according to wherein said subtraction-like function is performed by a voltage subtractor circuit.5. The method according to wherein:a first sense amplifier compares said selected memory cell to said first reference cell;a second sense amplifier compares said selected memory cell to said second reference cell; anda third sense amplifier compares outputs from said first and second sense amplifiers to each other to find the output with the largest delta voltage or current.6. The method according to wherein said first claim 5 , second claim 5 , and third sense amplifiers are voltage sense amplifiers or current sense amplifiers.7. The method according to wherein:a first voltage subtractor compares said selected memory cell to said first reference cell;a second voltage subtractor compares said selected memory cell to said ...

NANO-SENSE AMPLIFIER

A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. 1. A sense amplifier (nSA) of a series of cells (Ci , Cj) of a memory , including:{'b': 1', '2, 'a writing stage comprising a CMOS inverter (T-T), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, and'}{'b': '3', 'a reading stage comprising a sense transistor (T), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter,'}wherein one or more of the transistors are multigate transistors.2. The sense amplifier according to claim 1 , wherein at least one multigate transistor is a FinFET.3. The sense amplifier according to claim 1 , wherein the input of the writing stage is directly connected to the input terminal of the inverter claim 1 , said input terminal being intended to be connected to a main bitline (MBL) which will address a plurality of sense amplifiers in parallel.44. The sense amplifier according to claim 1 , wherein the reading stage comprises an additional transistor (T) complementary to the sense transistor claim 1 , the additional transistor and the sense transistor forming a CMOS inverter claim 1 , the input of which is connected to the output of the reading stage and the output of which is connected to the input of the inverter of ...

Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths

A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation. 1. An apparatus , comprising:an array of memory cells; a first discharge node coupled to discharge a charge on said at least one bit line; and', 'a second discharge node coupled to discharge a charge on said at least one bit line, the first discharge node and the second discharge nodes at different locations along said at least one bit line; and, 'a plurality of bit lines accessing the array of memory cells, at least one bit line of the plurality of bit lines each havingdischarge circuitry electrically connected to the first discharge node and the second discharge node of the at least one bit line coupled to provide multiple discharge paths, wherein the discharge circuitry coupled to the first discharge node and the discharge circuitry coupled to the second discharge node are controlled by different signals.2. The apparatus of claim 1 , further comprising:control circuitry providing the different signals for the at least one bit line of the plurality of bit lines at a same time.3. The apparatus of claim 1 , a first plurality of discharge transistors electrically connected to the first discharge nodes of the plurality of bit lines, such that different bit lines of the plurality of bit lines discharge the charge through different discharge transistors of the first plurality of discharge transistors, and', 'a second plurality of discharge transistors electrically connected to the second discharge nodes of the plurality of bit lines, such that different bit lines of the plurality of bit lines discharge the charge through different discharge transistors of the second plurality of discharge transistors., 'wherein the discharge circuitry includes4. The apparatus of claim 1 ,wherein the discharge path of the ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier that is disposed above or below the memory cell array to be overlapped with the memory cell array in a planar fashion, connected to at least one bit line connected to the at least one cell bit line, and at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell; a decompression unit for decompressing a signal having a lower voltage level from among a signal of the at least one bit line and a signal of the at least one complementary bit line; a boosting unit for boosting a signal having a higher voltage level from among the signal of the at least one bit line and the signal of the at least one complementary bit line; and an equalizing unit for equalizing the signal of the at least one bit line and the signal of the at least one complementary bit line. 1. A semiconductor memory device comprising:a memory cell array that is disposed at a first layer and comprises at least one word line, at least one cell bit line, and at least one memory cell which is disposed in a region where the at least one word line and the at least one cell bit line cross each other;at least one sense amplifier configured to sense data stored in the at least one memory cell, the at least one sense amplifier being disposed at a second layer different from the first layer and connected to at least one bit line and at least one complementary bit line, the at least one bit line being connected to the at least one cell bit line,output device that is connected to the at least one cell bit line,wherein the bit line is connected to the output device via the cell bit line.2. (canceled)3. The semiconductor memory device of claim 1 , wherein ...

Systems and methods for modeling binary synapses

Methods and system for modeling the behavior of binary synapses are provided. In one aspect, a method of modeling synaptic behavior includes receiving an analog input signal and transforming the analog input signal into an N-bit codeword, wherein each bit of the N-bit codeword is represented by an electronic pulse ( 1001 ). The method includes loading the N-bit codeword into a circular shift register ( 1002 ) and sending each bit of the N-bit codeword through one of N switches. Each switch applies a corresponding weight to the bit to produce a weighted bit. A signal corresponding to a summation of the weighted bits is output and represents a synaptic transfer function characterization of a binary synapse ( 1009 ).

Semiconductor storage device

According to one embodiment, a semiconductor storage device includes a stripe, a sense amplifier, a global signal line, and a controller. Blocks are in the stripe. The blocks are formed in a first direction. Each of blocks is made a read unit of data and includes a memory cell capable of holding the data provided along a row and a column. The sense amplifier is provided just under each of the blocks, and reads the data. The global signal line is formed so as to penetrate through the stripe in the first direction, and transfers the data read from the block to the sense amplifier. The controller controls a value of a reference current applied to the sense amplifier according to positional relationship between each area in which the sense amplifier is arranged and the block, which is made a read target of the data, out of the blocks.

INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY

An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier. 1. A apparatus comprising:a first plurality of sense amplifiers, a first sense amplifier of the first plurality of sense amplifiers configured to provide a first output signal based on a first sensed state, wherein the first sense amplifier has a first output current drive setting;a second plurality of sense amplifiers, a second sense amplifier of the plurality of sense amplifiers configured to provide a second output signal based on a second sensed state, wherein the second sense amplifier has a second output drive setting, the second output current drive setting different than the first output current drive setting; anda data output circuit coupled to the first plurality of sense amplifiers and to the second plurality of sense amplifiers, the data output circuit configured to receive the first output signal and the second output signal and to provide output signals based on at least one of the first output signal or the second output signal.2. The apparatus of claim 1 , wherein the first sense amplifier comprises a first current driver configured to provide the first output signal having the first output current drive setting claim 1 , and wherein the second sense amplifier comprises a second current driver configured to provide the second output signal having the second output current drive setting.3. The apparatus of claim 2 , wherein the first current driver comprises a source follower stage comprising a plurality of transistors claim 2 , wherein each transistor of the plurality of transistors is coupled to a respective switch pair claim 2 , wherein the respective switch pair is configured to activate an associated transistor of the ...

MEMORY DEVICE, METHOD OF PERFORMING READ OR WRITE OPERATION AND MEMORY SYSTEM INCLUDING THE SAME

Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided. 1. A memory device , comprising:a first switch configured to receive a first CSL signal and to input or output data;a second switch configured to receive a second CSL signal;a sensing and latch circuit coupled between the first and second switches; andat least one memory cell coupled to the second switch,wherein the second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal.2. The memory device of claim 1 , wherein the second CSL is a write CSL (WCSL) and the second switch is a write switch.3. The memory device of claim 1 , wherein claim 1 , in a write operation claim 1 , the sensing and latch circuit is configured to latch.4. The memory device of claim 1 , wherein claim 1 , in a write operation claim 1 , the device operates in a voltage mode.5. The memory device of claim 1 , wherein the second CSL is a read CSL (RCSL) and the second switch is a read switch.6. The memory device of claim 1 , wherein claim 1 , in a read operation claim 1 , the sensing and latch circuit is configured to operate as a sense amplifier.7. The memory device of claim 1 , wherein claim 1 , in ...

Sense amplifier with offset current injection

A sense amplifier includes a sense input node, a current mirror circuit to mirror the current on the sense input node, and a result output node. A current source supplies an offset current. The sense amplifier increases the current on the sense input node by the offset current and reduces the offset current from the mirrored current at the result output node.

STORAGE DEVICE

Noise attributed to signals of a word line, in first and second bit lines which are overlapped with the same word line in memory cells stacked in a three-dimensional manner is reduced in a storage device with a folded bit-line architecture. The storage device includes a driver circuit including a sense amplifier, and first and second memory cell arrays which are stacked each other. The first memory cell array includes a first memory cell electrically connected to the first bit line and a first word line, and the second memory cell array includes a second memory cell electrically connected to the second bit line and a second word line. The first and second bit lines are electrically connected to the sense amplifier in the folded bit-line architecture. The first word line, first bit line, second bit line, and second word line are disposed in this manner over the driver circuit. 1. A semiconductor device comprising:a driver circuit comprising a sense amplifier, the sense amplifier being electrically connected to a first bit line and a second bit line;a first memory cell array comprising a first memory cell, the first memory cell being electrically connected to the first bit line and a first word line; anda second memory cell array comprising a second memory cell over the first memory cell array, the second memory cell being electrically connected to the second bit line and a second word line,wherein the first bit line is provided over the first word line,wherein the second word line is provided over the second bit line, andwherein the first memory cell overlaps with the second memory cell.2. The semiconductor device according to claim 1 , wherein the first memory cell array is provided over the driver circuit.3. The semiconductor device according to claim 2 , wherein the driver circuit comprises a transistor comprising a channel formation region in a single-crystal semiconductor substrate.4. The semiconductor device according to claim 1 , wherein each of the first ...

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. 1. A semiconductor device comprising:a first local bit line coupled to a plurality of memory cells arranged in a first area;a second local bit line coupled to a plurality of memory cells arranged in a second area;a local sense amplifier of a differential type amplifying a voltage difference between the first and second local bit lines;a global bit line arranged in an extending direction of the first and second local bit lines;a first switch controlling an electrical connection between the first local bit line and the global bit line; anda second switch controlling an electrical connection between the second local bit line and the global bit line.2. The semiconductor device according to claim 1 , further comprising a global sense amplifier of a single-ended type connected to one end of the global bit line.3. The semiconductor device according to claim 1 , further comprising a control circuit controlling the first and second switches claim 1 ,wherein in response to a selected memory cell of the memory cells, the control circuit renders one of the first and second switches conductive and renders the other thereof non-conductive.4. The semiconductor device according to claim 3 , wherein the control circuit renders the first switch conductive when the selected memory cell is in the first area claim 3 , and renders the second switch conductive when the selected memory cell is in the second area.5. The semiconductor device according to claim 4 , ...

SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES

Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. 18.-. (canceled)9. A sensing circuit comprising:a data column including an output voltage node, a memory cell, a first PMOS transistor that is diode-connected, and a first differential threshold NMOS transistor having a drain connected to a drain of the first PMOS transistor to form the output voltage node and a source connected to a first node; anda first memory column comprising a second differential threshold NMOS transistor having a drain connected to the first node; anda second memory column connected to the first node in parallel with the first memory column, wherein each memory column includes a differential threshold MOS transistor;wherein one or more of the differential threshold transistors are transistors that each have a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage.10. The sensing circuit of further comprising one or more additional memory columns.11. A sensing circuit or differential sense amplifier comprising:a reference column including a reference voltage node, a reference memory cell, a first differential threshold PMOS transistor that is diode-connected and has a drain connected to the reference voltage node, and a first differential threshold NMOS transistor having a drain connected to the reference ...

Sense-amplifier circuit of memory and calibrating method thereof

A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided.

SYSTEM AND METHOD OF REFERENCE CELL TESTING

Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. 1. A method comprising:coupling a first reference cell of a first reference cell pair of the a memory array to a first input of a first sense amplifier of the memory array; andproviding a reference signal to a second input of the first sense amplifier, wherein the reference signal is associated with a second reference cell pair of the memory array.2. The method of claim 1 , wherein the first sense amplifier includes comparator circuitry configured to output a comparator output value that is dependent upon a first signal received at the first input of the first sense amplifier and upon a second signal received at the second input of the first sense amplifier.3. The method of claim 1 , further comprising after coupling the first reference cell to the first input of the first sense amplifier and providing the reference signal to the second input of the first sense amplifier claim 1 , determining whether the first reference cell is functional by comparing an output of the first sense amplifier to a first predetermined threshold.4. The method of claim 3 , further comprising when the first reference cell is determined to be non-functional claim 3 , replacing use of the first reference cell in the memory array with use of a redundant reference cell of the memory array.5. The method of claim 3 , further comprising:coupling a second reference cell of the first reference cell pair to a first input of a second sense amplifier of the memory array;providing a second reference signal to a second input of the second sense ...

SYSTEM AND METHOD FOR MODIFYING ACTIVATION OF A SENSE AMPLIFIER

Systems, methods, and other embodiments associated with controlling a sense amplifier in a memory device are described. According to one embodiment, an apparatus includes a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device. The apparatus includes a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation. The apparatus also includes a controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit. The plurality of semiconductor gates are connected in parallel. 1. An apparatus , comprising:a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device;a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation; anda controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit, where the plurality of semiconductor gates are connected in parallel.2. The apparatus of claim 1 , wherein the memory device is a static random access memory (SRAM) and the apparatus is integrated with the SRAM.3. The apparatus of claim 1 , wherein the controller is configured to modify the timing of the sense enable signal to advance when the sense enable signal occurs.4. The apparatus of claim 3 , wherein the controller is configured to advance when the sense enable signal occurs by an amount based on a number of the plurality of semiconductor ...

SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal. 1. An apparatus , comprising:a first transistor configured to receive an input signal and adjust a resistance of a second transistor based, at least in part, on the input signal, the first transistor configured to provide an output signal based, at least in part, on the input signal,wherein a rate at which the output signal is provided is based, at least in part, on a magnitude of the resistance of the second transistor.2. The apparatus of claim 1 , wherein the resistance is an ON-resistance.3. The apparatus of claim 1 , wherein the input signal comprises an analog signal and the output signal comprises a digital signal.4. The apparatus of claim 3 , wherein the first transistor is configured to provide the output signal having a first state when the input signal has a voltage less than a reference voltage and to provide the output signal having a second state when the input signal has a voltage greater than the reference voltage.5. The apparatus of claim 1 , wherein a terminal of the first transistor and a terminal of the second transistor are capacitively coupled.6. The apparatus of claim 1 , ...

Memory having isolation units for isolating storage arrays from a shared i/o during retention mode operation

A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. 1. A method of operation within a memory component , the method comprising:receiving, during a first command reception interval, a row command and a row address, the row address indicating a row of storage cells within the memory component;decoding the row address upon receiving the row command to select a row of storage cells within the memory component;receiving, during a second command reception interval and after decoding the row address has commenced, a first column command and a first column address, the first column address indicating a first column of data within a first subrow of storage cells included within the row of storage cells, and the first column command indicating a memory access operation to be carried out with respect to the first column of data; andtransferring a first subrow of data, including the first column of data, from the first subrow of storage cells to a first set of sense amplifiers in response to the first column command.2. The method of further comprising executing the memory access operation indicated by the first column command with respect to the first column of data after transferring the first subrow of data from the first subrow of storage cells to the first set of sense amplifiers.3. The method of wherein executing the memory access operation comprises transferring the first column of data from the first set of sense amplifiers to an output driver of the memory component in a memory read operation claim 2 , the output driver to output the first column of data from the memory component claim 2 , wherein an elapsed time between receipt of the first column ...

Spin-transfer torque memory self-reference read method

A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE

To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground. 1. A sense amplifier circuit comprising:a sensing transistor that is connected between a first power supply and a second power supply through a memory cell connection line that extends to a memory cell;a resistance element that is connected between the first power supply and a control terminal of the sensing transistor; anda capacitance element that is connected between the second power supply and the control terminal of the sensing transistor.2. The sense amplifier circuit according to claim 1 , wherein a first capacity from the sensing transistor to the second power supply through the capacitance element is equal to a second capacity from the sensing transistor to the second power supply through the memory cell connection line.3. The sense amplifier circuit according to claim 1 , comprising a current-mirror circuit that mirrors a current flowing through the sensing transistor claim 1 ,wherein a first capacity from the sensing transistor to the second power supply through the capacitance element is based on a second capacity from the sensing transistor to the second power supply through the memory cell connection line and a third capacity of a circuit in an output side of the current-mirror circuit.4. The sense amplifier circuit according to claim 3 , wherein the third capacity is a capacity in which a parasitic capacity of an output-side transistor of the current-mirror circuit claim 3 , a whole parasitic capacity of an output line from the output-side transistor to an output inverter which is an output ...

Refresh request queuing circuitry

An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.

Line memory device and image sensor including the same

A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

Systems, memories, and methods for repair in open digit memory architectures

A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.

SEMICONDUCTOR MEMORY DEVICE

In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced. 2. The semiconductor memory device of claim 1 , whereinthe first and second signal lines are local bit lines,the third and fourth signal lines are global bit lines,the local and global bit lines form a hierarchical bit line architecture.3. The semiconductor memory device of claim 1 , wherein a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,', 'a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,', 'a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,', 'a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,', 'a fifth cell transistor of the second conductivity type ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells, and a column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches. One of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled. 1. A semiconductor memory device comprising:a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells; anda column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches,one of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled.2. The semiconductor memory device according to claim 1 ,wherein, when a set of the sense amplifiers capable of handling one of the cell columns is set as a sense amplifier set, a set of the data latches capable of handling one of the cell columns is set as a data latch set, and a set of the one of the sense amplifier sets and the one of the data latch sets is set as a column set,the sense amplifier-data latch unit includes a common control circuit that is used in common for controlling a ...

Bipolar primary sense amplifier

A sense amplifier for a memory includes two bipolar transistors and isolation switches for selectively coupling and decoupling the base of the bipolar transistors to bit lines during portions of a read cycle. The sense amplifier has a feedback circuit that couples the collector of one of the bi polar transistors to the base of the other bipolar transistor and vice versa.

Redundant memory array for replacing memory sections of main memory

Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.

SINGLE-ENDED READ RANDOM ACCESS MEMORY

A single-ended read random access memory including a plurality of memory units, a clock generator, a bit line load circuit, a control processing unit, and a sensing unit is revealed. The memory units are coupled to a bit line and the clock generator is for generating a clock signal. The bit line load circuit charges the memory units to an operating voltage according to the clock signal. The control processing unit controls at least one of the memory units according to the clock signal to make the memory unit store a stored voltage according to the operating voltage. The sensing unit generates a sensing threshold according to the clock signal and a data dependency, and outputs a data signal according to the sensing threshold and the stored voltage. The operating voltage includes a noise whose ratio to the operating voltage is inversely proportional to the operating voltage. 1. A single-ended read random access memory comprising:a plurality of memory units coupled to a bit line;a clock generator that generates a clock signal;a bit line load circuit that charges the memory units to an operating voltage according to the clock signal;a control processing unit that controls at least one of the memory units according to the clock signal so as to make the memory unit stores a stored voltage in accordance with the operating voltage; anda sensing unit that generates a sensing threshold according to the clock signal and the stored voltage, and outputs a data signal according to the sensing threshold and the stored voltage;wherein the operating voltage includes a noise and a ratio of the noise to the operating voltage is inversely proportional to the operating voltage.2. The device as claimed in claim 1 , wherein the sensing unit outputs an amplified voltage according to the stored voltage.3. The device as claimed in claim 2 , wherein the sensing unit outputs the amplified voltage according to the noise so as to output the data signal.4. The device as claimed in claim 1 , ...

Semiconductor device and method of operating the same

A semiconductor device and a method of operating the same, the semiconductor device including a sense amplifier connected between a bit line and a complementary bit line; a first power supply circuit configured to select between supplying a power supply voltage to the first node and blocking the power supply voltage from the first node in response to a first control signal; a second power supply circuit configured to select between supplying a ground voltage to the second node and blocking the ground voltage from the second node in response to a second control signal; and a first boosting circuit configured to boost a voltage at the first node in response to a third control signal.

Apparatuses and methods for improved memory operation times

Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus.

Semiconductor memory device with sense amplifier and bitline isolation

A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.

Memory device from which dummy edge memory block is removed

A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

E-FUSE ARRAY CIRCUIT

An e-fuse array circuit includes a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line, a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor, a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line, and a second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor. 1. An e-fuse array circuit comprising:a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line;a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor;a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line; anda second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor.2. The e-fuse array circuit of claim 1 , further comprising:a third select transistor configured to have a gate terminal connected to the first select line and have a first terminal connected to a second bit line;a third e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the third select transistor;a fourth select transistor configured to have a gate terminal connected to the second select line and have a first terminal connected to the ...

SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER

In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. 1. A semiconductor memory device , comprising:a plurality of sense amplifiers driving bit lines to which memory cells are connected;a plurality of sense amplifier drivers supplying a power supply to the sense amplifiers, each of sense amplifier drivers having first and second driver transistors, and the first driver transistor having a first diffusion regions in a first well region and the second driver transistor having a second diffusion region in a second well region which is different conductivity type from the first well region, andan element separation region formed between the first and second well region,wherein the first and second driver transistors are arranged in parallel with a first direction so as to be arranged one of second driver transistors between two of the first driver transistors,wherein the first diffusion region comprises first and second sides, the first side is parallel to the first direction and the second side is perpendicular to the first direction,wherein the second diffusion region comprises third and fourth sides, the third side is parallel to the first direction and the fourth side is ...

CIRCUITS AND METHODS FOR CALIBRATING OFFSET IN AN AMPLIFIER

In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset cancels a least a portion of the offset of the amplifier. In one implementation, the amplifier is a sense amplifier in a memory. 120-. (canceled)21. A method for determining offset in an amplifier , the method comprising:generating, using offset generation circuitry, an offset value at an input of an amplifier;determining, using offset detection circuitry, whether an output of the amplifier is greater than an output threshold; andsetting, using control circuitry, an offset inject value which indicates that an offset should be generated at the input of the amplifier if the output is determined to be greater than the output threshold.22. The method of claim 21 , further comprising:generating an incremented offset value by incrementing the offset by an offset increment value if the output is determined to be greater than the output threshold;determining, using offset detection circuitry, whether the output of the amplifier is greater than a output threshold; andstoring, using offset value storage circuitry, the incremented offset value if the output is less than or equal to the output threshold.23. The method of claim 22 , wherein the offset value and incremented offset value is determined by successive approximation.24. The method of claim 21 , wherein the input of the amplifier is a first polarity input of the amplifier and the output of the amplifier is associated with the first polarity of the input.25. The method of claim 21 , further comprising storing the generated ...

SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME

A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed; a sink unit configured to provide a sense voltage in response to the enable signal; and a sense unit configured to generate an output signal in response to the sense voltage and the input signals. 1. A sense amplifier circuit , comprising:an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed;a sink unit configured to provide a sense voltage in response to the enable signal; anda sense unit configured to generate an output signal in response to the sense voltage and the input signals.2. The sense amplifier circuit according to claim 1 , wherein the enable signal generation unit receives a sense control signal and supplies the sense control signal as the enable signal when the change in the voltage level of the input signals is sensed.3. The sense amplifier circuit according to claim 2 , further comprising a cut-off unit configured to prevent the sense voltage from being supplied to the sense unit when the sense control signal is disabled.4. The sense amplifier circuit according to claim 2 , wherein:the input signals are a pair of input signals, andthe enable signal generation unit provides the sense control signal as the enable signal when a voltage level of one of the pair of input signals shifts to a specific voltage level.5. The sense amplifier circuit according to claim 1 , wherein the enable signal generation unit further comprises a first PMOS transistor operably coupled in parallel with a second PMOS transistor.6. The sense amplifier circuit according to claim 5 , wherein the enable signal generation unit receives input signals through a gate of the first PMOS transistor and a gate of the second PMOS transistor.7. A sense amplifier circuit claim 5 , comprising:an enable signal generation unit configured to generate ...

Passive Offset and Overshoot Cancellation for Sampled-Data Circuits

A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE

A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. 1. A semiconductor device comprising:a first conductive line;a second conductive line;a first transistor coupled between the first conductive line and a first power supply line, the first transistor including a control terminal coupled to a first control line;a second transistor coupled between a second power supply line and a first node, the second transistor including a control terminal coupled to a second control line different from the first control line; anda third transistor coupled between the first conductive line and the first node, the third transistor including a control terminal coupled to a third control line;wherein the third control line is able to be supplied a first voltage and a second voltage different from the first voltage, both the first and second voltages are intermediate between a voltage of the first power supply line and a voltage of the second power supply line.2. The semiconductor device according to claim 1 , further comprising a memory cell coupled between the first conductive line and a plate line.3. The semiconductor device according to claim 1 , ...

Apparatuses and methods for coupling load current to a common source

Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.

SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT

Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation. 1. A semiconductor device comprising:a first line;a second line;a first node;a second node supplied with a first power supply potential;a first control element that controls an amount of current flowing between the second line and the first node according to a potential of the first line;a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line;a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential;a second control circuit that performs a second operation to connect the first node to the second node; anda third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation.2. The semiconductor device as claimed in claim 1 , wherein the first potential and the second potential are substantially the same potential.3. The semiconductor device as claimed in claim 1 , further comprising first and second memory cells claim 1 ,wherein the first line receives data read from the first memory cell, and the ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a memory cell unit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to provide a read value in response to an activated word line, a reference value generating unit including a plurality of reference value generating cells coupled between the plurality of word lines and a reference bit line, and configured to provide a single reference value in response to the activated word line, and a sense circuit configured to provide a sense output signal based on the single reference value and the read value. 1. A semiconductor memory device , comprising:a memory cell unit including a plurality of memory cells coupled to and disposed between a plurality of word lines and a plurality of bit lines and configured to provide a read value in response to an activated word line;a reference value generating unit including a plurality of reference value generating cells coupled to and disposed between the plurality of word lines and a reference bit line and configured to provide a single reference value in response to the activated word line; anda sense circuit configured to provide a sense output signal based on the single reference value and the read value.2. The semiconductor memory device according to claim 1 , wherein each of the memory cells and the reference value generating cells includes one transistor and one magnetic tunnel junction (MTJ) claim 1 , andwherein an MTJ included in a reference value generating cell is larger than an MTJ included in a memory cell.3. The semiconductor memory device according to claim 1 , further comprising a data determining unit configured to receive the sense output signal and determine the read value as first data if the read value is the same as or greater than the single reference value and as second data if the read value is smaller than the single reference value.4. The semiconductor memory device according to claim 1 , wherein ...

SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE

A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. 1. A semiconductor device comprising:a first conductive line;a second conductive line;a first transistor coupled between the first conductive line and a first power supply line, the first transistor including a control terminal coupled to a first control line;a second transistor coupled between a second power supply line and a first node, the second transistor including a control terminal coupled to a second control line different from the first control line;a third transistor coupled between the first conductive line and the first node, the first transistor including a control terminal coupled to a third control line; anda fourth transistor coupled between the second conductive line and a third power supply line, the fourth transistor including a control terminal connected to the first node;wherein the first power supply line is able to be supplied an intermediate voltage which is intermediate between a voltage of the second power supply line and a voltage of the second power supply line.2. The semiconductor device according to claim 1 , further comprising a memory cell coupled ...

Sense amplifier circuitry for resistive type memory

Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

SEMICONDUCTOR DEVICE, METHOD OF RETRIEVING DATA, AND MICROCOMPUTER

A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing inverted data of the reference data; a sense amplifier unit; and a data output unit. In a first retrieving process, the sense amplifier unit differentially amplifies the data and the reference data, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference. In a second retrieving process, the sense amplifier unit differentially amplifies the data and the inverted data, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the predetermined retrievable voltage difference. The data output unit determines and outputs the data according to a result of the first retrieving process and the second retrieving process. 1. A semiconductor device comprising:a data memory cell for storing data;a reference data memory cell for storing reference data to be compared with the data;an inverted data memory cell for storing inverted data of the reference data;a sense amplifier unit; anda data output unit,wherein said sense amplifier unit is configured to perform a first retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the reference data stored in the reference data memory cell, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference,said sense amplifier unit is configured to perform a second retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the inverted data stored in the inverted data memory cell, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the ...

Bitline for Memory

Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.

SEMICONDUCTOR DEVICE HAVING OPEN BITLINE STRUCTURE

Disclosed herein is a semiconductor device that includes: a plurality of memory arrays disposed in a first direction and a second direction that crosses the first direction; a plurality of row decoders disposed along a first side of the memory arrays; a plurality of first column decoders each disposed along a second side that does not face the first side of an associated one of the memory arrays; and a plurality of second column decoders each disposed along a third side that faces the second side of an associated one of the memory arrays. Each of the memory arrays is sandwiched between a corresponding one of the first column decoders and a corresponding one of the second column decoders. 1. A semiconductor device comprising:a plurality of memory mats arranged in a first direction and selected based on a mat address, the plurality of memory mats including a first memory mat disposed in one end portion of the first direction, a second memory mat disposed in the other end portion of the first direction, and a third memory mat positioned between the first and second memory mats; anda plurality of sense amplifier areas each arranged between two of the memory mats that are adjacent to each other in the first direction, each of the sense amplifier areas including a plurality of sense amplifiers, whereineach of the memory mats includes a plurality of bit lines extending in the first direction, a plurality of word lines extending in a second direction that crosses the first direction, and a plurality of memory cells disposed at intersections of the bit lines and word lines,each of the sense amplifiers is connected to an associated one of the bit lines included in an adjacent one of the memory mats on one side of the first direction, and to an associated one of the bit lines included in an adjacent one of the memory mats on the other side of the first direction,the first and third memory mats are selected when the mat address indicates a first value, andthe second and third ...

Semiconductor memory apparatus and method of operating using the same

A semiconductor memory apparatus includes a resistive memory cell coupled between a bit line and a bit line bar; a control unit configured to couple the bit line to a first node and apply a reference voltage to a second node in response to a first sense amplifier enable signal and a second sense amplifier enable signal; a data output sense amplifier configured to sense and amplify a voltage of the first node and a voltage of the second node; a data transfer unit configured to couple the first and second nodes to a data line and a data line bar in response to a column select signal; and a data input unit configured to drive the bit line and the bit line bar according to voltage levels of the first and second nodes in response to a write enable signal.

SEMICONDUCTOR STORAGE DEVICE

According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part. 1. A semiconductor storage device , comprising:a plurality of peripheral circuits on a semiconductor substrate;a memory cell array having a plurality of semiconductor layers above the peripheral circuits, the memory cell array including two or more regions;a plurality of upper bit lines disposed in one or more layers above the memory cell array and extending in a first direction, each of the upper bit lines electrically connected to at least one of the peripheral circuits;a plurality of lower bit lines disposed in one or more layers below the memory cell array and extending in the first direction, each of the lower bit lines corresponding to a respective upper bit line; anda plurality of connection parts including contact plugs connecting upper bit lines to corresponding lower bit lines,wherein a first group of the upper bit lines are connected to the peripheral circuits via a first connecting part and respective lower bit lines, the first connecting part disposed between two regions of the memory cell array, and a second group of the upper bit lines are connected to the peripheral circuits via a second connecting part and respective lower bit ...

Compact High Speed Sense Amplifier for Non-Volatile Memory with Reduced layout Area and Power Consumption

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Memory Device, System Having the Same, and Method for Manufacturing the Same

A memory device includes a memory cell array including normal memory cells arranged in a form of matrix, and a sense amplifier array including sense amplifiers each amplifying a signal output from each of the normal memory cells. Some of the sense amplifiers have different sizes so that they may have different sense capabilities depending on a layout location. The size is determined according to at least one of a channel length and a channel width of a MOS transistor included in each of the some sense amplifiers. 1. A memory device , comprising:a memory cell array including memory cells arranged in a matrix; anda sense amplifier array including a plurality of sense amplifiers, each sense amplifier configured to amplify a signal output from each cell of a set of memory cells;wherein each sense amplifier of the sense amplifier array is formed of a plurality of transistors, andwherein an average size among the plurality of transistors that form a first sense amplifier of the sense amplifier array is larger than an average size among the plurality of transistors that form a second sense amplifier of the sense amplifier array.2. The memory device of claim 1 , wherein the first sense amplifier is an edge sense amplifier claim 1 , and the second sense amplifier is an inner sense amplifier.3. The memory device of claim 1 , wherein an average channel length among the plurality of transistors that form the first sense amplifier of the sense amplifier array is larger than an average channel length among the plurality of transistors that form the second sense amplifier of the sense amplifier array.4. The memory device of claim 1 , wherein an average channel width among the plurality of transistors that form the first sense amplifier of the sense amplifier array is larger than an average channel width among the plurality of transistors that form the second sense amplifier of the sense amplifier array.5. (canceled)6. (canceled)7. The memory device of claim 1 , wherein an average ...

MEMORY WITH REDUNDANT SENSE AMPLIFIER

Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state. 1. An apparatus , comprising:a plurality of data storage cells;a decoder circuit configured to select a data storage cell from the plurality of data storage cells;a control circuit configured to store test data in the selected data storage cell;a first sense amplifier configured to amplify the stored test data in the selected data storage cell using a first gain level;wherein the control circuit is further configured to compare test data to the stored data amplified using the first gain level; anda second sense amplifier configured to amplify the stored test data in the selected data storage cell using a second gain level responsive to a determination that the stored test data amplified using the first gain level does not match the test data, wherein the second gain level is greater than the first gain level; and compare the test data to the stored test data amplified using the second gain level; and', 'store information indicative of the strength of the selected data storage cell dependent upon the comparison of the test data to the stored data amplified using the second gain level., 'wherein the control circuit is further configured to2. The apparatus of claim 1 , ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption. 1. A semiconductor memory device comprising:a first core region and a second core region disposed along a first reference line substantially parallel to a major axis, the first reference line connecting an input pad and an output pad;first and second cell blocks disposed in the first core region along the first reference line;third and fourth cell blocks disposed in the second core region along the first reference line; anda repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, through a first global input/output line in a read operation for the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line.2. The semiconductor memory device according to claim 1 , further comprising:a data output unit configured to receive the data amplified by the repeater, through the second global input/output line, and output the received data to a third global input/output line.3. The semiconductor memory ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a sense amplifier circuit region including first wells disposed in a first direction, a driving circuit region including second wells disposed in a second direction, and a conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region. 1. A semiconductor memory device , comprising:a sense amplifier circuit region including first wells disposed in a first direction;a driving circuit region including second wells disposed in a second direction; anda conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region.2. The semiconductor memory device as claimed in claim 1 , wherein the part of each of the first wells in the conjunction region includes first and second partial wells extending from the sense amplifier circuit region at both sides of the conjunction region into the conjunction region claim 1 , the first and second partial wells being spaced apart from each other.3. The semiconductor memory device as claimed in claim 2 , wherein a length of the first partial well or the second partial well in the first direction is greater than about 5% of a width of the conjunction region in the first direction.4. The semiconductor memory device as claimed in claim 2 , wherein lengths of the first partial well and the second partial well in the first direction are substantially identical to each other.5. The semiconductor memory device as claimed in claim 2 , further comprising a third well in the conjunction region claim 2 , the third well connecting the first partial well ...

SEMICONDUCTOR DEVICE

A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed. 1. A semiconductor device , comprising:a first memory cell;a second memory cell;a first bit line extending in a first direction and being connected to the first memory cell;a second bit line extending in the first direction and being connected to the second memory cell;a first power line; anda sense amplifier circuit comprising a first transistor and a second transistor, the first transistor including a first gate electrode that is formed over a first channel region and connected to the first bit line, a first diffusion region that is connected to the second bit line and includes a first side edge defining the first channel region and a second diffusion region that is connected to the first power line and includes a second side edge defining the first channel region, and the second transistor including a second gate electrode that is formed over a second channel region and connected to the second bit line, a third diffusion region that is connected to the first bit line and includes a third side edge defining the second channel region and a fourth diffusion region that is ...

SENSE AMPLIFIER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

A sense amplifier circuit includes a first pull-up transistor configured to pull-up drive a data bar line in response to a voltage of a data line, a first pull-down transistor configured to pull-down drive the data bar line in response to the voltage of the data line, and to receive the voltage of the data line through a back gate of the first pull-down transistor, a second pull-up transistor configured to pull-up drive the data line in response to a voltage of the data bar line, and a second pull-down transistor configured to pull-down drive the data line in response to the voltage of the data bar line, and to receive the voltage of the data bar line through a back gate of the second pull-down transistor. 1. A sense amplifier circuit comprising:a first pull-up transistor configured to pull-up drive a data bar line in response to a voltage of a data line;a first pull-down transistor configured to pull-down drive the data bar line in response to the voltage of the data line, and to receive the voltage of the data line through a back gate of the first pull-down transistor;a second pull-up transistor configured to pull-up drive the data line in response to a voltage of the data bar line; anda second pull-down transistor configured to pull-down drive the data line in response to the voltage of the data bar line, and to receive the voltage of the data bar line through a back gate of the second pull-down transistor.2. The sense amplifier circuit of claim 1 , wherein each of the first pull-down transistor and the second pull-down transistor includes a fully depleted silicon on insulator (FDSOI) NMOS transistor.3. The sense amplifier circuit of claim 2 , wherein each of the first pull-up transistor and the second pull-up transistor includes a PMOS transistor.4. A memory device comprising:one or more cell arrays,a bit line and a bit bar line connected to the one or more cell arrays;a first pull-up transistor configured to pull-up drive the bit bar line in response to a ...

Sense amplifier

Embodiments of the invention provide a sense amplifier, a SRAM chip comprising the sense amplifier and a method of performing read operation on the SRAM chip. The sense amplifier according to embodiments of the invention comprises an additional driving assist portion, which further takes a global data bus as input, the driving assist portion is configured to enable the sense amplifier to provide assisted driving for other sense amplifiers. With the solution according to embodiments of the invention, driving capability of a sense amplifier on global data bus can be enhanced.

Sense Amplifier Circuit for Nonvolatile Memory

A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal.

SEMICONDUCTOR MEMORY DEVICES

A semiconductor memory device includes a memory bank having a first cell block including a plurality of memory cells coupled to a first word line which can be activated in response to a row address signal, a second cell block including a plurality of memory cells coupled to a second word line, and a dummy cell block including a plurality of memory cells coupled to a third word line which can be activated in response to the row address signal. The first and second cell blocks share a first sense amplifier. The second cell block and the dummy cell block share a second sense amplifier. The first cell block is disposed adjacent to a first edge of the memory bank, and the dummy cell block is disposed adjacent to a second edge of the memory bank opposing the first edge. 1. A semiconductor memory device comprising:a first cell block including a first plurality of memory cells coupled to a first word line;a second cell block including a second plurality of memory cells coupled to a second word line; anda dummy cell block including a third plurality of memory cells coupled to a third word line,wherein the first and second cell blocks share a first sense amplifier, the second cell block and the dummy cell block share a second sense amplifier, the first cell block is disposed adjacent to a first edge of the semiconductor memory device where a row address signal is inputted, and the dummy cell block is disposed adjacent to a second edge of the semiconductor memory device opposing the first edge.2. The semiconductor memory device of :wherein when the row address signal indicates the first cell block is being accessed and no failed memory cells exists in the first cell block, the first and third word lines are simultaneously activated; andwherein when the row address signal indicates the first cell block is being accessed and at least one failed memory cell exists in the first cell block, the first and third redundancy word lines are simultaneously activated.3. The semiconductor ...

Bit line sense amplifier and layout method therefor

A bit line sense amplifier and a layout method therefor which can reduce coupling capacitance. The bit line sense amplifier is disposed between a first memory cell block and a second memory cell block adjacent to the first memory cell block and configured to include first and third switching elements substantially symmetrically formed in a first direction so that the drain terminals of the first and third switching elements face each other, second and fourth switching elements substantially symmetrically formed in the first direction so that the drain terminals of the second and fourth switching elements face each other, a first line configured to electrically couple the gate terminal of the first switching element and the drain terminal of the second switching element, and a second line configured to electrically couple the gate terminal of the third switching element and the drain terminal of the fourth switching element.

SENSE AMPLIFIERS, MEMORIES, AND APPARATUSES AND METHODS FOR SENSING A DATA STATE OF A MEMORY CELL

Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances. 1. An apparatus , comprising:a data line and a reference line;a precharge circuit configured to precharge the data line and the reference line during a precharge phase;a switch block having a data line input coupled to the data line, a reference data line input coupled to the reference line, a reference input, and a feedback input, the switch block further including a data line output, a reference data line output, a reference output, and a feedback output, during the precharge phase the switch block configured to couple the reference input to the data line output, the reference data line output, and the reference output, and further couple the feedback input to the feedback output, during an evaluation phase the switch block configured to couple the data line input to the data line output and further couple the reference data line input to the reference data line output;a first capacitance coupled to the data line output;a second capacitance coupled to the reference data line output; anda differential amplifier coupled to the first and second capacitances and configured to ...

TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. 1. A semiconductor memory device comprising:a plurality of memory cells; anddata write and sense circuitry coupled to the plurality of memory cells, wherein the data write and sense circuitry is configured to perform a read operation and a writeback operation on a first memory cell of the plurality of memory cells, wherein the data write and sense circuitry is also configured to perform a disturbance recovery operation on a second memory cell of the plurality of memory cells, and wherein the disturbance recovery operation is performed in between the read operation and the writeback operation.2. The semiconductor memory device according to claim 1 , wherein the data write and sense circuitry comprises a plurality of local data sense amplifiers coupled to a plurality of global data sense amplifiers via one or more global bit lines.3. The semiconductor memory device according to claim 2 , wherein the plurality of local data sense amplifiers are arranged in one or more local data sense amplifier subarrays claim 2 , and the plurality of global data sense amplifiers are arranged in one or more global data sense amplifier subarrays.4. The semiconductor memory device according to claim 2 , wherein the plurality of local data sense amplifiers are coupled to a single global data sense amplifier via a single global bit line.5. The semiconductor ...

DATA VERIFICATION DEVICE AND A SEMICONDUCTOR DEVICE INCLUDING THE SAME

A semiconductor device includes a data verification device. The data verification device includes a data storage unit for storing data to be input to a memory region in response to a first or second control signal, an input data verifier for deactivating an output of a sense amplifier in response to the first control signal and transmitting the input data stored in the data storage unit to an external pad, and a sense-amplifier verifier for transmitting the input data stored in the data storage unit to the sense amplifier upon in response to the second control signal. 1. A data verification device comprising:a data storage unit configured to store input data in response to a first or second control signal generated in a test mode;an input data verifier configured to deactivate an output of a sense amplifier in response to the first control signal, and transmit the input data provided by the data storage unit to an external pad; anda sense-amplifier verifier configured to transmit the input data provided by the data storage unit to the sense amplifier in response to the second control signal, wherein the sense amplifier senses the input data transmitted thereto and transmits sensed data to the external pad.2. The data verification device according to claim 1 , wherein the data storage unit includes a latch that stores the input data in response to the first or second control signal.3. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the input data verifier in response to the first control signal.4. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the sense-amplifier verifier in response to the second control signal.5. The data verification device according to claim 1 , wherein the data storage unit is coupled to a data input buffer claim 1 , and receives the input data through the data input buffer and stores the input data.6. The data verification device ...

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started. 1. A semiconductor apparatus comprising:a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started; anda switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started.2. The semiconductor apparatus according to claim 1 , further comprising a control unit configured to generate the control signal and the second read enable signal in response to the first read enable signal and a second select signal.3. The semiconductor apparatus according to claim 2 , wherein the control unit generates the second read enable signal by delaying the first read enable signal.4. The semiconductor apparatus according to claim 3 , wherein the first select signal comprises a signal enabled during a write operation.5. The semiconductor apparatus according to claim 4 , wherein the second select signal comprises a signal enabled during a read operation.6. The ...

Semiconductor memory device

According to an embodiment, sense amplifiers are arranged one by one within an arrangement width of k bit lines in a direction of the bit lines, and determine data stored in the memory cells, based on potentials of the respective bit lines. Transistors constituting the sense amplifier are arranged one by one within an arrangement width of the sense amplifier in the direction of the bit lines. A gate length direction of the transistors is identical to the direction of the bit lines. A longer side direction of a contact electrode connected to an active area of the transistor is identical to the direction of the bit lines.

SEMICONDUCTOR DEVICE AND DATA OUTPUT CIRCUIT THEREFOR

A semiconductor device includes a memory cell array configured to include a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines, a bit line sense amplifier connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment I/O line, a control signal generator configured to determine a level of an I/O switch control signal in response to a level of a power source voltage, and a local sense amplifier connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line. 1. A semiconductor device , comprising:a memory cell array configured to comprise a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines;a bit line sense amplifier (BLSA) connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment input/output (I/O) line;a control signal generator configured to determine a level of an I/O switch control signal in response to a level of a power source voltage; anda local sense amplifier (LSA) connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line.2. The semiconductor device according to claim 1 , wherein the control signal generator outputs the I/O switch control signal in response to a pre-switching control signal and a level detection signal determined by the level of the power source voltage.3. The semiconductor device according to claim 2 , wherein ...

SEMICONDUCTOR DEVICE INCLUDING BURIED GATE, MODULE AND SYSTEM, AND METHOD FOR MANUFACTURING

An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device. 1. A semiconductor device comprising:a recess formed in an active region;a gate buried in a lower part of the recess;a first capping insulation film formed over the gate;a second capping insulation film formed over the first capping insulation film; anda third capping insulation film formed over the second capping insulation film so as to fill the recess.2. The semiconductor device according to claim 1 , wherein the first capping insulation film comprises a silicon nitride film having a higher nitrogen ratio than a SiNmaterial.3. The semiconductor device according to claim 1 , wherein the first capping insulation film is formed over a sidewall of the recess and over the gate.4. The semiconductor device according to claim 1 , wherein the second capping insulation film includes an oxide film in which the first capping insulation film is partially oxidized.5. The semiconductor device according to claim 1 , wherein the third capping insulation film comprises a silicon nitride film having a higher nitrogen ratio than a SiNmaterial.6. The semiconductor device according to claim 1 , wherein the third capping insulation film includes an oxide film.7. The semiconductor device according to claim 6 , wherein the third capping insulation ...

JUNCTIONLESS SEMICONDUCTOR DEVICE HAVING BURIED GATE, APPARATUS INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current. 1. A junctionless semiconductor device comprising:an active region disposed over an underlying substrate and defined by a device isolation film over the underlying substrate;an insulation layer disposed between the active region and the underlying substrate; anda plurality of buried gates formed in the device isolation film and the active region,wherein source and drain regions and a body in the active region around a buried gate are doped with the same-type impurities.2. The junctionless semiconductor device according to claim 1 , wherein the impurities are implanted into the active region with substantially uniform density.3. The junctionless semiconductor device according to claim 1 , wherein the active region is formed of a silicon layer claim 1 , and the impurities are N-type impurities.4. The junctionless semiconductor device according to claim 1 , wherein the active region is formed using any of a silicon germanium (SiGe) substrate claim 1 , a germanium (Ge) substrate claim 1 , and a group 3 compound semiconductor substrate or a group 5 compound semiconductor substrate claim 1 , and the impurities are P-type impurities.5. The junctionless semiconductor device according to claim 1 , wherein the active region is isolated from the underlying substrate by the insulation layer.6. The junctionless semiconductor ...

MEMORY DEVICE AND METHOD OF PERFORMING A READ OPERATION WITHIN SUCH A MEMORY DEVICE

A memory device is provided comprising an array of memory cells. During a read operation, voltage on a read bit line will transition towards a second voltage level if a data value stored in that activated memory cell has a first value, and sense amplifier circuitry will then detect this situation. If that situation is not detected, the sense amplifier circuitry determines that the activated memory cell stores a second value. Bit line keeper circuitry is coupled to each read bit line and is responsive to an asserted keeper pulse signal to pull the voltage on each read bit line towards the first voltage level. Keeper pulse signal generation circuitry asserts the keeper pulse signal at a selected time. The selected time is such that the voltage on the associated read bit line will have transitioned to the trip voltage level before the keeper pulse signal is asserted. 1. A memory device comprising:an array of memory cells arranged as a plurality of rows and columns, each row of memory cells being coupled to an associated read word line, each column of memory cells forming at least one column group, and the memory cells of each column group being coupled to an associated read bit line;word line driver circuitry configured, during a read operation, to issue an asserted read word line pulse signal on the read word line coupled to an addressed row of the array so as to activate the memory cells within that addressed row whilst the read word line pulse signal is asserted;precharge circuitry configured, prior to the read operation, to precharge each read bit line to a first voltage level;during the read operation the voltage on the read bit line associated with any column group containing one of the activated memory cells being arranged to transition towards a second voltage level if a data value stored in that activated memory cell has a first value;sense amplifier circuitry connected to the associated read bit line of each column group, and configured for each activated ...

Memory circuits, systems, and methods for accessing the memory circuits

A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line, and a first S/D coupled to the global bit line, wherein the second transistor is configured to pre-charge the bit line.

TRANSISTOR VOLTAGE THRESHOLD MISMATCH COMPENSATED SENSE AMPLIFIERS AND METHODS FOR PRECHARGING SENSE AMPLIFIERS

Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored. 1. An apparatus , comprising:first and second field-effect transistors (FETs), the first and second FETs having a respective drain configured to receive a respective input signal; anda capacitance coupled between sources of the first and second FETs, the capacitance configured to store a voltage difference between the sources of the first and second FETs to compensate for threshold voltage differences between the first and second FETs.2. The apparatus of claim 1 , further comprising:an equilibration transistor coupled to the drain of the first FET and the drain of the second FET and configured to receive an equilibration signal, the equilibration transistor configured to couple the drain of the first FET to the drain of the second FET responsive to the equilibration signal.3. The apparatus of claim 1 , further comprising third and fourth FETs claim 1 , the third FET having a drain coupled to the drain of the first FET and the fourth FET having a drain coupled to the drain of the second FET.4. The apparatus of claim 1 , wherein the capacitance is configured to store the voltage difference during each of a plurality of precharge cycles.5. The apparatus of claim 1 , wherein the ...

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line. 1. A method comprising:accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line;transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; andrestoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line.2. The method as claimed in claim 1 , further comprising restoring claim 1 , in response to the data read mode claim 1 , the data into the memory cell through the global and local bit lines.3. The method as claimed in claim 2 , wherein the restoring responsive to the data read mode is carried out by a global sense amplifier connected to the global bit line and the restoring responsive to the refresh mode is carried out a restoring circuit connected to the local bit line.4. A method comprising:accessing a plurality of memory cells to all the memory cells to output data stored therein onto a plurality of local bit lines, respectively; and designating one of the local bit lines as a selected local bit line and remaining one of the local bit lines respectively as non-selected local bit lines;', 'transferring a data signal on the selected local bit line to a global bit line;', 'restoring the data into the memory cell connected to the selected bit line through the global bit line and the selected bit line; and', 'restoring the data into the memory cells connected respectively to the non-selected local bit lines while keeping each of the non-selected local bit lines electrically isolated ...

Circuits and Methods of a Self-Timed High Speed SRAM

Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power. 1. A SRAM memory , comprising:a plurality of SRAM cells having a bitlines (BL) and wordline (WL) that can be selected for access;at least one reference cell having a reference bitline in (BLin) and a reference bitline (RBL) that can be selected from one of a plurality of wordlines or from at least one reference wordline, the reference cell being selectable not earlier than any selected SRAM cells and the RBL being activatable not later than any selected SRAM cells to activate the selected BL;at least one sense amplifier to sense signals coupled to the selected BL from the at least one selected SRAM cell and convert the signals into digital data; andwherein the sense amplifier can be activated by the RBL signal to track the wordline and BL propagating delay.2. A SRAM memory as recited in claim 1 , wherein the at least one reference cell is placed near the far end of a driver to drive a selected wordline or a reference wordline.3. A SRAM memory as recited in claim 1 , wherein the reference cell has at least one inverter with an input coupled to BLin and an output NB coupled to RBL claim 1 , and wherein the RBL is activated by setting BLin at a voltage close to a supply voltage once the wordline or reference wordline is selected.4. A SRAM memory as ...

SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials. 1. (canceled)2. A semiconductor device comprising:a source line;a first bit line;a first word line;a memory cell connected to the source line, the first bit line and the first word line, wherein the memory cell comprises a first transistor and a gate of the first transistor is configured to hold a written potential in accordance with data to be held in the memory cell;a driver circuit configured to drive the first word line so as to select the memory cell specified by an address signal;a reading circuit comprising a plurality of comparing circuits; anda potential generating circuit configured to generate a plurality of reading potentials to supply to the reading circuit,wherein each of the plurality of comparing circuits is configured to compare a potential of the first bit line and one of the plurality of reading potentials, andwherein the reading circuit is configured to decide a potential range of the potential of the first bit line by comparing the potential of the first bit line with the plurality of reading potentials.3. The semiconductor device according to claim 2 , further comprising a control circuit configured to select one of a plurality of voltages for correction on a basis of comparison results between the potential of the first bit line and the plurality of reading potentials.4. The semiconductor device ...

Single-ended volatile memory access

A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory cell of the pair, the selected memory cell being an addressed memory cell while the remaining cell is an unaddressed memory cell. In response to a wordline enable signal, a pass gate in the addressed memory cell couples the addressed memory cell via a complement bitline to an evaluation gate that resolves the data from the read operation. During the read operation, the unaddressed memory cell couples via another pass gate to a true bitline that terminates without an evaluation gate to conserve energy.

SEMICONDUCTOR MEMORY DEVICE WITH DATA PATH OPTION FUNCTION

A semiconductor memory device may include a memory cell, a bit line connected to the memory cell, a bit line data latch circuit configured to sense-amplify data stored in the memory cell connected to the bit line and to store write data in the memory cell via the bit line; an input/output driver configured to output read data on the bit line to an external device or to drive the write data provided from the external device; and a selection unit configured to select whether the read data and the write data are communicated between the input/output driver and the memory cell with or without use of the bit line data latch circuit. 1. A semiconductor memory device comprising:a memory cell;a bit line connected to the memory cell;a bit line data latch configured to sense-amplify read data stored in the memory cell connected with the bit line and to store write data to be written in the memory cell through the bit line;an input/output driver configured to output the read data on the bit line to an external device and to drive the write data provided from the external device; anda selection circuit configured to select whether the bit line data latch is bypassed or is used or bypassed to sense-amplify read data stored in the memory cell and to store the write data to be written in the memory cell .2. The semiconductor memory device of claim 1 , wherein the selection circuit is configured to select whether data stored in the memory cell is transferred directly to the input/output driver or to the input/output driver via the bit line data latch at a read operation claim 1 , and to select whether the write data is transferred directly to the memory cell or to the memory cell via the bit line data latch at a write operation.3. The semiconductor memory device of claim 1 , wherein the memory cell is a magneto-resistive random access memory type of memory cell.4. The semiconductor memory device of claim 3 , wherein the magneto-resistive random access memory type of memory cell is ...

GENERATING AND EXECUTING A CONTROL FLOW

Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array. 120-. (canceled)21. An apparatus comprising:a central processing unit (CPU), configured to generate control flow instructions; and an array of memory cells;', 'an execution unit, coupled to the array, to execute the control flow instructions; and', 'a controller configured to control an execution of the control flow instructions on data stored in the array., 'a memory device, including22. The apparatus of wherein the CPU is further configured to generate the control flow instructions including instructions and an execution order associated with the instructions.23. The apparatus of claim 21 , wherein the CPU is further configured to:request data associated with a program from the memory device;store the data associated with the program in cache; andgenerate the control flow instructions from the data stored in the cache.24. The apparatus of claim 23 , wherein the CPU is further configured to:request data associated with a program from the memory device;cause an arithmetic logic unit (ALU) to generate the control flow instructions, andwherein the apparatus further comprises the ALU configured to generate the control flow instructions.25. The apparatus of claim 21 , wherein the memory device is further configured to receive the control flow instructions via at least one of a buffer claim 21 , the memory array claim 21 , and shift circuitry.26. An apparatus comprising:a system on a chip (SoC) configured to generate control flow instructions; and an array of memory cells;', 'an execution unit, coupled to the array, to execute the ...

DATA CACHING FOR FERROELECTRIC MEMORY

Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell. 1. An apparatus , comprising:a first memory sub-bank and a second memory sub-bank, the first memory sub-bank and the second memory sub-bank each comprising a plurality of memory cells;a first row buffer coupled with the first memory sub-bank and comprising a plurality of sense components configured to cache data associated with the first memory sub-bank;a second row buffer coupled with the second memory sub-bank and comprising a second plurality of sense components configured to cache data associated with the second memory sub-bank; anda bank control circuit configured to cache the data associated with the first memory sub-bank in the first row buffer and cache the data associated with the second memory sub-bank in the second row buffer.2. The apparatus of claim 1 , further comprising:a column decoder coupled with the first memory sub-bank and the second memory sub-bank, the column decoder configured to receive from the bank control circuit a column address of at least one memory cell of the first memory sub-bank or the second memory sub-bank, wherein the bank control circuit is configured to cache the data in the first row buffer or in the second row buffer based at least in part on the column decoder receiving the column address.3. The apparatus of claim 1 , wherein the data cached in the first row buffer or the second row buffer is written to at least one memory cell of the first memory sub-bank or the second memory sub-bank.4. The apparatus of claim 1 , wherein the data cached in the first row buffer or the second row buffer is ...

Independently addressable memory array address spaces

Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.