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Применить Всего найдено 3. Отображено 3.
25-01-2000 дата публикации

MEMORY DEVICE HAVING A DIRECT SENSE CIRCUIT

Номер: KR20000006492A
Автор: KIKIMASATO, MATSUMIYASATO
Принадлежит:

PURPOSE: The memory device having a direct sense circuit is provided to use commonness column decoder and sense buffer circuit in a plurality of memory block. CONSTITUTION: In the memory device having a direct sense circuit, when a memory block 0 is activated a direct sense activation circuit 20 which composed against sense circuit line 12A activate a direct sense operating line to answer an activated lead bus line of a control circuit. The plurality of memory block arrayed perpendicular to a sense circuit column. The plurality of memory block located between the column decoder 13 and the sense buffer circuit 15 and located a word decoder 11 at an edge side. COPYRIGHT 2000 KIPO ...

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Номер записи: 1
25-01-2000 дата публикации

MEMORY APPARATUS HAVING ROW DECODER

Номер: KR20000006546A
Автор: DAKITAMASATO, HASEGAWAMASATOMO, IKEDATOSIMI, MATSUMIYASATO
Принадлежит:

PURPOSE: The memory apparatus having row decoder is provide to reduced timing range for rapid operation. CONSTITUTION: The memory apparatus having row decoder comprises: a buffer gate, a row address register, a mutual signal generating circuit, a free decoder, a word decoder, a control circuit, a first timing generating circuit, a second timing generating circuit, and a strobe circuit. The buffer gate has input receiving a row address. The row address register has data input and clock input combined to the output of the buffer gate. The mutual signal generating circuit has data input combined to the data output of the row address register. The free decoder has data input combined to the data output of the mutual signal generating circuit. The word decoder has data input combined to the data output of the free decoder. The control circuit offered a control signal. The first timing generating circuit generated a first strobe signal. The second timing generating circuit generated a second ...

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Номер записи: 2
25-01-2000 дата публикации

SEMICONDUCTOR MEMORY APPARATUS AND DATA BUS AMPLIFIER ACTIVATING METHOD OF THEM

Номер: KR20000005692A
Автор: ETOSATOSHI, GAWAVATAGUNINORI, GIKUTAKEAKIRA, GOGADORU, MATSUMIYASATO, UZAWAYUICHI
Принадлежит:

PURPOSE: The semiconductor memory apparatus provided generation timing has a few margin of a data bus amplifier enable signal for activating a data bus amplifier mounted against a data bus. CONSTITUTION: The semiconductor memory apparatus comprises: a memory cell array, a column selection circuit, an extraction data bus, and record data bus. The column selection circuit select column of the memory cell array. The extraction data bus transmit extraction data generated by the column selected the column selection circuit select to the extraction data bus. The record data bus transmit record data generated by a data bus amplifier to the column selected the column selection circuit. COPYRIGHT 2000 KIPO ...

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Номер записи: 3