Устройство для защиты памяти

Sicherheitsschaltung zur Sicherung gespeicherter Daten in einem internen Mikrorechnerspeicher

SPEICHERPATRONE

BETRUGSSICHERE VERPACKUNG

SPEICHERANORDNUNG UND VERFAHREN ZUM VERIFIZIEREN EINES SPEICHERZUGRIFFS

Gemäß einer Ausführungsform wird eine Speicheranordnung beschrieben, die ein Speicherzellenfeld mit Spalten und Zeilen von beschreibbaren Speicherzellen, eine Speichersteuereinrichtung, die eingerichtet ist, einen Zugriff auf eine erste Gruppe von Speicherzellen einer Zeile von Speicherzellen zu veranlassen und zusammen mit dem Zugriff auf die erste Gruppe von Speicherzellen einen Lesezugriff auf eine zweite Gruppe von Speicherzellen der Zeile von Speicherzellen zu veranlassen und eine Verifizierungsschaltung aufweist, die eingerichtet ist, zu überprüfen, ob der Zugriff auf die erste Gruppe von Speicherzellen auf die korrekte Zeile von Speicherzellen durchgeführt wurde, basierend darauf, ob bei dem Lesezugriff auf die zweiten Gruppe von Speicherzellen gelesenen Werte mit zuvor von der zweiten Gruppe von Speicherzellen gespeicherten Werten übereinstimmen.

System und Verfahren zur Handhabung einer Unterbrechung der Versorgungsspannung in einem nichtflüchtigen Speicher

ELEKTRONISCHE UND/ODER ELEKTRISCHE INTEGRIERTE SCHALTUNG MIT ISOLATIONSMITTELN ENES FUNKTIONELLEN MODULS , ISOLATIONSANORDNUNG UND -VERFAHREN SOWIE IHRE VERWENDUNG

SCHREIBSCHUTZ DURCH VERWENDUNG EINES ZWEISIGNAL-STLEMENT MIT PARAMETERÄNDERUNGSFÄHIGKEIT, CHIPAUSWAHL UND WÄHLBARES SCHREIBEN IN NICHTFLÜCHTIGEM SPEICHER

Programmierverfahren und Programmierwiederaufnahmeverfahren für ein nichtflüchtiges Speicherbauelement

Programmierverfahren für ein nichtflüchtiges Speicherbauelement, mit folgenden Schritten: – Programmieren von Daten in eine erste Mehrzahl von Speicherzellen eines nichtflüchtigen Speicherbauelements, – Programmieren einer Bestätigungsinformation, welche mit den in die erste Mehrzahl von Speicherzellen programmierten Daten assoziiert ist, in wenigstens eine zweite Speicherzelle des nichtflüchtigen Speicherbauelements während des Programmierens der Daten in die erste Mehrzahl von Speicherzellen (Schritt 1000) und – Bestimmen, ob die Daten korrekt in die erste Mehrzahl von Speicherzellen programmiert sind, basierend auf der Ermittlung einer Schwellwertspannungsverteilung von wenigstens einem Teil der ersten Mehrzahl von Speicherzellen und der Schwellwertspannungsverteilung der wenigstens einen zweiten Speicherzelle (Schritte 1400 und 1500).

Elektrischer Leistungsschalter mit einem elektronischen Speicher für Kenngrößen und/oder Umrechnungsfaktoren

Ein Leistungsschalter (1) weist eine Schutzeinrichtung (10) und eine von der Schutzeinrichtung (10) getrennt im Leistungsschalter (10) untergebrachte elektronische Speichereinrichtung (40) für Kenngrößen und/oder Umrechnungsfaktoren auf. Eine zu der Speichereinrichtung (40) gehörende Trennschaltung sorgt dafür, dass ein in der Speichereinrichtung (40) befindlicher Speicher (41), insbesondere ein EEPROM, eine geeignete Betriebsspannung erhält, obwohl bestimmte Eigenschaften der Versorgungsspannung geändert werden, die der Speichereinrichtung (40) über Verbindungsleitungen (22, 23) zugeführt werden. Durch die Änderung wird ein Steuersignal für einen Schreibschutzanschluss (WC) des Speichers (41) gewonnen, um den Speicher (41) wahlweise gegen Beschreiben zu sperren.

STORAGE OF DATA IN STORE

Nonvolatile storage device

The operation information read out by the read-out sense amplifier 19 is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section 21 having a SRAM configuration and the second volatile memory section 23 configured with latch circuits, which are respectively connected in parallel with the data line DB. The operation information, which may be provided depending on an operation state of the write-protect information, etc., stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section 21 in response to the identification information linked with the operation information such as address. The operation information such as trimming information, etc., which must be constantly referable is written into the second volatile memory section 23 depending on the identification information which can be output in a constant state. Thus, the ...

A portable data storage device.

A portable data storage device (10)includes a universal serial bus (usb)coupling device (1)and an interface device (2)is coupled to the usb coupling device (1). The portable data storage device (10)also includes a memory control device (3)and a non volatile solid-state memory device (4). The memory control device (3)is coupled betweem the interface device (2)and the memory device (4)to control the flow of data from the memory device (4)to the usb coupling device (1) ...

A portable data storage device

A portable data storage device

WRITING PROTECTION BY USE OF TWO-SIGNAL EXPENSIVE MINUTES FOR AN INTEGRATED CIRCUIT ELEMENT WITH ABILITY OF CHANGE OF PARAMETER, CHIP SELECTION AND SELECTABLE LETTER IN NON VOLATILE MEMORY

PROCEDURE FOR THE RECOGNITION OF AN ATTACK BY ERROR INJECTION IN A MEMORY DEVICE AND AN EQUIVALENT MEMORY DEVICE

ARRANGEMENT, WHICH CONTAINS A MICROCOMPUTER SYSTEM WITH A MICROPROCESSOR, A FIXED PROGRAMME MEMORY AND A READ/WRITE MEMORY AND FOR THE CONTROL OF PLANTS SERVES

DISK UNIT

PROTECTION CIRCUIT FOR PROGRAMMABLE LOGIC ARRAY.

TARIFF EQUIPMENT WITH SAFE BI-DIRECTIONAL INTERFACE.

MEMORY CARTRIDGE

ELECTRONIC AND/OR ELECTRICAL INTEGRATED CIRCUIT WITH ISOLATION MEANS ENES OF FUNCTIONAL MODULE, ISOLATION ARRANGEMENT AND - PROCEDURES AS WELL AS YOUR USE

Single chip microprocessor, math co-processor, random number generator, real-time clock and ram having a one-wire interface

SECURE INTEGRATED CIRCUIT CHIP WITH CONDUCTIVE SHIELD

MEMORY WRITE PROTECTION CIRCUIT

USING TRANSFER BITS DURING DATA TRANSFER FROM NON-VOLATILE TO VOLATILE MEMORIES

Structures and methods for transferring data from non-volatile to volatile memories. An extra bit, called a "transfer bit", is included in each data word. The transfer bit is set to the programmed value, and is monitored by a control circuit during the memory transfer. If the supply voltage is sufficient for correct programming, the transfer bit is read as "programmed", and the data transfer continues. If the supply voltage is below the minimum supply voltage for proper programming, the transfer bit is read as "erased", and the data transfer is reinitiated. In one embodiment, a second transfer bit set to the "erased" value is included in each word.

MOBILE COMMUNICATION DEVICE HAVING INTEGRATED EMBEDDED FLASH AND SRAM MEMORY

The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

GLITCH LOCKOUT CIRCUIT FOR MEMORY ARRAY

GLITCH LOCKOUT CIRCUIT FOR MEMORY ARRAY The present invention relates to a glitch lockout circuit for a static random access memory (RAM) which prevents the writing or reading of incorrect data when a system clock is switched from a standard clock source to an alternate clock source. A dummy bit line is added to the memory arrangement which is always precharged during a first clock phase and discharged during a second clock phase. The state of the dummy bit line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase. Thus, if the dummy bit line stays low, the second clock phase will stay low and none of the RAM cells will be accessed.

METHOD AND APPARATUS FOR SYNCHRONIZING AN INDUSTRIAL CONTROLLER WITH A REDUNDANT CONTROLLER

A method for identifying memory modifications includes designating a first portion of a first memory as read-only. An abort condition is identified responsive to receiving a write instruction having a target address within the first portion. In response to the abort condition, a second portion of the first memory including at least the target address is flagged as being modified. The write instruction is executed.

MEMORY CARTRIDGE

ANTI-TAMPER BOND WIRE SHIELD FOR AN INTEGRATED CIRCUIT

An anti-tamper shield for an integrated circuit (IC) includes a bond wire which passes through a protective layer such as an epoxy encapsulating layer of the IC. The bond wire carries a signal, such as a steady state current, which allows an active component of the IC, such as a secure processor, to function. The bond wire is carried within and/or proximate to the encapsulating layer such that a decapsulation of the IC will cause a rupture of the electrically conductive member, thereby rendering the processor non-functional. The bond wire may be coupled to the processor in a variety of configurations, including the use of internal or external bond pads, lead frame contacts, and/or directly to a computer board on which the IC is carried. A metallic shield layer may be located between the active component and a top portion, of the encapsulating layer to prevent a pirate from using an electron, microscope, for example, to survey the active component region.

PROGRAMMABLE ACCESS PROTECTION IN A FLASH MEMORY DEVICE

A memory device (100) comprises a memory array (102) having corresponding first access control bits (202, 204) to control access thereto. A second set of access control bits (104) is provided to control write access to the first access control bits. The memory array is divided into memory blocks, each block having a corresponding access control bit. At least one such block (BLK0) is further subdivided into pages, each page having a corresponding control bit.

PROCEDURE FOR THE TRANSMISSION AND STORAGE OF INSTALLATION RELATED DATA.

POSTAGE METER AND METHOD FOR INITIALIZING THE, FOR MODIFICATION AND RECONFIGURE.

Memory, or smart, card reader for public telephones

The "smart" card reader consists of a recess (LG) with a slot (FE) through which the card (CM) is inserted. Built into the reader are a microprocessor (MT), which makes contact with the card when fully inserted by means of a connector (CO), a primary high-frequency device (CA) interacting with the )card by induction and a secondary high-frequency device (GE) operating by conduction within the microprocessor itself. One high-frequency device acts as a generator the other as a receiver. Card validation is determined by the microprocessor according to the difference between the signal detected by the receiver and that emitted by the gnerator.

PROCEDURE FOR STORING DATA IN AN ELECTRICALLY ERASABLE MEMORY AND ELECTRICAL OF ERASABLE MEMORY FOR THE EXECUTION OF THE PROCEDURE.

Automaton clock not sensitive to delays.

Mobile memory with Bluetooth anti-leakage and anti-lost effects

USB (Universal Serial Bus) flash disk capable of executing security authentication by wireless data transmission

U-Key disk with switch

The invention aims at providing a U-Key device provided with a switch and solves the problems that in the common U-Key device, the start and close of the U disk or the Key can not be controlled separately, thus avoiding the potential safety hazard of the Key and ensuring the convenience of use. The invention has the beneficial effects that in the use process of the product, two devices are respectively controlled in virtue of the switch, any of which is started and closed according to actual requirement, thus avoiding the use conflict between the two devices, ensuring the safety of the Key but not affecting the convenience of the U disk. Moreover, the U-Key device has simple structure, safety and reliability and very low additional production cost.

Encryption method of power quality monitoring equipment

Feedback type overcharge-prevention sensitive amplifier and control method thereof

Fingerprint voice recording pen

USB status restriction equipment and method of use thereof

The invention relates to a USB state limiting device for reducing abuse of USB device and reinforcing the safety of internal sensitive information of host computer, which comprises a communication module, a control module, a connecting module, a USB port module and an authority module. The communication module is used for realizing communication. The control module is used for controlling the work of internal individual modules in the USB state limiting device, coordinate and control communication work with outside, and monitor whether USB device is inserted into the USB port. The connecting module is used for establishing the connection between the host computer connected with the USB state limiting device and the USB device which is inserted into the USB port. The USB port module is used for connecting with the USB device which is inserted into the USB port to complete information interaction. The authority module is connected with the control module, and at the same time has the functions ...

ELECTRIC SYSTEM AND/OR JUST ELECTRONICS HAVE MEANS Of INSULATION Of FUNCTIONAL UNMODULE, DEVICE AND PROCESS Of INSULATION AND UTILISATIONCORRESPONDANTS

FOR MEMORY READ CIRCUIT

LOCKING DEVICE HAS NEVER A PROGRAMMABLE CELL HAVING A FLOATING GATE.

SAFETY DEVICE OF DATA MEMORISEES USING A CIRCUIT OF TEMPORIZATION

Improved microcircuit card reader

ELECTRIC DETECTOR OF BINARY LOGICAL LEVEL

Control of the current taken by an electronic circuit used in reading the security code from a device such as a bankers card of portable telephone to mask the period during which the code is read, but to reduce the masking period

L'invention propose un procédé de gestion d'un circuit électronique du type comprenant une mémoire (EEPROM) pour le stockage d'informations confidentielles, procédé comprenant le masquage des variations du courant électrique (I) consommé par le circuit électronique, pendant une fraction du temps seulement (ti-tj), et en tout état de cause pendant la ou les portions du temps pendant lesquelles est exécutée, entre autres, une instruction portant sur des données confidentielles, notamment une instruction de lecture dans la mémoire (EEPROM).

MEMORY CIRCUIT COMPRISING MEANS FOR DETECTING A FAULT INJECTION

L'invention concerne un circuit à mémoire (MEM1) comprenant un plan mémoire (MA) comportant des cellules mémoire (MC), et un décodeur d'adresse (RDEC) configuré pour appliquer au plan mémoire des signaux (V0-VI-1, Vsel) de sélection d'un groupe de cellules mémoire en fonction d'une adresse (AD1). Selon l'invention, le circuit à mémoire comprend des moyens (LCT) pour capturer des signaux (Vsel) de sélection de cellules mémoire apparaissant dans le plan mémoire, et des moyens (RCOD), pour reconstituer, à partir des signaux de sélection capturés, une adresse (AD2) d'un groupe de cellules mémoire sélectionné.

METHOD FOR LOWERING POWER CONSUMPTION IN SECURE DEVICES

L'invention concerne un dispositif sécurisé (200) et, plus particulièrement, des systèmes, des dispositifs et des procédés de réduction de la consommation d'énergie du dispositif sécurisé (200) en limitant la quantité de mémoire volatile sécurisée qui doit être alimentée par une batterie (102). Dans un mode d'alimentation de transport, les données sensibles mémorisées à l'origine dans une mémoire volatile (204) sont sauvegardées dans un format chiffré dans une mémoire non volatile (202), de sorte qu'aucune ou seulement une petite zone de la mémoire volatile sécurisée (204) doive être retenue et alimentée par la batterie (102) pour préserver les clés cryptographiques qui sont utilisées pour sauvegarder et récupérer les données sensibles. Ce dispositif sécurisé (200) est appliqué dans des applications à sécurité élevée telles que des terminaux financiers sécurisés.

Dispositif de verrouillage à cellule à grille flottante jamais programmable.

On réalise des dispositifs de verrouillage en utilisant une cellule à grille flottante (1) rendue jamais programmable électriquement en mettant entre sa zone drain (3) et la masse et entre sa zone source (4) et la masse, un limiteur de tension (5 et 6). La cellule n'est plus jamais programmable par rayons ultra-violets à cause de l'interposition d'un pavé de métal (12) au-dessus de sa grille de commande 2. On réalise un limiteur de tension (5 et 6), en utilisant une diode Zener réalisée en joignant aux zones drain (3) et source (4) une zone de dopage opposé (7 et 8), placée à l'extérieur de la zone canal (9) et connectée à la masse.

LOCAL CHECKPOINTING USING A MULTI-LEVEL CELL

READOUT CIRCUIT AND SEMICONDUCTOR DEVICE

감지 회로를 사용한 패리티 결정을 위한 장치들 및 방법들

... 본 개시는 감지 회로를 사용한 패리티 결정들에 관련된 장치들 및 방법들을 포함한다. 예시적인 방법은 감지 회로를 사용하여, 입력/출력 라인을 통해 어레이로부터 데이터를 전송하지 않고 다수의 데이터 값들에 대응하는 패리티 값을 결정함으로써 어레이의 감지 라인에 결합된 각각의 수의 메모리 셀들에 저장된 다수의 데이터 값들을 보호하는 단계를 포함할 수 있다. 패리티 값은 예를 들어, 다수의 XOR 연산들에 의해 결정될 수 있다. 방법은 감지 라인에 결합된 또 다른 메모리 셀에 패리티 값을 저장하는 단계를 포함할 수 있다.

SEMICONDUCTOR MEMORY DEVICE HAVING OVER-STRESS DETECTION FUNCTION AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME, ESPECIALLY COMPRISING MRS DECODER GENERATING DETECTION CONTROL SIGNAL

PURPOSE: A semiconductor memory device having an over-stress detection function and a semiconductor memory system including the same are provided to prevent the damage of the semiconductor memory device due to over-stress by detecting over-stress state of a frequency of a memory clock signal, external voltage and temperature. CONSTITUTION: According to the semiconductor memory device(100), an over-stress detection unit(200) is enabled or disabled in response to a detection control signal, and judges whether one of a memory clock signal and an external voltage and temperature is out of a set condition when it is enabled, and outputs a flag signal according to the judgment result. An MRS(Mode Register Set) decoder(101) generates the detection control signal in response to a first address signal or a command signal received from the external. The MRS decoder further outputs a reset control signal in response to the command signal and a second address signal, and the over-stress unit is reset ...

PROGRAMMABLE MAGNETIC MEMORY DEVICE FP-MRAM

A memory device has an information plane (32) for storing data bits in a magnetic state of an electro-magnetic material at an array of bit locations (31). The device further has an array of electro-magnetic sensor elements (51) that are aligned with the bit locations. The information plane (32) is programmable or programmed via a separate magnetic writing device (21). In particular a read-only sensor element (60) is described for a read-only magnetic memory. © KIPO & WIPO 2007 ...

MEMORY SYSTEM WITH MULTIPLE STRIPING OF RAID GROUPS AND METHOD FOR PERFORMING THE SAME

memory controller for use in access concentration decrease menagement and access concentration decrease method

Hardware anti-piracy via nonvolatile memory devices

One embodiment of the present disclosure may take the form of protected or safeguard memory, such as a nonvolatile memory device. In operation, the nonvolatile memory device may not perform a command operation, such as a read operation, on locked password-protected sectors of a primary memory array. Once a password is provided to the nonvolatile memory device (for example, from or via an associated electronic device), the nonvolatile memory device may unlock the password-protected sectors.

Integrated setback read with reduced snapback disturb

Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

Data protection method

The invention provides a data protection method, which is applied in a data storage device. The data storage device comprises a controller and a plurality of flash memories. The flash memories forms a data storage zone. When the user wants to protect at least one specific data in the data storage device, it will send a write filter command to the data storage device by a host. After the controller of the data storage device receives the write filter command, it will execute a write filter process. When the write filter process is executing, the controller divides at least a first partition and a second partition from the data storage zone, and sets the first partition as a read-only area for prohibiting data movement, so that the specific data stored in the first partition can be protected because it is forbidden to be moved.

Integrated semiconductor-memory and method to reset the memory-cells of an integrated semiconductor-memory

An integrated semiconductor-memory with memory-cells (MC) in a memory-cells array (1) has a decoder (2) to select one of the memory-cells (MC) and a control-circuit (3), which is connected with the memory-cell-array (1) and the decoder (2). The memory-cells (MC) are combined to each unit (4), which through the control-circuit (3) and the decoder (2) a parallel reset of the memory-cells (MC) inside the units (4) is carried out with a pro-given data-signal (DA) and a sequential reset of each unit (4) is carried out with the pro-given data-signal (DA). The detectability of the current-profile generated in reset is thus restricted, thus the data-safety of the semiconductor-memory relative to the access is improved.

Management apparatus, system, and method for protecting a memory storage card

CONTROLLED DATA ACCESS TO NON-VOLATILE MEMORY

A method of controlling data access to non-volatile memory is disclosed. The method includes storing a data file in a non-volatile memory. The non-volatile memory includes a memory array addressable by a plurality of address ranges one or more of which corresponding to a protected portion of the memory array and one or more of which corresponding to an unprotected portion of the memory array. The method also includes communicating to a host device an indication that a memory request with respect to the protected portion of the memory array is denied. The indication is communicated for instructing the host device to avoid a timeout.

MEMORY CIRCUIT COMPRISING MEANS FOR DETECTING AN ERROR INJECTION

The invention relates to a memory circuit (MEM1) comprising a memory plane (MA) comprising memory cells (MC), and an address decoder (RDEC) configured to apply to the memory plane signals (V0-VI-1, Vsel) for selecting a group of memory cells as a function of an address (AD1). According to the invention, the memory circuit comprises means (LCT) for capturing signals (Vsel) for selecting memory cells appearing in the memory plane, and means (RCOD), for reconstructing, on the basis of the selection signals captured, an address (AD2) of a selected group of memory cells.

PROGRAMMABLE MAGNETIC MEMORY DEVICE FP-MRAM

A memory device has an information plane (32) for storing data bits in a magnetic state of an electro-magnetic material at an array of bit locations (31). The device further has an array of electro-magnetic sensor elements (51) that are aligned with the bit locations. The information plane (32) is programmable or programmed via a separate magnetic writing device (21). In particular a read-only sensor element (60) is described for a read-only magnetic memory.

PROTECTION CIRCUIT FOR MEMORY IN DISPLAY PANEL AND DISPLAY PANEL

Disclosed in the present application are a protection circuit for a memory in a display panel and a display panel. Said circuit comprises a timing controller, a memory, a power supply circuit and a switch circuit. By removing a write protection signal originally provided by a computer, the power supply circuit outputs a stable and reliably write protection signal to the memory, so as to limit the data of the memory to be rewritten, and the timing controller controls the switch circuit to be turned on to connect the control terminal of the write protection signal of the memory to ground only when receiving an instruction for writing data to the memory.

ARRANGEMENT FOR AUTOMATIC ERASING OF THE INFORMATION CONTENTS IN DATA BASES

Arrangement to destroy by erasing the information contents in data memories and program memories included in a data base installation, without destroying the equipment. An operation device (MO) is brought to activate a first group of parallelly working address generators (AD1-ADn), these generators successively generating and selecting all addresses in a memory (DS1-DSn) which is separately connected to each of the generators and which is part of a first memory group. Gate circuits (GD11-GDn4) are connected to the data inputs on each memory unit in this first memory group through which binary digits of the same logical level is written into the selected addresses of the memories irrespective of what is already written there. The operation device (MO) also activates a second group of parallelly working address generators (AP1-APn), these generators successively generating and selecting all addresses in a memory (PS1-PSn) which is separately connected to each of the generators, said memory ...

Information storage apparatus and information processing apparatus using the same

In a small and thin memory module for sharing data among electronic devices such as information processing apparatuses, a write prohibit state can be visually recognized. A conductive seal is attached to a predetermined position on a support member, thereby setting the memory module in the write prohibit state. The conductive seal visually indicates the write prohibit state. When the memory module is mounted in a connector section of a card-shaped holder, connector pins are electrically connected to each other via the conductive seal. Thus, a write prohibit mechanism is realized at low cost.

Fusing and detection circuit

A fusing and detection circuit includes a diode fusing element which is coupled to a fuse input terminal of an integrated circuit. Upon the application of the proper voltage at the fuse input terminal, the fuse element is blown, causing the diode to become a low impedance resistor. The detection circuitry senses whether the fuse has been blown or not and provides a lock or unlock indication at an output terminal. The fusing and detection circuit is designed to thwart attempts to change the lock status to an unlock status after the fuse has been blown.

Secure module with microprocessor and co-processor

An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.

Programmable time base circuit with protected internal calibration

A timeout circuit with internal calibration includes an oscillator (11) for generating an initial frequency for division by a modulo-n counter (20). The counter (20) receives the value of n from a calibration register (22) and divides the frequency of the oscillator by the value of n. A gate (26) prevents alteration of the contents of the register (22). The output of the counter (20) provides a calibrated frequency which is further divided by a day counter (32) for output to a countdown counter (34). The countdown counter (34) provides a predetermined countdown of the signal output by the day counter (32) and, at the end of the count, generates a Timeout signal. The predetermined countdown value is determined by a value stored in a register (36) which can be protected by a customer lock out circuit (42).

System and method to protect SDRAM data during warm resets

A system and method in which a warm-reset request event is detected by reset hardware that subsequently blocks the warm reset request and places the SDRAM in a self-refresh mode in which the SDRAM data continually refreshes its stored data. Once the SDRAM is in the self-refresh mode the reset hardware resets the SDRAM's controller. Because the SDRAM is in the self-refresh mode when its controller is reset, none of the invalid signals on the controllers control lines will affect the stored data.

Programmable power supply systems and methods providing a write protected memory having multiple interface capability

A programmable power controller controls power between a primary power source and a secondary power source and powering first circuitry. The primary power source has a first voltage and the secondary power source has a second voltage. A control register has a first field, which is field used to activate circuitry used to direct power from the primary power source to the secondary power source. First logic circuitry compares the first voltage and the second voltage to determine which is greater and then couples the primary power source or the secondary power source, depending upon which is greater, to power the first logic circuitry, second logic circuitry, and memory. The memory is coupled to the first logic circuitry and is read and written to via an input/output buffer. The second logic circuitry is coupled to the memory and to said first logic circuitry and activates write protection circuitry to prevent writing to the memory if the secondary power source is powering the first logic ...

Write protection security for memory device

An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.

System and method for write-protecting predetermined portions of a memory array

A system and method wherein a predetermined soft fuse value may be written to a corresponding soft fuse register to control subsequent access to a number of lock bits in a non-volatile semiconductor memory array which are provided for selectively precluding writes to predetermined portions of the memory array. In a specific embodiment, the system and method may be utilized in conjunction with radio frequency ("RF") identification ("ID") transponders incorporating a non-volatile ferroelectric random access memory ("FRAM") array integrated circuit.

Non-volatile storage device with physical authentication

A non-volatile memory device uses physical authentication to enable the secure programming of a boot partition, when the boot partition is write protected. This physical authentication can also be used to enable other features/functions.

Method and arrangement for the verification of NV fuses as well as a corresponding computer program product and a corresponding computer-readable storage medium

The invention relates to a method and an arrangement for the verification of NV fuses as well as to a corresponding computer program product and to a corresponding computer-readable storage medium which can be used notably for the detection of attacks on the smart card security which modify EEPROM contents and hence also the contents of EEPROM fuses. During the reset phase the fuses are read from the EEPROM. The fuse values successively read out are then automatically verified. One possible implementation is, for example, to load the fuse values read out into a signature register, followed by comparison with a reference value. Appropriate security measures can be activated should the automatic verification indicate an error, for example, due to unauthorized modification of a fuse or attack on the boot operation.

SYSTEM AND METHOD FOR PROBABILISTIC DEFENSE AGAINST REMOTE EXPLOITATION OF MEMORY

A system and method is provided for probabilistic defense against remote exploitation of memory. In certain embodiments, the system comprises one or more processors, read and execute (RX) portions of memory, read and write (RW) portions of memory, execute only (XOM) portions of memory, and one or more programs stored in the memory. The one or more programs include instructions for maintaining all pointers to RX memory instructions in XOM memory. In addition, the one or more programs include instructions for preventing all direct references to RX memory in RW memory by forcing pointers in RW memory to reference XOM memory first, which then references RX memory instructions.

Multiple location load control system

A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source.

STORAGE DEVICE, NON-VOLATILE MEMORY DEVICE, AND METHOD OF OPERATING THE NON-VOLATILE MEMORY DEVICE

A storage device, a non-volatile memory device, and a method of operating the non-volatile memory device are provided. The storage device includes a storage controller configured to send a command and program data including a pattern of one or more bits, a non-volatile memory device configured to receive the command and the program data, and a pattern monitoring circuit configured to monitor a pattern of the program data sent from the storage controller. The pattern monitoring circuit is configured to send an abnormal status check bit to the storage controller when the program data includes repeated patterns that are repeated a preset number of times or more, and the storage controller is configured to resend the program data to the non-volatile memory device in response to receiving the abnormal status check bit.

Mobile communication device having integrated embedded flash and sram memory

METHOD AND DEVICE FOR PROTECTION OF AN MRAM DEVICE AGAINST TAMPERING

An apparatus and a method for erasing data stored in a memory device

The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal. Such an approach enables the security of a memory device to be improved, and in particular prevents hackers from taking advantage ...

Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering

An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity (2, 4, 6, 30; 12, 14, 16, 32) with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants (C) in the substrate (38) rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops (CSO) so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads (8, 18, 28, 34) over the transistor array, with a uniform pattern of heavily doped implant taps (ST, DT) from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.

STORED INFORMATION PROTECTING CIRCUIT

PURPOSE: To inhibit the reading of any arbitrary bit and any arbitrary area in an EPROM with simple constitutive circuits by adding an EPROM cell for writing data for read inhibition to wiring. CONSTITUTION: When inhibiting the read of the EPROM at the time of a PROM mode, a read inhibit control signal 117 is previously written into an EPROM cell 101 as a prescribed high voltage. When write is performed by injecting electric charges to the floating gate of the EPROM cell 101 with FAMOS structure, since the threshold voltage is increased, the EPROM cell 101 keeps an OFF state even when the read inhibit control signal 117 is turned to a logical level H. Therefore, the voltage level of a drain 113 at the EPROM cell 101 is pulled up to a power supply level through a resistor 108 and turned to H. Since a gate input is turned to H, an (n) channel MOS transistor 103 is turned on, and the voltage of a drain 1 14 at the (n) channel MOS Tr 103 is turned to an L level. COPYRIGHT: (C)1995,JPO ...

MAIN MEMORY UNIT

PURPOSE: To make it possible to use a write control part for each band in common by preventing a write to other memory modules for a certain period after a certain time passes since a start of a partial write to one memory module. CONSTITUTION: When a write or read request is given to the main memory unit within one cycle, partial write data are stored in register 2 of the bank. Then, the bus is released which consists of interface control part 1, selector circuit 3, error- correction code generating circuit 4, and memory part 6. After time (t1) passes, a bus to a band different by time (t2) when rewrite data obtained through matching with error detecting correction circuit 5 by selector circuit 3 are written in memory part 6 becomes impossible. Through the control not to send out a request for inputting all write data to selector circuit 3 after time (t1), therefore, marks of all write data and rewrite data by selector circuit 3 are eliminated, so that the data system control circuit of ...

INSPECTION METHOD OF SEMICONDUCTOR MEMORY DEVICE

PURPOSE: Not to sacrifice test precision of semiconductor memory of mass storage capacity and, moreover, to shorten testing time in a semiconductor memory device constituted as follows that an arrangement of memory cells constituted in an equal semiconductor integrated circuit is divided to each memory cell group having a common input line or output line. COPYRIGHT: (C)1977,JPO&Japio ...

ВОСПРОИЗВОДЯЩЕЕ УСТРОЙСТВО И СПОСОБ ВОСПРОИЗВЕДЕНИЯ

Изобретение относится к воспроизводящему устройству и к способу воспроизведения для проверки поддельной информации файла, записанного в съемной карточке памяти. Технический результат: возможность надежного опознавания поддельной информации ограничения воспроизведения и предотвращение воспроизведения содержимого с карточки памяти. Технический результат достигается тем, что в воспроизводящее устройство для воспроизведения данных с носителя записи, зону программы которого используют для записи множества файлов, а зону управления - для управления запрещающей подделку информацией относительно файла, записанного в зоне программы, содержит вычислительное средство для вычисления запрещающей подделку информации при каждом воспроизведении файла, сравнивающее средство для сравнения величины, вычисленной при команде на воспроизведение, с предшествующей текущей, с величиной, вычисленной при текущей команде на воспроизведение, и при совпадении этих величин сохраняют последнюю величину в качестве величины ...

ОПТИЧЕСКИЙ НОСИТЕЛЬ ИНФОРМАЦИИ, УСТРОЙСТВО И СПОСОБ ЗАПИСИ НА НЕГО/ВОСПРОИЗВЕДЕНИЯ С НЕГО И НОСИТЕЛЬ ИНФОРМАЦИИ, СЧИТЫВАЕМЫЙ КОМПЬЮТЕРОМ, НА КОТОРОМ ХРАНИТСЯ ПРОГРАММА ДЛЯ ВЫПОЛНЕНИЯ СПОСОБА

... 1. Оптический носитель информации, на котором записан блок элемента записи/воспроизведения, причем блок элемента записи/воспроизведения содержит недостоверные данные, используемые в сертификации диска, и идентификатор дополнения для указания, что в блок элемента записи/воспроизведения включены недостоверные данные, причем недостоверные данные используются при сертификации диска на части оптического носителя информации или на всем оптическом носителе информации. 2. Оптический носитель информации по п.1, в котором блок элемента записи/воспроизведения содержит блок данных, включающий в себя недостоверные данные, и блок доступа для доступа к блоку данных, причем блок доступа включает в себя информацию адреса недостоверных данных в блоке данных и идентификатор дополнения. 3. Оптический носитель информации по п.1, в котором блоком элемента записи/воспроизведения является физический кластер, содержащий LDS (длинной протяженности) кластер, и BIS (подкода индикатора пакета) кластер, BIS-кластер ...

Устройство для стирания информации в перепрограммируемых блоках памяти

УСТРОЙСТВО ДЛЯ СТИРАНИЯ ИНФОРМАЦИИ В ПЕРЕПРОГРАММИРУЕМЫХ БЛОКАХ ПАМЯТИ, содержащее формирователь адресных сигналов j накопитель, один вход которого подключен к выходу формирователя адресных сигналов,отличающееся тем, что, с целью повышения надежности устройства за счет исклю:чения несанкционированного стирания информации, в него введены элемент ИЛИ-НЕ, элемент И, причем входы элемента ИЛИ-НЕ подключены к другим входам накопителя и являются адресными входами устройства, выход элемента ШШ-НЕ соединен с одиим входом элемента И, другой вход которого является управляющим входом устройства, выход элемента И подключен к входу формирователя адресных сигналов. (Л ...

Блок считывания информации для запоминающего устройства

Изобретение относится к вычислительной технике и предназначено для использования в магнитных запоминающих устройствах. Целью изобретения является повьшение надежности блока считывания. Устройство содержит предварительный усилитель,фильтр усилитель воспроизведе.ния, дискриминатор , формирователь строба, блок задержки, группу усилителей воспроизведения , группу дискриминаторов, группу формирователей строба, группу фильтров, элементы И, элемент ИЛИ. В блоке достигается повышение надежности за счет организации анализа и параметров системных сигналов. 1 ил. (Л с: ю 00 00 00 4 со ...

Halbleiterbauelement mit einer lichtundurchlässigen Schicht

ELEKTRISCHE/ELEKTRONISCHE SCHALTUNGSANORDNUNG

Memory erase methods and devices

Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.

Electrostatic discharge protection circuit

An electrostatic discharge protection circuit includes a diode chain coupled between a power supply voltage end and a control node, a control voltage generator configured to generate a control voltage in response to a first current flowing through the diode chain, and a discharger configured to discharge a second current from the power supply voltage end to a ground voltage end in response to the control voltage, wherein the diode chain includes a plurality of P-well regions formed in an N-well region, diodes formed in the respective P-well regions, and a resistor coupled between the diodes.

Implementing physically unclonable function (puf) utilizing edram memory cell capacitance variation

A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data.

Memory module cutting off dm pad leakage current

A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.

Data storage medium having security function and output apparatus therefor

Provided are a storage medium, which has a security function, for storing media content and an output apparatus for outputting data stored in the storage medium. The storage medium includes a controller for converting at least one of a position of pins of a connector and a storage position of media content in a memory unit in order to control transmission of the media content in the memory unit to the output apparatus.

Mobile terminal, memory card socket and method of writing protection for memory card in the mobile terminal

The present invention provides a mobile terminal, a memory card socket and a method of writing protection for a memory card in the mobile terminal. The mobile terminal comprising a memory card socket accommodating a pluggable memory card, the memory card socket externally provided with a metal shielding structure; the mobile terminal further comprising: a touch capacitance sensor connected to the metal shielding structure of the memory card socket and configured to sense a capacitance via the metal shielding structure; and a write control unit configured to determine whether the metal shielding structure is touched by a finger based on the capacitance sensed by the touch capacitance sensor, and prohibit data being written into the memory card when it is determined that the metal shielding structure is touched by a finger. The present invention ensures that the data can be safely written into the memory card.

Method for discharging a voltage from a capacitance in a memory device

In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by an architecture of the discharge circuit.

Non-volatile semiconductor memory device

A non-volatile semiconductor memory device includes: a power supply unit; a memory cell array powered on or off by the power supply unit; and a read unit for reading data recorded on the memory cell array, wherein the data recorded on the memory cell array is not read in response to a control signal, when the memory cell array is powered on or off.

Nonvolatile Memory And Writing Method Thereof, And Semiconductor Device

A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit. 1. A memory device comprising: a plurality of first memory cells; and', 'at least one second memory cell; and, 'a memory cell array comprisinga circuit for writing data to the plurality of first memory cells and the second memory cell,wherein, when the writing of the data to one of the plurality of first memory cells fails, the circuit is arranged to assign an address of the one of the plurality of first memory cells to the second memory cell and write the data to the second memory cell.2. The memory device according to claim 1 , further comprising an antenna which is capable of receiving an electric wave.3. The memory device according to claim 1 , wherein the plurality of first memory cells and the second memory cell are arranged to irreversibly change an electrical resistance thereof when the data is stored therein.4. The memory device according to claim 1 , further comprising a second circuit for confirming whether the data is normally stored in the plurality of first memory cells.5. The memory device according to claim 4 , further comprising a third circuit coupled with and arranged to ...

Semiconductor memory device, reading method thereof, and data storage device having the same

A reading method of a semiconductor memory device having a multi-level memory cell includes the steps of: reading flag data indicating whether the most significant bit (MSB) of data programmed in the multi-level memory cell is programmed or not; storing the read flag data; reading the least significant bit (LSB) of the data programmed in the multi-level memory cell, based on the read flag data; and reading the MSB of the data programmed in the multi-level memory cell based on the stored flag data.

DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP

A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. 1. A method for clearing a dynamic random access memory (DRAM) at power up , the method comprising the steps of:providing memory cells with a transistor body and a reference voltage connection to the transistor body;generating a boosted voltage during a period after the power up of the DRAM;removing the reference voltage connection to the transistor body;applying the boosted voltage to the transistor body of the memory cells in the DRAM; andallowing capacitors of the memory cells to equalize in voltage to clear data contents of the DRAM.2. The method of further comprising the step of:generating a power on reset (POR) signal on a chip containing the DRAM to generate the period for the boosted voltage.3. The method of further comprising an on chip circuit to provide the POR signal.4. The method of wherein the step of removing a reference voltage connection to the transistor body utilizes a body tie transistor that responds to a boost signal to remove the reference voltage connection between the body of the transistor and a reference voltage to allow the charge pump to provide the boosted voltage to the body of the transistor.5. The method of wherein the boosted voltage is provided by a charge pump.6. The method of wherein the DRAM comprises NFET transistors. ...

Nonvolatile memory device and operating method thereof

Disclosed is a memory system which includes a nonvolatile memory device configured to store data information; and a memory controller configured to control the nonvolatile memory device. The memory controller provides the nonvolatile memory device with a program command sequence including program speed information according to an urgency level of an internally requested program operation.

Repair method and device for abnormal-erase memory block of non-volatile flash memory

A repair method for an abnormal-erase memory block of a non-volatile flash memory is provided. The method includes steps of: sequentially scanning bit data in a page of a block when reading data in a NAND flash; determining whether the page is an abnormal-erase page; setting logic “0” bit data in the page to logic “1” when the page is an abnormal-erase page; and re-erasing the block.

PHYSICAL UNCLONABLE FUNCTION WITH IMPROVED START-UP BEHAVIOR

An electric physical unclonable function (PUF) () is provided comprising a semiconductor memory element () connectable to a PUF control means for reading content from the memory element and for deriving at least in part from said content a digital identifier, such as a secret key. Upon powering the memory element it settles into one of at least two different stable states. The particular stable state into which the memory element settles is dependent at least in part upon random physical characteristics of the memory element introduced during manufacture of the memory element. Settling of the memory element is further dependent upon a control input () of the memory element. The electric physical unclonable function comprises shielding means () for shielding, during a time period including the power-up of the memory element and lasting at least until the settling of the memory element, the control input from receiving control signals upon which the particular stable state into which the memory element settles is dependent. In this way, the dependency of the memory element on its physical characteristics is improved, and dependency on possibly irreproducible control signals is reduced. 119.-. (canceled)22. An electric physical unclonable function as in claim 21 , wherein the interconnected semiconductor gates comprises at least two gates connected in a cross-coupled loop.23. An electric physical unclonable function as in claim 22 , wherein at least one of the two gates connected in the cross-coupled loop is a multiple input gate.24. An electric physical unclonable function as in claim 23 , wherein the memory element is a latch claim 23 , a flip-flop or a register.25. An electric physical unclonable function (PUF) as in claim 20 , wherein the time period lasts at least until the reading of the content of the memory element by the PUF control means.26122. An electric physical unclonable function as in claim 20 , wherein the deriving of the digital identifier depends on ...

Nonvolatile memory device and program method thereof

Disclosed is a nonvolatile memory device which includes a nonvolatile memory including a plurality of LSB and MSB pages at a plurality of wordlines; and a controller controlling the nonvolatile memory. The controller controls the nonvolatile memory such that an LSB program operation on a first wordline (first LSB page) of the plurality of wordlines is programmed and then an LSB program operation on a second wordline of the plurality of wordlines (second LSB page) is programmed. When the LSB program operation on the second wordline (second LSB page) is performed, the nonvolatile memory stores information about LSB data programmed at the first wordline (first LSB page) at a spare area of the second wordline (second LSB page).

Semiconductor device capable of block protection

A semiconductor device includes: a memory cell array comprising a plurality of blocks each comprising a memory cell arranged at an intersection between a word line and a bit line; and a block state information storing unit configured to store state information of the respective blocks. The block state information storing unit stores lock state information to partially limit access to each of the blocks in response to a power-up signal.

Integrated circuit chip and memory device

A memory device includes a pad that provides an interface with an exterior, a first setting unit that generates a termination setting signal for setting the pad for a purpose of termination data strobe using a first specific code of a mode register set operation, a second setting unit that generates a mask setting signal for setting the pad for a purpose of data mask using a second specific code of the mode register set operation, and a third setting unit that generates a write inversion setting signal for setting the pad for a purpose of write data bus inversion using third specific code of the mode register set operation. When a setting signal with a higher priority is activated, a setting signal with a lower priority is deactivated regardless of a value of the corresponding code.

Memory system

A memory system includes a processor and a plurality of memories. The processor includes a plurality of ECCs having different error restoration rates with each other, and a plurality of memories is coupled to the plurality of ECCs, respectively, according to distances from the processor.

System and Method for Employing Secure Non-Volatile Storage Devices in Gaming Machines

A write-protection system and method for use with a gaming machine. The system having a non-volatile data storage device, an interface device and an electrically conductive connector. The storage device having electronic data storage and a write-protection controller providing a write-protected state and a write-permitting state, the electronic data storage being blocked from receiving electronic write commands in the write-protected state and being able to receive write commands in the write-permitting state. The interface device electrically connecting the data storage device to a power supply and control circuitry of the gaming machine. The interface device connected to the electronic data storage through the controller and the connector. 1. A write-protection system for use with a gaming machine , comprising:a non-volatile data storage device having electronic data storage operatively connected to a write-protection controller, the controller having a control element, associated circuitry and control logic stored on a computer-readable medium for activating a write-protected state and a write-permitting state, in the write-protected state electronic write commands being blocked from being received by the electronic data storage by the controller and in the write-permitting state electronic write commands being able to be received by the electronic data storage;an interface device electrically connecting the data storage device to a power supply and control circuitry of the gaming machine, the interface device connected to the electronic data storage through the controller, andan electrically conductive connector connecting the controller and the interface device, the connector carrying a voltage generated by the power supply.2. The system of where the interface is a serial advanced technology attachment interface.3. The system of where the interface device and storage device have separate connections for the transmission of data and power supplied to the storage ...

STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY

A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information. 1. A stacked memory chip device , comprising:a plurality of stacked memory chips;read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips;data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive data of a particular one of the cache lines is not stored in a same memory chip with the respective substantive data, the information to protect the substantive data of the cache lines being one of mirroring information and ECC information.2. The stacked memory chip device of where the information is to be stored at row/column granularity.3. The stacked memory chip device of where the information is to be stored at bank granularity4. The stacked memory chip device of wherein the information is to be stored in a region of the plurality of memory chips that is reserved for storage of respective information to protect respective substantive data of multiple cache lines.5. The stacked memory chip device of wherein the information is ...

Integrated circuit for storing information

An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.

Memory Device with a Fuse Protection Circuit

A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse. 1. A memory device comprising: a supply line configured to receive a supply voltage,', 'a memory cell including a fuse, and', 'a program line configured to receive a program voltage for programming the fuse; and, 'a memory circuit, including'}a fuse protection circuit coupled to the memory circuit, wherein the fuse protection circuit is configured to couple one of the supply line and the program line to a ground when an electro-static discharge (ESD) current flows through the other of the supply line and the program line.2. The memory device of claim 1 , further comprising an ESD protection circuit coupled to the memory circuit and configured to reduce an ESD voltage to a reduced ESD voltage claim 1 , wherein the ESD current is associated with the reduced ESD voltage.3. The memory device of claim 1 , further comprising a second program line selectively coupled to the program line claim 1 , wherein the fuse protection circuit is configured to couple the second program line to the ground in the presence of the ESD current on one of the supply line and the program line.4. The memory device of claim 1 , further comprising a word line coupled to the memory cell claim 1 , wherein the fuse protection circuit is configured to couple the word line to the ground when the detector detects the ESD current.5. The memory device of claim 1 , further comprising:a second program line; anda program enabling circuit coupled between the program line and the second program line and configured to receive an enable signal and to selectively couple and decouple the second program line to and from the program line ...

Cryptographic key management

Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.

Write protection circuit for memory and display apparatus

A write protection circuit for memory and a display apparatus are provided. The write protection circuit includes an interference signal absorbing circuit connected with a data writing triggering terminal to absorb a first level signal when the receiving of the first level signal by the data writing triggering terminal is detected.

PROTECTION CIRCUIT OF MEMORY IN DISPLAY PANEL AND DISPLAY APPARATUS

Disclosed is a protection circuit of a memory in a display panel. The circuit includes: a timing controller (), for outputting a first control signal; a memory (), for storing software data of the timing controller (); a power supply circuit (), for outputting a power signal; and a monitor circuit (), having three input ends and a signal output end, two input ends being respectively connected to the power supply circuit () and a control signal output end, and the other one input end being input with a write control signal; the monitor circuit () controls the memory () to be in a write protection state when in a normal state, and controls the memory () to be in a write enable state when a level state collection of the power signal, the first control signal, and the write control signal satisfies a preset level state collection. 1. A protection circuit of a memory in a display panel , comprising:a timing controller, having a signal transmission end and a control signal output end, the timing controller being configured to output a first control signal of high/low level;a memory, having a signal transmission end and a write protection control end, the signal transmission end of the memory being connected to the signal transmission end of the timing controller; the memory being configured to store software data of the timing controller;a power supply circuit, being configured to output a power signal; anda monitor circuit, having a first input end, a second input end, a third input end, and a signal output end, the first input end being connected to the power supply circuit, the second input end being connected to the control signal output end, the third input end being configured to be input with a write control signal, and the signal output end being connected to the write protection control end;wherein the monitor circuit is configured to:output a write protection signal when in a normal state, to control the memory to be in a write protection state; andoutput a ...

Memory structure for self-erasing secret storage

In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

Storage system and method for die-based data retention recycling

The subject technology performs the following in a storage system including memory dies, where each memory die includes its own temperature sensor. The subject technology determines a temperature of each of the memory dies based on a temperature reading from each memory die's temperature sensor. The subject technology determines whether data is hot data or cold data, where hot data is more likely to be changed after it is written than cold data. In response to determining that the data is hot data, the subject technology stores the data in a memory die with a relatively higher temperature than another one of the memory dies. Further, in response to determining that the data is cold data, the subject technology stores the data in a memory die with a relatively cooler temperature than another one of the memory dies.

SEMICONDUCTOR MEMORY DEVICE INCLUDING A CONTROL CIRCUIT AND AT LEAST TWO MEMORY CELL ARRAYS

A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state. 1. A semiconductor memory device , comprising:a memory cell array;a cache that holds data transferred from the memory cell array; anda control circuit configured to output first information indicating whether or not access to the cache from outside the device is available and second information indicating whether or not a reservation for access to the cache from outside the device is available.2. The device according to claim 1 , wherein the control circuit includes a first pad through which the first information is output and a second pad through which the second information is output.3. The device according to claim 1 , wherein a first command received from outside the device has the access to the cache and a second command received from outside the device subsequently to the first command has the reservation for the access.4. The device according to claim 3 , wherein the control circuit includes a first register for storing an address specified in the first command and a second register for storing an address specified in the second command.5. The device according to claim 4 , wherein the control circuit outputs information that the reservation for access to the cache from outside the device is available through the second information upon completion of the first command.6. The device according to claim 5 , wherein an address specified in a third ...

PHYSICAL UNCLONABLE FUNCTION FOR NON-VOLATILE MEMORY

A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port. 1. A method for generating a data set for storage on a memory , comprising:generating, by a first circuit, first level security information having N bits of data, N being an integer greater than 1;generating, by a second circuit, second level security information having M bits of data, the second level security information being generated as a function of the N bits of data of the first level security information, M being an integer that is less than N; andstoring the second level security information in the memory as the data set.2. The method of claim 1 , wherein the first circuit is a random number generator and the N bits of data of the first level security information are obtained from a randomly generated number.3. The method of claim 2 , wherein the random number generator is a physical unclonable function (PUF) circuit and the N bits of data of the first level security information are obtained using the randomly generated number and programmable memory cells of the PUF circuit.4. The method of claim 1 , wherein the function used to generate the second level security information is a hash function.5. The method of claim 4 , wherein the second circuit applies the hash function to the first level ...

PHYSICAL UNCLONABLE FUNCTION FOR NON-VOLATILE MEMORY

A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port. 1. A method for generating a data set on an integrated circuit including a set of programmable memory cells , comprising:exposing the set of programmable memory cells having addresses on the integrated circuit to a process inducing variant thresholds in the programmable memory cells in the set within a starting distribution of thresholds;finding a first subset of the set of programmable memory cells having thresholds in a first part of the starting distribution, and a second subset of the set of programmable memory cells having thresholds in a second part of the starting distribution; andusing the addresses of at least one of the first and second subsets to generate the data set.2. The method of claim 1 , wherein said using the addresses includes:selecting the programmable memory cells using the addresses of the programmable memory cells in said at least one of the first and second subsets;applying a biasing operation to the selected programmable memory cells to establish a changed distribution of thresholds for the set of programmable memory cells, the changed distribution having a sensing margin between the first and second subsets; andreading the programmable memory cells in the set using a read ...

PHYSICAL UNCLONABLE FUNCTION USING DIVIDED THRESHOLD DISTRIBUTIONS IN NON-VOLATILE MEMORY

A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port. 1. A method for generating a data set on an integrated circuit including a set of programmable memory cells , comprising:exposing the set of programmable memory cells having addresses on the integrated circuit to a process inducing variant thresholds in members of the set within a starting distribution of thresholds;finding a first dividing line and a second dividing line different than the first dividing line, in the starting distribution;identifying a first subset of the set of programmable memory cells having thresholds below the first dividing line in a first part of the starting distribution, and a second subset of the set of programmable memory cells having thresholds above the second dividing line in a second part of the starting distribution; andgenerating the data set using addresses of at least one of the first and second subsets.2. The method of claim 1 , wherein said generating the data set includes using the addresses to select memory cells in said at least one of the first and second subsets; andreading the programmable memory cells in the set using a read voltage between the first and second dividing lines.3. The method of claim 1 , wherein said generating the data set includes ...

Non-volatile Memory Device With Secure Read

Technology that provides security for a requestor of data stored in a non-volatile memory device is disclosed. In one aspect, the non-volatile memory device provides data on a host interface only if a digest for the data matches an expected digest for the data. The non-volatile memory device may store expected digests for data for various logical addresses. Upon receiving a request on the host interface to read data for a logical address, the non-volatile memory device may access the data for the logical address, compute a digest for the accessed data, and compare the computed digest with the expected digest. The non-volatile memory device provides the accessed data on the host interface only if the computed digest matches the expected digest, in one aspect. The non-volatile memory device may be used to provide a secure boot of a host. 1. An apparatus , comprising:non-volatile memory;a host interface; and access data stored in the non-volatile memory in response to a request on the host interface for data for a logical address;', 'compute a digest of the accessed data; and', 'provide the accessed data on the host interface only if the computed digest matches an expected digest for data for the logical address., 'a control circuit in communication with the non-volatile memory and the host interface, the control circuit configured to2. The apparatus of claim 1 , wherein the control circuit is further configured to:verify integrity of the accessed data based on whether the computed digest matches the expected digest; andprovide the accessed data on the host interface only if the integrity of the accessed data is verified.3. The apparatus of claim 2 , wherein the control circuit is further configured to:verify authenticity of the accessed data based on whether the computed digest matches the expected digest; andprovide the accessed data on the host interface only if the authenticity of the accessed data is verified.4. The apparatus of claim 1 , wherein the control ...

RRAM-BASED MONOTONIC COUNTER

A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit. 1. A circuit , comprising:a memory array having a plurality of memory cells;a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state;a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; andan encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.2. The circuit of claim 1 , wherein the plurality of memory cells each comprises a resistive random access memory (RRAM) cell.3. The circuit of claim 1 , wherein the first memory cell presents a substantially lower resistance value when the first memory cell transitions from the first resistance state to the second resistance state.4. The circuit of claim 1 , wherein:the control logic circuit is further configured to use a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state;the counter circuit is further configured to again increment the count by one in response to the first memory cell's ...

NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING

A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block. 1. A method of operating a non-volatile memory device , the method comprising:upon initiating operation of the non-volatile memory device, reading control information from an information block in the non-volatile memory device, and reading lock information from an additional information block in the non-volatile memory device;determining whether a secure block of the non-volatile memory device will be locked in response to the lock information;upon determining that the secure block will be locked, generating a lock enable signal associated with the secure block that inhibits access to data stored in the secure block, and also activating a read-only enable signal associated with the additional information block that prevents change in the data stored in the additional information block.2. The method according to claim 1 , further comprising:upon determining that the secure block will not be locked, performing at least one of a read operation, a program operation, and an erase operation on the secure block.3. The method according to claim 1 , wherein the information block and the additional information block are separate and distinctly addressable regions within a memory cell array of the non-volatile memory device.4. The method of claim 1 , wherein the non-volatile memory comprises a row decoder that receives an address claim 1 , and the method further comprises:applying the lock enable signal to the row decoder to prevent selection of any word line in the secure block during any data access operation.5. The method of claim 4 , further ...

Semiconductor memory device including a control circuit and at least two memory cell arrays

A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.

Ephemeral Peripheral Device

An ephemeral peripheral system includes an ephemeral memory system and controller circuit for securing user data for a smartphone application. Different secure operating modes are provided for customizing user security requirements across end-to-end communications links, including in exchanges of electronic data between smartphone devices. 1. A portable peripheral computing device adapted to secure data for an application executing on a separate mobile device comprising:an interface on the portable peripheral computing device which is adapted to communicate data between the portable peripheral computing device and a high speed port on the separate mobile device;an ephemeral memory on the portable peripheral computing device which is adapted to store ephemeral data based on a security designation provided by the separate mobile device;an ephemeral memory controller circuit on the portable computing device adapted to write and read said ephemeral data to and from the ephemeral memory based on security parameters provided by the separate mobile device application;the ephemeral memory controller on the portable peripheral computing device being adapted to effectuate at least two (2) separate data erase modes, including:1) a first erase mode in which first ephemeral data in the ephemeral memory is deleted on a bulk basis based on a dedicated erase operation;2) a second erase mode in which second ephemeral data in the ephemeral memory is automatically deleted on a byte or bit basis as part of a read access operation made to such ephemeral data;wherein said second erase mode alters an original physical charge state of cells storing such second ephemeral data, and such that an original value of said second ephemeral data is unreadable.2. The device of wherein the separate mobile device is a smartphone.3. The device of wherein the device is adapted to support a mobile smartphone application implementing a secure communications channel in which no received data from a second ...

SEMICONDUCTOR MEMORY DEVICE FOR PSEUDO-RANDOM NUMBER GENERATION

According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value. 1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells;a random number generation circuit configured to generate a random number; anda controller configured to control the memory cell array and the random number generation circuit,wherein the random number generation circuit includes:a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter; anda pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.2. The device of claim 1 , wherein the random number control circuit includes:a control parameter generation circuit configured to generate the control parameter; andan accumulation circuit configured to generate the seed value by executing an accumulation process on read-out data of the memory cell, which is input.3. The device of claim 2 , wherein the control parameter generation circuit includes:an address setting circuit configured to receive a random number generation trigger signal from the controller, and to generate a control parameter of an address at a time of reading out data from the memory cell array, by using an output value of the pseudo-random number generation circuit; anda ...

Method and device for transfer of data to or from a memory

A method for reading or writing data at an address of a memory is disclosed. The data includes a number of consecutive words that each has a plurality of bits. The words are transferred to or from the memory in synchronization with a clock signal so that each word is transferred in one cycle of the clock signal. The bits are scrambled or unscrambled by applying a logic function to the bits of each word. The logic function is identical for the scrambling and the unscrambling and makes use of a bit-key that is dedicated to the word and is identical for the scrambling and the unscrambling. Each bit-key comes from a pseudo-random series generated based on the address.

TECHNIQUES FOR PREVENTING TAMPERING WITH PROM SETTINGS

Techniques for preventing tampering with programmable read-only memory of an integrated circuit are provided. A method according to these techniques includes performing a randomized read of data stored in the programmable read-only memory based on an input from an entropy source, writing the data to one or more registers of the integrated circuit, and initializing one or more components of the integrated circuit using the data stored in the one or more registers. 1. A method for preventing tampering with programmable read-only memory of an integrated circuit , the method comprising:performing a randomized read of data stored in the programmable read-only memory based on an input from an entropy source;writing the data to one or more registers of the integrated circuit; andinitializing one or more components of the integrated circuit using the data stored in the one or more registers.2. The method of claim 1 , further comprising:determining whether the data stored in the programmable read-only memory needs to be read in a particular order;performing a preliminary read of the data stored in the programmable read-only memory in the particular order prior to performing the randomized read of the data;comparing data read in the randomized read to the data read in the preliminary read; andaborting initialization of the integrated circuit responsive to the data read in the randomized read not matching the data read in the preliminary read.3. The method of claim 1 , further comprising:generating at least one pseudo-random value using the entropy source.4. The method of claim 3 , wherein the entropy source comprises a default value of uninitialized logic.5. The method of claim 4 , wherein the uninitialized logic comprises a plurality of non-resettable flip-flops.6. The method of claim 3 , wherein the entropy source further comprises a mechanism to compensate for process biasing.7. The method of claim 6 , wherein the mechanism comprises an LFSR-based power up detector ...

STORAGE DEVICE, OPERATION PROCESSING DEVICE, AND CONTROL METHOD OF STORAGE DEVICE

A storage device includes: a first disabling unit configured to output write enable signals without change when at least two write addresses of a plurality of write addresses for which write enable signals are enabled and held by a first holding unit do not match; a second holding unit configured to hold sets of the plurality of write addresses held by the first holding unit and the plurality of write enable signals output by the first disabling unit; a second disabling unit configured to output one write enable signal of the plurality of write enable signals held by the second holding unit without change in a test mode; and a third holding unit configured to write data in accordance with sets of the plurality of write addresses held by the second holding unit and the plurality of write addresses output by the second disabling unit. 1. A storage device comprising:a first holding unit configured to hold a plurality of sets of write addresses and write enable signals;a first disabling unit configured to output the write enable signals without change when at least two write addresses of a plurality of write addresses for which write enable signals are enabled and held by the first holding unit do not match;a second holding unit configured to hold sets of the plurality of write addresses held by the first holding unit and the plurality of write enable signals output by the first disabling unit;a second disabling unit configured to output one write enable signal of the plurality of write enable signals held by the second holding unit without change and disable other write enable signals of the plurality of write enable signals held by the second holding unit to output the disabled signals or configured to disable all the write enable signals to output the disabled signals in a test mode, the second disabling unit being configured to output the plurality of write enable signals held by the second holding unit without change in a normal mode; anda third holding unit ...

SEMICONDUCTOR DEVICE AND SECURITY SYSTEM

A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion. 1. A semiconductor device comprising:a unique-information generation portion operating in a plurality of operation environments to generate unique information, wherein the unique information comprises stable information and unstable information, the stable information is the constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments;a detection portion detecting the unstable information;a memory portion storing the unique information and identification information for identifying the unstable information; anda readout portion reading out the unique information and the identification information and outputting the unique information and the identification information to an external portion.2. The semiconductor device according to claim 1 , further comprising:an erasing portion deleting the unique information and the identification information which are stored in the memory portion.3. The semiconductor device according to claim 2 , wherein the erasing portion deletes the unique ...

APPARATUSES AND METHODS FOR CHIP IDENTIFICATION IN A MEMORY PACKAGE

Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes an identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information. 1. An apparatus comprising: first and second input terminals configured to receive first and second input signals, respectively; and', 'first and second output terminals configured to output first and second output signals, respectively, the first output signal being produced responsive to the first input signal and having a different logic level from the first input signal, the second output signal being produced responsive to the second input signal and having a same logic level as the second input signal,, 'a plurality of semiconductor chips, each of the plurality of semiconductor chips comprisingwherein the plurality of semiconductor chips are stacked with each other such that the first and second output terminals of a lower one of the plurality of semiconductor chips are coupled to the second and first input terminals of an upper one of the plurality of semiconductor chips, respectively, andwherein each semiconductor chip of the plurality of semiconductor chips is configured ...

PUF APPLICATIONS IN MEMORIES

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

SHUT-OFF MECHANISM IN AN INTEGRATED CIRCUIT DEVICE

Described herein are technologies related to self-disabling feature of a integrated circuit device to avoid unauthorized access to stored data information 1. An integrated circuit (IC) device comprising:a sensor configured to measure a signal;a control unit configured to process the measured signal and provide a triggering signal based upon the measured signal;a high-surge voltage component coupled to the control unit, the high-surge voltage component configured to provide a voltage based upon the triggering signal, wherein the provide voltage is greater than a voltage threshold of a storage component in the IC device, the voltage threshold includes a maximum voltage of operation of the storage component;2. The IC device as recited in claim 1 , wherein the sensor is a dosimeter that is configured to measure amount of radiation exposure of the IC device.3. The IC device as recited in claim 1 , wherein the sensor is an ohm meter that is configured to measure total resistance in a circuitry of the IC device.4. The IC device as recited in claim 1 , wherein the measured signal includes measured biometric identification signals.5. The IC device as recited in claim 1 , wherein the control unit is configured to generate one or more of a remote triggering signal claim 1 , a local software triggering signal claim 1 , or a local hardware triggering signal.6. The IC device as recited in claim 1 , wherein the high-surge voltage component includes one or more of a charged capacitor or a voltage supply that is configured to generate the supplied voltage that is above the threshold voltage of the storage component.7. The IC device as recited in claim 1 , wherein the high-surge voltage component includes a charged capacitor that is configured to generate the supplied voltage when a wireless device is powered OFF.8. A wireless device comprising: The IC device as recited in .9. The IC device as recited in further comprising a micro electro mechanical system (MEMS) coupled to the ...

RANDOM BIT CELL WITH MEMORY UNITS

A random bit cell incudes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line. 1. A random bit cell comprising:a volatile memory unit having a first data terminal and a second data terminal;a first non-volatile memory unit coupled to the first data terminal of the volatile memory unit;a second non-volatile memory unit coupled to the second data terminal of the volatile memory unit;a first select transistor having a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line; anda second select transistor having a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to the word line;wherein:during an enroll operation, a programming state of one of the first non-volatile memory unit and the second non-volatile memory unit is changed; andduring a load operation after the enroll operation, the volatile memory unit is configured to store a random bit according to programming states of the first non-volatile memory unit and the second non-volatile memory unit.2. The random bit cell of claim 1 , wherein: ...

Protection against side-channel attacks on non-volatile memory

A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.

SRAM BASED AUTHENTICATION CIRCUIT

A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature. 1. A memory device , comprising:a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state; 'a first sense amplifier, coupled to the plurality of memory cells, wherein while at least some of the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, located in first and second columns of the memory cell array, respectively, and based on the comparison, provide a first output signal for generating a first PUF signature; and', 'a physically unclonable function (PUF) generator, comprisinga pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on a data state of the plurality of memory cells before the first and second memory cells are accessed.2. The memory device of claim 1 , wherein the first and second memory cells are arranged in a same row of the memory cell array and arranged in a first column and a second column of the memory cell array claim 1 , respectively claim 1 , and wherein the first and second columns are next to each other without additional column ...

CODE GENERATING APPARATUS AND ONE TIME PROGRAMMING BLOCK

The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell. 1. A code generating apparatus , comprising:a plurality of first one time programming (OTP) memory cells, coupled to a first bit line;a reference signal provider, providing a reference signal; anda sense amplifier, coupled to the first bit line and the reference signal provider,wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code; andwherein a current value of the reference signal is set within a range, and the range is determined according to a relationship between a plurality of bit currents and a plurality of bit counts of the first OTP memory cells, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.2. The code generating apparatus as claimed in claim 1 , wherein each of the OTP memory cells provides the read current in sequence claim 1 , and the sense amplifier generates the output code with a plurality of bits by comparing the read current and the reference signal ...

CODE GENERATING APPARATUS AND ONE TIME PROGRAMMING BLOCK

The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell. 1. A code generating apparatus , comprising:a plurality of one time programming (OTP) memory cell strings, and each of the OTP memory cell strings comprising a plurality of OTP memory cells, wherein the OTP memory cell strings are respectively coupled to a plurality of bit lines;a switch, coupled to the bit lines; anda sense amplifier, coupled to the switch,wherein all of the plurality of OTP memory cells are programmed and the switch selects two of the bit lines to respectively couple to a first input end and a second input end of the sense amplifier, and the sense amplifier senses a difference of signals on the two selected bit lines to generate an output code; andwherein, the output code is determined by at least one manufacturing variation of the two selected OTP memory cells.2. The code generating apparatus as claimed in claim 1 , wherein two of the OTP memory cells in different OTP memory cell strings respectively provides two read currents to the selected bit lines claim 1 , and the sense amplifier generates the output code by comparing the read currents.3. The code generating apparatus as claimed in claim 1 , further comprising:an encoder, coupled ...

Memory disablement for data security

Apparatuses and methods related to memory disablement for memory security. Disabling the memory for memory security can include, responsive to receiving a trigger signal, provide a voltage, which may be in excess of an operating or nominal voltage, to the access circuitry. The voltage may thus be sufficient to render the access circuitry inoperable for accessing data stored in the memory array.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to the embodiment includes a memory cell array including memory cells; and a data write unit, the memory cells including a first selected memory cell defined for a memory cell targeted to data write, a second selected memory cell defined for a memory cell targeted to the data write next to the first selected memory cell, and non-selected memory cells defined for other memory cells, and the data write unit, at the time of write operation to the first selected memory cell, providing the second selected memory cell with a first non-selection electric pulse having electric energy within a range causing no change in the physical state of a memory element, and providing the non-selected memory cells with a second non-selection electric pulse having smaller electric energy than the first non-selection electric pulse.

POWER DELIVERY CIRCUITRY

A memory device may include one or more circuit boards. Additionally, memory circuitry and an energy storage device may be disposed on the one or more circuit boards. The energy storage device may supplant or supplement an external power source, for example, when power of the external power source is eliminated or insufficient. 1. A memory device comprising:one or more circuit boards;memory circuitry disposed on the one or more circuit boards; andan energy storage device disposed on the one or more circuit boards, wherein the energy storage device is configured to supplant or supplement an external power source configured to provide power to the memory circuitry.2. The memory device of claim 1 , comprising power delivery circuitry configured to regulate power from the external power source to the memory circuitry and to regulate power from the energy storage device to the memory circuitry.3. The memory device of claim 2 , wherein a first electrical connection of the energy storage device is configured to be switched between a reference voltage and an output voltage of the power delivery circuitry.4. The memory device of claim 2 , wherein the power delivery circuitry comprises a buck mode DC to DC converter.5. The memory device of claim 1 , wherein the energy storage device is configured to supplement the external power source in response to an increased power demand of the memory circuitry.6. The memory device of claim 5 , wherein the increased power demand is associated with an increased performance of the memory circuitry.7. The memory device of claim 6 , wherein the increased performance comprises a reduction in latency.8. The memory device of claim 5 , where in the energy storage device is configured to supplement at least 25 milliwatts (mW) of power.9. The memory device of claim 1 , comprising a serial advanced technology attachment (SATA) interface configured to transmit memory data between an external system and the memory circuitry.10. The memory device of ...

NONVOLATILE MEMORY DEVICES AND SOLID STATE DRIVES INCLUDING THE SAME

A nonvolatile memory device includes a memory cell array, a voltage generator, and a control circuit. The voltage generator generates word-line voltages to be applied to the memory cell array. The control circuit generates control signals that control the voltage generator in response to a command and an address. The control circuit includes a hacking detection circuit. The hacking detection circuit disables an operation of the nonvolatile memory device when a hacking is detected, wherein the hacking is detected when an access sequence of the command and the address does not match a standard sequence of the nonvolatile memory device a consecutive number of times. 1. A nonvolatile memory device , comprising:a memory cell array;a voltage generator configured to generate word-line voltages to be applied to the memory cell array; anda control circuit configured to generate control signals that control the voltage generator in response to a command and an address,wherein the control circuit includes a hacking detection circuit configured to disable an operation of the nonvolatile memory device when a hacking is detected, wherein the hacking is detected when an access sequence of the command and the address does not match a standard sequence of the nonvolatile memory device a consecutive number of times.2. The nonvolatile memory device of claim 1 , wherein the hacking detection circuit comprises:an access sequence analyzer configured to analyze the access sequence and to output a decision signal that is enabled when the access sequence does not match the standard sequence;a counter configured to count the decision signal that is enabled and to output a counting signal; anda hacking detection signal generator configured to receive the counting signal and to output a hacking detection signal that is enabled when the counting signal exceeds a reference value.3. The nonvolatile memory device of claim 2 , wherein the access sequence analyzer is configured to output the ...

Shift register capable of defending against dpa attack

The present invention discloses a shift register capable of defending against DPA attack, comprising 4 master-slave D flip-flops, 12 two-input NAND/AND gates, 4 three-input NOR/OR gates and 40 inverters; the 4 master-slave D flip-flops are provided with reset function; it is based on TSMC 65 mm CMOS technique; as indicated by Spectre simulation verification, the shift register of the present invention has correct logic function with NED and NSD below 2.66% and 0.63% respectively under multi PVT combinations, which is provided with significant performance in defense differential power consumption analysis.

MEMORY DEVICE AND A METHOD OF OPERATING THE SAME

A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain non-selected conductive lines at a first voltage level and boost a selected conductive line to a second voltage level in an access operation, the second voltage level being higher than the first voltage level. 1. A method of operating a semiconductor memory device , the method comprising:selecting a control line in an access operation, the control line coupled to a row of memory cells;selecting a conductive line associated with the selected control line, the conductive line coupled to the row of memory cells; andmaintaining non-selected conductive lines at a first voltage level and boosting the selected conductive line to a second voltage level during the access operation, the second voltage level being higher than the first voltage level.2. The method of further comprising asserting the selected control line at the first voltage level when boosting the selected conductive line to the second voltage level.3. The method of claim 2 , wherein the access operation includes a write operation claim 2 , further comprising:identifying whether a difference between a data line and a complementary data line reaches a threshold; andboosting the selected control line to the second voltage level when the difference reaches the threshold.4. The method of further comprising maintaining the selected control line at the first voltage level when the difference does not reach the threshold.5. The method of claim 3 , wherein the threshold is reached when the data line and the complementary data line have the same voltage level.6. A method of operating a semiconductor memory device claim 3 , the method comprising:selecting a control line in an access operation, the control line coupled ...

INTEGRATED CIRCUIT HAVING AN ELECTROSTATIC DISCHARGE PROTECTION FUNCTION AND AN ELECTRONIC SYSTEM INCLUDING THE SAME

An integrated circuit includes a data processing circuit, an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail and protects the data processing circuit from an ESD event on the voltage rail, and a switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal. 1. An integrated circuit , comprising:a data processing circuit;an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail, and protects the data processing circuit from an ESD event on the voltage rail; anda switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal.2. The integrated circuit of claim 1 , further comprising a controller which determines whether the data processing circuit performs a data processing operation claim 1 , and generates the control signal for controlling the connection between the voltage rail and the data processing circuit according to a result of the determination.3. The integrated circuit of claim 2 , wherein the controller generates the control signal for connecting the voltage rail and the data processing circuit when the data processing circuit performs the data processing operation claim 2 , and generates the control signal for blocking the connection between the voltage rail and the data processing circuit when the data processing circuit does not perform the data processing operation.4. The integrated circuit of claim 3 , wherein the data processing operation is a write operation or a read operation.5. The integrated circuit of claim 1 , wherein the switch circuit includes:a first switch which is connected between the voltage rail and the data processing circuit and includes a first control terminal; anda second switch which is connected between the first control terminal and the ground rail, includes a second control ...

Semiconductor integrated circuit

A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

READ CIRCUITRY FOR ELECTROSTATIC DISCHARGE SWITCHING MEMRISTIVE ELEMENT

In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor. 1. An apparatus comprising:a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin; andread circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor,wherein the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor,2. The apparatus of claim 1 , wherein the coupling between the read circuitry and the memristive element includes a direct path for current from the ESD event to a dopant diffusion region of the first transistor.3. The apparatus of claim 1 , wherein the read circuitry comprises:a current source to provide a reference current;a current mirror to replicate the reference current to be passed through the memristive element; anda voltage comparator to compare a voltage drop across the ...

SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE

Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command. 1. A method for controlling a memory device comprising:supplying a clock signal to a clock terminal of the memory device;supplying a chip select signal a chip select terminal to the memory device;supplying a first selected one of an address signal and a command signal to a first plurality of terminals of the memory device a first predetermined latency after supplying the chip select signal, wherein the first predetermined latency is an integer number of periods of the clock signal and the memory device retains the first selected one of an address signal and a command signal in a register; andreceiving the contents of the register from data terminals of the memory device.2. The method for controlling a memory device as claimed in claim 1 , further comprising supplying a second selected one of an address signal and a command signal to a second plurality of terminals of the memory device a first predetermined latency after supplying the chip select signal claim 1 , wherein the memory device retains the second selected one of an address signal and a command signal in the register.3. The method for controlling a memory ...

APPARATUSES AND METHODS FOR ADJUSTING WRITE PARAMETERS BASED ON A WRITE COUNT

According to one embodiment of the present invention, an apparatus disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters. 1. An apparatus comprising:a memory array having a plurality of memory cells;memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals;control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.2. The apparatus of claim 1 , further comprising:a parameter table defining a plurality of write cycle bins, wherein the control logic configured to compare the number of write operations performed by the memory access circuits to the plurality of write cycle bins to select the set of write parameters.3. The apparatus of claim 2 , wherein the parameter table is to ed in the memory array.4. The apparatus of claim 2 , wherein the parameter table includes a minimum number of write operations and a maximum number of write operations for each of the plurality of write cycle bins.5. The apparatus of claim 1 , wherein the plurality of memory cells includes one or more phase change memory cells.6 ...

UNCHANGEABLE PHYSICAL UNCLONABLE FUNCTION IN NON-VOLATILE MEMORY

A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set. 1. A circuit configured for maintaining PUF keys in unchangeable form when needed , comprising:a plurality of non-volatile memory cells, wherein the plurality of non-volatile memory cells includes an array of memory cells with peripheral circuits for access to the array;logic to use a physical unclonable function to produce a key, and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells; andlogic to disable changes to data in the set of non-volatile memory cells after the key is stored in the set, wherein the peripheral circuits have a first state in which access to the set of non-volatile memory cells to write the key is enabled, and a second state in which access to the set of non-volatile memory cells to write is disabled while access to other non-volatile memory cells in the array to write is enabled, and wherein the logic to disable changes to data in the set of non-volatile memory cells includes an indicator to set the first state or the second state.2. The circuit of claim 1 , wherein the physical unclonable function utilizes entropy generated using non-volatile memory cells in the plurality of non-volatile memory cells to produce the key.3. The circuit of claim 1 , wherein the logic to disable changes to data in the set of non-volatile memory cells further includes logic that disables use of the physical ...

WRITE ASSIST CIRCUIT FOR WRITE DISTURBED MEMORY CELL

A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed. 1. A circuit comprising:a first memory cell having a first port and a second port, the first port associated with a first write assist circuit, the second port associated with a second write assist circuit;a second memory cell having a third port and a fourth port, the third port associated with a third write assist circuit, the fourth port associated with a fourth write assist circuit; anda disturb control circuit configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.2. The circuit of claim 1 , whereinthe disturb control circuit is configured to generate a first write assist enable signal, a second write assist enable signal, a third write assist enable signal, and a fourth write assist enable signal corresponding to the first write assist circuit, the second write assist circuit, the third write assist circuit, and the fourth write assist circuit.3. The circuit of claim 2 , wherein the disturb control circuit is ...

KEY VALUE SSD

A storage device includes: a plurality of memory devices configured as a virtual device utilizing stateless data protection; and a virtual device layer configured to manage the virtual device to store objects by applying a first data protection to some of the objects and a second data protection to other ones of the objects depending on respective sizes of the objects. 1. A storage device comprising:a plurality of memory devices, each of the memory devices being configured as a virtual device and having a minimum size value allowable, which is the minimum object size that the memory device is configured to store; anda virtual device layer configured to manage the virtual device to store an object by applying one of a first data protection and a second data protection to the object, based, at least in part, on the size of the object, apply the first data protection to the object based on a space overhead of the first data protection for the object being less than a space overhead of the second data protection for the object;', 'apply the second data protection to the object based on the space overhead of the first data protection for the object being greater than the space overhead of the second data protection for the object., 'wherein the virtual device layer is configured to2. The storage device of claim 1 , wherein the virtual device layer is configured to: apply one of the first data protection or the second data protection to the object when the space overhead of the first data protection for the object is equivalent to the space overhead of the second data protection for the object.3. The storage device of claim 1 , wherein the memory devices are configured as one or more data devices and one or more parity devices.4. The storage device of claim 3 , wherein the parity devices are a fixed subset of the memory devices.5. The storage device of claim 3 , wherein the parity devices comprise a changing subset of the memory devices claim 3 , and wherein each of the ...

TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE

A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation. 1. A device comprising:a plurality of detection memory cells, each detection memory cell of the plurality of detection memory cells configured to be pre-programmed to a respective initial predetermined state, the initial predetermined state of each of the plurality of detection memory cells configured to be unmodifiable by subsequent commands directed to the memory device;a plurality of reference bits, each reference bit of the plurality of reference bits corresponding to a respective one of the plurality of detection memory cells, wherein the initial predetermined state of each detection memory cell is represented by a corresponding reference bit of the plurality of reference bits; andcomparator circuitry coupled to the plurality of detection memory cells and the plurality of reference bits, the comparator circuitry configured to compare a current state of each detection memory cell of the plurality of ...

TAMPER-RESISTANT NON-VOLATILE MEMORY DEVICE

A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges in a variable state in accordance with application of different electrical signals, a control circuit that, in operation, receives a control signal, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells in accordance with the control signal, and an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. 1. A non-volatile memory device comprising:a memory cell array including memory cells arranged in an array, each of the memory cells having a resistance value and having a property that the resistance value reversibly transitions among resistance value ranges in a non-volatile manner in a variable state in accordance with application of different electrical signals;a control circuit that, in operation, accepts an input of a control signal;a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells in accordance with the control signal input to the control circuit; andan arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, wherein, in operation,the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, thereby generating individual discrimination information.2. The non-volatile memory device according to claim 1 , whereinthe resistance value ranges include a first resistance value range and a second ...

METHOD OF CONTROLLING ON-DIE TERMINATION AND SYSTEM PERFORMING THE SAME

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation. 1. A method of operating a low power double data rate 5 (LPDDR5) dynamic random access memory (DRAM) in a multi-rank memory system including a plurality of memory ranks , the method comprising:receiving a CAS command and a write command, wherein the CAS command and the write command conform to an LPDDR5 standard, the write command is dedicated to a first memory rank among the plurality of memory ranks and the write command is not dedicated to a second memory rank among the plurality of memory ranks;enabling a reception buffer in the first memory rank;disabling a transmission driver in the first memory rank;disabling a reception buffer and a transmission driver in the second memory rank;receiving a data strobe signal pair;enabling on-die terminal (ODT) circuits of the first memory rank and the second memory rank in response to the write command;receiving write data signals while the data strobe signal pair is toggled during the enabling of the ODT circuits of the first memory rank and the second memory rank;receiving the CAS command and a read command, wherein the read command conforms to the LPDDR5 standard, the read command is dedicated to the first memory rank and the read command is not dedicated to the second memory rank;enabling the transmission driver in the first memory rank;disabling the reception buffer in the first memory rank;disabling the ...

Device, system and method for providing information security

A cryptography system comprising a first node having a unique identifier generator configured to generate at least one physical unclonable function (PUF); and a second node configured to remotely send an attestation request to the first node is disclosed. In some embodiments, the cryptography system may form at least part of a distributed ledger and the PUF is configured to respond to the attestation request.

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes a nonvolatile memory therein and an input terminal configured to receive a test control signal and an input signal of a writing/erasing voltage from an external device. The semiconductor apparatus includes: an output terminal; a positive pulse detection circuit configured to detect a positive test control signal, and output the positive test control signal to the output terminal; and a negative pulse detection circuit configured to detect a negative test control signal, and output the negative test control signal to the output terminal after inverting. 1. A semiconductor apparatus including a nonvolatile memory therein and an input terminal configured to receive a test control signal and an input signal of a writing/erasing voltage for the nonvolatile memory from an external device , the semiconductor apparatus comprising:an output terminal configured to output a signal to another circuit provided in the semiconductor apparatus;a positive pulse detection circuit configured to detect a positive test control signal received at the input terminal, and output the positive test control signal to the output terminal;a negative pulse detection circuit configured to detect a negative test control signal received at the input terminal, and output the negative test control signal to the output terminal after inverting; andan OR circuit configured to receive an output of the positive pulse detection circuit and an output of the negative pulse detection circuit and output a logical sum to the output terminal.2. The semiconductor apparatus according to claim 1 , further comprising:a low-pass filter configured to allow a low frequency component of an output signal of the OR circuit; anda buffer circuit configured to output an output signal of the low-pass filter after determining with a predetermined threshold.3. The semiconductor apparatus according to claim 1 , further comprising:a pull-down resistor provided between the input terminal and a ...

Migration of memory devices

A computing device that includes a plurality of memory devices and firmware to provide a migration data storage option that reserves a portion of a memory device to store, at least, encrypted metadata describing the physical layout information of the memory devices in preparation for migration of the memory devices.

Data Storage System and Method Based on Data Temperature

The subject technology performs the following in a storage system including memory dies, where each memory die includes its own temperature sensor. The subject technology determines a temperature of each of the memory dies based on a temperature reading from each memory die's temperature sensor. The subject technology determines whether data is hot data or cold data, where hot data is more likely to be changed after it is written than cold data. In response to determining that the data is hot data, the subject technology stores the data in a memory die with a relatively higher temperature than another one of the memory dies. Further, in response to determining that the data is cold data, the subject technology stores the data in a memory die with a relatively cooler temperature than another one of the memory dies. 1. A data storage system , comprising:a plurality of memory devices; and determining whether data is hot data or cold data; and', 'when the data is cold data, storing the data in a first one of the plurality of memory devices, wherein the first one of the plurality of memory devices is located farther away from the controller than a second one of the plurality of memory devices,', 'wherein cold data is less likely to be changed after it is written than hot data., 'a controller configured to cause2. The data storage system of claim 1 , wherein when the data is hot data claim 1 , the controller is configured to cause: storing the data in the second one of the plurality of memory devices claim 1 , wherein the second one of the plurality of memory devices is located closer to the controller than the first one of the plurality of memory devices.3. The data storage system of claim 1 , wherein each of the plurality of memory devices comprises a temperature sensor claim 1 , and wherein the controller is configured to cause: determining when to start data retention recycling on a memory-device-by-memory-device basis based on a temperature reading of each respective ...

PROTECTION CIRCUIT FOR MEMORY IN DISPLAY PANEL AND DISPLAY PANEL

The present application discloses a protection circuit for a memory in a display panel and a display panel. The circuit comprises a timing controller, a memory, a power circuit, and a switching circuit. By removing the write protection signal originally provided by the computer, the power circuit outputs a stable and reliable write protection signal to the memory to limit the memory data from being overwritten, and then the timing controller controls the switching circuit to be turned on for grounding the control terminal of the write protection signal of the memory only when receiving an instruction to write data to the memory. 1. A protection circuit for a memory in display panel , wherein the protection circuit for a memory in display panel comprises:a timing controller having a signal transmission end and a write control signal output end;a memory having a signal transmission end and a write protection signal control end, the signal transmission end of the memory being connected to the signal transmission end of the timing controller; the memory is configured to store software data of the timing controller;a power circuit, an output end of which being connected to the write protection signal control end, the power circuit being configured to output a write protection signal to the memory to limit data of the memory from being overwritten; anda switching circuit, an input end of which is interconnected with the output end of the power circuit and the write protection signal control end, an output end of the switching circuit being grounded, a controlled end of the switching circuit being connected to the write control signal output end;the timing controller is configured to control the switching circuit to be in a normally turn-off state, and control the switching circuit to be turned on when receiving a data write instruction to the memory.2. The protection circuit for a memory in display panel according to claim 1 , wherein the switching circuit includes a ...

PUF APPLICATIONS IN MEMORIES

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit. 1. A memory device , comprising:an array of memory cells;a physically unclonable function (PUF) circuit in the memory device to generate PUF codes;a deterministic random bit generator (DRBG) to generate a sequence of at least pseudo random numbers based upon personalization strings;a data path including a first path connecting a first circuit comprising one of (i) the PUF circuit and (ii) a first set of memory cells at a first location in the array of memory cells storing a PUF code, to the DRBG in the memory device and a second path connecting the DRBG to a second set of memory cells at a second location in the array of memory cells for storing keys; andsecurity logic circuitry to apply PUF code output, received from the first circuit via the first path to the DRBG, and to apply pseudorandom number sequences generated by the DRBG, to the second set of memory cells via the second path.2. The memory device of claim 1 , wherein the pseudorandom number sequences generated by the DRBG are used for initializing encryption operations on data to be provided.3. The memory device of claim 1 , wherein the applying of the pseudorandom number sequences generated by the DRBG to the second set of memory cells via the second path claim 1 , further includes:storing a sequence of numbers generated by the DRBG as a key in the second set of memory cells in the array of memory cells.4. The memory device of claim 1 , wherein PUF codes are applied by the security logic circuitry for initializing the DRBG.5. The memory device of claim 4 , wherein a ...

MULTIPLE LOCATION LOAD CONTROL SYSTEM

A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source. 120-. (canceled)21. A load control device for controlling power to an electrical load from an AC power source , the load control device comprising:a semiconductor switch configured to conduct a load current from the AC power source to the electrical load;a first terminal and a second terminal, the first and second terminals adapted to be coupled to a remote device;a first switching circuit coupled to the second terminal, the first switching circuit configured to conduct a charging current through the second terminal to power the remote device;a second switching circuit coupled between the first terminal and the second terminal; anda control circuit configured to control the semiconductor switch to control the power to the electrical load, the control circuit further configured to render the first switching circuit conductive to conduct the charging current to the remote device through the second terminal during a first time period of a present half-cycle of the AC power source, the control circuit further configured to subsequently render the first and second switching circuits conductive and non-conductive on a complementary basis to communicate with the remote ...

SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE

Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command. 1. (canceled)2. A semiconductor device comprising:a command decoder;a verification circuit configured to receive a command signal, an address signal and a parity signal, and output an error signal when detecting that at least one of the command signal and the address signal includes an error;a command address latency circuit configured to receive a chip select signal and output a first internal chip select signal;a first selector configured to receive the chip select signal and the first internal chip select signal and output a second internal chip select signal;a parity latency circuit configured to receive the second internal chip select signal, the command signal, and the address signal, and output a first internal command signal and a first internal address signal; anda second selector configured to receive the command signal, the address signal, the first internal command signal, and the first internal address signal, and output a second internal command signal and a second internal address signal to the command decoder.3. The semiconductor device as claimed in claim 2 , wherein the command address latency circuit ...

Memory Device with a Fuse Protection Circuit

A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Using dark bits to reduce physical unclonable function (puf) error rate without storing dark bits location

Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a transistor coupled to a first capacitor and a second capacitor in series, respectively. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells, and wherein the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first capacitor or second capacitor. 1. A semiconductor device , comprising:a gate dielectric layer;a first semiconductor film disposed on a first side of the gate dielectric layer;a first metal structure disposed on a second side of the gate dielectric layer opposite to the first side, wherein the first metal structure extends along a first lateral direction;a first conductive structure disposed on the second side over the first semiconductor film, wherein the first conductive structure extends along the first lateral direction to traverse across the first semiconductor film, and further extends along a vertical direction;a second conductive structure disposed on the second side over the first semiconductor film, wherein the second conductive structure extends along the vertical direction; anda third conductive structure disposed on the second side over the first semiconductor film, wherein the third conductive structure extends along the vertical direction.2. The semiconductor device of claim 1 , wherein the first conductive structure is in contact with a traversing claim 1 , middle portion of the first semiconductor film claim 1 , the second conductive structure is coupled to a first corner portion of the first semiconductor film with a first dielectric film interposed therebetween claim 1 , and the third conductive structure is coupled to a second corner portion of ...

MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME

Provided herein may be a memory system and a method of operating the same. A semiconductor memory device may include a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin and a control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device. 1. A semiconductor memory device comprising:a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin; anda control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device.2. The semiconductor memory device according to claim 1 , wherein the control logic comprises an internal state detection unit configured to provide the external device with a detection signal representing an unstable operation condition of the semiconductor memory device through the write protect pin.3. The semiconductor memory device according to wherein the internal state detection unit generates the detection signal when an external or internal voltage of the semiconductor memory device is a threshold voltage or less.4. The semiconductor memory device according to wherein the internal state detection unit generates the detection signal when an internal temperature of the semiconductor memory device is a preset low temperature or less or is a preset high temperature or greater.5. The semiconductor memory device according to claim 2 , further comprising an output buffer configured to provide the detection signal to the external device through the write protect pin.6. The semiconductor memory device according to claim 1 , wherein the write protect pin ...

Unchangeable physical unclonable function in non-volatile memory

A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

ELECTROSTATIC DISCHARGE PROTECTION STRUCTURES FOR EFUSES

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source. 1. A structure comprising an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse , the ESD protection structure being structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.2. The structure of claim 1 , wherein the ESD protection structure is a diode formed in parallel with the eFuse claim 1 , wherein both terminals of the eFuse and the diode are each shared terminals.3. The structure of claim 2 , wherein one of the terminals of the diode are directly coupled to the source.4. The structure of claim 2 , wherein the diode is forward biased during the ESD event and reverse biased during normal operation.5. The structure of claim 4 , wherein the diode is clamped during a negative pulse such that parasitic current from a FET network will not unintentionally program the eFuse.6. The structure of claim 1 , wherein the ESD protection structure is a diode formed in series with the eFuse.7. The structure of claim 6 , wherein the diode is reverse biased during the ESD event and forward biased during normal operations.8. The structure of claim 7 , wherein the diode prevents a voltage from forming across the eFuse above its threshold.9. The structure of claim 6 , wherein the diode is coupled in series to a bank of eFuses.10. The structure of claim 6 , wherein the diode is between the eFuse and a FET network.11. The structure of claim 1 , wherein the ESD protection structure is a FET in parallel with the eFuse.12. The structure of claim 1 , wherein the ESD protection structure is a FET in series with the eFuse claim 1 , where a ...

Puf with dissolvable conductive paths

The generation of “fingerprints”, also called challenge-response pairs (CRPs) of Physically Unclonable Functions (PUFs), can often stress electronic components, leaving behind traces that can be exploited by crypto-analysts. A non-intrusive method to generate CRPs based on Resistive RAMs may instead be used, which does not disturb the memory cells. The injection of small electric currents (magnitude of nanoAmperes) in each cell causes the resistance of each cell to drop abruptly by several orders of magnitudes through the formation of temporary conductive paths in each cell. A repeated injection of currents into the same cell, results in an almost identical effect in resistance drop for a single cell. However, due to the small physical variations which occur during manufacturing, the cells are significantly different from each other, in such a way that a group of cells can be used as a basis for PUF authentication.

Disabling a command associated with a memory device

In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

ACCIDENTAL FUSE PROGRAMMING PROTECTION CIRCUITS

Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a packaged radio frequency module includes a package substrate and a semiconductor die attached to the packaged substrate. The semiconductor die includes a power supply pad, a fuse, a fuse programming transistor having a source electrically connected to the power supply pad and a gate configured to receive a fuse programming signal, a cascode transistor electrically connected between a drain of the fuse programming transistor and the fuse, and a fuse protection capacitor electrically connected between the power supply pad and a gate of the cascode transistor and operable to inhibit unintended programming of the fuse. 1. A fuse system for a semiconductor die , the fuse system comprising:a power supply pad configured to receive a power supply voltage;a first fuse;a first fuse programming transistor having a source electrically connected to the power supply pad and a gate configured to receive a fuse programming signal;a first cascode transistor electrically connected between a drain of the first fuse programming transistor and the first fuse; anda first fuse protection capacitor electrically connected between the power supply pad and a gate of the first cascode transistor, the first fuse protection capacitor operable to inhibit unintended programming of the first fuse.2. The fuse system of further comprising a voltage regulator configured to bias the gate of the first cascode transistor with a regulated voltage.3. The fuse system of wherein the voltage regulator generates the regulated voltage based on the power supply voltage claim 2 , the first fuse protection capacitor operable to prevent accidental programming of the first fuse arising from a delay of the voltage regulator in providing voltage regulation.4. The fuse system of further comprising a programming logic circuit configured to generate the fuse programming signal based on a ...

REGISTER FILE DEVICE

A register file device includes: a multi-port latch; and a write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, wherein the write circuit includes: a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, and a changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal. 1. A register file device comprising:a multi-port latch; anda write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, whereinthe write circuit includes:a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, anda changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal.2. The register file device according to claim 1 , whereinthe detection circuit outputs an address match signal when detecting a simultaneous writing to at least two ports of a multi-port latch.3. The register file device according to claim 2 , whereinthe detection circuit outputs an alarm in response to the address match signal.4. A register file device comprising:a multi-port latch; anda write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write address, and write data,wherein the write circuit includes:a detection circuit that outputs an address match signal when a first write address of one ...

Techniques for secure writes by non-privileged users

Methods, systems, and devices associated with techniques for secure writes by non-privileged users are described. A memory device may be configured with one or more blocks of memory operating in a secure write mode. The memory device may receive an append command from a non-privileged user. The append command may indicate data to write to the block of memory at an address determined by the memory device. The memory device may identify a pointer to the address for storing the data within the block of memory. The memory device may write the data to a portion of the block of memory based on identifying the pointer and may update the pointer associated with the block of memory based on writing the data.

Physical Identifiers for Authenticating an Identity of a Semiconductor Component

This document describes techniques for authenticating an identity of a semiconductor component using a physical identifier. In some aspects, a physical identifier comprised of a region of features located indiscriminately within a surface of an encapsulated semiconductor component is fabricated. The physical identifier is then mapped. The map is then stored for use when authenticating the identity of the semiconductor component. 1. A method for enabling authentication of an identity of a semiconductor component , the method comprising:fabricating, as part of an encapsulation process defining a surface of the semiconductor component, a physical identifier, the physical identifier a region of features located indiscriminately within the surface;mapping the physical identifier, the map representing the region;reading, electrically from integrated circuitry of the semiconductor component, a binary identifier; andstoring the map and the binary identifier to enable authentication of the identity of the semiconductor component.2. The method of claim 1 , wherein fabricating the region having features located indiscriminately within the surface fabricates a microridge region claim 1 , the microridge region comprising a plurality of microridges located indiscriminately within the surface of the semiconductor component.3. The method of claim 2 , wherein mapping the physical identifier includes measuring the microridge region via a pressure-indicating sensor film claim 2 , a high-resolution camera claim 2 , or an interferometer.4. The method of claim 1 , wherein fabricating the region having features located indiscriminately with the surface fabricates a magnetic field region claim 1 , the magnetic field region comprising a plurality of magnetic nanoparticles located indiscriminately within the surface of the semiconductor component.5. The method of claim 4 , wherein mapping the physical identifier includes reading the magnetic field region via an induction mechanism claim 4 , ...

Depletion mode ferroelectric transistors

A depletion-mode FeFET (“FeDFET”) is programmable to a first programmed state, under a first set of voltage biasing conditions, and to a second programmed state, under a second set of voltage biasing conditions. In both the first and second programmed states, the storage transistor has a threshold voltage that is not greater than 0 volts. A memory circuit may be organized as memory cells, with each memory cell including select transistors, transistor switches and FeDFETs in a static random-access memory (SRAM) cell configuration.

Memory management system with backup system and method of operation thereof

An memory management system with backup system, and a method of operation of a memory management system with backup system thereof, including: a memory module controller for detecting a power failure condition, the memory module controller including a nonvolatile memory controller; a compression controller integrated within the nonvolatile memory controller for receiving a data block from volatile memory; a compression engine within the compression controller for compressing the data block to form a compressed data block; and a sequencer for writing the compressed data block to nonvolatile memory.

Non-volatile memory device

A non-volatile memory device comprises a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.

STROBE SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

A strobe signal generation circuit includes a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal; a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; and a second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal from among the at least one pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal. 1. A strobe signal generation circuit comprising:a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal;a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; anda second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal.2. The strobe signal generation circuit according to claim 1 , wherein the trigger circuit comprises:a serializer configured to generate a pre-pull-up signal and a pre-pull-down signal by serializing signals inputted through a first data input terminal and a second data input terminal, according to the clock signal;a first pre-driver configured to generate the pull-up signal by driving the pre-pull-up signal; anda second pre-driver configured to generate the pull-down signal by driving the pre-pull-down signal.3. The strobe signal generation circuit according to claim 2 , wherein the serializer is configured to receive a power supply voltage through the first data input terminal and receive a ground voltage through the second data input terminal.4. The strobe signal generation circuit according to claim 1 , ...

METHOD OF CONTROLLING ON-DIE TERMINATION AND SYSTEM PERFORMING THE SAME

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation. 1. A memory system operating in synchronization with an operation clock signal pair , the memory system comprising:a plurality of memory ranks, each memory rank including a plurality of memory devices, and each memory device including first and second mode registers for storing a target on-die termination (ODT) resistance value and a non-target on-die termination (ODT) resistance value respectively;a memory controller configured to set the first and second mode registers in each memory device and to perform a write operation on one of the plurality of memory ranks, the memory controller including a third mode register for storing a memory controller on-die termination (ODT) resistance value;a control bus shared by the plurality of memory ranks and coupled to the memory controller, and through the control bus, the memory controller transmitting a first CAS command and a write command to the plurality of memory ranks for a write operation;a data bus shared by the plurality of memory ranks and coupled to the memory controller, and through the data bus, the memory controller transmitting write data to the plurality of memory ranks;a plurality of rank selection signals, each of which connecting the memory controller to corresponding memory rank, wherein, when a first rank selection signal connected to a first memory rank among the plurality of memory ranks is ...

Data storage device and operating method thereof

A data storage device includes a nonvolatile memory device including dies including word line groups in which word lines are grouped; and a controller. The controller includes a word line health rating logic configured to determine a health rating of each word line and a health rating of each word line group based on state information on each of health rating factors associated with the word lines; a memory including a word line health rating table in which the health rating of each word line and the health rating of each word line group are stored; and a mapping logic configured to generate a management target logical super block by mapping one word line group having a lowest health rating and word line groups having a highest health rating, and generate a normal logical super block by mapping word line groups having intermediate health ratings.

APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY

The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line. 1. A method , comprising:protecting a number of data values stored in a respective number of memory cells coupled to a sense line of an array via a parity value corresponding to the number of data values that is determined without transferring data from the array via an input/output (I/O) line; andstoring the parity value in another memory cell coupled to the sense line.2. The method of claim 1 , wherein protecting the number of data values comprises performing claim 1 , using sensing circuitry claim 1 , exclusive OR (XOR) operations on the number of data values stored in the respective number of memory cells to determine the parity value.3. The method of claim 2 , wherein performing the XOR operations without transferring data from the array via an I/O line comprises performing the XOR operations without performing a sense line address access.4. The method of claim 2 , wherein performing XOR operations comprises performing a first XOR operation on a data value stored in a memory cell coupled to a first access line of the number of memory cells and a data value stored in a memory cell of the number of memory cells coupled to a second access line.5. The method of claim 4 , wherein performing XOR operations comprises performing a second XOR operation on a result of the first XOR operation and a data value stored in a memory cell coupled to a third access line of the number ...

Semiconductor Device

A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.

SYSTEM AND METHOD FOR MEMORY INTEGRATED CIRCUIT CHIP WRITE ABORT INDICATION

Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred. 1. A memory device controller comprising:memory integrated circuit chip inquiry circuitry configured to send an inquiry to a memory integrated circuit chip, the inquiry indicative of requesting the memory integrated circuit chip to send one or more flag values and the associated addresses, the one or more flag values indicative of execution of a command at the associated addresses by the memory integrated circuit chip; andabort identification circuitry configured to identify, based on the one or more flag values and the associated addresses, a section of memory within the memory integrated circuit chip containing valid data resulting from proper execution of the command or invalid data resulting from aborted execution of the command.2. The memory device controller of claim 1 , wherein the memory device controller is within a memory device;further comprising power down circuitry configured to determine whether an unexpected power down of the memory device occurred; andin response to determining that the unexpected power ...

CIRCUIT FOR DETECTION OF PREDOMINANT DATA IN A MEMORY CELL

A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold. 1. A memory device comprising a matrix of memory cells , the matrix being provided with at least one first column of cells wherein each of said cells comprises:at least one first storage node to store logical data, particularly “1” or “0”, the value of which corresponds to the value of at least one potential at said first storage node,at least one read port that, when activated, transmits the potential of the first storage node to a first bit line shared by the cells in the first column of cells,the device further being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold, said test circuit comprising:a first read node coupled to one end of the first bit line,a second read node coupled to one end of a second bit line, the second bit line forming a reference bit line associated with a plurality of second logical information storage nodes, said second storage nodes being configured to all store the same logical information or belonging to said cells in said first column respectively, and being storage nodes complementary to said first nodes,at least one stage forming a variable resistance to adjust said predetermined threshold, said stage being coupled to at least the first read node, said test circuit being configured to:concomitantly activate k read ports of a number k of cells in said first column while simultaneously activating k other read ports of a corresponding number k of second ...

Memory Device with a Fuse Protection Circuit

A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

MEMORY CARD

According to one embodiment, a memory card includes a housing and a switch. The housing includes a first surface and a second surface. The second surface is opposite to the first surface. The switch includes a first part, a second part, and a third part. The first part is disposed outside from the housing. The third part is disposed in the housing. The second part is connected to both the first part and the third part. The third part is in contact with both the first surface and the second surface. 1. A memory card comprising:a housing including a first surface and a second surface, the second surface being opposite to the first surface; anda switch including a first part, a second part, and a third part, the first part being disposed outside from the housing, the third part being disposed in the housing, the second part being connected to both the first part and the third part, the third part being in contact with both the first surface and the second surface.2. The memory card according to claim 1 , whereinthe third part includes symmetrical structure to a line passing through a center of the second part.3. The memory card according to claim 1 , whereinthe first surface includes a first side surface, and the second surface includes a second side surface.4. The memory card according to claim 3 , whereinthe third part includes a first portion being in contact with the first side surface and a second portion being in contact with the second side surface.5. The memory card according to claim 3 , whereinthe third part includes a convex portion on an opposite side of a side where the second part is connected.6. The memory card according to claim 3 , whereinthe third part includes asymmetrical structure to a line passing through a center of the second part.7. The memory card according to claim 6 , whereina thickness of the first side surface is thicker than that of the second side surface.8. The memory card according to claim 7 , whereinthe thickness of the first side ...

Tamper-proof storage using signatures based on threshold voltage distributions

An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level. 1. An apparatus , comprising:an interface, configured to communicate with a memory comprising multiple memory cells that store data as respective analog values, wherein the memory is addressable using physical addresses; and perform a first read operation from a physical address, and determine first analog values retrieved by the first read operation;', 'perform a second read operation from the physical address, and determine second analog values retrieved by the second read operation;', 'evaluate a variation between the first analog values and the second analog values; and', 'determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level., 'storage circuitry, which is configured to2. The apparatus according to claim 1 , wherein the storage circuitry is configured to generate a reference signature based on the first analog values claim 1 , to generate a test signature based on the second analog values claim 1 , and to evaluate the ...

Semiconductor memory device

A memory device includes first and second memory cell arrays, and a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array.