Integrated semiconductor-memory and method to reset the memory-cells of an integrated semiconductor-memory

An integrated semiconductor-memory with memory-cells (MC) in a memory-cells array (1) has a decoder (2) to select one of the memory-cells (MC) and a control-circuit (3), which is connected with the memory-cell-array (1) and the decoder (2). The memory-cells (MC) are combined to each unit (4), which through the control-circuit (3) and the decoder (2) a parallel reset of the memory-cells (MC) inside the units (4) is carried out with a pro-given data-signal (DA) and a sequential reset of each unit (4) is carried out with the pro-given data-signal (DA). The detectability of the current-profile generated in reset is thus restricted, thus the data-safety of the semiconductor-memory relative to the access is improved.