СПОСОБ И УСТРОЙСТВО ДЛЯ НЕЯВНОЙ ПРЕДВАРИТЕЛЬНОЙ ЗАРЯДКИ ДИНАМИЧЕСКОЙ ОПЕРАТИВНОЙ ПАМЯТИ (DRAM)

Изобретение относится к устройству и способу неявной предварительной зарядки динамической оперативной памяти. Техническим результатом является расширение функциональных возможностей. Устройство памяти содержит, по меньшей мере, один банк, состоящий из ячеек памяти, организованных во множество строк ячеек памяти; и логическое средство управления, соединенное, по меньшей мере, с одним банком, и реагирующее на прием устройством памяти команды активации одиночной строки для открывания конкретной строки таким образом, что, если нет открытых строк, когда принята команда активации строки, то конкретная строка, по меньшей мере, в одном банке открывается, а если в банке открыта другая строка, отличная от конкретной строки, когда принята команда активации строки, то другая строка закрывается и конкретная строка открывается. Устройство управления памятью содержит первое местоположение хранения, в котором сохраняются данные относительно строк в банке ячеек памяти в устройстве памяти и логическое средство ...

СПОСОБ СЕЛЕКТИВНОГО ПРОГРАММИРОВАНИЯ ЭНЕРГОНЕЗАВИСИМОГО НАКОПИТЕЛЯ

Изобретение относится к области программирования энергонезависимых накопителей. Техническим результатом является снижение потребления энергии. Способ состоит в том, что сначала прикладывают отрицательное программирующее напряжение ко всем шинам слов WLi, WLj, а затем ко всем неселектированным шинам слов WLj прикладывают положительное напряжение для компенсации на них отрицательных зарядов. 2 з.п.ф-лы, 2 ил.

ЭНЕРГОНЕЗАВИСИМОЕ УСТРОЙСТВО ПАМЯТИ, УСТРОЙСТВО ЗАПИСИ И СПОСОБ ЗАПИСИ

Энергонезависимое устройство памяти включает в себя таблицу управления логическими/физическими адресами для управления данными, записанными дискретно в энергонезависимом устройстве памяти, составленном из множества блоков, каждый из которых служит в качестве блока стирания данных и включает в себя соседние страницы, каждая из которых имеет фиксированную длину и служит в качестве блока считывания/записи данных. Технический результат - сокращение времени, необходимого для управления памятью. 3 н. и 13 з.п. ф-лы, 18 ил.

МОДУЛЬ ОПЕРАТИВНОЙ ПАМЯТИ

1. Модуль памяти, содержащий множество микросхем памяти, размещенных на одной поверхности печатной платы и соединенных с соединительными разъемами, расположенными на печатной плате, отличающийся тем, что множество микросхем памяти образуют каналы памяти, при этом центры микросхем памяти одного канала расположены на одной прямой линии, параллельной прямым линиям, на которых расположены центры микросхем памяти других каналов памяти, и параллельной двум внешним поверхностям каждого соединительного разъема, которые размещены на поверхности платы противоположной поверхности, на которой размещены микросхемы памяти. 2. Модуль памяти по п.1, отличающийся тем, что один канал памяти соединен с одним соединительным разъемом. 3. Модуль памяти по п.1, отличающийся тем, что длина соединительных элементов, соединяющих микросхемы памяти одного канала памяти с одним соединительным разъемом, одинакова. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 94 750 (13) U1 (51) МПК G11C 8/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ, ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21), (22) Заявка: 2010105702/22, 18.02.2010 (24) Дата начала отсчета срока действия патента: 18.02.2010 (45) Опубликовано: 27.05.2010 9 4 7 5 0 R U Формула полезной модели 1. Модуль памяти, содержащий множество микросхем памяти, размещенных на одной поверхности печатной платы и соединенных с соединительными разъемами, расположенными на печатной плате, отличающийся тем, что множество микросхем памяти образуют каналы памяти, при этом центры микросхем памяти одного канала расположены на одной прямой линии, параллельной прямым линиям, на которых расположены центры микросхем памяти других каналов памяти, и параллельной двум внешним поверхностям каждого соединительного разъема, которые размещены на поверхности платы противоположной поверхности, на которой размещены микросхемы памяти. 2. Модуль памяти по п.1, отличающийся тем, что один канал памяти соединен с одним соединительным разъемом. 3. ...

ЭЛЕМЕНТ ВХОДНОГО РЕГИСТРА

Изобретение относится к вычислительной технике и может быть использовано при построении быстродействующих адресных регистров запоминающих устройств и входных регистров микропроцессорных систем. Техническим результатом является повышение быстродействия. Схема элемента входного регистра содержит шину питания высокого уровня напряжения VDD, шину питания низкого уровня напряжения GND, шесть МОП-транзисторов Р-типа и шесть МОП-транзисторов N-типа, первый, второй и третий инверторы, управляющие входы СЕ и , вход данных D и выходы OUT и . 1 ил.

УСТРОЙСТВО СИНХРОНИЗАЦИИ

Устройство синхронизации, состоящее из триггера, отличающееся тем, что введены асинхронное оперативное запоминающее устройство, первый сумматор, второй сумматор, третий сумматор, четвертый сумматор, мультиплексор, счетчик переключения кода мультиплексора, счетчик количества импульсов синхронизации, первый счетчик формирования длительности паузы, второй счетчик формирования длительностей импульсов, SR-триггера, причем первый выход асинхронного ОЗУ, вход которого является первым входом устройства синхронизации, шиной соединен с первым входом счетчика количества импульсов синхронизации, выход которого подключен к первому входу первого счетчика формирования длительности паузы, выход первого счетчика формирования длительности паузы подключен к первому входу SR-триггера, выход которого является выходом устройства синхронизации, второй выход асинхронного ОЗУ шиной соединен с первым входом второго счетчика формирования длительности импульсов, первым входом первого сумматора, первым входом второго сумматора, первым входом третьего сумматора и первым входом четвертого сумматора, третий выход асинхронного ОЗУ подключен к второму входу первого сумматора, четвертый выход асинхронного ОЗУ соединен с вторым входом второго сумматора, пятый выход асинхронного ОЗУ соединен с вторым входом третьего сумматора, шестой выход ОЗУ соединен со вторым входом четвертого сумматора, выход первого сумматора подключен к первому входу мультиплексора, выход второго сумматора подключен к второму входу мультиплексора, выход третьего сумматора соединен с третьим входом мультиплексора, выход четвертого сумматора соединен с четвертым входом мультиплексора, выход мультиплексора подключен к второму входу первого счетчика формирования длительности паузы, причем объединенные 3-й вход первого счетчика формирования длительности паузы и второй вход второго счетчика формирования длительности импульсов является вторым входом устройства синхронизации, выход второго счетчика формирования длительности импульсов ...

СИНХРОНИЗАЦИЯ ВРЕМЕННЫХ ХАРАКТЕРИСТИК ДЛЯ НИСХОДЯЩЕЙ (DL) ПЕРЕДАЧИ В СКООРДИНИРОВАННЫХ МНОГОТОЧЕЧНЫХ (CoMP) СИСТЕМАХ

Изобретение относится к технике связи и может использоваться в системах беспроводной связи. Технический результат состоит в повышении надежности связи. Для этого раскрыта технология для регулирования временной характеристики приемника беспроводного устройства в скоординированной многоточечной (CoMP) системе. В соответствии с одним из способов обрабатывают в UE множество специфичных для узла опорных сигналов (RS), принимаемых от множества узлов в конфигурации CoMP, генерируют множество специфичных для узла временных характеристик RS, принимаемых антенными портами по меньшей мере для двух узлов, выполняют оценку средней временной задержки из множества временных характеристик принятых RS и регулируют временные характеристики приемника в составе UE по меньшей мере частично, на основе средней временной задержки. 3 н. и 21 з.п. ф-лы, 11 ил.

СХЕМА ДВОЙНОГО ПИТАНИЯ В СХЕМЕ ПАМЯТИ

... 1. Полупроводниковое устройство памяти с двойным напряжением, содержащее: ! множество формирователей записи, принимающих входные сигналы данных низкого напряжения и, в ответ, записывающих значения данных в сердечник памяти; ! схему отслеживания синхронизации, функционирующую для обеспечения задержки сигнала числовой шины высокого напряжения в соответствии со временем, связанным с множеством формирователей записи, записывающих данные в сердечник памяти; и ! множество ячеек памяти, реагирующих на сигнал числовой шины высокого напряжения и на формирователи записи, записывающие значения данных, для сохранения в них данных. ! 2. Полупроводниковое устройство памяти с двойным напряжением по п.1, дополнительно содержащее множество разрядных шин, подключенных к формирователям записи, чтобы принимать значения данных. ! 3. Полупроводниковое устройство памяти с двойным напряжением по п.1, дополнительно содержащее: ! множество схем сдвига уровня адресного сигнала, сконфигурированных с возможностью преобразования ...

ПОЛУПРОВОДНИКОВОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО (ВАРИАНТЫ)

Предлагаемое полупроводниковое запоминающее устройство, имеющее множество групп блоков памяти, буфер сигнала строба адреса строки, буфер сигнала адреса столбца и выполняющее операцию выборки данных в ответ на информацию о длине пакета и задержка, связанную с системными тактовыми импульсами заранее заданной частоты, содержит прибор для выборки сигнала, который автоматически предзаряжает одну группу блоков памяти из групп блоков памяти по сигналу строба адреса строки и сигналу с информацией о длине пакета и задержке после того, как выполнена операция адресации для группы блоков памяти.

УСТРОЙСТВО ПРЕДОТВРАЩЕНИЯ НЕСАНКЦИОНИРОВАННОГО ДОСТУПА ПРИ ЗАПУСКЕ, ЗАВЕРШЕНИИ СЕАНСА, ПЕРЕУСТАНОВКЕ ГЕОГРАФИЧЕСКИХ ИНФОРМАЦИОННЫХ СИСТЕМ

Устройство предотвращения несанкционированного доступа при запуске и завершении сеанса программы на постоянном запоминающем устройстве компьютера путем проверки некоторых регистров центрального вычислительного устройства правомерности выполняемых операций при инициализации в режиме отладки под управлением утилиты отладчика, отличающиеся тем, что для расширения функциональных возможностей устройства за счет предотвращения несанкционированного доступа при запуске и завершении сеанса, при переустановке географических информационных систем и цифровой топографической основы электронной базы данных выполняется разделение всех оперируемых данных на три класса необходимого, спонтанного и комбинированного необходимо-спонтанного типа данных, интеграция модуля матрицы контроля доступа и модуля утилиты безопасности.

СДВИГОВЫЙ РЕГИСТР

Сканнер шин выборки для жидкокристаллического дисплея включает в себя множество каскадированных ступеней, каждая из которых имеет входной и выходной выводы. Каждая ступень включает в себя синхронизированную выходную схему,содержащую последовательно соединенные повышающий и понижающий транзисторы. Дополнительный транзистор имеет проводящий путь, подключенный между управляющим электродом повышающего транзистора и точкой с потенциалом, достаточным для выключения повышающего транзистора. Управляющий электрод дополнительного транзистора подключен к выходу последующей из каскадированных ступеней или, альтернативно, к источнику синхросигналов с фазой, отличающейся от фазы синхросигналов, поданных на указанную выходную схему, для гарантирования того, что выход соответствующей ступени не сможет дрейфовать к включенному состоянию.

Устройство для выборки адресов

Устройство адресации буферной памяти

Изобретение относится к автоматике и может быть использовано для накопления информации в длительных гелиогеофизических и медико-биологических исследованиях и экспериментах . Целью изобретения является увеличение эффективной емкости адресуемой памяти за счет запоминания только результатов измерения и жесткой привязки к текущему времени. Устройство содержит счетчик секунд по основанию шестьдесят, счетчик минут по основанию шестьдесят,счетчик часов по основанию двадцать четыре , сумматор, счетный триггер, входы синхронизации и начальной установки , адресные выходы. Цель изобретения достигается нелинейным преобразованием кода времени в код адреса буферной памяти (БП), что позволяет осуществить жесткую привязку каждого результата измерения, записанного в БП, к текущему московскому (мировому) времени без фиксации в БП кодов временной привязки. 1 ил., 1 табл. (Л ...

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Изобретение относится к вычислительной технике, а именно к быстродействующим логическим схемам, может быть использовано в полупроводниковых запоминакнтих устройствах, в устройствах вычислительной техники и автоматики . Целью изобретения является снижение потребляемой мощности дешифратора . Цель достигается тем, что дешифратор содержит диоды 4 второй группы и диоды 5 смещения с соответствующими связями. При смене адреса входной ток дешифратора через диоды 4, 5 перезаряжает паразитную емкость выхода 8 дешифратора. В результате отпадает необходимость в специальных источниках тока. 1 ил.

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Изобретение относится к вычислительной технике и может быть использовано в микросхемах памяти с резервированием . Цель изобретения - расширение области применения за счет использования дешифраторов в схемах памяти с резервированием. Поставленная цель достигается за счет введения в каждый логический блок элемента памяти (ЭП). Использование дешифратора в ППЗУ позволяет осуществить постоянную блокировку части формирователей выборки, выходы которых связаны со строками или разрядами с дефектными ЭП. Информация будет считываться из резервных частей накопителя. 2 ил.

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Изобретение относится к вычислительной технике и может быть использовано для формирования токов выборки в трансформаторных дешифраторах с общей обмоткой. Целью изобретения является упрощение способа при формировании двухполярньпс токов выборки . Для этого после приложения импульсов тока к входным обмоткам всех трансформаторов, кроме выбранного, суммирования их с помощью общей обмотки на выходной обмотке выбранного трансформатора и формировании в подключенной к ней нагрузке тока выборки прикладывают к входной обмотке выбранного трансформатора импульс тока той же полярности для формирования в нагрузке тока выборки другой полярности. 1 ил. (Л е fco СП 4 Ю ...

Дешифратор на МДП-транзисторах

Изобретение относится к вычис- лител 1ной технике и может быть исnj « 2J пользовано в составе запоминающего устройства. Цель изобретения - снижение потребляемой мощности. Поставленная цель достигается тем, что в дешифратор дополнительно введены группы ключевых транзисторов 30, 31, адресные транзисторы 26-29, разрешающий транзистор 36, транзисторы обнуления 37 с соответствующими связями. При этом в два раза уменьшается количество ячеек дешифратора. Кроме того, транзистор 36 обеспечивает работу дешифратора в микрорежиме. В результате достигается снижение потребляемой мощности. 2 ил. а ЗГ (Л . t 2( со ю СП ел ел 00 иг-z) 3( )t4n}ln гл Фиг.} гпв ...

Устройство для выбора адреса внешней памяти

Устройство для распределения памяти

Изобретение относится к вычислительной технике и может быть использовано при пострюении многоразрядных оперативных запоминающих устройств (ОЗУ). Цель изобретения - повышение быстродействия. Устройство содержит счетчик -1, блок 3 управления , блоки 2 и 14 памяти адресов , коммутаторы 7... 10, рег истры 12 и 13. Устройство формирует в блоке 14 памяти группу адресов занятых и группу адресов свободных ячеек ОЗУ. При загрузке ОЗУ процессором устройство выбирает ОЗУ по адресу, первому из группы адресов свободных ячеек, и одновременно вьщает этот .адрес в ОЗУ. При очистке процессором определенной ячейки ОЗУ устрой ство производит считывание из ОЗУ по этому адресу, а сам адрес переносит в группу адресов свободных ячеек, увеличивая тем самым ее размер . Выигрьш в быстродействии при определении адреса свободной ячейки ОЗУ достигается исключением процесса поиска этого адреса и непосредственным его считыванием из справочного массива. 6 ил., 1 табл-. (Л ...

Адресный формирователь

Дешифратор адреса

ДЕШИФРАТОР АДРЕСА, содержащий ключевые МОП-транзисторы, истокн . которых объединены, затворы являются адресными входами первой группы дешифратора, усилительный МОП-транзистор, сток которого является входом питания дешифратора, а исток - выходом дешифратора, о т ли ч а ю щ и и с я тем, что, с целью повышения быстродействия, стоки ключевых МОП-транзисторов являются адресными входами второй группы дешифратора , а затвор усилительного МОП-транзистора соединен с истоками ключевых МОП-транзисторов..

Устройство для формирования адресных сигналов

Адресный блок запоминающего устройства

Элемент памяти для накопителя с произвольной выборкой

ЭЛЕМЕНТ ПАМЯТИ ДЛЯ НАКОПИТЕЛЯ С ПРОИЗВОЛЬНОЙ ВЫБОРКОЙ , содержащий шину выборки-записи строки, разрядную шину выборки-записи , шину считывания и первый резистор, первый вывод которого соединен с шиной питания, отличающийся тем, что, с целью повышения быстродействия и снижения потребляемой мош,ности, в него введены второй резистор и лавинный двухэмиттерный транзистор, коллектор которого соединен с вторым выводом первого резистора, первый эмиттер - с шиной выборки-записи строки, второй эмиттер - с шиной считывания, а база - с первым выводом второго резистора, второй вывод которого соединен с разрядной шиной выборки-записи . (Л о О5 j; со 00 fUZ. 1 ...

Адресный формирователь

Изобретение относится к вычислительной технике, а именно к блока адресации накопителей информации, и может быть применено в запоминающих устройствах с резервированием. Цель изобретения - снижение энергопотребления и повышение надежности формирователя. Формирователь содержит элементы И-НЕ 1 и 2, мажоритарный элемент 3, элементы НЕ 4. Поставленная цель достигается за счет использования мажоритарного элемента 3, обеспечивающего необходимую для программирования адресных дешифраторов разность напряжений. При этом отпадает необходимость в повышенном питании элементов адресного формирователя. 3 ил.

Устройство для выборки информации из блоков памяти на магнитных сердечников

Устройство для выборки информации из матричного накопителя

УСТРОЙСТВО ДЛЯ ВЫБОРКИ ИНФОРМАЦИИ ИЗ Г-1АТРИЧНОГО НАКОПИТЕЛЯ, содержащее первую группу ключевых транзисторов, истоки которых подключены к первой разрядной шине, вторую группу ключевых транзисторов , истоки которых подключены к второй разрядной шине, стоки ключевых транзисторов первой и второй групп являются входами устройства, и первый и второй транзисторы предзаряда , исток первого транзистора предзаряда соединен с первой разрядной шиной, исток второго транзистора предзаряда соединен с второй разрядной шиной, отличающееся тем, что, с целью упрощения устройства , затворы первого и второго транзисторов предзаряда подключены к первой управляющей шине, их стоки подключены к шине питания, а затворы ключевых транзисторов первой и второй групп соединены с второй управляющей шиной.«g ±1 (Л со а ...

Устройство для коммутации селектирующих проводов магнитного запоминающего устройства матричного типа

Устройство для управления выборкой разрядных шин

Постоянное запоминающее устройство

Адресный дешифратор

Устройство для выбора адресных слов

Doppelreihige Adressendekodierung- und Auswahlschaltung für eine elektrisch löschbare und programmierbare nichtflüchtige Speicheranordnung mit Redundanz, insbesondere für Flash-EEPROM Anordnungen

Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften

ANORDNUNG VERFLOCHTENER UND VERSCHLUNGENER WORTLEITUNGEN FUER HALBLEITERSPEICHER

Stossbetrieb-SRAM zur Benutzung mit Hochgeschwindigkeitstakt

Umwandlungsdetektorgerät zur Erzeugung eines Pulses mit variabler Zeitdauer

Halbleiterbauelement mit nichtflüchtigem Speicher

Integrierter CMOS-statischer RAM

SPEICHEREINHEIT.

Halbleiterspeicheranordung und Informationgerät

Impulssignalgenerator und Redundanzauswahlsignalgenerator.

Zwei Torspeicher mit Lese- und Schreiblese-Toren

Video-Doppelzugriffsspeichersystem mit einem halbsynchronen Dateneingang und Datenausgang.

Halbleiterspeicheranordnung

VERFAHREN UND VORRICHTUNG ZUM SPEICHERN UND DREHEN VON BITMUSTERN

Datenspeichervorrichtung mit mehreren Eingängen mit verbesserter Zellenstabilität

A multi-ported data storage device arranged to overcome the cell stability problems associated with prior art devices by unidirectionally isolating, by means 48, memory cells 10 of the multi-ported data storage device from read ports 26 of the multi-ported data storage device. The unidirectional isolation means 48 such as FET operates to prevent external signals from the read ports 26 and read port loading from influencing data stored in the memory cells, but continues to allow the memory cells to be read by the read ports associated therewith. The improved multi-ported data storage device not only allows simultaneous access to its memory cells by a large number of read ports without fear that cell stability will cause corruption of the memory cells, but also requires only a minimal amount of additional die area. Moreover, access time is independent of the number of ports being simultaneously accessed. To provide differential sensing additional circuitry (56, 58, Fig 6) may be provided ...

HALBLEITERSPEICHERGERAET.

HALBLEITERSPEICHERANORDNUNG MIT EINER RUECKSETZSIGNALGENERATORSCHALTUNG.

INTEGRIERTE SCHALTUNG MIT VERAENDERBAR AUFGELADENEM KNOTEN.

Bildaufnahmesystem

Halbleiterspeicheranordnung.

SPEICHERPATRONE

egrierten Halbleiterschaltkreis unter deren Anwendung und Signalübertragungssystem

Echotakt auf Speichersystem mit Warteinformationen

Ein Verfahren zum Betreiben einer Doppeldatenraten-Speichervorrichtung, mit folgenden Schritten: Bereitstellen einer bidirektionalen Leitung in einem Systembus der Speichervorrichtung, um ein WAIT_DQS-Signal zu übertragen, wobei das WAIT_DQS-Signal die Funktionalität von (i) einem WAIT-Signal, das in einem Lesezyklus anzeigt, wann gültige Daten auf einem Datenbus vorliegen, und in einem Schreibzyklus, wann ein Speicher bereit ist, um Daten anzunehmen, und (ii) einem Datenübernahme- (DQS-) Signal, das als ein Zeitgebungssignal für gültige Daten dient, aufweist; und Weiterleiten des WAIT_DQS-Signals in einer bidirektionalen Leitung in einem Systembus der Speichervorrichtung, wobei die bidirektionale Leitung mit dem Speicher und einer Systemsteuerung gekoppelt ist.

Adressierbare Speichereinheit mit Einheitsauswahlschaltung.

SPEICHER-CMOS-DEKODIER- UND ANTRIEBSSCHALTUNG.

Videospeicheranordnung.

Energieeinsparvorrichtung und -verfahren für Speichervorrichtung mit Delay-Locked Loop

Speichergerät mit:einer Delay-Locked-Loop (DLL) mit einer DLL-Verriegelungszeit;einer Speichervorrichtung (140) mit einer Anfangs-Datenzugriffslatenzzeit (370); undeiner Speichersteuerung (120), die eine Steuerungslatenzzeit aufweist und zum Empfang eines Speicherzugriffsbefehls konfiguriert ist, wobei die Speichersteuerung der DLL (180) einen DLL-Einschaltbefehl auf der Grundlage des Empfangs des Speicherzugriffsbefehls, der Steuerungslatenzzeit (330), der Anfangs-Datenzugriffslatenzzeit (370) und der DLL-Verriegelungszeit liefert,wobei die Summe der Steuerungslatenzzeit (330) und der Anfangs-Datenzugriffslatenzzeit (370) die DLL-Verriegelungszeit (392) überschreitet.

Multi-gate data storage arrangement for computer

The multi-gate data storage arrangement has a write-read-memory element and data registers and time multiplexers to coordinate data transfer between the gates and the memory element. The memory element is space multiplex and has m*n bit data in/outputs in the data transfer connection plane (DAE). The gates each have a word width of n-bits and are connected to the data registers (DER, DAR, SR) and the memory element so that the nth plane of the gates is connected via time multiplex element (AMUX1, AMUX2, EMUX, BSMUX) one above the other and with the respective n-plane of the memory element to the width of m words.

DATENSPEICHER UND VERFAHREN ZUM BEREITSTELLEN DESSELBEN

Ein Datenspeicher umfasst eine Speicherzellenanordnung mit einer Mehrzahl von flächig angeordneten Speicherzellen und eine mehrlagige Anordnung von Verbindungselementen, die eine Verbindung zwischen der Mehrzahl von Speicherzellen bereitstellt und die mit der Speicherzellenanordnung zumindest teilweise überlappt. Die mehrlagige Anordnung von Verbindungselementen ist ausgebildet, dass bei einer Entfernung einer ersten Lage von Verbindungselementen unter Verbleib einer zwischen der ersten Lage und der Speicherzellenanordnung angeordneten zweiten Lage von Verbindungselementen eine Unterbrechung zumindest einer Verbindung eintritt.

Verfahren und System zur Datenübertragung auf Basis eines flüchtigen und eines nicht-flüchtigen Speichers

BETRUGSSICHERE VERPACKUNG

Verhinderung der Veränderung von Daten, die in einer sicheren integrierten Speicherschaltung gespeichert sind.

Signalspielraumprüfsystem.

SPEICHEREINRICHTUNG UNTER VERWENDUNG VON ADRESSENMULTIPLEX.

Integrierte Schaltung umfassend Speichermodul mit einer Mehrzahl von Speicherbänken

Eine integrierte Schaltung umfassend ein Speichermodul mit einer geraden Anzahl von Speicherbänken, die mindestens vier ist. Jede Speicherbank weist eine Mehrzahl von Speicherzellen auf, wobei jeweils zwei Speicherbänke einen Speicherbankbereich bilden und wechselweise mit einem m-Bit-Datenbus verbunden sind. Die Speicherbänke sind in zwei Gruppen unterteilt, wobei jede Gruppe eine Speicherbank jedes Speicherbankbereichs umfasst. Das Speichermodul umfasst weiterhin eine Auswahleinheit, die mit den Speicherbänken verbunden ist und die auf Auswahlbits reagiert. Die Auswahleinheit wählt eine der zwei Speicherbankgruppen und eine Gruppe von i-Speicherzellen innerhalb der Speicherbank der ausgewählten Speicherbankgruppe aus, um über die zugehörigen m-Bit-Datenbusse der Speichergruppen, die die ausgewählten Speicherbänke umfassen, auf die ausgewählten i-Speicherzellen pro Takt zuzugreifen, wobei m gleich einem ganzzahligen Vielfachen von i ist.

Dynamischer Direktzugriffsspeicher mit Schattenschreibzugriffen

Verfahren und Vorrichtung zur Verringerung von Schreib-zu-Lese-Durchlaufzeiten unter Verwendung von Schatten-Schreibzugriffen in Memory Controllern und einem DRAM sind offengelegt. Ausführungsformen von Controllern, die Schatten-Schreib-Steuerlogik beinhalten, können in Antwort auf das Empfangen einer Schreibanfrage einen externen Schreib-Column-Address-Strobe (CAS) an den DRAM ausgeben, um eine gültige Schreib-CAS-Adresse zu latchen und anzunehmen, dass eine Menge von Schreib-Datenwerten in einer Menge von DRAM-Positionen, entsprechend der Schreib-CAS-Adresse, gespeichert wird. Nach dem Annehmen des Schreib-CAS und vor dem Annehmen der vollständigen Menge von Schreib-Datenwerten können solche Memory Controller in Antwort auf das Empfangen einer Leseanfrage einen externen Lese-CAS an den DRAM ausgeben, um eine gültige Lese-CAS-Adresse anzuzeigen. Eine Menge von Lese-Datenwerten von einer zweiten Menge von DRAM-Positionen entsprechend der Lese-CAS-Adresse wird mit verringerter Durchlaufzeit ...

Halbleiterspeichervorrichtung

Ein Mehrport-Speicher

Zeilendekodierer für Speicher

Electronic control arrangement, has control module with control units e.g. dynamic random access memories, having decoder units to decode bit string of signal, and connecting wire to connect each control unit with signal producing unit

The arrangement has an electronic control module (100) with electronic control units (101a-101n) e.g. dynamic random access memories. A selection signal producing unit (105) produces a selection signal (103). A connecting wire (106) connects each control unit with the unit (105). Each control unit has a decoder unit (107a-107n) to decode a preset bit string of the signal, where one control unit is selected by the string. An independent claim is also included for a method of activating and deactivating electronic control units that are arranged in an electronic control module.

INTEGRIERTE SCHALTUNG ZUR SPEICHERUNG UND WIEDERAUFFINDUNG VON MEHREREN DIGITALEN BITS PRO NICHTFLÜCHTIGER SPEICHERZELLE

Memory access control with generator of address, control etc. signals - has programming device of memory signal time mode, responding to given time control signals

The memory signal generator provides also address and control signals for the memory access as a reaction to a physical address. A device programs the time mode of the memory signals in response to preset time control signals, determining the time requirements of the memory. The programming device pref. includes a memory for the time control bit, and a selector responding to the time control bit for the selection of time control parameter from a number of such parameters. The programming device also contains a device, responding to the time control parameter and to a selection control signal. USE/ADVANTAGE - E.g. for DRAM. Sufficient flexibility to operate under different time control requirement.

Zugriffschaltung fuer Speicheranordnungen

Halbleiterspeicher mit Refresh- und Redundanzschaltungen

Verfahren für einen Zugriff auf eine Speichereinrichtung

Die Speichereinrichtung (SE) ist über einen ersten Anschluß (R/W1) mit einer ersten Zugriffseinrichtung (CPU1) und über einen zweiten Anschluß (R/W2) mit einer zweiten Zugriffseinrichtung (CPU2). Infolge eines Lese- bzw. Schreibzugriffs auf eine Speicherzelle (SZ1, ..., SZn) der Speichereinrichtung (SE) durch die erste und/oder die zweite Zugriffseinrichtung (CPU1, CPU2) wird eine, in der Speicherzelle (SZ1, ..., SZn) gespeicherte Information zeitlich nacheinander n-mal ausgelesen und anschließend verglichen, wobei die Information als korrekt ausgelesen bzw. eingeschrieben gilt, wenn die n ermittelten Informationen identisch sind.

STATISCHE HALBLEITERSPEICHERANLAGE.

TRUE/COMPLEMENT GENERATOR

HALBLEITER-SPEICHERVORRICHTUNG

INTEGRIERTE HALBLEITERSCHALTUNGSANORDNUNG.

Nichtflüchtiger ferroelektrischer Speicher

Nichtflüchtiger ferroelektrischer Speicher mit - einem Hauptzellenarray (71) mit: - einer Anzahl von Unterzellenarrays (71_1, 71_2, ...), - einer Anzahl globaler Hauptbitleitungen (BLG_n, BLG_n+1, ...) und mindestens einem Paar globaler Bezugsbitleitungen (BLRG_1, BLRG_2), die über die Unterzellenarrays (71_1, 71_2, ...) hinweg ausgebildet sind, - lokalen Hauptbitleitungen (BLLn_n, BLLn_n+1, ...) und lokalen Bezugsbitleitungen (BLLR_1, BLLR_2), die entsprechend den globalen Hauptbitleitungen (BLG_n, BLG_n+1, ...) und den globalen Bezugsbitleitungen (BLRG_1, BLRG_2) ausgebildet sind, und - Schaltern (SW11, SW12, SW21, SW22), die zwischen lokalen Bitleitungen (BLLn_n, BLLn_n+1, ...; BLLR_1, BLLR_2) und entsprechenden globalen Bitleitungen (BLG_n, BLG_n+1, ...; BLLR_1, BLLR_2) vorhanden sind, - einer über oder unter den Hauptzellenarray (71) ausgebildeten Bezugsbitleitungssteuerung (77) mit einem Bezugsleseverstärker (77a), der mit einer Bezugsbitleitung (BLRG_2) des Paars globaler Bezugsbitleitungen ...

Integrierter Speicher

Der integrierte Speicher weist einen ersten Adreßpfad auf, über den Adreßanschlüsse (ADR) mit ersten Auswahlleitungen (CSL) einer ersten Gruppe (G1) verbunden sind und der entsprechende erste Leitungen (L1) und eine erste Decoderschaltung (DEC1) aufweist. Außerdem weist er einen zweiten Adreßpfad auf, über den die Adreßanschlüsse (ADR) mit ersten Auswahlleitungen (CSL) einer zweiten Gruppe (G2) verbunden sind und der entsprechende zweite Leitungen (L2) und eine zweite Decoderschaltung (DEC2) aufweist. Die erste Decoderschaltung (DEC1) ist schneller als die zweite Decoderschaltung (DEC2). Die ersten Leitungen (L1) weisen eine größere Signallaufzeit auf als die zweiten Leitungen (L2).

HALBLEITERSPEICHERVORRICHTUNG

ADDRESSING DEVICE FOR THE DELIVERY OF ADDRESS CODES TO A MEMORY

Multiplexer für einen Speicher

Es wird ein Multiplexer vorgeschlagen, umfassend eine erste Kette, die den Zugang zu Sourceleitungen des Speichers steuert, wobei die erste Kette zwei Hochspannungstransistoren und mehrere Niederspannungstransistoren umfasst; und eine zweite Kette, die den Zugang zu den Bitleitungen des Speichers steuert, wobei die zweite Kette zwei Hochspannungstransistoren und mehrere Niederspannungstransistoren umfasst. Außerdem wird ein Verfahren zum Betreiben eines derartigen Multiplexers bereitgestellt.

ARCHITEKTUR FÜR DAS BLOCKWEISE AUFTEILEN EINES NICHTFLÜCHTIGEN SPEICHERS

Output enable signal generation circuit of semiconductor memory

An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).

УСТРОЙСТВО ДЛЯ ДОСТУПА К КОНФИДЕНЦИАЛЬНОЙ ИНФОРМАЦИИ

Устройство для доступа к конфиденциальной информации, содержащее разъем повышенной долговечности, микроконтроллер с модулем светодиодной индикации подключения к электронному порту и блок памяти, контакты разъема повышенной долговечности подключены через микроконтроллер к блоку памяти, отличающееся тем, что содержит модуль светодиодной индикации факта автоматического удаления использованного случайного шифрующего ключа, подключенного входами и выходами к микроконтроллеру, при этом гнездо разъема повышенной долговечности выполнено по индивидуальной схеме расположения выступов. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 98 076 (13) U1 (51) МПК G11C 8/20 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ, ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21), (22) Заявка: 2010110775/22, 22.03.2010 (24) Дата начала отсчета срока действия патента: 22.03.2010 (45) Опубликовано: 27.09.2010 (73) Патентообладатель(и): Серпуховской военный институт ракетных войск (СВИ РВ) (RU) U 1 9 8 0 7 6 R U Ñòðàíèöà: 1 ru CL U 1 Формула полезной модели Устройство для доступа к конфиденциальной информации, содержащее разъем повышенной долговечности, микроконтроллер с модулем светодиодной индикации подключения к электронному порту и блок памяти, контакты разъема повышенной долговечности подключены через микроконтроллер к блоку памяти, отличающееся тем, что содержит модуль светодиодной индикации факта автоматического удаления использованного случайного шифрующего ключа, подключенного входами и выходами к микроконтроллеру, при этом гнездо разъема повышенной долговечности выполнено по индивидуальной схеме расположения выступов. 9 8 0 7 6 (54) УСТРОЙСТВО ДЛЯ ДОСТУПА К КОНФИДЕНЦИАЛЬНОЙ ИНФОРМАЦИИ R U Адрес для переписки: 142202, Московская обл., г. Серпухов, ул. Бригадная, 17, СВИ РВ (72) Автор(ы): Закатин Михаил Сергеевич (RU), Смирнова Оксана Викторовна (RU), Ефремов Владислав Павлович (RU), Родин Сергей Сергеевич (RU), Шиманов Сергей Николаевич (RU) RU 5 10 15 20 25 30 35 ...

Декодер командно-программной и телеметрической информации бортовой аппаратуры командно-измерительной системы

Полезная модель относится к вычислительной технике и может найти применение в бортовой аппаратуре командно-измерительной системы для управления космическими аппаратами. Применение заявленной полезной модели расширит выполняемые функции бортовой аппаратуры командно-измерительной системы за счёт выполнения временных программ, поступающих в бортовую аппаратуру напрямую, минуя бортовой комплекс управления, разгрузив его ресурсы. Предложенная функция может быть использована в режиме программной перестройки рабочей частоты бортовой аппаратуры командно-измерительной системы. Декодер командно-программной и телеметрической информации содержит программируемую логическую интегральную схему с внутренним оперативным запоминающим устройством с коррекцией ошибок, коммутационно-распределительное устройство и дублированное программно-временное устройство и соединён с цифровым приёмником, цифровым формирователем ответного сигнала, бортовым синхронизирующим устройством, бортовым комплексом управления, бортовой аппаратурой телесигнализации. Принятая в формате командно-программной информации временная программа хранится во внутреннем оперативном запоминающем устройстве с коррекцией ошибок и выполняется при совпадении кода времени срабатывания разовой команды с кодом бортовой шкалы времени, принятым от бортового синхронизирующего устройства. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 181 964 U1 (51) МПК B64G 3/00 (2006.01) H04B 7/185 (2006.01) G11C 8/10 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК B64G 3/00 (2006.01); H04B 7/185 (2006.01); G11C 8/10 (2006.01) (21)(22) Заявка: 2017123593, 05.07.2017 (24) Дата начала отсчета срока действия патента: Дата регистрации: 30.07.2018 (45) Опубликовано: 30.07.2018 Бюл. № 22 U 1 1 8 1 9 6 4 R U (56) Список документов, цитированных в отчете о поиске: RU 168932 U1, 28.02.2017. RU 2493592 C1, 20.09.2013. RU 2611606 C1, 28.02.2017. US 6735501 B1, 11.05.2004. JP S6489723 A, 04.04.1989. (54) ...

Apparatus and method for determining dynamic voltage scaling mode, and apparatus and method for detecting pumping voltage using the same

A mode determination apparatus in a semiconductor apparatus includes a first condition detection block configured to generate a first condition signal in response to a clock enable signal activated when the semiconductor apparatus enters a dynamic voltage scaling mode, a second condition detection block configured to generate a second condition signal in response to an external high voltage in the dynamic voltage scaling mode, the external high voltage having a voltage level in the dynamic voltage scaling mode different from a voltage level in a normal mode, and a signal processing block configured to generate a dynamic voltage scaling mode signal in response to the first condition signal and the second condition signal.

Rfid access method using an indirect memory pointer

A method of operating a memory in an RFID application includes locating a memory pointer at a fixed read/writeable memory location in the memory, determining a range of a pedigree buffer, initializing the memory pointer to a lowest value in the range, providing a second memory location that serves as a trigger address for an indirect write, and writing to a next location in the pedigree buffer by directing write data to the trigger address, which is then automatically written at a location pointed to by the memory pointer.

Memory devices and methods having multiple address accesses in same cycle

A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.

Method for writing in a mram-based memory device with reduced power consumption

A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption.

Semiconductor memory device

A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.

Enhanced addressability for serial non-volatile memory

Example embodiments for providing enhanced addressability for a serial non-volatile memory device may comprise accessing a storage location based, at least in part, on an extended address value and an address, the extended address value to identify a subset of storage locations from a plurality of storage locations, the address to identify the storage location within the subset of storage locations.

Memory system with delay locked loop (dll) bypass control

A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

Method and apparatus for word line decoder layout

A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

Integrated circuits for providing clock periods and operating methods thereof

An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.

Semiconductor integrated device

To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved.

Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device

A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal.

Method and apparatus for word line driver with decreased gate resistance

A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.

Sub word line driver and apparatuses having the same

A sub word line driver is provided. The sub word line driver includes a first layer including a plurality of first pads disposed in a first line of a first direction, a plurality of second pads arranged in a second line of the first direction, and two first word lines arranged twisted twice in the first direction between the plurality of first pads and the plurality of second pads, each of the two first word lines being connected to a corresponding pad among the plurality of second pads; and a second layer, which is formed at a lower part of the first layer, and includes the second layer including a plurality of third pads, each the plurality of third pads each being embodied disposed at each corresponding a position corresponding to a pad from among one of the plurality of first pads and the plurality of second pads.

Nonvolatile semiconductor memory device and driving method thereof

A nonvolatile semiconductor memory device has a first select transistor having a gate electrode connected to a first select word line, a source connected to a first sub bit line, and a drain connected to a first main bit line, and a second select transistor having a gate electrode connected to a second select word line, a source connected to a second sub bit line, and a drain connected to a second main bit line. The first sub bit lines are controlled by the first select transistor so as to be electrically isolated from each other between memory cell groups each formed by the memory cells to be erased simultaneously. On the other hand, the second sub bit lines are connected in common to the memory cells of memory cell groups to be erased separately, by the second select transistor.

Non-volatile memory device

A non-volatile memory device includes a cell array configured to read or write data, a local column switch configured to selectively connect a bit line of the cell array to a global bit line in response to a column selection signal, a global column switch configured to selectively connect the global bit line to a sense-amp in response to an enable signal, and a switching unit configured to selectively connect or sever a current path of the global column switch in response to a control signal corresponding to a bank active operation.

Devices and system providing reduced quantity of interconnections

Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.

Semiconductor device

A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow in a direction corresponding to the logic of a data signal to all bit lines in a selected segment, and writes the data signal to a memory cell of the selected block. A segment decoder, when the address of one segment has been input from the outside, selects one segment corresponding to the address and couples the same to the selected first DL driver, and the segment decoder, when the addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to the first DL driver and the second DL driver, respectively.

Delay locked loop circuit of semiconductor memory apparatus

Various embodiments of a delay locked loop circuit of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the delay locked loop circuit may include an input correction unit configured to correct a duty ratio of an input clock based on a duty control signal and generate a reference clock; a delay line configured to delay the reference clock by a delay time and generate a delay locked clock; an output correction unit configured to correct a duty ratio of the delay locked clock based on the duty control signal and generate a corrected clock; and a control signal generation unit configured to generate the duty control signal when a correction activation signal is enabled.

Dual port static random access memory cell layout

A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.

Charge pump system for low-supply voltage

The present invention discloses a charge pump system for low-supply voltage including: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage)-clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.

Data paths using a first signal to capture data and a second signal to output data and methods for providing data

Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Semiconductor device having point-shift type FIFO circuit

For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Charge pump control scheme using frequency modulation for memory word line

A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage.

Allocation method and apparatus of moderate memory

An allocation method comprises: partitioning moderate memory into a plurality of physical memory pages having predetermined page size according to the predetermined page size; scanning the moderate memory using the predetermined page size and recording the physical address and damage degree of each physical memory page; obtaining the allocation information of the physical memory pages when a memory request is received and allocating physical memory to the request based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information. A moderate memory is scanned and the physical address and damage degree of each physical memory page are recorded, then the physical memory is allocated based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information.

Write circuitry for hierarchical memory architectures

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Continuous mesh three dimensional non-volatile storage with vertical select devices

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Programming reversible resistance switching elements

A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption.

Three dimensional non-volatile storage with multi block row selection

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Method and apparatus for phase selection acceleration

A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.

Memory device with robust write assist

A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.

NAND logic word line selection

A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Semiconductor device and method of generating voltages using the same

A semiconductor device includes a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address; a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where the received control bits are generated in response to the command signal and a control signal; and a voltage generation circuit for outputting voltages distributed in response to the enable signals.

Memory controller for strobe-based memory systems

A memory controller for strobe-based memory systems is disclosed. The memory controller comprises a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit comprises an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.

Column address counter circuit of semiconductor memory device

The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most significant counter unit configured to generate the most significant bit of the column address in response to a mask clock, where the mask clock is toggled when the internal clock is toggled by a set number of times.

Column address strobe write latency (cwl) calibration in a memory system

Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.

Semiconductor device including plural chips stacked to each other

Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection.

Semiconductor device

A semiconductor device according to the present invention includes plural controlled chips CC 0 to CC 7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A 13 to A 15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A 13 to A 15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A 13 to A 15 reach the controlled chips earlier than the command signal ICMD.

Circuits and methods for providing refresh addresses and alternate refresh addresses to be refreshed

Circuits and refresh address circuits for providing a refresh address, and methods for refreshing memory cells. An example method includes refreshing a first plurality of memory cells and interrupting the refreshing of the first plurality of memory cells. A second plurality of memory cells is refreshed, at least one of the second plurality of memory cells the same as one of the first plurality of memory cells. Refreshing of the first plurality of memory cells is resumed following the refreshing of the second plurality of memory cells. An example refresh address circuit includes a refresh address counter configured to provide addresses to be refreshed and a refresh address interrupt circuit configured to interrupt the provision of addresses. An alternate refresh address circuit is configured to provide an alternate address and the refresh address counter resumes providing the addresses responsive to completing the refreshing of the alternate address.

Method for Distributing Content to a User Station

A non-transitory computer-readable storage medium having stored thereon computer-executable instructions that, in response to being executed by a computing device, cause the computing device to perform operations including upon occurrence of a scheduled time, polling an update distribution server to determine that an update for a computer executable software application is available, the computer executable software application configured to operate on the computing device and in response to determining that the update is available, obtaining the update over the Internet from the update distribution server, and selecting whether to install the update at a first time or to defer installing the update until a second time that is later than the first time.

Semiconductor memory devices with a power supply

A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage. The driving signal generator generates a driving signal based on the virtual voltage, such that the driving signal has a voltage level that is reinforced as compared with a voltage level of the driving voltage. The load driver drives a load based on the driving voltage and the driving signal.

Non-volatile memory device and memory system including the same

A non-volatile memory device and a read method thereof are disclosed. The read method includes providing a memory block having memory cells connected to word lines and connected in serial to a bit line, sensing potential of the bit line by applying a first read voltage to a selected word line of the word lines and providing a first pass voltage to an unselected word line adjacent to the selected word line, sensing potential of the bit line by applying a second read voltage higher than the first read voltage to the selected word line and providing a second pass voltage lower than the first pass voltage to the unselected word line adjacent to the selected word line, and sensing potential of the bit line by applying a third read voltage higher than the second read voltage to the selected word line and providing a third pass voltage lower than the second pass voltage to the unselected word line adjacent to the selected word line.

System and method of decoding data from memory based on sensing information and decoded data of neighboring storage elements

Systems and methods to decode data stored in a data storage device are disclosed. Data bits stored in a first group of storage elements are decoded using data in a second group of storage elements together with physical characteristics of the second group of storage elements to aid in the decoding of the first group of storage elements.

Synchronous data processing system and method

A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

Semiconductor memory device and method of setting operation environment therein

A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.

Circuit providing load isolation and noise reduction

Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Mobile terminal, memory card socket and method of writing protection for memory card in the mobile terminal

The present invention provides a mobile terminal, a memory card socket and a method of writing protection for a memory card in the mobile terminal. The mobile terminal comprising a memory card socket accommodating a pluggable memory card, the memory card socket externally provided with a metal shielding structure; the mobile terminal further comprising: a touch capacitance sensor connected to the metal shielding structure of the memory card socket and configured to sense a capacitance via the metal shielding structure; and a write control unit configured to determine whether the metal shielding structure is touched by a finger based on the capacitance sensed by the touch capacitance sensor, and prohibit data being written into the memory card when it is determined that the metal shielding structure is touched by a finger. The present invention ensures that the data can be safely written into the memory card.

Delay circuit and latency control circuit of memory, and signal delay method thereof

A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.

Variable Resistance Switch Suitable for Supplying High Voltage to Drive Load

A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage from a charge pump to a selected word line. The circuit includes a charge pump that generates the high voltage and decoding circuitry that is connected to receive this high voltage and selectively apply it to a load. The decoding circuitry receives the high voltage through a switch, where the switch is of a variable resistance that progressively passes the high voltage in response to a control signal. In a particular example, the switch includes a transistor connected between the charge pump and the decoding circuitry, where the control gate of the transistor is connected to the output of a second charge pump that is connected to receive the high voltage and a settable clock signal as its inputs.

Internal wordline current leakage self-detection method, detection system and computer-readable storage medium for nor-type flash memory device

A wordline internal current leakage self-detection method, system and a computer-readable storage medium thereof employ the originally existed high voltage supply unit and the voltage detector connected to the wordline in the flash memory device, in which the high voltage supply unit applies the test signal to the selected wordline, and the voltage detector detects the voltage signal of the wordline. By comparing the test signal with the voltage signal, the wordline will be indicated as current leakage when the voltage signal is lower than the test signal.

Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate

A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

Integrated circuit memory device

A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2̂K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

Method for discharging a voltage from a capacitance in a memory device

In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by an architecture of the discharge circuit.

Chip select circuit and semiconductor apparatus including the same

A chip select circuit includes a chip select identification unit, a chip select control unit and a data input unit. The chip select identification unit generates a chip select identification signal in response to a chip select enable signal and an address signal. The chip select control unit provides the chip select identification signal as a chip select signal or provides a signal fixed to a predetermined level as the chip select signal, in response to a test mode signal. The data input unit receives data in response to the chip select signal.

Semiconductor memory device

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Memory system with data line switching scheme

A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.

Memory circuit and word line control circuit

The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system

A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.

System-in package including semiconductor memory device and method for determining input/output pins of system-in package

A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.

Line driver circuits, methods, and apparatuses

Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

Input buffer circuit, semiconductor memory device and memory system

An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.

Semiconductor apparatus

A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

Floating addressing of an eeprom memory page

A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row i is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

High voltage generation circuit and semiconductor device including the same

A high voltage generation circuit includes a plurality of pumps configured to generate a final pump voltage, a plurality of switches configured to couple the pumps to various nodes, a voltage division circuit configured to divide the final pump voltage from the pumps interconnected by the switches, and outputting a divided voltage, a section signal generation circuit configured to generate a plurality of section signals by comparing the divided voltage with each of different reference voltages, and a section signal combination circuit configured to generate enable signals for controlling the switches by combining the section signals.

Select devices for memory cell applications

Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.

IMAGE DECODING APPARATUS, IMAGE ENCODING APPARATUS, AND METHOD AND PROGRAM FOR IMAGE DECODING AND ENCODING

An encoded bit stream is processed by a lossless decoding unit (), an inverse quantization unit (), and an inverse orthogonal transform unit () in this order, to obtain orthogonally transformed coefficient data and encoding parameter information. The inverse orthogonal transform unit () performs an inverse orthogonal transform on the coefficient data by using bases that are set beforehand in accordance with the locations of transform blocks in a macroblock indicated by the encoding parameter information. In this manner, prediction error data is obtained. An intra prediction unit () generates predicted image data. An addition unit () adds the predicted image data to the prediction error data, to decode image data. By using bases that are set in accordance with the locations of transform blocks, an optimum inverse orthogonal transform can be performed, and encoding efficiency can be increased. 1. An image decoding apparatus that performs an orthogonal transform on prediction error data of each transform block , and decodes image data from an encoded bit stream generated by processing coefficient data subjected to the orthogonal transform , the prediction error data being a difference between the image data and predicted image data ,the image decoding apparatus comprising:a data processing unit configured to process the encoded bit stream to obtain the coefficient data subjected to the orthogonal transform and encoding parameter information;an inverse orthogonal transform unit configured to perform an inverse orthogonal transform on the coefficient data by using a base to obtain the prediction error data, the base being set beforehand in accordance with a location of the transform block in a macroblock indicated by the encoding parameter information;a predicted image data generation unit configured to generate the predicted image data; andan addition unit configured to add the predicted image data generated by the predicted image data generation unit to the prediction ...

Memory apparatus

A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal.

CONTROL OF INPUTS TO A MEMORY DEVICE

A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. 1. A semiconductor integrated circuit device comprising:a command decoder configured to control a memory system by decoding a memory system input signal;interface logic electrically coupled to the command decoder and configured to receive the memory system input signal and a control signal, the interface logic further configured to disable the memory system input signal based at least in part on the control signal;self-refresh logic configured to provide a self-refresh signal based at least in part on an external clock enable signal, the control signal based at least in part on the self-refresh signal; anda path-gate electrically coupled to the self-refresh logic and configured to receive the external clock enable signal and provide the external clock enable signal to the self-refresh logic, the path-gate receiving power from a main voltage generator and a secondary voltage generator in the event that the main voltage generator powers off.2. The semiconductor integrated circuit device of wherein the main voltage generator is configured to provide a generator state signal indicating a voltage level of the main voltage generator.3. The semiconductor integrated circuit device of wherein the control signal is based at least in part on the self refresh signal and the generator state signal.4. The semiconductor integrated circuit device of wherein the control signal causes the interface logic to disable the memory system input signal when the main voltage generator ...

FAST-WAKE MEMORY

One or more timing signals used to time data and command transmission over high-speed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different-frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links. 1. A method of operation within a memory controller , the method comprising:outputting a first memory access command via a first command signaling interface in response to a first clock signal during an exit from a first power mode; andoutputting a second memory access command via a second command signaling interface in response to a second clock signal during a second power mode.2. The method of wherein the memory controller consumes more power in the second power mode than in the first power mode.3. The method of wherein the first clock signal has a lower frequency ...

Voltage supply circuit, semiconductor memory device, and operating method thereof

A voltage supply circuit includes a high voltage generator configured to generate an operating voltage, a global word line switch configured to transfer the operating voltage to global word lines, a plurality of local line switches coupled to the global word lines and configured to transfer the operating voltage to corresponding local word lines, a precharge unit configured to supply a precharge voltage to an unselect local line switch adjacent to a select local line switch to which the operating voltage will be supplied, from among the plurality of local line switches, in a preparation section before an operation is started, and a coupling unit configured to couple the unselect local line switch and the global word line switch when the operation is started.

IMAGE SIGNAL ENCODING APPARATUS AND IMAGE SIGNAL ENCODING METHOD

An encoding method encodes a first image signal of a first view and a second image signal of a second view. The method includes encoding the first image signal to generate a base stream. The method also includes encoding the second image signal to generate a dependent stream, and inserting a dependent delimiter indicating a picture boundary between pictures in the dependent stream at the beginning of a picture in the dependent stream. 1. An encoding method for encoding a first image signal of a first view and a second image signal of a second view , the method comprising:encoding the first image signal to generate a base stream; andencoding the second image signal to generate a dependent stream, and inserting a dependent delimiter indicating a picture boundary between pictures in the dependent stream at the beginning of a picture in the dependent stream.2. An encoding apparatus for encoding a first image signal of a first view and a second image signal of a second view , the apparatus comprising:means for encoding the first image signal to generate a base stream; andmeans for encoding the second image signal to generate a dependent stream and for inserting a dependent delimiter indicating a picture boundary between pictures in the dependent stream at the beginning of a picture in the dependent stream.3. An encoding apparatus for encoding a first image signal of a first view and a second image signal of a second view , the apparatus comprising:a processing unit configured to encode the first image signal to generate a base stream, to encode the second image signal to generate a dependent stream, and to insert a dependent delimiter indicating a picture boundary between pictures in the dependent stream at the beginning of a picture in the dependent stream. This application is a continuation of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 12/993,400, filed Nov. 18, 2010, the entire content of which is incorporated herein by reference. U.S. ...

Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line

A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.

METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER

A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. 1. A memory controller to control a dynamic random access memory component (DRAM) , the memory controller comprising:first circuitry to receive a strobe signal from the DRAM, the first circuitry to adjust a phase of a first clock signal in accordance with phase information derived from the strobe signal and provide a phase-adjusted clock signal; andreceiver circuitry to sample data using the phase adjusted clock signal, the data being provided by the DRAM.2. The memory controller of wherein the phase adjusted clock signal is out of phase with the strobe signal.3. The memory controller of wherein the phase adjusted clock signal is 90 degrees out of phase with the strobe signal.4. The memory controller of wherein the first circuitry includes a delay-locked loop that receives the strobe signal and the first clock signal and outputs the phase adjusted clock signal.5. The memory controller of wherein the phase adjusted clock signal transitions at a midpoint of a data eye of the data.6. The memory controller of claim 1 , wherein the strobe signal transitions irregularly between relatively high and low levels.7. The memory controller of claim 6 , wherein the strobe signal is a pseudo-random signal.8. The memory controller of claim 6 , wherein the strobe signal is generally idle absent the data.9. A method for communicating data to a memory controller from a dynamic random access memory component (DRAM) claim 6 , the method comprising:receiving a strobe signal accompanying the data from the DRAM, the strobe signal ...

Method and Apparatus of Addressing A Memory Integrated Circuit

A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. 1. An integrated circuit , comprising:an input receiving a memory command for the memory array, the memory command including an encoded memory address; and 'an address decoder receiving the encoded memory address and generating a decoded memory address from the encoded memory address, wherein the decoded memory address is longer than the encoded memory address; and', 'control circuitry accessing the memory array on the integrated circuit, comprisingthe memory array.2. The circuit of claim 1 , wherein the memory command is sent from a location off of the integrated circuit.3. The circuit of claim 1 , wherein the encoded memory address is encoded at a location off of the integrated circuit.4. The circuit of claim 1 , wherein the memory command includes an operation code and the encoded memory address.5. The circuit of claim 1 , wherein the memory array is addressable by the decoded memory address and not addressable by the encoded memory address.6. The circuit of claim 1 , wherein the decoded memory address is associated with a communication duration of fewer address load cycles than the encoded memory address.7. The circuit of claim 1 , wherein the decoded memory address is associated with a serial communication duration of fewer address load cycles than the encoded memory address.8. A method claim 1 , comprising:receiving a memory command for a memory array in an integrated circuit, the memory command including an encoded ...

SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER TO CONTROL OUTPUT TIMING OF DATA AND DATA PROCESSING SYSTEM INCLUDING THE SAME

Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage. 1. A semiconductor device comprising:a command decoder generating a first internal command in response to a first internal clock signal; and a gate control signal generation unit generating a plurality of output gate signals in response to a second internal clock signal that is different from the first internal clock signal;', 'a plurality of delay circuits each receiving an associated one of the output gate signals and generating an associated one of a plurality of input gate signals, each of the delay circuits including a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage, the first power supply voltage being different from the second power supply voltage; and', 'a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command as a second internal command in response to one of the output gate signals., 'a latency counter that includes;'}2. The semiconductor device as claimed in claim 1 , wherein each of the first and ...

Method and apparatus for word line suppression

A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.

SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections. 115-. (canceled)16. A semiconductor device , comprising:a first logic section and a second logic section each including a plurality of storage sections, each storage section including (i) an address decoder which decodes a memory operation address inputted from a first address line or a logic operation address inputted from a second address line and outputs a word selection signal to a word line, and (ii) a plurality of storage elements being connected to the word line and a data line, which store data configuring a truth table defining a logic operation or connection relation, and are connected to the data line inputting and outputting the data by the word selection signal inputted from the word line; andan arithmetic processing section which includes (i) a first input/output section connecting the first address line of the storage sections included in the first logic section and the data line, (ii) a second input/output section connecting the second address line of ...

LOCAL WORD LINE DRIVER

A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver. 1. A memory circuit , comprising:a word line driver receiving a first voltage reference signal, a second voltage reference signal, and an input signal, the word line driver having an output coupled to a word line; andcontrol circuitry configured to deselect the word line by applying the input signal to the input of the word line driver, wherein during an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.2. The memory circuit of claim 1 , wherein claim 1 , during the program operation in which the word line is deselected and another word line is selected claim 1 , the control circuitry prevents discharge of the word line via only a p-type transistor of the word line driver.3. The memory circuit of claim 1 , wherein the input signal having one of at least a select value and a deselect value claim 1 , the select value and the deselect value having a same voltage polarity during an operation.4. The memory circuit of claim 1 , wherein the first voltage reference signal is received from a global word line claim 1 , the global word line selecting or deselecting a plurality ...

Selector circuit and processor system

A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.

STORAGE DEVICE, CONTROL METHOD OF STORAGE DEVICE, AND CONTROL METHOD OF STORAGE CONTROL DEVICE

Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B to B in a sector, in which a block address BA for selecting one of blocks B to B is held in block address buffer (BAB) . Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption. 124.-. (canceled)25. A control method of a storage device which comprises a memory cell array comprised of a plurality of sectors each of which is a memory cell region that is associated as a unit with an erase operation , the control method comprising:inputting a first address signal which selects a partial region when a readout operation and a write operation starts, the partial region being defined as one unit of access;holding the inputted first address signal during the readout operation and the write operation of the partial region, wherein the partial region comprises a plurality of data readout lines which are placed in the sector and partitioned; andretaining the plurality of the data readout lines in a selected state during the readout operation and/or the write operation depending on the held first address signal.26. The control method of the storage device of claim 25 , further comprising commonly selecting a memory cell selection line which intersects with the data readout lines in the sector regardless of the first address signal.27. The control method of the storage ...

Nonvolatile Memory And Writing Method Thereof, And Semiconductor Device

A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit. 1. A memory device comprising: a plurality of first memory cells; and', 'at least one second memory cell; and, 'a memory cell array comprisinga circuit for writing data to the plurality of first memory cells and the second memory cell,wherein, when the writing of the data to one of the plurality of first memory cells fails, the circuit is arranged to assign an address of the one of the plurality of first memory cells to the second memory cell and write the data to the second memory cell.2. The memory device according to claim 1 , further comprising an antenna which is capable of receiving an electric wave.3. The memory device according to claim 1 , wherein the plurality of first memory cells and the second memory cell are arranged to irreversibly change an electrical resistance thereof when the data is stored therein.4. The memory device according to claim 1 , further comprising a second circuit for confirming whether the data is normally stored in the plurality of first memory cells.5. The memory device according to claim 4 , further comprising a third circuit coupled with and arranged to ...

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

The present technology relates to an image processing device, an image processing method, and a program capable of reducing the amount of processing required for ROT and DCT or inverse DCT and inverse ROT. Image information obtained by decoding an encoded image is dequantized to obtain a low frequency component of the image information, which is obtained by a first orthogonal transform unit, and to obtain a frequency component higher than the low frequency component of the image information, which is obtained by a second orthogonal transform unit. The low frequency component and the high frequency component are subjected to an inverse orthogonal transform according to the same method. The present technology can be applied when encoding and decoding images, for example. 1. An image processing device comprising:a dequantization unit that dequantizes a quantized image to obtain a low frequency component having a predetermined size of the image, which is obtained by performing a second orthogonal transform after a first orthogonal transform, and to obtain a high frequency component, which is a component other than the low frequency component of the image and is obtained by the first orthogonal transform; andan inverse orthogonal transform unit that, when a size of the image is the predetermined size, performs a third inverse orthogonal transform, which is a combined transform of a first inverse orthogonal transform corresponding to the first orthogonal transform and a second inverse orthogonal transform corresponding to the second orthogonal transform, on the image which is the low frequency component, and that, when the size of the image is larger than the predetermined size, performs the second inverse orthogonal transform on the low frequency component and performs the first inverse orthogonal transform on the low frequency component having been subjected to the second inverse orthogonal transform and the high frequency component obtained by the dequantization unit.2 ...

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address, an address providing unit configured to provide a memory address to the path control unit in response to an active signal, and a plurality of memory banks each configured to receive the memory address provided through the corresponding address transmission path of the path control unit, wherein the bank address corresponds to a memory bank of the plurality of memory banks.

VIDEO CAMERA

Embodiments provide a video camera that can be configured to highly compress video data in a visually lossless manner. The camera can be configured to transform blue and red image data in a manner that enhances the compressibility of the data. The data can then be compressed and stored in this form. This allows a user to reconstruct the red and blue data to obtain the original raw data for a modified version of the original raw data that is visually lossless when demosacied. Additionally, the data can be processed in a manner in which the green image elements are demosaiced first and then the red and blue elements are reconstructed based on values of the demosaiced green image elements. 1. (canceled)2. A method of compressing mosaiced digital image data , comprising: first pixel data corresponding to first pixels of the plurality of sensor pixels and that represents light corresponding to a first color; and', 'second pixel data corresponding to second pixels of the plurality of sensor pixels and that represents light corresponding to a second color; and, 'with a plurality of digital image sensor pixels, generating mosaiced image data, the mosaiced image data comprising at leastfor each second pixel of a plurality of the second pixels, and based on values of the first pixel data corresponding to two or more of the first pixels, transforming the second pixel data corresponding to the second pixel, said two or more of the first pixels located on opposite sides of and in the vicinity of the second pixel;compressing the transformed second pixel data; andstoring the compressed, transformed second pixel data on a memory device.3. The method of claim 2 , wherein said transforming comprises:calculating an average of the values of the first pixel data corresponding to said two or more of the first pixels; andsubtracting the calculated average from a value of the second pixel data corresponding to the second pixel.4. The method of claim 2 , wherein said two or more of the ...

INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME

A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus. 1. An output method of a semiconductor apparatus , comprising the steps of:(a) generating a first data group based on data applied to a plurality of input lines;(b) generating a second data group to be the same as the first data group, based on the data applied to the plurality of input lines;(c) outputting at least a portion of the first data group at a first timing; and(d) outputting at least a portion of the second data group at a second timing after the first timing.2. The output method according to claim 1 , further comprising the step of:(e) repeating the steps (c) and (d) until the first data group and the second data group are all outputted,wherein the steps (a), (b), (c), (d) and (e) are repeated twice.3. The output method according to claim 1 , wherein the first timing is a rising edge of an input clock claim 1 , and the second timing is a falling edge of the input clock.4. The output method according to claim 1 , wherein the at least a portion of the second data group which is outputted in the step (d) is the same as the at least a portion of the first data group which is outputted in the step (c).5. The output method according to claim 1 ,wherein the first data group and the second data ...

SYSTEM WITH CONTROLLER AND MEMORY

According to the system of the present invention, data (DQ) signals are outputted/received between a controller and a memory based on a data strobe signal sent out from the controller . The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal. 1. A system comprising:a controller comprising first, second and third terminals provided independently of each other; anda memory comprising fourth, fifth, sixth, seventh and eighth terminals provided independently of each other and the fourth, fifth and sixth terminals being provided correspondingly to the first, second and third terminals of the controller;the controller being configured to output a write data signal to the third terminal while the controller is clocking the first terminal, and the memory being configured to receive the write data signal from the sixth terminal while the fourth terminal is being clocked in response to the clocking the first terminal;the memory being configured to output a read data signal to the sixth terminal while the memory is clocking the fifth terminal and the controller being configured to receive the read data signal from the third terminal while the second terminal is being clocked in response to the clocking the fifth terminal, the memory being configured to clock the fifth terminal while the fourth terminal is being clocked, the fourth terminal is being clocked while the controller is clocking the first terminal, the fourth and seventh terminals being clocked in a differential transmission system, and the fifth and eighth terminals being clocked in the differential transmission system.2. The system according to claim 1 , wherein the controller is configured to output the write data signal to the third ...

MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD

A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length. 1. A memory access control device comprising:a logical address receiving unit configured to receive a logical address specifying a range in a storage area of an external memory;a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length;a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address;a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length; andan output unit configured to generate a second bit sequence composed of bits that are equal in number to the bits stored in the range specified by the logical address, by using the one or more bit sequences extracted by the bit sequence ...

INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP

Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry. 1. An integrated circuit (IC) , comprising:first circuitry to generate a first clock signal by delaying an input clock signal by a first delay;second circuitry to determine a code based on the input clock signal and the first clock signal, wherein the code represents a second delay which, when applied to the first clock signal, produces a second clock signal that has a desired phase delay with respect to the input clock signal; andthird circuitry to produce an output clock signal based on the input clock signal and the code, wherein the third circuitry is capable of delaying the input clock signal by the second delay.2. The IC of claim 1 , wherein the first delay is substantially equal to a buffer delay of a clock buffer.3. The IC of claim 2 , wherein the IC further comprises fourth circuitry to provide the output clock signal as an input to the clock buffer.4. The IC of claim 2 , further comprising:a duty-cycle corrector (DCC) to adjust a duty cycle of the output clock signal; andfourth circuitry to provide an output signal of the DCC as an input to the clock buffer.5. The IC of claim 1 , wherein the desired phase delay is zero.6. The IC of claim 1 , wherein the second circuitry comprises:fourth circuitry to generate a set of ...

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

In the printer, the correction content setting portion sets equal to or more than one correction contents, the decimation rate setting portion sets decimation rates for respective planes of Y, Cb, and Cr of JPEG data (compressed data) based on the set correction contents. Pixels are decimated at the set decimation rates and the decompression processing unit decompresses the JPEG data so as to generate image data. In this manner, decimation processing is performed in accordance with the plurality of correction contents. Therefore, for example, inverse quantization processing, inverse DCT operation processing, and the like, can be omitted in accordance with the correction contents. The decompression processing may be executed on a sampling image to be used for sampling when the contents of correction to be performed on the image data are determined and on a print image to be used for printing. 1. An image processing device that decompresses compressed data which has a plurality of planes and has been compressed with a compression method with DCT operation so as to generate image data , the image processing device comprising:a correction content setting unit that sets equal to or more than one correction contents relating to the image data;a decimation rate setting unit that sets a decimation rate for each of the plurality of planes based on the set correction contents,and a decompression processing unit that decimates pixels at the decimation rate set for each of the plurality of planes and decompresses the compressed data so as to generate the image data.2. The image processing device according to claim 1 ,wherein the correction content setting unit sets the correction contents including equal to or more than one of face information, exposure degree, intensity, contrast, blurring degree and noise degree, andthe decimation rate setting unit sets the decimation rates for the planes in accordance with the correction contents including equal to or more than one of the ...

NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE

A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted. 1. A flash memory device comprising:a memory bank having a plurality of planes, including a first plane and a second plane, each of the plurality of planes having a page buffer for storing write data for programming to a corresponding plane and for storing read data from the corresponding plane; and,the first plane and the second plane both being configured to be selectively enabled at the same time when required based on configuration data and address data in relation to a memory operation within the flash memory device.2. The flash memory device of claim 1 , wherein each of the plurality of planes includes a dedicated row decoder for driving wordlines.3. The flash memory device of claim 1 , wherein the plurality of planes are organized as tiles claim 1 , where each of the tiles includes two planes coupled to a shared row decoder for driving wordlines in the two planes.4. The flash memory device of claim 3 , wherein the shared row decoder of each of the tiles selectively drives wordlines of at least one of the two planes in response to row decoder enabling signals.5. The flash memory device of claim 4 , wherein the shared row decoder includesa row driver for selectively passing row drive signals to the wordlines of the one of the two planes in response to a first output voltage, and to the wordlines of the ...

Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same

A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. 1. A method of controlling a memory system that includes a memory device and a memory controller , the method comprising:generating and transmitting a data set including a command and data to the memory device, using the memory controller;decoding the command from the data set, and storing the data in a storage region of the memory device based on the decoding result;generating a parameter control signal based on the data stored in the storage region; andchanging an AC timing characteristic of a parameter used to access a memory cell of the memory device according to the parameter control signal.2. The method of claim 1 , wherein the generating the parameter control signal includes:generating a plurality of DC voltages according to a first portion of the data stored in the storage region;generating a plurality of AC timing signals according to a second portion of the data stored in the storage region; andgenerating the parameter control signal by mixing one of the DC voltages and one of the AC timing signals in response to selection signals.3. The method of claim 1 , wherein the parameter is a program time claim 1 , an erase time claim 1 , a read time claim 1 , a program voltage claim 1 , an erase voltage claim 1 , a read voltage claim 1 , a reference cell voltage claim 1 , a program current claim 1 , an erase current claim 1 , a read current claim 1 , and/or a reference cell current claim 1 ,4. The method of claim 1 , wherein the AC timing characteristic is a parameter control signal time value.5. The method of claim 1 , wherein the command included in the data set instructs the memory ...

REDUCED LEAKAGE BANKED WORDLINE HEADER

A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication. 1. An electronic device , comprisinga memory bank comprising a plurality of wordlines adapted to activate memory cells; an input to activate the wordline driver,', 'the output to activate the respective one of the plurality of wordlines, and a power input that receives current to power the wordline driver;, 'a plurality of wordline drivers, each of the plurality of wordline drivers coupled via an output to a respective one of the plurality of wordlines and comprising'}a decoder adapted to decode a memory access request and to generate a memory address indication from a decoded memory access request, the decoder coupled to control delivery of power from an array supply to the power inputs of the plurality of wordline drivers based on a first part of the memory address indication and coupled to control selective activation of the plurality of word line drivers via the inputs thereof based on a second part of the memory address indication.2. The electronic device according to further comprising a header control device coupled to receive the first part of the memory address indication from the decoder and coupled to provide power to the power inputs of the plurality of wordline drivers in accordance with the first part of memory address indication.3. ...

TAMPER-RESISTANT MEMORY INTEGRATED CIRCUIT AND ENCRYPTION CIRCUIT USING SAME

The present invention provides an integrated memory circuit applicable to an S-box of a cryptographic circuit, the integrated memory circuit having a row decoder, a column decoder, and a sense amplifier composed of a domino-RSL circuit, wherein data reading and data writing from/to memory cells of a memory cell array are performed via two complementary bit lines, and the transition probability of a signal line is equalized by input of random-number data supplied from a random-number generating circuit using an arbiter circuit. 1. An integrated memory circuit comprising a memory cell array , a row decoder , a column decoder , a sense amplifier , and an input/output driver , wherein data reading and data writing from/to memory cells of the memory cell array is performed via two complementary bit lines , and each of the row decoder , the column decoder , and the sense amplifier comprises a circuit in which transition probabilities of signal lines are equalized by random-number data that is externally supplied.2. The integrated memory circuit according to claim 1 , wherein each of the row decoder claim 1 , the column decoder claim 1 , and the sense amplifier comprises a domino-RSL circuit.3. The integrated memory circuit according to claim 2 , wherein:the row decoder comprises a first predecoder and a word line driver for driving word lines of the memory cells;the first predecoder comprises a plurality of first inverters for inverting a part of multiple-bit data that constitutes address data, and a plurality of first domino-RSL gates;the first domino-RSL gates comprise first to eighth transistors and a second inverter;the first and fifth transistors are PMOS transistors;the second to fourth and sixth to eighth transistors are NMOS transistors;the first to fourth transistors are sequentially connected in series by connecting their sources or drains;a power-supply voltage is applied to a source of the first transistor disposed at one end of the first to fourth transistors ...

SEMICONDUCTOR DEVICE HAVING PLURAL SELECTION LINES

The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group. 1. A semiconductor device comprising:a plurality of circuit sets each including a plurality of drive circuits;a plurality of selection circuits each assigned to an associated one of the circuit sets such that each of the selection circuits are coupled in common to the driver circuits included in the associated one of the circuit sets; anda plurality of selection lines, whereinone of the selection circuits selected by a first signal supplies an active potential to a first output node thereof, andeach of the drive circuits includes a first transistor coupled between an associated one of the selection lines and the first output node of the associated one of the selection circuits, the first transistor having a control electrode supplied with a second signal that id different from the first signal.2. The semiconductor device as claimed in claim 1 , whereinthe first signal includes a plurality of address bits each taking one of first and second potentials,the other of the selection circuits that are not selected by the first signal supplies an inactive potential to the first output node thereof, anda first voltage between the first and second potentials is different from a second voltage between the active potential and the inactive potential.3. The semiconductor device as ...

Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device

A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals edge specifying information that takes a selected one of first and second states, the edge specifying information being supplied to the device to cause the device to activate a data strobe signal at a first timing when the selected one of the edge specifying information is the first state and at a second timing, that is different from the first timing, when the edge specifying information is the second state, the control circuit being further configured to generate and output onto the set of first terminals a read command, the read command being supplied to the device to cause the device to return to the controller a data signal.