Dual-edge trigger clock gater

Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating. In some embodiments, the clock gater circuitry includes a buffering element configured, when gating, to copy data stored in one of the first and second storage elements to the other of the first and second storage elements.

Management of core power state transition in a microprocessor

A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory. The memory stores program code, which, when executed on the processor, performs an operation for adjusting a frequency of a processor. The operation includes inhibiting one or more processor cores from exiting an idle state. The operation further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The operation also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The operation includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Flip flop using dual inverter feedback

Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages.

Managing interconnect electromigration effects

A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.

Accelerating microprocessor core wake up via charge from capacitance tank without introducing noise on power grid of running microprocessor cores

A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source.

Generating an overdrive voltage for power switch circuitry

Techniques are disclosed relating to generating an overdrive voltage for power switch circuitry. In some embodiments, the value of the overdrive voltage is adjusted dynamically in order to reduce leakage current during power gating. In some embodiments, an apparatus includes a power switch circuit element configured to gate power to circuitry in the apparatus based on a control signal. In some embodiments, the power switch circuit element is powered by a supply voltage. In some embodiments, the apparatus also includes control circuitry configured to generate the control voltage at a different voltage level than the supply voltage, based on comparison of leakage current of ones of a plurality of replicas of the power switch circuit element. In some embodiments, the replicas are configured to receive different reference voltages as respective replica control signals. In various embodiments, the disclosed techniques may generate overdrive voltages that reduce leakage current during power gating.

Management of core power state transition in a microprocessor

A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Deterministic current based frequency optimization of processor chip

A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Predictively turning off a charge pump supplying voltage for overdriving gates of the power switch header in a microprocessor with power gating

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit.

Contributor-based power modeling of microprocessor components

A method for generating a power model for a device includes identifying a device-level set of power contributors for a given state of the device, wherein each power contributor in the device-level set of power contributors contributes to power dissipation when the device is in the given state, and generating the power model for the device based on the device-level set of power contributors, wherein the power model is independent of process, voltage, and temperature.

Modulation of Power Supply Voltage for Varying Propagation Delay

Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle. 1. An apparatus comprising:a first signal path coupled between a first timing element circuit and a second timing element circuit, the first signal path comprising at least one logic circuit connected to a first supply voltage at a first supply voltage rail and a second supply voltage at a second supply voltage rail;a second signal path coupled between the first timing element circuit and a third timing element circuit, the second signal path comprising at least one logic circuit connected to the first supply voltage and the second supply voltage, and the second signal path having a propagation delay longer than a propagation delay of the first signal path; and control a voltage difference between the first supply voltage and the second supply voltage to a first voltage range during a first time period in a cycle of a clock signal, and', 'control the voltage difference between the first supply voltage and the second supply voltage to a second voltage range during a second time period in the cycle of the clock signal, the second voltage range higher than the first voltage range., 'a control circuit coupled to the first supply voltage rail to ...

FLIP FLOP USING DUAL INVERTER FEEDBACK

Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages. 1. A flip-flop comprising:a first match multiplexer having a feedback output terminal and a data input terminal configured to receive an input data signal, the first match multiplexer configured to control, based on logic levels at a pair of nodes, a logic level at the feedback output terminal to correspond to a version of the input data signal or a logic level associated with one of the pair of nodes;a separable inverter comprising a clock input terminal and a feedback input terminal coupled to the feedback output terminal, the separable inverter configured to change a logic level at one of the pair of nodes based on the logic level at the feedback output terminal but maintain a logic level at the other of the pair of nodes responsive to a change of a logic level at the clock input terminal; anda second match multiplexer configured to, based on the logic levels at the pair of nodes, maintain a logic level at a signal output terminal of the second match multiplexer or control a logic level at the signal output terminal to correspond to the logic level associated with one of the pair of nodes.2. The flip-flop of claim 1 , wherein:the version of the input data signal at the ...

Dynamic Workload Frequency Optimization

The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions. 1. A microprocessor comprising:an architecture configured to create a time domain partition, the architecture comprising at least first and second circuitry each in communication with a clock, wherein the first circuitry is configured to operate at a first frequency, the second circuitry is configured to operate at a second frequency different from the first frequency, and wherein the first frequency is a default operating frequency;an instruction processing unit in communication with the architecture the instruction processing unit to receive an instruction, and dynamically detect a frequency change condition associated with the instruction;a frequency modulation unit in communication with the instruction processing unit, the frequency modulation unit to perform a frequency modulation in response to the dynamic detection, including the frequency modulation unit to select the second frequency for optimal instruction processing; andan instruction execution unit in communication with the instruction processing unit, the instruction execution unit to complete execution of the instruction at the second frequency.2. The microprocessor of claim 1 , further comprising the instruction processing unit to activate a ...

Measuring Data Switching Activity in a Microprocessor

A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.

CONTROL SIGNAL MEMOIZATION IN A MULTIPLE INSTRUCTION ISSUE MICROPROCESSOR

A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit. 120-. (canceled)21. A microprocessor for multiple instruction issue in the microprocessor , the microprocessor comprising:an instruction buffer;instruction decode and issue logic;a dependency cache; anda plurality of functional units, identifies an instruction group to be issued to the plurality of functional units in the microprocessor;', 'determines whether a dependency cache entry exists for the instruction group in the dependency cache, wherein the dependency cache entry includes control signals for executing the instruction group in a pipe of the microprocessor;', 'uses the control signals in the dependency cache entry to control execution of the instruction group in the microprocessor in response to a dependency cache entry existing for the instruction group in the dependency cache; and', 'computes control signals for the instruction group to form computed control signals and stores the computed control signals in the dependency cache in association with the instruction group in response ...

REDUCED LEAKAGE BANKED WORDLINE HEADER

A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication. 1. An electronic device , comprisinga memory bank comprising a plurality of wordlines adapted to activate memory cells; an input to activate the wordline driver,', 'the output to activate the respective one of the plurality of wordlines, and a power input that receives current to power the wordline driver;, 'a plurality of wordline drivers, each of the plurality of wordline drivers coupled via an output to a respective one of the plurality of wordlines and comprising'}a decoder adapted to decode a memory access request and to generate a memory address indication from a decoded memory access request, the decoder coupled to control delivery of power from an array supply to the power inputs of the plurality of wordline drivers based on a first part of the memory address indication and coupled to control selective activation of the plurality of word line drivers via the inputs thereof based on a second part of the memory address indication.2. The electronic device according to further comprising a header control device coupled to receive the first part of the memory address indication from the decoder and coupled to provide power to the power inputs of the plurality of wordline drivers in accordance with the first part of memory address indication.3. ...

CONTRIBUTOR-BASED POWER MODELING OF MICROPROCESSOR COMPONENTS

A method for generating a power model for a device includes identifying a device-level set of power contributors for a given state of the device, wherein each power contributor in the device-level set of power contributors contributes to power dissipation when the device is in the given state, and generating the power model for the device based on the device-level set of power contributors, wherein the power model is independent of process, voltage, and temperature. 1. A method for generating a power model for a device , the method comprising:identifying a device-level set of power contributors for a given state of the device, wherein each power contributor in the device-level set of power contributors contributes to power dissipation when the device is in the given state;generating the power model for the device based on the device-level set of power contributors, wherein the power model is independent of process, voltage, and temperature.2. The method of claim 1 , wherein the identifying comprises:determining a set of constituent cells of the device;determining states of the constituent cells; anddetermining, for each of the constituent cells, a cell-level set of power contributors that contribute to power dissipation when the constituent cells are in the states, where the device-level set of power contributors aggregates the cell-level set of power contributors for all of the constituent cells.3. The method of claim 2 , wherein the given state of the device is incompletely specified claim 2 , and the states of the constituent cells comprise claim 2 , for each of the constituent cells claim 2 , a plurality of states associated with a plurality of probabilities.4. The method of claim 3 , wherein the plurality of probabilities is determined using a probabilistic propagation technique.5. The method of claim 3 , wherein the plurality of probabilities is determined using a random simulation technique.6. The method of claim 3 , wherein the cell-level set of power ...

BALANCING DELAY ASSOCIATED WITH DUAL-EDGE TRIGGER CLOCK GATERS

Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode. 1. An apparatus , comprising:a first series of dual-edge triggered (DET) clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry, wherein ones of the DET clock gater circuits are controlled by respective control signals and wherein ones of the DET clock gater circuits are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock; anda first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.2. The apparatus of claim 1 , wherein ones of the DET clock gaters are configured to switch between inverting and non-inverting modes based on whether prior clock gating lasted an even or odd number of clock edges.3. The apparatus of claim 1 , wherein the first adjustable delay circuit includes an inverter and wherein the ...

Method for Multiplexing Between Power Supply Signals for Voltage Limited Circuits

In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

DETERMINISTIC CURRENT BASED FREQUENCY OPTIMIZATION OF PROCESSOR CHIP

A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor. 18-. (canceled)9. A system , comprising:a processor; anda memory, wherein the memory includes a program configured to adjust a frequency of a multi-core processor, the operations comprising:determining a total current and a temperature of the multi-core processor;estimating a leakage current for the multi-core processor;calculating a switching current by subtracting the leakage current from the total current;calculating an effective switching capacitance based at least in part on the switching current;calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data; andenforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.10. The system of claim 9 , wherein estimating the leakage current comprises using vital product data to estimate the leakage current for a voltage and temperature condition.11. The system of claim 10 , wherein estimating the leakage current further comprises adjusting the leakage current for a number of active cores of the ...

Deterministic current based frequency optimization of processor chip

A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

MANAGEMENT OF CORE POWER STATE TRANSITION IN A MICROPROCESSOR

A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state. 1. A method for adjusting a frequency of a multi-core processor , comprising:inhibiting one or more processor cores from exiting an idle state;determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores;selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores;setting the maximum frequency for both the inhibited and the non-idle processor cores; anduninhibiting the processor cores requesting exit from the idle state.2. The method of claim 1 , wherein inhibiting one or more processor cores from exiting an idle state further comprises setting a status in a control register.3. The method of claim 1 , wherein determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores further comprises inspecting a status for each processor core in a control register.4. The method of claim 1 , further comprising claim 1 , before uninhibiting the processor cores claim 1 , adjusting a voltage for each of the processor cores.5. The method of claim 4 , wherein adjusting the voltage is based at least in part ...

Management of core power state transition in a microprocessor

A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory. The memory stores program code, which, when executed on the processor, performs an operation for adjusting a frequency of a processor. The operation includes inhibiting one or more processor cores from exiting an idle state. The operation further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The operation also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The operation includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Voltage Regulation Using Local Feedback

A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.

Method for multiplexing between power supply signals for voltage limited circuits

In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. 1. A method of operating an integrated circuit with power gating , the method comprising:configuring a power header switch to connect and disconnect any one of a plurality of circuits to a common voltage source, wherein a powered off circuit in the plurality of circuits is disconnected from the common voltage source;controlling a first capacitor and a second capacitor to supply wakeup electrical charge to a given circuit of the plurality of circuits, the first capacitor and the second capacitor being connectable to the given circuit and the powered off circuit; andconfiguring a controller to controllably connect at least one of the first capacitor and the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, in response to the powered off circuit being previously connected to at least one of the first capacitor and the second capacitor.2. The method of claim 1 , wherein the at least one of the first capacitor and the second capacitor are charged by having been connected to the powered off circuit before the powered off circuit is disconnected from the common voltage source.3. The method of claim 1 , wherein the given circuit is disconnected from the ...

EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. 1. An integrated circuit with power gating , the integrated circuit comprising:a power header switch configured to connect and disconnect any one of a plurality of circuits to a common voltage source, wherein a powered off circuit in the plurality of circuits is disconnected from the common voltage source;a first capacitor and a second capacitor configured to supply wakeup electrical charge to a given circuit of the plurality of circuits, the first capacitor and the second capacitor being connectable to the given circuit and the powered off circuit; anda controller configured to controllably connect at least one of the first capacitor and the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, in response to the powered off circuit being previously connected to at least one of the first capacitor and the second capacitor.2. The integrated circuit of claim 1 , wherein the at least one of the first capacitor and the second capacitor are charged by having been connected to the powered off circuit before the powered off circuit is disconnected from the common voltage source.3. The integrated circuit of claim 1 , wherein the given circuit is disconnected ...

Predictively turning off a charge pump supplying voltage for overdriving gates of the power switch header in a microprocessor with power gating

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit.

PREDICTIVELY TURNING OFF A CHARGE PUMP SUPPLYING VOLTAGE FOR OVERDRIVING GATES OF THE POWER SWITCH HEADER IN A MICROPROCESSOR WITH POWER GATING

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit. 1. A method of operating an integrated circuit with power gating , the method comprising:configuring a power header switch to connect and disconnect a circuit to a common voltage source, wherein the circuit is a powered off circuit when disconnected from the common voltage source;configuring a multiplexer to selectably connect a charge pump or the common voltage source to a gate terminal of the power header switch, wherein the charge pump provides a higher voltage to the gate terminal than the common voltage source; andconfiguring a controller to control a selection of the multiplexer to the charge pump and the common voltage source, the controller configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to at least one of a following conditions:a prediction of a demand core power-up request;an increase in a gate leakage current; anda reduction in a temperature of the powered off circuit.2. The method of claim 1 , wherein the conditions claim 1 , for the controller to disconnect ...

ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES

A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source. 1. A method of operating an integrated circuit with power gating , the method comprising:configuring a power switch to connect and disconnect any one of a plurality of circuits to a common voltage source;configuring a capacitor tank to supply wakeup charge to a given circuit of the plurality of circuits;configuring a controllable element, which is connected to the given circuit and to the capacitor tank, to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit; andresponsive to the power switch disconnecting the given circuit from the common voltage source and responsive to the given circuit being turned on to wake up, turning on the controllable element to supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit, thereby reducing an amount of electrical charge transferred from the plurality of circuits connected to the common voltage source.2. The method of claim 1 , wherein a feed ...

ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. 1. A method for an integrated circuit with power gating , the method comprising:providing a power header switch to connect and disconnect any one of a plurality of circuits to a common voltage source, wherein a powered off circuit is disconnected from the common voltage source;configuring a power-up sequencer to comprise an initial stages power-up component and a final stages power-up component, wherein the final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit; andconfiguring the initial stages power-up component to execute initial stages of the power-up process for the powered off circuit, the initial stages power-up component being activated in response to a predictive power-up request.2. The method of claim 1 , further comprising configuring the initial stages power-up component to provide a partial wakeup of the powered off circuit.3. The method of claim 1 , further comprising configuring the initial stages power-up component to turn on partial functionality of the powered off circuit.4. The method of claim 3 , wherein the powered off circuit comprises an array of memory cells claim 3 , an automatic built-in self test circuit claim 3 , and other circuitry that reads and executes ...

Accelerating microprocessor core wake up via charge from capacitance tank without introducing noise on power grid of running microprocessor cores

A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source.

ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. 1. An integrated circuit with power gating , the integrated circuit comprising:a power header switch configured to connect and disconnect any one of a plurality of circuits to a common voltage source, wherein a powered off circuit is disconnected from the common voltage source; anda power-up sequencer comprising an initial stages power-up component and a final stages power-up component, wherein the final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and wherein the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit, the initial stages power-up component being activated in response to receiving a predictive power-up request.2. The integrated circuit of claim 1 , wherein the initial stages power-up component is configured to provide a partial wakeup of the powered off circuit.3. The integrated circuit of claim 1 , wherein the initial stages power-up component is configured to turn on partial functionality of the powered off circuit.4. The integrated circuit of claim 3 , wherein the powered off circuit comprises an array of memory cells claim 3 , an automatic built-in self test circuit claim 3 , and other circuitry ...

SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP

In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. 1. A semiconductor system configured to enhance reliability or reduce performance variability comprising:a primary layer including a first semiconductor chip that is a microprocessor chip, said microprocessor chip including at least one first critical block; and a first means for detecting a need for replacing, or enhancing performance of, a resource in said first semiconductor chip;', 'a second means for scanning a pool of existing execution resources or memory resources to find an eligible replacement resource for, or an eligible performance-enhancing resource for, said resource in said first semiconductor chip;', 'a third means for configuring at least one element of said set of configurable resources to replace, or to enhance performance of, said resource in said first semiconductor chip;', 'at least one general logic block including a look-up table embodying preprogrammed recovery schemes for various faults., 'an auxiliary layer including a second semiconductor chip attached ...

Managing Interconnect Electromigration Effects

A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent. 1. A method , in a data processing system , for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors , the method comprising:for each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, determining a current modeled age of the interconnect group;determining whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value; andresponsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, sending an indication to take corrective action with the at least one associated interconnect group.2. The method of claim 1 , further comprising:responsive to none of the current modeled age of the interconnect group for the set of interconnect groups being less than or equal to the end-of-life value, repeating the process to calculate a new modeled age for each of the set of interconnect groups;determining whether at least one of the new modeled age of the interconnect group for the set of interconnect groups is greater than the end-of-life value; andresponsive to at least one new modeled age of the interconnect group being greater ...

Low leakage power switch

A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

Management of core power state transition in a microprocessor

A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Efficient wakeup of power gated domains through charge sharing and recycling

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor.

Efficient wakeup of power gated domains through charge sharing and recycling

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor.

EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. 1. A method of operating an integrated circuit with power gating , the method comprising:configuring a power header switch to connect and disconnect any one of a plurality of circuits to a common voltage source, wherein a powered off circuit in the plurality of circuits is disconnected from the common voltage source;controlling a first capacitor and a second capacitor to supply wakeup electrical charge to a given circuit of the plurality of circuits, the first capacitor and the second capacitor being connectable to the given circuit and the powered off circuit; andconfiguring a controller to controllably connect the first capacitor and the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, in response to the powered off circuit being previously connected to at least one of the first capacitor and the second capacitor;wherein a first coupling element and a second coupling element are turned on to connect the first capacitor and the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit; andwherein a third coupling element is turned off which disconnects the powered off circuit from the first ...

EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. 1. A method of operating an integrated circuit with power gating , the method comprising:configuring a power header switch to connect and disconnect any one of a plurality of circuits to a common voltage source, wherein a powered off circuit in the plurality of circuits is disconnected from the common voltage source;controlling a first capacitor and a second capacitor to supply wakeup electrical charge to a given circuit of the plurality of circuits, the first capacitor and the second capacitor being connectable to the given circuit and the powered off circuit; andconfiguring a controller to controllably connect the first capacitor and the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, in response to the powered off circuit being previously connected to at least one of the first capacitor and the second capacitor;wherein a first coupling element and a second coupling element are turned on to connect the first capacitor and the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit; andwherein a third coupling element and a fourth coupling element are turned off to disconnect the powered off ...

Voltage Regulation Using Local Feedback

A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.

ROTATING VOLTAGE CONTROL

According to one embodiment, a system is provided that includes at least one power gated component and two or more power switch transistors configured to provide one or more conductive paths between a common power supply rail, the at least one power gated component, and a ground. The two or more power switch transistors each include a source terminal, a drain terminal, and a gate terminal configured to control current flow between the source and drain terminals. The system also includes a rotating voltage control coupled to the gate terminals and configured to apply a sequence of control signals rotating between an on-state and an off-state to each of the gate terminals while the at least one power gated component is turned on. A switch activation ratio level is programmable to set a number of power switch transistors in the on-state relative to a total number of power switch transistors. 1. A system , comprising:at least one power gated component;two or more power switch transistors configured to provide one or more conductive paths between a common power supply rail, the at least one power gated component, and a ground, the two or more power switch transistors each comprising a source terminal, a drain terminal, and a gate terminal configured to control current flow between the source and drain terminals; anda rotating voltage control coupled to the gate terminals of the two or more power switch transistors and configured to apply a sequence of control signals rotating between an on-state and an off-state to each of the gate terminals while the at least one power gated component is turned on, and a switch activation ratio level of the rotating voltage control is programmable to set a number of the two or more power switch transistors in the on-state relative to a total number of the two or more power switch transistors.2. The system of claim 1 , wherein the rotating voltage control further comprises a rotation controller configured to rotate the two or more power ...

Method for multiplexing between power supply signals for voltage limited circuits

In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Efficient Retention Flop Utilizing Different Voltage Domain

A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

Power Switch Multiplexer with Configurable Overlap

A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal. 1. An integrated circuit comprising:a first functional circuit block coupled to receive a supply voltage from a first supply voltage node; and a first input circuit configured to, responsive to receiving a first input signal, assert a first activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node and subsequently assert a first deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node; and', during operation in a first mode, assert a first output signal to a first logic level from a second, different logic level, responsive to receiving the first activation signal and prior to receiving the first deactivation signal at a logic level eguivalent to that of the first activation signal; and', 'during operation in a second mode, assert the first output signal from the first logic level to the second logic level responsive to receiving both the first activation signal and the first deactivation signal at equivalent logic ...

Processor with demand-driven clock throttling power reduction

Symbolic Execution of Instructions on In-Order Processors

A method is provided for processing instructions by a processor, in which instructions are queued in an instruction pipeline in a queued order. A first instruction is identified from the queued instructions in the instruction pipeline, the first instruction being identified as having a dependency which is satisfiable within a number of instruction cycles after a current instruction in the instruction pipeline is issued. The first instruction is placed in a side buffer and at least one second instruction is issued from the remaining queued instructions while the first instruction remains in the side buffer. Then, the first instruction is issued from the side buffer after issuing the at least one second instruction in the queued order when the dependency of the first instruction has cleared and after the number of instruction cycles have passed.

Power switch multiplexer with configurable overlap

A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal.

Processor with demand-driven clock throttling power reduction

A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

Method for implementing dynamic lifetime reliability extension for microprocessor architectures

A method for implementing dynamic lifetime reliability extension for microprocessor architectures having a plurality of primary resources and a secondary resource pool of one or more secondary resources includes configuring a resource operational mode controller to selectively switch of the primary and secondary resources between an operational mode and a non-operational mode, wherein the non-operational mode corresponds to a lifetime extension process; configuring a resource mapper associated with the secondary resource pool and in communication with the resource operational mode controller to map a secondary resource placed into the operational mode to a corresponding primary resource placed into the non-operational mode; and configuring a transaction decoder to receive incoming transaction requests and direct the requests to one of a primary resource in the operational mode and a secondary resource in the operational mode, the secondary resource mapped to an associated primary resource placed in the non-operational mode.

Power Converter with Charge Injection from Booster Rail

A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.

Method and apparatus for control signals memoization in a multiple instruction issue microprocessor

A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Power converter with charge injection from booster rail

A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.

Voltage regulation using local feedback

A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.

System and method of execution of register pointer instructions ahead of instruction issue

A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.

Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power

A device for controlling power parameters in a microprocessor (10) includes a resource activation control unit (12) for controlling the maximum power of the microprocessor (10) and two or more resources (261, 262, 263). The resource activation control unit (12) controls the activation of the resources (261, 262, 263).such that the consumed and dissipated power of the microprocessor (10) does not exceed a power bound which is configurable to a predetermined value below the maximum power.

Merged power delivery

A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

Merged Power Delivery

A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

System and method of execution of register pointer instructions ahead of instruction issues

A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.

Method for multiplexing between power supply signals for voltage limited circuits

In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Prozessor mit anforderungsgesteuerter taktdrosselung zur leistungsreduzierung

Method and apparatus for preventing soft error accumulation in register arrays

A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold.

Power Converter Circuit For Use with Multiple Low-Current Power Rails

A power management circuit for computer systems includes a power converter circuit that generates different voltage levels at different time periods. Multiple voltage regulator circuits are coupled to the output of the power converter circuit and to respective local power supply nodes. Switch devices are used to bypass the voltage regulator circuits during corresponding ones of the different time periods.

Power converter circuit for use with multiple low-current power rails

A power management circuit for computer systems includes a power converter circuit that generates different voltage levels at different time periods. Multiple voltage regulator circuits are coupled to the output of the power converter circuit and to respective local power supply nodes. Switch devices are used to bypass the voltage regulator circuits during corresponding ones of the different time periods.

Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power

A device for controlling power parameters in a microprocessor (10) includes a resource activation control unit (12) for controlling the maximum power of the microprocessor (10) and two or more resources (261, 262, 263). The resource activation control unit (12) controls the activation of the resources (261, 262, 263).such that the consumed and dissipated power of the microprocessor (10) does not exceed a power bound which is configurable to a predetermined value below the maximum power.

Method for extending lifetime reliability of digital logic devices through removal of aging mechanisms

A method for extending lifetime reliability of CMOS circuitry includes coupling a first switching device between a logic high supply rail/logic low supply rail, and coupling a virtual supply rail to the CMOS circuitry. In a first mode of operation the first switching device supplies the full voltage value between the logic high supply rail and the logic low supply rail, and in a second mode of operation, the first switching device isolates the virtual supply rail from the logic high supply rail/logic low supply rail, thereby reducing the voltage supplied to the CMOS circuitry. A second switching device is coupled between the virtual supply rail and the logic low supply rail/logic high supply rail, wherein in a third mode of operation, the voltage on the virtual supply rail and the logic low supply rail/logic high supply rail is equalized.

Dynamic workload frequency optimization

The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.

Deterministic current based frequency optimization of processor chip

A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Modulation of power supply voltage for varying propagation delay

Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle.

Accelerating the microprocessor core wakeup by predictively executing a subset of the power-up sequence

A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request.