Accelerating microprocessor core wake up via charge from capacitance tank without introducing noise on power grid of running microprocessor cores

23-08-2016 дата публикации

Номер:

US0009423865B2

Автор: Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban, BOSE PRADIP, BUYUKTOSUNOGLU ALPER, JACOBSON HANS, ZYUBAN VICTOR

Принадлежит: GLOBALFOUNDRIES INC., GLOBALFOUNDRIES INC

Контакты:

Номер заявки: 44-64-1402

Дата заявки: 13-09-2013

CPC - классификация

G G0 G06 G06F G06F1 G06F1/G06F1/2 G06F1/26 G06F1/3 G06F1/32 G06F1/328 G06F1/3287 Y Y0 Y02 Y02B Y02B6 Y02B60 Y02B60/Y02B60/1 Y02B60/12 Y02B60/128 Y02B60/1282 Y02D Y02D1 Y02D10 Y02D10/Y02D10/0 Y02D10/00

IPC - классификация

G G0 G06 G06F G06F1 G06F1/G06F1/2 G06F1/26 G06F1/3 G06F1/32 G06F1/322 G06F1/3228 G06F1/328 G06F1/3287 G06F1/329 G06F1/3293

Цитирование НПИ

307/115
327/142
327/538
Kawaskaki et al. “A Sub- μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support,” Fujitsu Laboratories Ltd., 2008 Symposium on VLSI Circuits Digest of Technical Papers, 978-I-4244-1805-3/08, IEEE, 2 pages.
Mark Lehn et al, “A 0.13- 1-GS/s CMOS Discrete-Time FFT Processor for Ultra-Wideband OFDM Wireless Receivers”, 2011; 12 pages.
Michael Powell et al, “Gated-Vdd—a circuit technique to reduce leakage in deep-submicron cache memories”, 2000, Purdue University, School of Electrial and Computer Engineering, 6 pages.
Office Action for related U.S. Appl. No. 14/171,836 dated Feb. 12, 2016; 24 Pages.
Richard Strong et al, “Fast switching of threads between cores”, ACM SIGOPS Operating Systems Review, vol. 43, Issue 2, Apr. 2009, pp. 35-45; 12 pages.

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