УПРАВЛЕНИЕ ЭНЕРГИЕЙ БАТАРЕИ ДЛЯ ЭЛЕКТРОННОГО УСТРОЙСТВА

Использование: в области электротехники. Технический результат - обеспечение управления мощностью батареи при низких температурах. Контроллер содержит логическую схему для приема показателя температуры для электронного устройства, подключаемого к первой батарее, содержащей химический состав на основе ионов лития, и второй батареей, содержащей химический состав на основе литий трифторхлоробората; для активации электронного устройства используя первую батарею, когда показатель температуры выше, чем пороговое значение; и для воплощения процедуры управления питанием, когда показатель температуры ниже, чем пороговое значение, при этом процедура управления питанием содержит активацию электронного устройства используя вторую батарею. 4 н. и 18 з.п. ф-лы, 9 ил.

ОКОНЧАНИЕ ИНСТРУКЦИИ С УЧЕТОМ ПОТРЕБЛЯЕМОЙ ЭНЕРГИИ

Изобретение относится к способу, устройству и системе управления логикой окончания инструкций. Техническим результатом является уменьшение потребляемой энергии. Способ содержит: прием статической информации, связанной с инструкцией, при выделении инструкции, и сохранение участка статической информации в первом участке буфера выделения, и сохранение второго участка статической информации во втором участке буфера выделения, если статическая информация обозначает событие, которое должно быть выполнено во время окончания инструкции; выработку раннего сигнала гарантии во время окончания инструкции для инструкции, если статическая информация, связанная с инструкцией, не присутствует во втором участке буфера выделения; и в противном случае включение питания второго участка буфера выделения, для обеспечения доступа ко второму участку статической информации, в котором если выработан ранний сигнал гарантии, выключают второй участок буфера выделения, для уменьшения потребляемой энергии во время нормальных ...

АРХИТЕКТУРА С УЛЬТРАНИЗКОЙ МОЩНОСТЬЮ ДЛЯ ПОДДЕРЖКИ ПОСТОЯННО ВКЛЮЧЕННОГО ПУТИ К ПАМЯТИ

Группа изобретений относится к технологии доступа к памяти. Технический результат – обеспечение возможности использования несколько шин подачи питания для уменьшения потребления энергии. Для этого предложено устройство, которое включает в себя первую шину подачи питания, в котором множество подсистем должны получать питание от первой шины подачи питания. Устройство также включает в себя вторую шину подачи питания, в котором множество автономных подсистем должны получать питание от шины подачи питания, в котором вторая шина подачи питания должна быть постоянно включена, постоянно доступна и иметь малую мощность. 3 н. и 19 з.п. ф-лы, 4 ил.

СИНХРОНИЗАЦИЯ РАЗБЛОКИРОВАНИЯ ТАКТОВОГО СИГНАЛА ВЭЛЕКТРОННОМ УСТРОЙСТВЕ

Способ синхронизации разблокирования общего тактового генератора для главного и второго процессоров в электронном устройстве, имеющем режим низкой мощности, включает в себя первый этап завершения коммуникационной деятельности главным процессором. Далее отслеживают сигнал разблокирования тактового сигнала от второго процессора. Сравнивают таймирование второго процессора с известным таймированием главного процессора, если на этапе слежения второй процессор не разблокировал тактовый генератор. Вычисляют таймирование, необходимое для синхронизации разблокирования тактового генератора вторым процессором с соответствующим действием главного процессора. Включают и выключают второй процессор под управлением главного процессора для синхронизации периодического таймирования второго процессора с таймированием главного процессора. Способ позволяет уменьшить потребление энергии тактовым генератором. 9 з.п. ф-лы, 5 ил.

ЭНЕРГОСБЕРЕГАЮЩЕЕ ПЛАНИРОВАНИЕ ПОТОКОВ И ДИНАМИЧЕСКОЕ ИСПОЛЬЗОВАНИЕ ПРОЦЕССОРОВ

Изобретение относится к средствам обеспечения энергосберегающего планирования потоков и динамического использования процессоров. Технический результат заключается в уменьшении потребления электроэнергии. Определяют, какие ядра из упомянутого множества ядер активно выполняют работу. Создают маску приостановки ядер с использованием битового значения для представления приостановленного или работающего состояния ядра. Определяют маски привязки потока к процессору, представляющие одно или более ядер, которым назначена обработка потока. Обеспечивают, по меньшей мере, часть плана производительности и энергосбережения для ядер путем объединения инвертированной маски приостановки ядер и масок привязки потока к процессору, используя оператор "И", чтобы создать набор доступных процессоров. Вычисляют, какие ядра обозначаются как приостановленные или работающие, на основе, по меньшей мере частично, набора доступных процессоров. Приостанавливают по меньшей мере одно из ядер, активно выполняющих работу ...

СПОСОБЫ И УСТРОЙСТВО ДЛЯ ОСУЩЕСТВЛЕНИЯ СВЯЗИ ЧЕРЕЗ УДАЛЕННОЕ ТЕРМИНАЛЬНОЕ УСТРОЙСТВО

Изобретение относится к области вычислительной техники для осуществления связи через удаленное терминальное устройство. Технический результат заключается в улучшении инструментов настройки сети и мониторинга сети. Приведенное в качестве примера устройство содержит первый модуль центрального процессора, который предназначен для связи с хостом системы управления технологическим процессом. Приведенное в качестве примера устройство также содержит первую стойку, содержащую объединительную панель и множество щелевых разъемов. Множество щелевых разъемов содержит основной щелевой разъем для приема первого модуля центрального процессора. Объединительная панель соединяет с возможностью связи первый модуль центрального процессора по меньшей мере с одним из первого модуля связи или первого модуля ввода-вывода, вставленного во второй из щелевых разъемов. Объединительная панель содержит первую коммуникационную шину для передачи данных ввода-вывода и вторую коммуникационную шину для передачи по меньшей ...

УСТРОЙСТВО ДЛЯ АРХИТЕКТУРЫ ВЫСОКОЭФФЕКТИВНОГО УПРАВЛЕНИЯ ЭЛЕКТРОПИТАНИЕМ ПЛАТФОРМЫ В РЕЖИМЕ РЕАЛЬНОГО ВРЕМЕНИ

Изобретение относится к устройствам подачи питания в вычислительных системах. Техническим результатом является повышение быстродействия управления подачей питания в режиме реального времени. Согласно настоящему изобретению используют прямое управление за счет интегрированных регуляторов напряжения, а также с использованием прямого интерфейса управления электропитанием (DPMI) для обмена сообщениями о состоянии электропитания. Интегрированные регуляторы напряжения, такие как регуляторы напряжения на кремнии (ISVR), можно использовать для выполнения более быстрых, более высокочувствительных переходов состояний электропитания. 3 н. и 20 з.п.ф-лы, 12 ил.

СПОСОБ И АППАРАТ ДЛЯ ПРОБУЖДЕНИЯ ЭЛЕКТРОННОГО УСТРОЙСТВА

Изобретение относится к области управления электронными устройствами, имеющими средства беспроводной связи, а именно к пробуждению электронного устройства, находящегося в режиме энергосбережения. Техническим результатом является обеспечение возможности быстрой удаленной активизации спящего электронного устройства за счет широковещательной передачи команды пробуждения, не требующей установления соединения с пробуждаемым устройством. Для этого осуществляют получение целевого электронного устройства в той же целевой локальной сети, что и пробуждаемое электронное устройство, и отправляют команду пробуждения целевому электронному устройству так, что целевое электронное устройство широковещательно передает в целевой локальной сети сообщение пробуждения для пробуждения пробуждаемого электронного устройства в соответствии с командой пробуждения. При этом определение целевой локальной сети, к которой обращается пробуждаемое электронное устройство, осуществляют в соответствии с предварительно утвержденным ...

СХЕМА СОПРЯЖЕНИЯ, СПОСОБ И УСТРОЙСТВО ДЛЯ ПЕРЕКЛЮЧЕНИЯ СОСТОЯНИЙ

СПОСОБ ЭКСПЛУАТАЦИИ ПОЛЬЗОВАТЕЛЬСКОГО ТЕРМИНАЛА СЕЛЬСКОХОЗЯЙСТВЕННОЙ МАШИНЫ И СЕЛЬСКОХОЗЯЙСТВЕННАЯ МАШИНА

Спосооб и устройство дл блокировки сигнала синхронизации в многопоточном процессоре

... 1. Способ, включающий в себя этапы: осуществляют индикацию ожидающего обработки события для каждого из множества потоков, поддерживаемых в многопоточном процессоре, осуществляют индикацию активного или неактивного состояния для каждого из множества потоков, поддерживаемых в многопоточном процессоре, обнаруживают условие блокировки синхронизации, указываемое индикацией отсутствия ожидающих обработки событий для каждого из множества потоков и неактивное состояние для каждого из множества потоков, и блокируют сигнал синхронизации, если он разрешен, для, по меньшей мере, одного функционального блока в многопоточном процессоре в зависимости от обнаружения условия блокировки синхронизации. 2. Способ по п.1, включающий в себя обнаружение условия разрешения синхронизации, на которое указывает индикация ожидающего обработки события, для, по меньшей мере, одного потока из множества потоков, поддерживаемых в многопоточном процессоре, или индикация активного состояния для, по меньшей мере, одного потока ...

ОБНАРУЖЕНИЕ И ИСПРАВЛЕНИЕ ОШИБОК НА СТУПЕНЯХ ОБРАБОТКИ ИНТЕГРАЛЬНОЙ СХЕМЫ

... 1. Интегральная схема для выполнения обработки данных, содержащая обнаружитель ошибок, действующий для обнаружения ошибок в работе интегральной схемы путем двойной дискретизации значений сигнала данных в интегральной схеме, причем разница между дискретизированными значениями указывает на ошибку; логическую схему исправления ошибок, реагирующую на обнаружитель ошибок и действующую для исправления ошибок в работе; и контроллер рабочего параметра, действующий для управления одним или более рабочими параметрами управления быстродействием интегральной схемы; при этом контроллер рабочего параметра динамически управляет по меньшей мере одним из одного или более параметров управления быстродействием в зависимости от одной или более характеристик ошибок, обнаруженных обнаружителем ошибок, для поддержания ненулевой частоты ошибок при работе, причем ошибки в работе исправляются логической схемой исправления ошибок так, чтобы обработка данных интегральной схемой продолжалась. 2. Интегральная схема ...

ФИЗИЧЕСКИЙ УРОВЕНЬ ВЫСОКОПРОИЗВОДИТЕЛЬНОГО МЕЖСОЕДИНЕНИЯ

... 1. Устройство, содержащеелогическую схему интерфейса, предназначенную для того, чтобы дифференцированно передавать сигналы по нескольким путям передачи данных,логическую схему интерфейса, предназначенную для передачи нескольких флитов, причем несколько флитов содержат несколько полубайтов;и при этом логическая схема интерфейса для передачи нескольких флитов, содержит логическую схему интерфейса для передачичистой границы флита, по меньшей мере, с участком начальных полубайтов от первого флита из множества флитов по нескольким путям передачи данных в первом единичном интервале (UI); иперекрытие полубайтов, по меньшей мере, от двух флитов из множества флитов по нескольким путям передачи данных во время следующего UI.2. Устройство по п. 1, в котором множество флитов содержит, по меньшей мере, пять флитов, которые необходимо передать за 48 UI до того, как надо будет передать следующую чистую границу флита.3. Устройство по п. 1, в котором флит содержит 192 бита, а полубайт содержит 4 бита.4.

Verfahren und Anordnung zur Leistungseinsparung in einem Computersystem unter Benutzung eines Leistungssteuerungs-Pseudogeräte-Treibers

Anwendungsprozessor mit Sprachtriggersystem mit niedriger Leistung und direktem Weg zum Unterbrechen, elektronisches Gerät mit demselben und Verfahren zum Betreiben desselben

Ein Anwendungsprozessor kann einen Host-Prozessor, ein Sprachtriggersystem und ein Audio-Subsystem beinhalten, das elektrisch mit einem Systembus verbunden ist. Das Sprachtriggersystem kann konfiguriert werden, um einen Sprachtriggervorgang durchzuführen und ein Triggerereignis auszugeben. Das Audio-Subsystem kann konfiguriert werden, um einen Audio-Ausgangsstrom über eine Audio-Schnittstelle wiederzugeben. Ein direkter Bus kann konfiguriert werden, um einen Kommunikationsweg zwischen dem Sprachtriggersystem und dem Audio-Subsystem während einer Unterbrechungs-Bedingung bereitzustellen, in der der Sprachtriggervorgang und die Wiedergabe des Audio-Ausgangsstroms gemeinsam durchgeführt werden. Der Anwendungsprozessor kann konfiguriert werden, um kompensierte Triggerdaten zu erzeugen, indem er eine Echounterdrückung in Bezug auf von einem Mikrofon empfangene Mikrofondaten durchführt, und das Sprachtriggersystem kann konfiguriert werden, um den Sprachtriggervorgang während der Unterbrechungs-Bedingung ...

Energiesparmodus für Signalsystem eines Bahnsystems

Es wird vorgeschlagen, zum Energiesparen Teile eines Signalsystems z.B. mittels einer Bedienung abzuschalten. Die abzuschaltenden Rechner speichern für den Bahnbetrieb sicherheitsrelevante Daten vorzugsweise auf einem zentralen Speichermedium, z.B. einer NAS-Festplatte. Nach deren Re-Aktivierung, lesen die Rechner die sicherheitsrelevanten Daten und der Betrieb kann fortgesetzt werden. Durch diese Lösung ist es möglich, auch Rechner, die mit für den Bahnbetrieb sicherheitsrelevanten Daten arbeiten, in einen Energiesparmodus zu versetzen, ohne dabei die Sicherheit des Bahnbetriebs zu gefährden.

Verfahren und Vorrichtung zum Optimieren von Systembatterielebensdauer für statische oder halbstatische Bildbetrachtungsnutzungsmodelle

Ein Computersystem, welches aufweist: Einen Graphikprozessor, einen Anzeigecontroller, der einen anzeigelokalen Framebuffer aufweist, eine Anzeigevorrichtung und einen Speicher. Der Speicher speichert Anweisungen, die, wenn sie durch das Computersystem ausgeführt werden, ein Verfahren durchführen, um einen Energieverwaltungszustand zu betreten. Das Verfahren weist das Detektieren auf, dass das Computersystem inaktiv ist und einen optionalen Annäherungsdetektor zum Bestimmen, wenn ein Benutzer vor dem System anwesend ist. Wenn das Computersystem inaktiv ist und der Benutzer in der Nähe des Systems, wird der anzeigelokale Framebuffer aktiviert. Anzeigeinformationen, die durch den Graphikprozessor übertragen werden, werden in dem anzeigelokalen Framebuffer gespeichert. Anfänglich wird ein Energiereduktionszustand für das Graphikuntersystem, einschließlich des graphischen Prozessors initiiert, und die Anzeigevorrichtung wird in einen Selbstaktualisierungszustand gesetzt, wobei die Anzeige von ...

Verfahren und Vorrichtung zum Verbinden eines Benutzers mit einer mobilen Rechnereinrichtung

Verfahren, das folgendes umfaßt: Liefern von Informationen an eine Benutzerschnittstelle (410), die eine sekundäre Anzeige (311, 351, 411) besitzt und mit einer mobilen Rechnereinrichtung (310, 350, 450, 701) mit einer primären Anzeige (406) verbunden ist, wobei die mobile Rechnereinrichtung in mehreren Leistungszuständen (501–504) betrieben werden kann und die Benutzerschnittstelle die primäre Anzeige nicht umfaßt; und Betreiben der mobilen Recheneinrichtung in einem Zustand geringer Leistung (504, 505), während die Informationen zu der Benutzerschnittstelle geliefert werden.

Monitor für einen PC und mit mindestens einem Steckverbinder für ein Videosignal

Der Monitor für einen PC (50) und mit mindestens einem Vielfach-Steckverbinder (58) für ein Bildsignal, das über ein Videokabel (56) geliefert wird, welches den Monitor (60) mit dem PC (50) verbindet, sowie mit einer Netzleitung (76) einer Spannungsversorgung, hat ein Relais (72), das mindestens einen Schaltkontakt (74) und einen Aktuator (70) hat. Der Schaltkontakt (74) ist in die Netzleitung (76) eingefügt und unterbricht diese wahlweise oder nicht. Der Aktuator (70) ist mit demjenigen Vielfach-Steckanschluss des Vielfach-Steckverbinders (58) verbunden, der normalerweise eine 5 Volt Gleichspannung liefert.

Mobiles Endgerät

Mobiles Endgerät, das aufweist:eine Anzeigeeinheit (151) mit einer Beleuchtung zum Beleuchten der Anzeigeeinheit,einen Berührungssensor (140), der ausgelegt ist, eine Berührungseingabe zu erfassen, undeine Steuereinrichtung (180), die ausgelegt ist zum:falls eine erste auf den Berührungssensor (140) aufgebrachte Antippeingabe erfasst wird in einem Zustand, in dem die Beleuchtung aus ist und der Berührungssensor (140) mit einer ersten Periode angesteuert wird, Bestimmen eines Bereichs der Anzeigeeinheit (151), der der ersten Antippeingabe entspricht;falls eine zweite auf den Berührungssensor (140) aufgebrachte Antippeingabe innerhalb eines vorgegebenen Zeitraums nach der ersten Antippeingabe erfasst wird, Bestimmen, ob die zweite Antippeingabe innerhalb des bestimmten Bereichs angewendet wird; undfalls die zweite Antippeingabe innerhalb des bestimmten Bereichs und innerhalb des vorgegebenen Zeitraums nach der ersten Antippeingabe angewendet wird, Umschalten der Anzeigeeinheit (151) durch ...

Verfahren und Vorrichtung für Energiesparbetrieb von Mehrkern-Prozessoren

Verfahren, umfassend: Empfangen (302) einer Anforderung in einen Energiesparmodus einzutreten; Kontinuierlich Erkennen (304) eines oder mehrerer nicht zugeteilter Software-Threads für eine aktive Arbeitsauslastung im Energiesparmodus; Erkennen von Energiemerkmalen oder Wärmemerkmalen für jeden der Mehrzahl von Kernen eines Mehrkern-Prozessors; Auswählen eines Satzes von Prozessorkernen basierend auf den erkannten Energiemerkmalen oder Wärmemerkmalen; Kontinuierlich Zuteilen (306) des einen oder der mehreren erkannten nicht-zugeteilten Software-Threads für die aktive Arbeitsbelastung, um auf dem Satz der ausgewählten Prozessorkerne des Mehrkern-Prozessors zu laufen, wobei der ausgewählte Satz an Prozessorkernen weniger als eine Gesamtanzahl an Prozessorkernen des Mehrkern-Prozessors umfasst; Verringern der Anzahl von Prozessorkernen in dem Satz von Prozessorkernen; Zuteilen des einen oder der mehreren nicht-zugeteilten Software-Threads, um auf dem verringerten Satz an Prozessorkernen zu ...

Architekturen und Verfahren zur Verwaltung von Fahrzeuginternen vernetzten Steuerungen und Vorrichtungen

Offenbart werden Steuerungsalgorithmen und Systemarchitekturen zur Verwaltung des Betriebs vernetzter Steuerungen und Vorrichtungen, einschließlich Fahrzeuge mit einem Bordnetz von elektronischen Steuergeräten (ECU) und Steuerlogik zum Regeln des Ruhens und Aktivierens dieser ECUs. Ein Verfahren zur Verwaltung des fahrzeuginternen Netzwerks von ECUs in einem Kraftfahrzeug beinhaltet: das Ermitteln von Statusvektoren für eine Gruppe von ECUs, wobei jeder Statusvektor angibt, ob das entsprechende ECU aktiv oder nicht aktiv ist; das Ermitteln der Vorrichtungsrollen für diese ECUs - Slave oder Master; das Ermitteln einer zugewiesenen Hierarchie zum Auswählen der ECUs als Master-Vorrichtung; das Empfangen eines Modusänderungssignals, das anzeigt, dass ein ECU beabsichtigt, in den Ruhezustand oder in den aktivierten Zustand überzugehen; und in Reaktion darauf, das Modifizieren der jeweiligen Vorrichtungsrolle für ein ECU vom Master zum Slave und der jeweiligen Vorrichtungsrolle für ein anderes ...

Halbleitervorrichtung und Halbleitersystem

Es wird eine Halbleitervorrichtung (3) und ein Halbleitersystem offenbart. Die Halbleitervorrichtung (3) weist eine Hardwareautotaktausblend- (HWACG-) Logik (105), die konfiguriert ist, um ein Taktausblenden eines Blocks (200) eines geistigen Eigentums (IP) zu liefern, und eine Speicherstromsteuerung (400) auf, die konfiguriert ist, um basierend auf der HWACG-Logik (105), die das Taktausblenden für den IP-Block (200) liefert, ein Stromausblenden eines Speichers (410), der mit dem IP-Block (200) elektrisch verbunden ist, durchzuführen. Die HWACG-Logik (105) weist eine erste Taktquelle, die konfiguriert ist, um ein erstes Taktsignal zu liefern, eine zweite Taktquelle, die konfiguriert ist, um das erste Taktsignal, das durch die erste Taktquelle geliefert wird, zu empfangen und ein zweites Taktsignal (CLK) zu dem IP-Block (200) zu liefern, eine erste Taktsteuerschaltung, die konfiguriert ist, um die erste Taktquelle zu steuern, und eine zweite Taktsteuerschaltung auf, die konfiguriert ist, ...

Registereinrichtung zur Erleichterung des Wechsels von Teilprogrammen und Teilprogrammschnitten in einem elektronischen Rechner

Verfahren und Vorrichtung um Turboleistung für das Event-Handling zu verbessern

System und Verfahren zur Speicherung von Daten als Reaktion auf offene und geschlossene Ereignisse bei einer mobilen Kommunikationsvorrichtung

Power conservation for mobile device displays

Processor architecture

Power gating in an electronic device

An electronic device 2 has circuitry 4, e.g. a processor or memory, which operates in a first voltage domain 6 supplied with a first voltage level VDD1 and a reference voltage level 10, e.g. ground. A voltage regulator 14 generates the first voltage level VDD1 from a second, higher voltage level VDD2. At least one power gate is provided for selectively coupling the circuitry 4 to one of the first voltage level VDD1 (header switching) or the reference level (footer switching). Thus, power gate 20 or 30 may connect circuitry 4 to ground. The control signal 22 for the power gate 20 is generated by control circuitry 24 operating in a second voltage domain supplied with the higher voltage level VDD2. The control circuitry 24 may operate in a voltage domain VDD3 lower than VDD2, but higher than VDD1 (fig.2). Hence, within the device 2, an existing high voltage source, which may be an energy harvesting system, can be re-used for applying a boosted control voltage 22 to power gates 20 to improve ...

Tracking control flow of instructions

Embedded Computing Device

Processor architecture

Maintaining wireless communications in a portable computer in a power off state.

A system for maintaining wireless communications in a portable computer 11 in a power off state comprises a power supply 12, a controller 14 and two circuits 13 and 131. A first main circuit 13 provides the main functions of the computer and contains within it a second circuit 131. The second circuit comprises a storage unit 1312 and a communication unit 1311. In a first operating slate, power is supplied to the first circuit allowing a wireless transmission to occur. In a second power-off state, power is provided to the second circuit only which maintains the wireless transmission capability of the device. A second power supply and storage unit (Fig 5) may also be provided. The second power supply may be used to power the second circuit when the capacity of the first power supply is below a predetermined maximum. The second supply may also be used to charge the first power supply. The arrangement is particularly suited to a portable computer and allows the user to receive electronic mail ...

Frequency generation circuit

A frequency generation circuit comprises a crystal oscillator (10) for providing an input frequency, and a phase-locked loop circuit (28). The frequency generation circuit can generate a plurality of different output frequencies by using a plurality of frequency dividers for supply to respective DAB and FM tuners (50, 60, 70). The frequency generation circuit can be used, together with a baseband circuit (14), in a radio receiver (1, 2). The same oscillator and phase-locked loop circuit is used to drive the baseband circuit.

Power management on a vehicle

A hypervisor for controlling a power state of a vehicle controller, the vehicle controller comprising at least two virtual machines hosted on the vehicle controller. The hypervisor is configured to: receive 100 an active status indication from at least one virtual machine; determine 102, in dependence on the active status indication, if at least one virtual machine is active; and inhibit 104 a reduced power state of the vehicle controller if the hypervisor determines that at least one virtual machine is active. In doing so, the hypervisor can inhibit the vehicle controller entering a reduced power state (i.e. stand-by) until the virtual machine has completed the tasks for which it requires power. Also provided is a method of controlling a power state of a vehicle controller.

Enabling and disabling clocking signals to elements

Computer system having direct media access mode

An interface for serial data communication

Power control circuit

Power load management apparatus and method

A power load management apparatus 130 having an appliance switching unit 231 to activate or deactivate one or more appliances, and a controller 232 to activate an inactive appliance in response to a command if it determines that the total power load will not then exceed a set threshold. Additionally there is a control method for the power load management apparatus and a computer-readable storage medium with computer program instructions to execute the control method. The apparatus may have a scheduling unit 234 for future activation of appliances as power load capacity becomes available, and appliances may be scheduled based on priority, monitored load 235 and allowances for measured dumb load requirements. A diagnostic unit 236 may also be provided that may determine an appliance fault by comparison with historical power measurements. Load devices may be smart and part of the Internet of Things (IoT), or dumb and connected to the system by an adapter if control is required.

Chip pads

A pad driver 53 in an integrated circuit comprises a logic level converter 52 which is stated to be capable of converting a logic signal 40 from the core of the IC to a voltage level suitable for the pad circuit irrespective of whether the pad supply voltage 51 is higher or lower than the core supply voltage 54. The logic level converter receives a voltage supply 56 from a switch 55 which selects the higher of the pad or core voltages. The logic level converter may comprise a potential divider.

System and method for entering and exiting sleep mode in a graphics subsystem

Methods and apparatus to implement communications via a remote terminal unit

Methods and apparatus to implement communications via a remote terminal unit are disclosed. An example apparatus includes a first central processing unit module to be in communication with a host of a process control system. The example apparatus also includes a first rack including a backplane and a plurality of slots. The plurality of slots includes a master slot to receive the first central processing unit module. The backplane communicatively couples the first central processing unit module to at least one of a first communication module or a first input/output (I/O) module inserted in a second one of the slots. The backplane includes a first communication bus for communication of I/O data and a second communication bus for communication of at least one of maintenance data, pass- through data, product information data, archival data, diagnostic data, or setup data. The first communication bus is independent of the second communication bus.

Embedded computing device management

An apparatus (e.g. a smart watch, handheld communications device or personal fitness tracker) comprises at least one processing core and a memory that includes program code configured to cause the apparatus to predict, based on a calendar application, a need for a rich media interface, and to trigger the start-up of a higher-capability processing device (e.g. core) in the apparatus at a time selected based on the prediction. The apparatus my be configured to cause the higher-capability processing device to enter and leave the hibernation state based on a determination by a low-capability processing device (e.g. core) concerning an instruction from outside the apparatus. The low-capacity core may be unable to render the rich media interface and be configured to cause the high capability core to hibernate when it determines that a user interface type not supported by it is no longer requested. The apparatus may be configured to obtain calendar events occurring during the same day, to display ...

Power management of processor cache during processor sleep

A control circuit 30 is configured to transmit a set of operations to a circuit block 18A, which is being powered up after being powered down, in order to reinitialize the circuit block. The circuit block may be a cache coupled to one or more processors 16, and the operations may be connected to configuration registers 56A-D within the cache. The operations may be stored in a memory 60 (e.g. a set of registers) to which the control circuit is coupled. The control circuit is also configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. This allows the circuit block to be powered up or powered down during times that the processors in the system are powered down (and thus software is not executable at the time), without requiring the waking of the processors for the power up/power down event, and therefore conserving power.

Independent power control of processing cores

Computer system, operational method for a microcontroller, and computer program product

A computer system or method to switch the computer from an operating state (e.g. ACPI S0, low power idle) to an off state (e.g. ACPI S5, soft off, standby) wherein when a power button is held for a certain time indicating forced switching (e.g. 4 seconds, hardware shutdown, Step S1), the microcontroller waits so that the computer system is reset (“e.g. it waits for a time period of 1 s so that system components such as a USB controller, a network controller etc of the system are safely reset, step S4). A decision step S1 may check whether the shutdown event corresponds to a power button override (forced shutdown) request or a normal shutdown request (e.g. triggering of a software request within a user interface). In the case of a normal shutdown request, the computer system 1 may be shut down under software control (step S2). A forced switching may interrupt both the supply voltage (Vcc) and the standby voltage (Vaux) in a step S3. Resetting a computer (e.g. resetting wake-up values e.g ...

Controlling transitions of devices between normal state and quiescent state

Increasing power efficiency of turbo mode operation in a processor

In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

Activating an electronic device

An electronic device 101 comprising: a processor 103 having a motion activation mode and an operating mode; an orientation sensor 107 operable to detect the orientation of the device, and a clock 105 configured to, when the processor is in the motion activation mode, periodically power-up the processor; wherein the processor is configured to, when powered-up in its motion activation mode, obtain a measurement of the orientation of the device from the orientation sensor; store the obtained measurement; and process the obtained measurement in dependence on one or more stored measurements of the orientation of the device so as to determine whether the obtained measurement and the one or more stored measurements are indicative of a predetermined sequence of orientations of the device: the processor being configured to transition from its motion activation mode to its operating mode in response to determining that the obtained measurement and the one or more stored measurements are indicative ...

Power control circuitry for controlling power domains

Power strobed digital computer system

For use with a digital computer system utilizing a processing unit having a higher computational capability than required, means for removing power from system components not required to remember computational variables when the processing unit has completed its prescribed tasks.

Feedforward control with intermittent Re-Initalization based on estimated state information

Autonomous core perimeter for low power processor states

An interactive apparatus

An electronics module for a wearable articel, a systemm, and a method of activation of an electronics module for a wearable article

A system 10 comprises a primary controller, a secondary controller coupled to the primary controller and a microphone coupled to the secondary controller. The secondary controller is configured to operate at a lower power than the primary controller. The secondary controller is further configured to: receive incoming voice data input via the microphone, detect the presence of a keyword from the incoming voice data, and in response to the detection of a keyword, transmit a command to the primary controller. The command may be to configure the primary controller to receive and process subsequent incoming voice data from the secondary controller. The secondary controller may be configured to receive the subsequent incoming voice data from the microphone, and to pass on the data to the primary controller after processing them. The system may comprise an electronics module 100 for a wearable article 200 and a user electronic device 300 communicatively coupled to the electronics module, wherein ...

Apparatus for controlling standby power

Apparatus for controlling standby power

DATA PROCESSING CIRCUIT WITH CACHE AND DEVICE WITH SUCH CIRCUIT

SELECTIVE ACTIVATION OF HF-DEVICES

SLEEP CONDITION TRANSITION

INTEGRATED PROCESSOR SYSTEMS FOR PORTABLE INFORMATION DEVICES

CONTROLLING OF THE TEMPORAL ALLOCATION OF DATA PROCESSING ACHIEVEMENT OF A COMPUTER

Terminal control method and apparatus, and terminal

Embodiments of the present invention provide a terminal control method and apparatus, and a terminal. The method includes: when a screen of a terminal is switched from a screen-on state to a screen-off state, detecting whether an enabling condition of a power saving mode is satisfied; and if the enabling condition of the power saving mode is satisfied, performing a power saving operation, where the power saving operation is used to reduce power consumption that occurs when an application program in the terminal runs in a background. In the embodiments of the present invention, power consumption in a screen-off state is reduced as much as possible without affecting normal use of a user. When a screen of a terminal is switched from a screen-on state to a screen-off state, detect whether an enabling condition of a power saving mode is satisfied If the enabling condition of the power saving mode is satisfied, perform a power saving operation, where the power saving operation is used to reduce ...

Portable electronic device having high and low power processors operable in a low power mode

Smart NEMA outlets and associated networks

Adaptive power conservation in storage clusters

Each node and volume in a fixed-content storage cluster makes an independent decision whether to reduce power consumption based on lack of requests from client applications and nodes over a configurable time period. Node configuration parameters and respectively determine how long to wait until idling a node or volume, and how long to wait while idle before again performing integrity checks. A bid value is calculated by each node and reflects how much it will cost for that node to write a file, read a file, or keep a copy of the file. A node with the lowest bid wins, and nodes that are idle have a premium added to each bid to help ensure that idle nodes are kept idle. Normally, nodes with more capacity will submit a lower bid to write a file. In an archive mode, writes bids are reversed meaning that nodes with less capacity submit lower bids, meaning that fuller nodes fill up faster and are then idled, while empty or near empty nodes may remain idle for some time before winning a write ...

System and method for performing power management on a distributed system

POWER SOURCE DEVICE AND COMMUNICATION SYSTEM

Wristband device input using wrist movement

A function of an electronic device can be invoked using a wrist gesture (e.g., flexion or extension) that is detected by a wrist-worn device. The gesture can be detected using sensors in the wrist-worn device, e.g., in the wristband and/or behind a face member. A specific gesture can 5 be identified from a library based on analysis of sensor signals. The invoked function can be executed on the wrist-worn device or another device that is in communication with the wrist worn device.

Electronic device and method for driving camera module in sleep mode

A method for operating an electronic device which is in a first mode is provided. The method includes detecting a grip state of the electronic device, detecting a change in tilt when the detected grip state is equal to or greater than a predetermined value, and switching a mode from the first mode to a second mode when the detected change in tilt is within a set tilt range. 48765101 (GHMallers) P95474 AU 18/1112013 ...

Monitoring and managing processor activity in power save mode of portable electronic device

An electronic device and a method operative therein monitor automatic wakeup events that occur during a power save mode. Wakeup events are monitored for respective applications executable within the electronic device. Applications with 5 processing activity during the power save mode are then listed, on the basis of at least the monitored wakeup events. An indication of which apps are consuming battery power during the power save mode can then be obtained. 48772981 (GHMatters) P95483,AU 18/11/13 C'C Ca2 E3- 0-ca-C C3- c I -c -ccCA ...

Energy management by dynamic functionality partitioning

A sensor and processing system dynamically partitions or allocates functionality between various remote sensor nodes and a processing subsystem based on energy management management considerations. Redundant functionality is located at the processing subsystem and each of the various remote sensor nodes, and each sensor node coordinates with the processing subsystem to determine the location (e.g., at the processing subsystem or at the sensor node) at which a particular functionality is executed.

Communication device, information processing device, and communication method

... [Problem] To provide a communication device, an information processing device, and a communication method. [Solution] A communication device provided with a detection unit for detecting an optical signal and converting the optical signal to an electric signal, a data processing unit for processing the electric signal converted by the detection unit and acquiring data, and a control unit for controlling an operation state on the basis of the optical signal detected by the detection unit, the operation state including a standby state in which the activity of the data processing unit is paused in order to save power consumption and an active state in which the data acquisition state is ready to execute acquisition of data, the detection unit detecting the optical signal in the standby state.

GAME CONSOLE AND MEMORY CARD

... ² A portable, handheld game console includes a ²main body incorporating a first display screen, and a ²cover body incorporating a second display screen. The ²main body is hingedly connected to the cover body along ²adjacent forward and rearward edges, respectively, such ²that the cover body is movable between a closed and open ²positions. The main body is provided with a plurality of ²control buttons and a pair of game card slots for ²receiving game cards of different dimensions. One of the ²game cards is substantially square and comprises a ²substantially flat card body having a plurality of ²electrically conductive terminal strips adjacent the ²forward edge. One of the side edges of the card has a ²single continuous step configuration along substantially ²the entire length dimension of the card. A first notch ²is formed in a first forward corner of the card where the ²forward edge meets the other of the pair of side edges ²and a second notch is formed along the other of the pair ²of side ...

SYSTEM AND METHOD FOR ACTIVATING AN ELECTRONIC DEVICE USING TWO OR MORE SENSORS

The disclosure provides a system and method for activating an electronic device. The activation circuit comprises: a first sensor to monitor for a first condition relating to an environment as affected by a user of the device; a second sensor to monitor for the first condition relating to an environment isolated from effects of the user; and an activation circuit to evaluate signals from the first and second sensors to determine whether to change an activation state of a component on the device. This may involve activating or deactivating the component.

CALCULATOR

SHUTDOWN CONTROL

INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC CELLS

An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.

NEURAL NETWORK PROCESSOR USING COMPRESSION AND DECOMPRESSION OF ACTIVATION DATA TO REDUCE MEMORY BANDWIDTH UTILIZATION

A deep neural network ("DNN") module can compress and decompress neuron-generated activation data to reduce the utilization of memory bus bandwidth. The compression unit can receive an uncompressed chunk of data generated by a neuron in the DNN module. The compression unit generates a mask portion and a data portion of a compressed output chunk. The mask portion encodes the presence and location of the zero and non-zero bytes in the uncompressed chunk of data. The data portion stores truncated non-zero bytes from the uncompressed chunk of data. A decompression unit can receive a compressed chunk of data from memory in the DNN processor or memory of an application host. The decompression unit decompresses the compressed chunk of data using the mask portion and the data portion. This can reduce memory bus utilization, allow a DNN module to complete processing operations more quickly, and reduce power consumption.

UNCREWED AERIAL VEHICLE COMMUNICATION METHOD AND COMMUNICATIONS DEVICE AND SYSTEM

Disclosed by the embodiments of the present application are an unmanned aerial vehicle communication method, device, and system, relating to the technical field of communications, to solve the problem of high failure rate and/or disconnection rate of existing unmanned aerial vehicles during cell handover. The method comprises: a first access network device receiving indication information from a first access and mobility management network element; the first access network device is a device currently providing an access service to an unmanned aerial vehicle; the indication information is used for indicating the access information of the next hop of the unmanned aerial vehicle, the access information comprises information regarding the second access network device and/or information regarding the cell of a second access network device, and the second access network device is used for providing an access service for the next hop of the unmanned aerial vehicle; according to the indication ...

POWER MANAGEMENT INTEGRATED CIRCUIT

ABSTRACT The present invention concerns a power management integrated circuit comprising a reference signal generator, a start-up unit and a supervisory circuit. The supervisory circuit comprises: an electrical resistance circuit connected between a first end node and a second end node; a power supply input; a low reference potential node; a comparator for comparing a reference voltage value at a first input and a divided voltage value at a second input connected to an internal electrical node of the electrical resistance circuit, the comparator being configured to output a monitoring signal. The supervisory circuit further comprises a switch between the second end node and the low reference potential node, this switch being controlled by the start-up unit to selectively close and open based on a detected operational state of the reference signal generator. The present invention has the advantage of reducing power consumption. Date recue/Date Received 2020-08-28 ...

USER-FRIENDLY, NETWORK CONNECTED LEARNING THERMOSTAT AND RELATED SYSTEMS AND METHODS

ON-DEMAND CLOCK SWITCHING

First and second functional circuit blocks (FCBs) control the operation of a clock circuits coupled thereto in dependence upon processing requirements of the FCBs as well as power consumption considerations. When the FCB is not processing data, the clock circuit coupled to that FCB has one of its clock signal frequency reduced or is disabled so that the FCB consumes significantly reduced amounts of electrical power. Through controlling clock frequency and enabling and disabling of the clock circuit, electrical power consumption of the FCB is advantageously reduced.

SYSTEM AND METHOD FOR MANAGE AND CONTROL NEAR FIELD COMMUNICATION FOR A MOBILE MULTIFUNCTIONAL DEVICE WHEN THE DEVICE IS UNCHARGED OR ONLY PARTIALLY CHARGED

The invention refers to a mobile electronic multifunctional device providing at least an interface for at least one first functionality and an interface to a near field communication (NFC) functionality, said device comprising a component providing an interface to said first functionality, and an interface to an NFC-communication component providing said NFC-communication functionality, a battery interface, a battery control circuit, connected to said battery interface, wherein said battery control circuit is provided to control the operation of said mobile electronic multifunctional device in accordance with a battery charging condition of a battery connected to said battery interface, wherein said battery control circuit provides a number of operating conditions for said mobile electronic multifunctional device in accordance with the charging condition of a battery connected to said battery interface, said charging condition including two or more operating conditions from the selection ...

SYSTEM AND METHOD FOR MANAGE AND CONTROL NEAR FIELD COMMUNICATION FOR A MOBILE MULTIFUNCTIONAL DEVICE WHEN THE DEVICE IS UNCHARGED OR ONLY PARTIALLY CHARGED

The invention refers to a mobile electronic multifunctional device providing at least an interface for at least one first functionality and an interface to a near field communication (NFC) functionality, said device comprising a component providing an interface to said first functionality, and an interface to an NFC-communication component providing said NFC-communication functionality, a battery interface, a battery control circuit, connected to said battery interface, wherein said battery control circuit is provided to control the operation of said mobile electronic multifunctional device in accordance with a battery charging condition of a battery connected to said battery interface, wherein said battery control circuit provides a number of operating conditions for said mobile electronic multifunctional device in accordance with the charging condition of a battery connected to said battery interface, said charging condition including two or more operating conditions from the selection ...

POWER SOURCING EQUIPMENT CHIP, AND POWER OVER ETHERNET DEVICE AND METHOD

A power souring equipment (PSE) chip, power over Ethernet (PoE) equipment and method, the method being capable of determining the access situation of a powered device (PD) of a corresponding terminal when powering with four cable pairs. PSE chip comprises a channel controller, a first channel detector and a second channel detector; the channel controller transmits a first detection voltage along a first group of cable pair in Ethernet twisted-pair cables via the first channel detector, and transmits a second detection voltage along a second group of cable pair in Ethernet twisted-pair cables via the second channel detector; and determining a first impedance according to the current detected by the first detection voltage and the first channel detector, and determining a second impedance according to the current detected by the second detection voltage and the second channel detector; and determining the first group of cable pair connected to an effective PD when the first impedance is within ...

SYSTEM AND METHOD FOR SAVING DATA IN RESPONSE TO OPEN AND CLOSE EVENTS IN A MOBILE COMMUNICATION DEVICE

A method for automatically saving data in a wireless device is provided. The wireless device has a sensor connected to a processor and a memory connected to the processor. The sensor provides an open signal to the processor indicating an open event when the wireless device is opened and providing a close signal to the processor indicating a close event when the wireless device is closed. The method includes detecting occurrence of the close event while data is being entered in an application; saving the data in the memory; creating and saving a notification in the memory that the data is saved; linking the notification to the saved data; and displaying the saved notification on a primary display screen of the wireless device.

SYSTEM AND METHOD FOR AUTOMATICALLY POWERING ON AND SYNCHRONIZING A WIRELESS REMOTE CONSOLE TO A CENTRAL CONTROL UNIT SO AS TO ALLOW REMOTE CONTROL OF A MEDICAL DEVICE

A system and method for controlling one or more medical devices by a remote console. The remote console communicates wirelessly with a central control unit that connects to one or more of the medical devices. To conserve battery power and simplify operation, the remote console is configured to automatically power on and initiate a wireless connection in response to being brought into proximity of the central control unit. According to another embodiment, the remote console automatically powers on and terminates any previously established wireless connections when brought into proximity of the central control unit.

SYSTEM AND METHOD FOR FORCING DATA CENTER POWER CONSUMPTION TO SPECIFIC LEVELS BY DYNAMICALLY ADJUSTING EQUIPMENT UTILIZATION

A system and method for forcing data center power consumption to specific levels by dynamically adjusting equipment utilization are provided.

User Interface for Easily Setting Computer Speaker Volume and Power Conservation Levels

COMPUTER POWER MANAGEMENT SYSTEM

A low power management system including both hardware and software is provided for a battery powered portable computer (not shown). The low power management system powers down various sections of the computer (DMA, VCO, DISPLAY, UART) when they are not used. The low power management system is controlled by a control program directing the microprocessor of the computer, and includes the capability to turn off clock signals (not shown) to the various sections of the computer based upon demand. Also included is the capability to turn on clock signals based upon demand. The low power management system also includes the capability to turn on the computer upon a press of a key on the computer keyboard. The low power management system monitors software application programs for keyboard activity so as to turn off the microprocessor in the computer in response to a loop looking for a keypress and certain other loops which can be monitored without use of the microprocessor.

Control module used especially in large microprocessors such as Digital Signal Processors, has arrangement which enables lower power consumption

The control module (1) includes the following elements, a dead Read-only-memory (ROM) (2), a temporary memory (6), to which the data in the ROM is to be transferred in order to be accessible from the exterior of the control module, a reading controller (3), for selecting from each reading cycle, the portions of this ROM transferred to the temporary memory. The portions selected by the reading controller, depends on the contents of this Read-only-memory.

УСТРОЙСТВО ДЛЯ РЕГУЛИРОВАНИЯ НАПРЯЖЕНИЯ ПИТАНИЯ ЭЛЕМЕНТОВ КОМПЬЮТЕРНОЙ СИСТЕМЫ В РЕЖИМЕ ОЖИДАНИЯ

В заявке описано устройство для регулирования напряжения питания элементов компьютерной системы в режиме ожидания, включающее блок питания, устройство сопряжения, служащее средством передачи сигнала, поступающего из блока контроля/управления, терминал ввода-вывода, передающий микропроцессору входные сигналы, поступающие от мыши и клавиатуры, детектор индивидуальной нагрузки, определяющий нагрузку периферийного устройства на основании получаемой информации о состоянии использования блока питания, датчик, определяющий присутствие или отсутствие пользователя, микропроцессор, переключающий коммутационное устройство согласно принимаемым сигналам с первого по третий и регулирующий напряжение источника питания, генерируемое в разъемах, генератор сигналов раздельного управления, генерирующий сигнал управления, включающий или выключающий переключатели коммутационного устройства, и блок контроля/управления, передающий микропроцессору сигнал команды регулирования питания и предоставляющий пользователю ...

Power-saving system and control method for the same

The accessibility of the assembly

Hybrid mobile terminal and method for controlling the same

Method And Apparatus For A Power-Efficient Framework to Maintain Data Synchronization of a Mobile Personal Computer to Simulate A Connected Scenario

An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed.

Information processing apparatus and power supply control circuit

Provided is an information processing apparatus including: a power supply control portion that performs control of a power supply; a detection signal emitting portion that, when a connection of an external power source is detected in an operation stand-by state in which power consumption is suppressed and an operation is on stand-by, emits a detection signal only for a certain time period, in accordance with the detection; and a power supply portion that supplies power to the power supply control portion based on the detection signal emitted by the detection signal emitting portion and also stops the power supply to the power supply control portion after a certain time period elapses from the connection in the operation stand-by state.

Semiconductor integrated circuit

In a semiconductor LSI that sequentially performs predetermined processing on data input successively, a host CPU, a plurality of sequencers, and a data engine are connected in a hierarchical manner with the host CPU at top and the data engine at bottom. Each sequencer includes a memory that stores a parameter for execution of the sequencer, a memory controller, a loop counter, a sequence controller, and an interface unit that handles transmission and reception of signals with an external unit of the sequencer. The interface units of the plurality of sequencers have the same specifications.

Multi-Port Interface Circuit and Associated Power Saving Method

In one aspect, a multi-port interface circuit applied to a playback apparatus which is able to switch among a plurality of input ports coupled to a plurality of source devices for playing back. Each input port has a receiver, the receiver including a front-end for receiving and processing a data stream from the source device and providing a data enable signal, and further including a content protection circuit for performing content protection according to the data enable signal. Each receiver records data enable information associated with the data enable signal of the data stream in an initial status. When one input port is selected, receivers of the other input ports operate in a power saving mode, the front-end circuits stop receiving the data stream, and the content protection circuit maintains operation according to a regenerated enable signal, which is regenerated according to the data enable information.

Semiconductor integrated circuit

A constantly power-ON domain and a standby-time power OFF domain are included on the same chip, and the constantly power-ON domain includes: a shutoff control circuit shutting off a signal inputted and outputted between the constantly power-ON domain and the standby-time power OFF domain when the first power source is ON and the second power source is OFF; and a shutoff control circuit outputting a first control signal indicating that shutoff of an emergent shutoff control circuit unit is to be enabled or disabled, the standby-time power OFF domain includes the emergent shutoff control circuit unit shutting off, based on the first control signal from the shutoff control circuit, the signal inputted between the emergent shutoff control circuit unit and the constantly power-ON domain.

Information processing apparatus and power supply control method

According to one embodiment, an information processing apparatus includes: an optical disk apparatus; a receiver which receives a command indicating that a tray provided in the optical disc apparatus is ejected; a power supply module which supplies electric-power to each of modules of the information processing apparatus; and a power supply controller which controls supply of electric-power to each of the modules from the power supply module. When the supply of electric-power to each of the modules is stopped, the power supply controller continues the supply of electric-power to the optical disc apparatus during a certain time. When the power supply controller receives the command within the certain time, the power supply controller ejects the tray and stops the supply of electric-power to the optical disc apparatus.

Smart nema outlets and associated networks

A control system ( 300 ) allows standard NEMA receptacles to be remotely monitored and/or controlled, for example, to intelligently execute blackouts or brownouts or to otherwise remotely control electrical appliances. The system ( 300 ) includes a number of smart receptacles ( 302 ) that communicate with a local controller ( 304 ), e.g., via power lines using the TCP/IP protocol. The local controller ( 304 ), in turn, communicates with a remote controller ( 308 ) via the internet.

Image forming apparatus and power control method thereof

An image forming apparatus and a power control method thereof are provided. The image forming apparatus includes: an image forming unit which forms an image; a power supply which supplies operating power for the image forming apparatus; a switching circuit unit which switches to selectively supply the operating power; a memory unit which stores information about power status of the switching circuit unit; and a controller which outputs a power control signal for controlling a switching operation of the switching circuit unit in accordance with the information about the power status stored in the memory unit if power is abnormally shut off and then supplied again from the power supply to the switching circuit unit. With this, the image forming apparatus operates in a last power status, so that power can be prevented from being wastefully consumed or data can be prevented from being lost.

Usb hub and power management method thereof

A USB HUB is provided. The USB HUB comprises a wireless communication module, a storage module, a USB interface connected to a host outside of the USB HUB and a HUB controller. The storage module stores a driver program of the wireless communication module. The USB interface transfers data with the host. The HUB controller is coupled to the USB interface, the wireless communication module and the storage module. The HUB controller disables the storage module and enables the wireless communication module when the driver program has been installed in the host.

Electronic device and power management method thereof

A method for managing power of an electronic device receives a power signal of a peripheral device of the electronic device, determines if a data signal of the peripheral device is received at a preset time interval, and sends a time record command to a timer of the electronic device if the data signal is not received to obtain a recorded time of the electronic device. The method further displays an idle status of the peripheral device if the recorded time is greater than a first preset value, and stops supplying power to the peripheral device if the recorded time is greater than a second preset value.

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Method and apparatus for cost and power efficient, scalable operating system independent services

A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

Systems for remotely waking up application processor of mobile device

Systems for waking up an application processor (AP) of a mobile device are disclosed. In one embodiment, one of the systems of the mobile device includes a Bluetooth device with Bluetooth Low Energy (BLE) feature configured to receive a connection request signal from an external device and a hardware module coupled to the Bluetooth device with BLE feature. The hardware module is configured to forward an AP ON request signal received from the external device via the Bluetooth device with BLE feature if the pairing request signal is determined to be valid, and wherein the Bluetooth device with BLE feature and the hardware module are supplied with quiescent current from a battery of the mobile device prior to the wake up of the AP.

Wireless charging of mobile device

Systems, circuits, and devices for wirelessly charging a mobile device are disclosed. In one embodiment, a system of a mobile device comprises a low power PAN module and a controller for the low power PAN module configured to monitor a connection request signal communicated from an external device while the mobile device is in a sleep mode, where the controller is supplied with quiescent current from a battery of the mobile device during the sleep mode. In addition, the system comprises an AP of the mobile device configured to wake up from the sleep mode when the connection request signal is validated by the controller, forward to the external device an equipment identity data of the mobile device and a charging status of the battery, and charge the battery of the mobile device with energy received from a wireless charging module associated with the external device.

Information processing apparatus and method of controlling the same

A first nonvolatile storage device has a higher access speed in a continuous access than a random access and a second nonvolatile storage device has a higher access speed in the random access than the continuous access. The information processing apparatus selects a first storage method in which an amount of continuous data is larger than an amount of random data if data stored in a volatile storage device is saved in the first nonvolatile storage device, and selects a second storage method in which an amount of random data is larger than an amount of continuous data if the data stored in the volatile storage device is saved in the second nonvolatile storage device, and saves the data stored in the volatile storage device into the specified nonvolatile storage device using the selected storage method when a predetermined condition is satisfied.

Data processing unit with multi-graphic controller and method for processing data using the same

A portable terminal that includes a first processing core configured to process data; a second processing core, which is faster than the first processing core, configured to process the data; and a storage unit configured to store multimedia data. The first and second processing cores are integrated into a single chipset, and are configured to be individually enabled or disabled based on a workload. The portable terminal is configured to be operated in one of a standby state and an operating state, to play back the multimedia data stored in the storage unit, and for Internet access.

Controller and program product

According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit.

Information processing apparatus and judging method

According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor.

Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack

Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

Semiconductor system, semiconductor device, and electronic device initializing method

According to one embodiment of the present disclosure, a semiconductor system may be disclosed. The semiconductor system according to the one embodiment may include, for example, a plurality of electronic devices and a host apparatus. The host apparatus may simultaneously initialize the plurality of electronic devices in units of group.

Mobile electronic device, control method and storage medium storing control program

According to an aspect, a mobile electronic device includes a first and a second display unit, a first and a second operation detection unit, and a control unit. The first and the second display unit display a first and second operation screen respectively. The first and the second operation detection unit detect an operation for the first and second display unit respectively. The control unit performs a switching control to switch between a first state and a second state. In the first state, a display of the second display unit is deactivated and an operation detected by the second operation detection unit is processed as an operation for the first operation screen. In the second state in, a display of the first display unit is deactivated and an operation detected by the first operation detection unit is processed as an operation for the second operation screen.

Method and apparatus for saving power by efficiently disabling ways for a set-associative cache

A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events

In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Selective rf device activation

Systems and methods for activating one or more devices are disclosed. According to one embodiment, the device listens for an activate code, the activate code having a length field and a mask field, the mask field including a mask value, the length field specifying a length of the mask field to a final bit of the mask value. Upon receiving the activate code, the length field is compared to a stored length value for determining whether the length field meets a predefined criterion. If the length field meets the predefined criterion, an address of the activate value is loaded (if an address field is present) and the appropriate bits (mask value) of the mask field are compared to a stored activate value. An activate signal is generated if the mask value matches the stored activate value. The activate signal can be used to activate additional circuitry including the entire device.

Electronic device enabled to decrease power consumption

An electronic device includes an input interface receiving a power signal, a voltage conversion unit converting the power signal into a voltage signal, a processing unit receiving the voltage signal to operate normally, a load unit, and a control unit electrically connected to the processing unit, the voltage conversion unit and the load unit. The processing unit detects whether the load unit stops operating. In response to the processing unit detecting that the load unit stops operating, the processing unit controls the control unit to cut off an electrical connection between the voltage conversion unit and the load unit, and thereby the voltage conversion unit stops providing the voltage signal to the load unit.

Adaptive Power Management

Disclosed are various embodiments of adaptive management of a device. The adaptive management includes, e.g., power management, energy management, and diagnostics. In one embodiment, a device including a power management unit (PMU) communicatively coupled to a processor is configured to transmit a status notification to the processor in response to an interrupt signal; obtain a high level state command from the processor in response to the status notification, and modify power operation of the device in response to the high level state command. In another embodiment, a method for charging a power source includes obtaining, by a PMU of a device, operational characteristics of a power supply in communication with the device; determining a power supply type based at least in part upon the operational characteristics; and controlling charging of the power source based at least in part upon the power supply type.

Semiconductor device, radio communication terminal using same, and clock frequency control method

A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU 0 ) that operates according to the clock signal, a storage circuit (e.g., IC 0 ) that is activated according to access from the arithmetic circuit CPU 0 , a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU 0 to the storage circuit IC 0 , and when the number of accesses increases, outputs a request signal (e.g., psreq 1 ), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq 1.

Method and system for reducing thermal load by forced power collapse

A system and method for reducing heat in a portable computing device includes clocking a processor such that it is provided with a full frequency over time t 0 to t 1 . A timer is set to trigger a forced power collapse (“FPC”) that removes all power to the processor from time t 1 to time t 2 . At time t 2 , the processor may be awakened such that it can resume processing at the full frequency. Advantageously, during the FPC, no leakage power (“P L ”) is consumed by the processor between t 1 and t 2 . The result is that the processor averages the same processing efficiency over time t 0 to t 2 as it otherwise would have if a reduced frequency had been provided to it. However, because no P L was consumed during the FPC, the generation of heat between time t 1 and t 2 that is related to P L is avoided.

System and method for entering and exiting sleep mode in a graphics subsystem

A technique is disclosed for a graphics processing unit (GPU) to enter and exit a power saving deep sleep mode. The technique involves preserving processing state within local memory by configuring the local memory to operate in a self-refresh mode while the GPU is powered off for deep sleep. An interface circuit coupled to the local memory is configured to prevent spurious GPU signals from disrupting proper self-refresh of the local memory. Spurious GPU signals may result from GPU power down and GPU power up events associated with the GPU entering and exiting the deep sleep mode.

Router and chip circuit

Routers in a data transfer system relay data between the first node and each of the second nodes. A router includes a load value processing section and an aggregation decision section. The load value processing section obtains information about a load value of another router connected to a communications bus. The load value is a time delay caused by that another router and/or the throughput of that router. The aggregation decision section chooses one of the second nodes at which the data is to be received, and determines a transmission path between the second node chosen and the first node in accordance with information about the load value obtained from each router and information determined during a design process about the number of stages of routers from the first node through each said second node and/or the length of data to be transferred.

Information processing apparatus, computer-readable recording medium, and method for controlling information

An information processing apparatus includes a processor that executes a plurality of application programs, a display that displays results of the execution of the plurality of application programs, and a storage that stores a first table in which the plurality of application programs and a plurality of pieces of operation information corresponding to the plurality of application programs are associated with each other and recorded, and a second table in which the plurality of application programs and order determined on the basis of power to be consumed by the processing unit to execute the plurality of application programs are associated with each other and recorded.

Method and Apparatus for User-Activity-Based Dynamic Power Management and Policy Creation for Mobile Platforms

A method and apparatus for user activity-based dynamic power management and policy creation for mobile platforms are described. In one embodiment, the method includes the monitoring of one or more sensor values of a mobile platform device to gather sensor activity data. Once the sensor activity data is gathered, the user state may be predicted according to the gathered user activity and an updated user state model. In one embodiment, the user state model is updated according to the sensor activity data. In one embodiment, a switch occurs from the present power management policy to a new power management policy if the new user state differs from a present user state by a predetermined amount. In one embodiment, at least one time-out parameter of a selected power management policy may be adjusted to comply with a predicted user state. Other embodiments are described and claimed.

Server cluster and control mechanism thereof

A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node performs an operation system and respectively includes a network port, a network chip and a south bridge chip. The network port is connected to the network switch via a cable. The network chip outputs a power-off signal according to a received power-off packet after the network switch is started. The south bridge chip outputs a shutdown signal to shut down the server node according to the power-off signal when the server node is turned on and the operation system is working normally.

Memory unit, information processing device, and method

A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit.

Integrating sensing systems into thermostat housing in manners facilitating compact and visually pleasing physical characteristics thereof

An occupancy sensing electronic thermostat is described that includes a thermostat body having a curved exterior front surface, a dot matrix display mounted within the body viewable by a user in front of the front surface, a passive infrared sensor for measuring infrared energy and a shaped Fresnel lens having a smooth outer surface that extends across only a portion of the exterior front surface of the thermostat body. The Fresnel lens is shaped and curved so as to conform to and form a part of the curved exterior front surface of the thermostat body. A second downwardly directed passive infrared sensor can also be provided to aid in the detection of an approaching user who intends to interact with the thermostat.

Controlling A Turbo Mode Frequency Of A Processor

In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

Microprocessor based power management system architecture

An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be independently powered. The power control manager includes a set of control registers storing individual control bits, a power switch for each power domain and a programmable microprocessor. The programmable microprocessor controls the digital state of individual bits within the control registers thereby controlling the ON and OFF state of the corresponding power domain.

METHOD, SYSTEM AND APPARATUS FOR LOW-POWER STORAGE OF PROCESSOR CONTEXT INFORMATION

A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core. 1. A method comprising:detecting an indication of a first power state transition of a first power domain including a processor core;in response to the detecting the indication of the power state transition, determining whether the power state transition includes a transition to a first power state of a plurality of power states of the first power domain; and saving a context information of the processor core in a first context storage external to the first power domain, else', 'if the power state transition of the processor core is determined to not include the transition to the first power state, then saving the context information of the processor core in a second context storage within the processor core., 'if the power state transition of the processor core is determined to include the transition to the first power state, then'}2. The method of claim 1 , wherein the first power state includes a state in which the processor core is powered down.3. The method of claim 1 , wherein the first context storage and the second context storage include a static random access memory (SRAM).4. The method of claim 1 , wherein saving the context information of the processor core in the first context storage includes:saving the context information of the processor core to the second context storage, and copying the context ...

Method, Apparatus and System for Device Management

A method, apparatus and system for managing a device are provided by the present invention, which relate to the field of communication. The method includes: according to a preset power management rule, determining a power supply policy of each single board in the current device (); and according to the power supply policy, performing power management on each single board (). The technical scheme provided by the present invention is applied to the power management of a device with multiple single boards, and the problem of serious energy consumption in redundancy backup is solved. 1. A method for managing a device comprising:determining a power supply policy of each single board in the device according to a preset power management rule;performing power management on each single board according to the power supply policy.2. The method for managing the device according to claim 1 , wherein claim 1 , the single board comprises a line card and a standby master control board claim 1 , and the step of determining a power supply policy of each single board in the device according to a preset power management rule comprises:a master control board monitoring a current operating state of the device, and determining the power supply policy of each single board in the device according to the preset power management rule;the step of performing power management on each single board according to the power supply policy comprises:the master control board distributing the power supply policy of each single board to a corresponding single board respectively;each single board executing a corresponding operation according to the power supply policy.3. The method for managing the device according to claim 1 , wherein claim 1 , the step of determining a power supply policy of each single board in the device according to a preset power management rule comprises:the master control board monitoring and informing each single board in the device of the current operating state of the device; ...

ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING

An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops. 1. An electronic circuit , comprising:a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode;a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode;a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; anda recovery circuit, coupled to a memory module and to the state flip-flops, said recovery circuit is arranged to ...

Modular integrated circuit with uniform address mapping

A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

COMPUTER AND CONTROL METHOD THEREOF

A computer includes a CPU and a system unit, and further includes a power source which generates source power, a system driving power generator which converts the source power to system power and which provides power to the system unit, a CPU driving power generator which outputs driving power to drive the CPU, and a controller which selectively supplies the source power or the system power to an input terminal of the CPU driving power generator according to an operation mode of the CPU. Thus, a computer adjusts a level of power supplied to a CPU driving power generator according to a CPU mode and improves power efficiency, and includes a control method thereof. 1. A computer comprising a CPU and a system unit , further comprising:a power source which generates source power;a system driving power generator which converts the source power to system power and which provides power to the system unit;a CPU driving power generator which outputs driving power to drive the CPU; anda controller which selectively supplies the source power or the system power to an input terminal of the CPU driving power generator according to an operation mode of the CPU.2. The computer according to claim 1 , wherein the operation mode of the CPU comprises a normal mode and a power saving mode claim 1 , and the controller supplies the system power to the input terminal of the CPU driving power generator when the CPU operates in the power saving mode.3. The computer according to claim 2 , wherein the controller supplies the source power to the input terminal of the CPU driving power generator when the CPU operates in the normal mode.4. The computer according to claim 3 , wherein the controller comprises:a first switch which supplies source power to the CPU driving power generator when the first switch is switched on; anda second switch which supplies system power to the CPU driving power generator when the second switch is switched on.5. The computer according to claim 4 , wherein the CPU ...

METHODS FOR OPERATING AN APPARATUS HAVING MULTIPLE STAND-BY MODES

A method for operating an apparatus, such as a video signal receiver, having first and second stand-by modes when the apparatus is in an off state, wherein the first stand-by mode provides a different start-up time and consumes a different amount of power than the second stand-by mode, is capable of saving power without requiring a user to wait a long time for a start-up sequence. According to an exemplary embodiment, the method includes enabling display of a user interface allowing user selections for a plurality of different time periods of a day; and enabling a user to select, via the user interface, one of at least three different options for each one of the different time periods, wherein a first one of the options includes setting the apparatus to the first stand-by mode for the time period, a second one of the options includes setting the apparatus to the second stand-by mode for the time period, and a third one of the options includes setting the apparatus to a statistical mode for the time period, wherein the statistical mode includes setting the apparatus to one of the first and second stand-by modes for the time period based on a user's past viewing habits during the time period. 18-. (canceled)9. An apparatus having first and second stand-by modes when in an off state , wherein said first stand-by mode consumes a different amount of power than said second stand-by mode , said apparatus comprising:means for enabling a user to select one of at least three different options for each one of a plurality of different time periods of a day, wherein a first one of said options includes setting said apparatus to said first stand-by mode for said time period, a second one of said options includes setting said apparatus to said second stand-by mode for said time period, and a third one of said options includes setting said apparatus to a statistical mode for said time period, wherein said statistical mode includes setting said apparatus to one of said first and ...

Power management in multiple processor system

Power management for a processing system that has multiple processing units, (e.g., multiple graphics processing units (GPUs), is described herein. The processing system includes a power manager that obtains performance, power, operational or environmental data from a power management unit associated with each processor (e.g., GPU). The power manager determines, for example, an average value with respect to at least one of the performance, power, operational or environmental data. If the average value is below a predetermined threshold for a predetermined amount of time, then the power manager notifies a configuration manager to alter the number of active processors (e.g., GPUs), if possible. The power may then be distributed among the remaining GPUs or other processors, if beneficial for the operating and environmental conditions.

IMAGE PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND STORAGE MEDIUM

A second control unit in an image processing apparatus receives a packet transmitted from an external apparatus, copies and stores the received packet, analyzes the header of the received packet, deletes the analyzed header, and, when transitioning the image processing apparatus from a second power mode to a first power mode based on the result of analysis in the case where the image processing apparatus is in the second power mode, transitions the image processing apparatus from the second power mode to the first power mode, and transfers to the first control unit the received packet that was stored and does not transfer to the first control unit the received packet from which the header was deleted. 1. An image processing apparatus capable of operating in any of a first power mode in which power is supplied to both a first control unit and a second control unit , and a second power mode in which power is supplied to the second control unit and is not supplied to the first control unit , the second control unit comprising:receiving means for receiving a packet transmitted from an external apparatus;storage means for copying and storing the packet received by the receiving means;analysis means for analyzing a header of the packet received by the receiving means, and deleting the analyzed header;determination means for, in a case where the image processing apparatus is in the second power mode, determining whether to transition the image processing apparatus from the second power mode to the first power mode based on a result of the analysis by the analysis means; andprocessing means for, in a case where it is determined by the determination means to transition the image processing apparatus from the second power mode to the first power mode, transitioning the image processing apparatus from the second power mode to the first power mode, and transferring to the first control unit the received packet stored by the storage means and not transferring to the first ...

Systems and methods of performing a data save operation

A method includes entering a hibernation mode in a data storage device with a controller, a non-volatile memory, and a volatile memory having a first portion and a second portion. The hibernation mode is entered by copying, to the second portion, data that is in the first portion and that is flagged to remain available at the volatile memory during the hibernation mode, and powering off the first portion while maintaining power to the second portion.

Systems and Methods for Decimation Based Over-Current Control

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active.

Control method, control device and terminal

A control method, a control apparatus and a terminal are provided according to embodiments of the present invention. The method includes: receiving a trigger event; determining from the trigger event whether the terminal enters a limited operation mode in which at least one component of the terminal is unusable; generating a first control instruction when it is determined that the terminal enters the limited operation mode; and controlling to turn off power supply to the at least one component terminal according to the first control instruction. With the present invention, it is possible to switch the terminal system between a limited operation mode and a normal operation mode in terms of hardware, thereby saving power and satisfying the low-carbon environmental preservation requirements.

ELECTRONIC SYSTEM WITH POWER SAVING FUNCTION

The present invention provides an electronic system with power saving function. In a first embodiment, the electronic system comprises a processing unit and a storage device. The storage device has a transmission interface, and the storage device is coupled to the processing unit via the transmission interface, wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the transmission interface. In a second embodiment, the electronic system comprises a processing unit and a storage device. The storage device has a transmission interface and an independent signal pin, and the storage device is coupled to the processing unit via the transmission interface and the independent signal pin, wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the independent signal pin. 1. An electronic system with power saving function , comprising:a processing unit; anda storage device, having a transmission interface, and the storage device being coupled to the processing unit via the transmission interface;wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the transmission interface.2. The electronic system of claim 1 , wherein the processing unit turns off power supply of the storage device completely via a specific signal pin of the transmission interface.3. The electronic system of claim 1 , wherein the electronic system is a PC claim 1 , a notebook computer claim 1 , an embedded computer claim 1 , or a tablet computer claim 1 , and the storage device is a Solid State Drive (SSD).4. The electronic system of claim 1 , wherein the transmission interface is a Serial Advanced Technology Attachment (SATA) interface or a Peripheral Component Interconnect Express (PCI-E) interface.5. An electronic system with ...

User Generated Data Center Power Savings

Technologies are described herein for providing power savings in a data center. Some example technologies may identify some user-provided hardware independent power saving codes from multiple virtual machines within the data center. The technologies may convert at least a portion of the user-provided hardware independent power saving codes into a device power management message specific to a computing system in the data center. The technologies may provide the device power management message to the computing system. The computing system may be configured to enable or disable one or more devices within the computing system according to the device power management message. 1. A method for providing power savings in a data center , the method comprising:identifying a plurality of user-provided hardware independent power saving codes from multiple virtual machines within the data center;converting at least a portion of the plurality of user-provided hardware independent power saving codes into a device power management message specific to a computing system in the data center; andproviding the device power management message to the computing system, wherein the computing system is configured to enable or disable one or more devices within the computing system according to the device power management message.2. The method of claim 1 , further comprising:converting a second portion of the plurality of power saving codes into a second device power management message specific to a second computing system in the data center; andproviding the second device power management message to the second computing system, wherein the second computing system is configured to enable or disable one or more devices within the second computing system according to the second device power management message.3. The method of claim 1 , wherein identifying the plurality of user-provided hardware independent power saving codes comprises:providing an application programming interface adapted to ...

SEMICONDUCTOR DEVICE

To individually control supply of the power supply voltage to circuits, a semiconductor device includes a CPU, a memory that reads and writes data used in arithmetic operation of the CPU, a signal processing circuit that generates an output signal by converting a data signal generated by the arithmetic operation of the CPU, a first power supply control switch that controls supply of the power supply voltage to the CPU, a second power supply control switch that controls supply of the power supply voltage to the memory, a third power supply control switch that controls supply of the power supply voltage to the signal processing circuit, and a controller that at least has a function of controlling the first to third power supply control switches individually in accordance with an input signal and instruction signals input from the CPU and the signal processing circuit. 1. A semiconductor device comprising:a CPU electrically connected to a first switch;a memory electrically connected to a second switch;a signal processing circuit electrically connected to a third switch; anda controller.wherein the signal processing circuit is configured to convert an operation data signal of the CPU,wherein each of the first switch, the second switch, and the third switch is electrically connected to a power supply line, andwherein the controller is configured to control the first switch, the second switch, and the third switch.2. The semiconductor device according to claim 1 ,wherein the CPU is configured to output a first signal which is input to the controller, andwherein the controller controls the first switch in accordance with the first signal.3. The semiconductor device according to claim 1 ,wherein the signal processing circuit is configured to output a second signal which is input to the controller, andwherein the controller controls the third switch in accordance with the second signal.4. The semiconductor device according to claim 1 ,wherein the memory includes a field- ...

INFORMATION PROCESSING APPARATUS, POWER-SAVE CONTROL METHOD, AND POWER-SAVE CONTROL PROGRAM

An information processing apparatus includes a main storage unit and a primary computing unit. When a power-save mode is set, power supply to the main storage unit is being continued while power supply to the primary computing unit is stopped. The primary computing unit includes an operation status information processing unit to store operation status information of the primary computing unit when shifting to the power-save mode; a storing destination information processing unit to store storing-destination information indicating a storage area of the operation status information; a power-supply stop control unit to stop power supply to the primary computing unit after storing the operation status information and storing-destination information; a return operation identifying unit to confirm return operation identification information and to initialize the primary computing unit after power supply to the primary computing unit is resumed; and an operation status restoring unit to read the operation status information. 1. An information processing apparatus comprising:a main storage unit;a primary computing unit, using a processing device, when a power-save mode is set for the information processing apparatus, power supply to the main storage unit being continued while power supply to the primary computing unit is stopped;an operation status information processing unit, using the primary computing unit, to store operation status information indicating operation status of the primary computing unit in the main storage unit when shifting to the power-save mode;a storing destination information processing unit, using the primary computing unit, to store storing-destination information indicating a storage area of the operation status information in the main storage unit to a secondary storage unit different from the main storage unit;a power-supply stop control unit, using the primary computing unit, to stop power supply to the primary computing unit after storing the ...

Power control module

A control module ( 12 ) for a battery-powered data gathering apparatus ( 10 ) in which a microcontroller ( 18 ) selectively activates and deactivates components in the apparatus in a power saving manner. By controlling power consumption, the control module may maximise the working lifetime of the cell ( 14 ) (e.g. battery) which provides power. In one aspect, the microcontroller is operable as a host controller for a USB cellular modem, whereby the control module enables a conventional cell to power periodic communications from a USB cellular modem. The microcontroller activates the USB interface only when it is required, thereby closely controlling power consumed by the USB interface and its corresponding connected device.

INFORMATION PROCESSING APPARATUS THAT PERFORMS USER AUTHENTICATION, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM

An information processing apparatus that improves the convenience of a user who performs authentication using an authentication medium. A communication system module acquires authentication information from an IC card. A sensor system module detects proximity of the IC card. A main circuit element group authenticates a user using the acquired authentication information. A power supply controller supplies power to those modules and the group. A power supply destination is controlled such that the apparatus is shifted to a power saving state in which power is supplied only to the sensor system module. In the power saving state, when the sensor system module detects proximity of the IC card, the power supply destination is controlled to cause the apparatus to shift to a normal power state in which power is supplied to the communication system module and the main circuit element group. 1. An information processing apparatus comprising:an acquisition unit configured to acquire authentication information from an authentication medium for use in authentication of a user;a detection unit configured to detect the authentication medium;a power supply unit configured to supply power to said acquisition unit and said detection unit; anda power control unit configured to control a power supply destination to which power is supplied from said power supply unit such that the information processing apparatus is shifted to a power saving state in which power is supplied to said detection unit, and the power supply to said acquisition unit is shut off,wherein in the power saving state of the information processing apparatus, when the authentication medium is detected by said detection unit, said power control unit controls the power supply destination to which power is supplied from said power supply unit such that the information processing apparatus is shifted to a normal power state in which power is supplied to said acquisition unit.2. The information processing apparatus ...

ELECTRONIC DEVICE, IMAGE PROCESSING APPARATUS, AND DEVICE CONTROL METHOD

According to an embodiment, provided is an electronic device that includes: an energy generation unit that generates electrical power; an accumulating unit that accumulates therein the electrical power generated by the energy generation unit; and a network control unit that includes: a first function unit that performs network response processing; a second function unit that performs network response processing with a relatively smaller processing load than the network response processing performed by the first function unit; and a third function unit that controls the electrical power supply to the function units. The third function unit stops the electrical power supply to the first function unit in a predetermined standby operation mode that is standby for a network response request, and supplies the electrical power to the second function unit directly from the energy generation unit bypassing the accumulating unit. 1. An electronic device comprising:an energy generation unit that generates electrical power;an accumulating unit that accumulates therein the electrical power generated by the energy generation unit; and a first function unit that performs network response processing;', 'a second function unit that performs network response processing with a relatively smaller processing load than the network response processing performed by the first function unit; and', 'a third function unit that controls the electrical power supply to the function units, wherein, 'a network control unit that comprises stops the electrical power supply to the first function unit in a predetermined standby operation mode that is standby for a network response request, and', 'supplies the electrical power to the second function unit directly from the energy generation unit bypassing the accumulating unit., 'the third function unit'}2. The electronic device according to claim 1 , wherein operates with the electrical power supplied from the energy generation unit and', 'performs ...

METHOD AND APPARATUS FOR SAVING POWER BY EFFICIENTLY DISABLING WAYS FOR A SET-ASSOCIATIVE CACHE

A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses. 1. An apparatus comprising:a cache memory including a plurality of ways;way predictor logic to generate a power signal associated with a first way of the plurality of ways to power down the first way, if the first way is determined to be powered down based on a predetermined number of misses to the first way.2. The apparatus of claim 1 , wherein the way predictor logic to generate a power signal associated with the first way to power down the first way claim 1 , if the first way is determined to be powered down based on a predetermined number of misses to the first way comprises:a first counter associated with the first way, wherein a value of the counter, by default, is set to the predetermined number of allowable misses;control logic coupled to the first counter to decrement the value of the counter in response to tracking a hit to a way of another group of ways, not including the first way; andlogic to generate the power signal, if the value of the first counter is decremented to zero. This is a Continuation of U.S. patent application Ser. No. 13/551,565, filed Jul. 7, 2012 now pending, which is a Continuation of U.S. patent application Ser. No. 11/541,174, filed Sep. 29, 2006, now U.S. Pat. No. 8,225,046, issued Jul. 17, 2012.This invention relates to the field of memory and, in particular, to power ...

Integrating energy budgets for power management

Power consumption of a device (e.g., flash storage driver, hard drive, etc.) connected to a host computer system is managed to promote efficient power usage and improved service. Communication between a host computer system (e.g., an operating system) and a device is enabled so that the host system can ascertain a power footprint of the device. Taking the power footprint of the device into consideration, along with the power consumption of the system as a whole (e.g., including the power consumption needs of other devices), a power manager can provide a power budget to the device based upon an informed decision. This allows for improved system power management through a coordination of the device's power consumption by the host system, specifically during operation allowing device performance to be enhanced for the task at hand.

APPARATUS AND METHOD FOR CONTROLLING POWER OF ELECTRONIC DEVICE HAVING MULTI-CORE

A method of controlling on/off of a core based on a used amount of an operating core and the number of tasks in an electronic device having a multi-core, and an apparatus thereof, includes confirming a load of an operating core and the number of executable tasks at a predetermined period, determining whether the load of the operating core and the number of executable tasks meet a defined on/off condition of the multi-core, and controlling on/off of the multi-core when the load of the operating core and the number of executable tasks meet the defined on/off condition of the multi-core. 1. A method of controlling power of an electronic device having a multi-core , the method comprising:confirming a load of an operating core and the number of executable tasks at a predetermined period;determining whether the load of the operating core and the number of executable tasks meet a defined on/off condition of the multi-core; andcontrolling on/off of the multi-core when the load of the operating core and the number of executable tasks meet the defined on/off condition of the multi-core.2. The method of claim 1 , wherein the defined on/off condition of the multi-core is set depending on states of the multi-core classified according to current consumption characteristics of the multi-core.3. The method of claim 1 , wherein controlling the on/off of the multi-core comprises simultaneously turning on/off at least one core in consideration of parallel processing of the executable tasks.4. The method of claim 3 , wherein turning off the at least one core comprises sequentially turning off the at least one core from a core having a low load.5. The method of claim 1 , wherein the predetermined period includes a core ON period for confirming an ON of an additional core and a core OFF period for confirming an OFF of the operating core.6. The method of claim 5 , wherein the core OFF period differs from the core ON period.7. The method of claim 1 , wherein controlling on/off of the multi ...

POWER SUPPLY MODULE AND POWER SUPPLY SYSTEM

The present disclosure provides a power supply module and a power supply system. The power supply module is used as a first power supply module in a computing system which further includes a second power supply module. The first power supply module and the second power supply module are cascaded in sequence. The first power supply module is in a power supplying state and the second power supply module is in an off state. The first power supply module itself is capable of automatically determining whether to turn on another power supply module or not, without any human intervention. In this way, the power distribution board can be simplified, or even eliminated, in which case the individual power supply modules can be connected by wire to reduce the cost. 1. A power supply module used as a first power supply module in a computing system which further comprises a second power supply module , the first power supply module and the second power supply module being cascaded in sequence , the first power supply module being in a power supplying state and the second power supply module being in an off state , the first power supply module comprising:a load detection unit configured to detect load of the computing system to generate a load detection value;a determination unit connected to the load detection unit and configured to generate determination information based on the load detection value for determining whether to turn on the second power supply module or not; anda turn-on/off unit configured to send a power supply on (PSON) signal to the second power supply module when the determination information indicates that the second power supply module is to be turned on,wherein the second power supply module is turned on in response to the PSON signal.2. The power supply module of claim 1 , wherein the load detection unit comprises: a current detection unit configured to detect an output current from the power supply module itself and generate a current detection value as ...

METHOD AND SYSTEM FOR CONTROLLING POWER

A method and system for controlling power is provided. The system is configured to selectively control a plurality of power control domains. The system may be configured to process audio data in at least one of the domains. The system may be configured to output audio data, while one or more of the power control domains is suspended. 1. A method for controlling power , the method comprising: decoding coded audio data with the processing unit to generate decoded audio data;', 'storing the decoded audio in memory;', 'powering down the processing unit; and', 'providing, with the audio interface, the decoded audio data from the memory to an output, while the processing unit is powered down., 'in an integrated circuit comprising a multimedia processor, said multimedia processor comprising an audio interface and a processing unit2. The method according to claim 1 , further comprising storing processor states for the processing unit in memory claim 1 , before powering down the processing unit.3. The method according to claim 1 , wherein the processing unit is powered down in response to a first amount of audio data being decoded.4. The method according to claim 1 , further comprising powering up the processing unit in response to an amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.5. The method according to claim 4 , further comprising retrieving stored processor states from the memory in response to the amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.6. The method according to claim 5 , further comprising decoding a burst of coded audio data in response to the amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.7. The method according to claim 1 , wherein the processing unit includes a vector processing unit claim 1 , a graphics processing unit claim 1 , and a video coder.8. The method according to claim 1 , wherein ...

OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit. 1. A processor comprising:a plurality of cores;logic circuitry to detect whether one of a plurality of architectural events has occurred within one of the plurality of cores;a plurality of thermal sensors of a first core to provide thermal data for the first core;a plurality of counters of the first core each to count a number of occurrences of one of the architectural events;a bus to couple the plurality of counters and the plurality of thermal sensors; anda power control unit to modify a power state of one of the plurality of cores in response to occurrence of one of the architectural events.2. The processor of claim 1 , wherein the plurality of counters includes public counters and private counters.3. The processor of claim 2 , wherein the power control unit is to determine whether to modify the power state of one of the plurality of cores based on the occurrence values of at least some of the plurality of counters.4. The processor of claim 1 , wherein the bus includes a plurality of branches and wherein each branch is to monitor each of the plurality of counters in a designated time slot.5. The processor of claim 1 , wherein the bus is to send the data collected from each of the plurality of counters to the power control unit.6. The processor of claim 1 , wherein the power control unit is to manage thermal and power events for the first core claim 1 , the power control unit further to receive the thermal data from the plurality of thermal sensors.7. The processor of claim 1 , wherein the logic circuitry is to initiate a power up ...

Multiprocessor system and method of controlling power

According to one embodiment, a multiprocessor system includes a plurality of processors, a power supply device and a shared memory. The shared memory includes a thread pool and a thread queue. In the thread pool, threads each having waiting events are registered in association with the numbers of the waiting events. In the thread queue, threads having no waiting event are registered. One or more first processors acquire first thread from the thread queue and execute the first thread. A second processor updates the number of waiting events of a second thread, which is registered in the thread pool, having completion of required procedure for the second thread by the first thread as a waiting event. A third processor operates supply of power to the first processors individually based on the number of threads in the thread queue and the number of waiting events.

ELECTRONIC DEVICE AND METHOD FOR SUPPLYING POWER TO AT LEAST TWO DIFFERENT LOADS BY SINGLE POWER SUPPLY

An electronic device and a method for supplying power are provided. The electronic device includes a power supply, a central processing module, at least two load power supply circuits including a capacitor, at least one switch and at least one feedback resistor unit. The switch is connected with the power supply and the central processing module, configured to be turned on or off according to a control signal output by the central processing module; the feedback resistor unit is connected with the switch and a load, configured to sample the load when the switch is turned on and feed back a sampled voltage, to the power supply through the switch, the power supply supplies power to the load; the capacitor is connected with the switch and the load, configured to be charged when the switch is turned on, or supply power to the load when the switch is turned off. 1. An electronic device , comprising a power supply and a central processing module , and further comprising: at least two load power supply circuits , wherein the load power supply circuit comprises a capacitor unit , at least one switch , and at least one feedback resistor unit;the switch is respectively connected with the power supply and the central processing module, and configured to be turned on or off according to a control signal output by the central processing module;the feedback resistor unit is connected with the switch and a load, the feedback resistor unit is configured to sample the load when the switch is turned on and feed back a sampled voltage obtained through sampling, to the power supply through the switch, so that the power supply supplies power to the load according to the sampled voltage; andthe capacitor unit is connected with the switch and the load, and configured to be charged when the switch is turned on, or supply power to the load when the switch is turned off.2. The electronic device according to claim 1 , wherein a discharge current of the capacitor unit is greater than a current ...

System wakeup on wireless network messages

While an information handling device is in a reduced power state, the information handling device transitions from the reduced power state to a higher power state in response to receiving a message over an established wireless network connection that maintains a presence on a wireless network. In turn, the information handling device processes the message accordingly in the higher power state.

Domain Specific Language, Compiler and JIT for Dynamic Power Management

The aspects enable a computing device or microprocessor to determine a low-power mode that maximizes system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. The various aspects provide mechanisms and methods for compiling a plurality of low power resource modes to generate one or more synthetic low power resources from which can be selected an optimal low-power mode configuration made up of a set of selected synthetic low power resources. 1. A method for conserving power in a computing device having a plurality of resources and at least one processor , comprising:defining a plurality of low power resource modes in a compilable expression, each of the plurality of low power resource modes identifying a set of resource dependencies, power savings and latency time characteristics associated with a resource as well as a low power state into which each of the plurality of resources can be placed when not in use;compiling the defined plurality of low power resource modes to generate one or more synthetic low power resources each having one or more synthetic low power resource modes that represent functionality, power savings, latency and resource dependencies characteristics of one or more of the plurality of low power resource modes;selecting at most one synthetic low power resource mode for each synthetic low power resource based on the synthetic low power resource mode's power savings, latency time, and dependency requirements; andentering and exiting the selected synthetic low power resource modes in the appropriate order when the processor becomes and leaves idle.2. The method of claim 1 , wherein at most one synthetic low power resource mode for each synthetic low power resource are selected considering ...

Method and System for Tracking and Selecting Optimal Power Conserving Modes of a PCD

A method and system for tracking and selecting optimal power conserving modes of a PCD includes detecting enablement or disablement of a reduced power mode and detecting one of a new and a change in a latency restriction. Next, a low power mode which has a minimum entry and exit latency may be identified. Then, it may be determined if a lowest latency restriction is less than the minimum entry and exit latency. A function pointer may be adjusted based on the output of the determining step. The function pointer may reference a halt state and a reduced power state for the PCD. Then, conditions favorable for at least one of an idle state and a reduced power mode of the PCD may be assessed. If conditions are favorable for an idle state or a reduced power mode for the PCD, then status of the function pointer may be read.

Reconfigurable recovery modes in high availability processors

A method for performing error recovery that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.

APPARATUS AND METHOD FOR CONTROLLING POWER OF EXTERNAL MEMORY IN MOBILE TERMINAL

An external memory power control apparatus and method capable of controlling power of an external memory inserted into a mobile terminal. The external memory power control apparatus includes an external memory power switch for switching between a power supply and an external memory to supply or block power for the external memory; and a controller, when ‘power-on’ is selected on the mobile terminal, for checking and notifying operability of the external memory inserted into the mobile terminal after completing booting while the external memory power switch turned off, wherein the controller may selectively turn on/off the external memory power switch depending on operability of the external memory. 1. An apparatus for controlling power of an external memory in a mobile terminal , comprising:a power switch for selectively supplying power to the external memory; anda controller for determining operability of the external memory inserted into the mobile terminal after booting responsive to a power-on of the mobile terminal while the power switch turned off and selectively supplying power to the external memory based on the detection outcome.2. The apparatus of claim 1 , wherein the controller supplies power to the external memory by turning on the power switch when the external memory is inserted into the mobile terminal.3. The apparatus of claim 1 , wherein the controller further notifiesa damage of the external memory when the external memory is determined to be inoperable or overcurrent is detected therefrom.4. The apparatus of claim 2 , wherein the controller blocks the power supplied to the external memory by turning off the power switch claim 2 , when the external memory is determined to be inoperable or overcurrent is detected therefrom.5. The apparatus of claim 1 , wherein the controller further determines a state of the external memory power switch during a power-off of the mobile terminal claim 1 , and if the power switch is on claim 1 , turns off the power ...

APPARATUS AND METHOD FOR MANAGING POWER IN A COMPUTING SYSTEM

A disable module may be coupled to an analog circuit of an electronic circuit. The disable module may detect an input voltage that is supplied to the analog circuit, and may disable (such as by powering off) the analog circuit if the input voltage is below a reference value. The reference value may be set at a voltage level at or below a maximum voltage that may be present across a transistor in the analog circuit. Accordingly, the analog circuit may be disabled without damage to the transistors of the analog circuit. The disable module may detect whether the input voltage is below the reference value level by comparing the input voltage to a reference voltage. The electronic circuit may include a voltage regulator, and the voltage regulator may include the analog circuit. 1. A power management apparatus , comprising:an analog circuit configured to receive an input voltage; anda disable module coupled to the analog circuit, the disable module being configured to detect if the input voltage is below a reference value, and to power off the analog circuit if the input voltage is below the reference value.2. The apparatus of claim 1 , wherein the disable module is configured to detect if the input voltage is below the reference value by comparison of the input voltage to a reference voltage having a voltage level equal to the reference value.3. The apparatus of claim 2 , wherein the reference voltage is used to supply power to one or more active components of the apparatus.4. The apparatus of claim 1 , wherein the input voltage is lowered from a first voltage to a second voltage during a low power state of the apparatus claim 1 , the first voltage being greater than the reference value and the second voltage being less than the reference value level and non-zero.5. The apparatus of claim 1 , further comprising an integrated voltage regulator claim 1 , wherein the integrated voltage regulator includes the analog circuit.6. The apparatus of claim 5 , wherein the analog ...

System and method of controlling devices operating within different voltage ranges

Semiconductor devices, systems, and methods are disclosed to facilitate power management. A method includes operating a first voltage range island of a semiconductor device within a first voltage range. The first voltage range includes a first midpoint. The first voltage range is provided in part by a voltage source that includes a tracking voltage regulator. The method also includes operating a second voltage range island of the semiconductor device within a second voltage range. The second voltage range includes a second midpoint. The first voltage range is different than the second voltage range.

Power reception control device, power reception device, power transmission and reception system, and electronic device

Provided is a power reception device in which power consumption at the time of wireless power supply is reduced. A power reception device is provided with a power reception control device capable of temporarily stopping supply of power supply voltage to a communication control unit for controlling communication in a break period of communication intermittently performed between a power transmission device and a power reception device. In the structure, a clock signal is generated on the basis of a power receiving signal transmitted from the power transmission device, and a period of communication intermittently performed can be measured using the clock signal. Further, a structure may be employed in which supply of power supply voltage to the communication unit in the power reception control device can be stopped in the break period of the communication.

Embedded controller with an internal timer

Example embodiments disclosed herein relate to a computing system including a controller hub to control system sleep states, and an embedded controller including an internal timer. The embedded controller is to remove power from the controller hub when the system enters a sleep state and to enable power to the controller hub prior to the system wake time, The internal timer is to determine when to enable power to the controller hub. Example methods and machine-readable storage media are also disclosed.

Sleep mode latency scaling and dynamic run time adjustment

The aspects enable a computing device or microprocessor to determine a low power mode that provides the most system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Aspects provide a mechanism for determining an optimal low power configuration made up of a set of low power modes for the various resources within the computing device by determining which low power modes are valid at the time the processor enters an idle state, ranking the valid low power modes by expected power savings given the current device conditions, determining which valid low power mode provides the greatest power savings while meeting the latency requirements, and selecting a particular low power mode for each resource to enter.

Intelligent power controller

A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

BROWSING TERMINAL, CHARGING TERMINAL, AND COMMUNICATION SYSTEM AS WELL AS TRANSMITTING/RECEIVING SYSTEM USING THE SAME

To provide a browsing terminal and the like with high security, which can effectively prevent contents data stored in a terminal from being stolen unlawfully by a third party even if the terminal is accidentally lost. The browsing terminal includes: a receiving part for receiving contents data; a volatile memory for storing the received contents data; a display device with a memory function, which displays the contents data stored in the volatile memory; and a secondary battery for supplying power to the volatile memory and the display device. 1. An inter-terminal communication system , including a distribution terminal and a browsing terminal , whereinthe distribution terminal comprises: a storage part for storing contents data transmitted from a distributor; a transmitting part for transmitting the contents data; and a charging part for charging the browsing terminal, andthe browsing terminal comprises: a receiving part for receiving the contents data transmitted from the transmitting part; a volatile memory for storing the received contents data; a display device with a memory function, which displays the contents data stored in the volatile memory; and a secondary battery for supplying power to the volatile memory and the display device.2. The inter-terminal communication system as claimed in claim 1 , wherein:the browsing terminal comprises a main power source switch; andwhen the main power source switch is turned off, the browsing terminal writes prescribed shutdown screen data to the volatile memory and displays the prescribed shutdown screen data on the display device, while continuing to supply the power to the volatile memory.3. The inter-terminal communication system as claimed in claim 1 , comprising: a measuring device for measuring a charging amount for the browsing terminal; and a fee-amount determining device for determining a fee amount based on the charging amount measured by the measuring device.4. The inter-terminal communication system as ...

DISTRIBUTED POWER DELIVERY SCHEME FOR ON-DIE VOLTAGE SCALING

A high-speed low dropout (HS-LDO) voltage regulation circuit suitable to enable a power gate unit to produce a variable voltage signal based on the load of a processor is disclosed herein. In various embodiments, selection logic may dynamically enable or disable the HS-LDO circuit to allow the power gate unit to operate under a fully-on or fully-off mode. Other embodiments may be disclosed or claimed. 1. An apparatus comprising:a plurality of power gate units, wherein respective ones of the plurality of power gate units have a fully-on output mode and a fully-off output mode; anda voltage regulation circuit coupled to the plurality of power gate units to provide the plurality of power gate units with a variable voltage output mode.2. The apparatus of claim 1 , wherein the voltage regulation circuit further comprises:an operational amplifier (op-amp) having a first input terminal configured to receive a reference voltage, a second input terminal coupled with an output terminal of the op-amp to form a feedback loop; anda plurality of predriver units respectively coupled to the output terminal of the op-amp,wherein respective ones of the plurality of predriver units are further coupled to a plurality of driver units,wherein respective ones of the plurality of driver units are further coupled to one or more of the plurality of power gate units, andwherein the plurality of driver units and the plurality of predriver units to cooperatively cause one or more of the plurality of power gate units to produce an output voltage based on the reference voltage in response to a control signal.3. The apparatus of claim 2 , wherein the op-amp comprises an operational transconductance amplifier.4. The apparatus of claim 2 , wherein the op-amp is configured to receive the reference voltage from a bandgap reference voltage generator configured to generate the reference voltage based on a voltage identification (VID) signal.5. The apparatus of claim 2 , wherein the plurality of driver ...

Mechanism for facilitating power extension service at computing devices

A mechanism is described for facilitating power extension service at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes calculating potential power saving by one or more of a plurality of power-saving techniques supported by a computing device. The calculating includes identifying the one or more of the plurality of power-saving techniques that are available for selection and an expected amount of power to be saved with the one or more of the plurality of power saving techniques. The method may further include generating a list identifying the one or more of the plurality of power-saving techniques and relevant information resulting from the calculation, and displaying the list.

STORAGE SYSTEM AND POWER CONSUMPTION CONTROL METHOD FOR STORAGE SYSTEM

A storage system that functions as one or more logical volumes includes a control unit and a plurality of storage units connected to the control unit, wherein the control unit includes a memory that stores allocation status information that indicates status of allocation of the plurality of storage units to a logical volume; an access request responding unit that controls at least one storage unit among the plurality of storage units in response to a request for access to each logical volume from a host device; and a power saving controller that identifies an unused storage unit not allocated to any logical volume among the plurality of storage units on the basis of the allocation status information and performs power saving control on the identified unused storage unit. 1. A storage system that functions as one or more logical volumes , comprising:a control unit; anda plurality of storage units connected to the control unit;wherein the control unit includesa memory that stores allocation status information that indicates status of allocation of the plurality of storage units to a logical volume,an access request responding unit that controls at least one storage unit among the plurality of storage units in response to a request for access to each logical volume from a host device, anda power saving controller that identifies an unused storage unit not allocated to any logical volume among the plurality of storage units on the basis of the allocation status information and performs power saving control on the identified unused storage unit.2. The storage system according to claim 1 ,wherein the plurality of storage units are daisy-chained to the control unit;wherein each of the plurality of storage units includesone or more storage devices,a relay processor that relays information addressed to another unit received from a preceding unit directly connected to a current unit to a subsequent unit directly connected to the current unit and relays information from the ...

Image forming apparatus and control method therefor

In an image forming apparatus, a first detection portion includes a pyroelectric sensor and detects the upper half of the human body. A first signal generation portion generates a first signal whose level varies according to the output value of the pyroelectric sensor. A second detection portion includes a pyroelectric sensor and detects a lower area than the first detection portion. A second signal generation portion generates a second signal whose level varies according to the output value of the pyroelectric sensor. A storage portion stores discrimination data including data defining, with respect to the waveforms of the first and second signals, a condition for recognizing a human moving toward the image forming apparatus and a condition for recognizing a human crossing a detection area of the pyroelectric sensors. A recognition portion recognizes the direction of movement of a human.

USER BEHAVIOR ADAPTIVE SENSING SCHEME FOR EFFICIENT POWER CONSUMPTION MANAGEMENT

A deactivated passive user interaction sensor may be activated or deactivated on demand based on an expected use of the sensor. The expected use may be ascertained by detecting a predetermined user interaction at another sensor that is already active. Once the predetermined user interaction is detected, the active sensor may be deactivated and the sensor that is expected to be used may be activated. Total sensor power consumption may be reduced by providing a predetermined sensor activation and deactivation sequence for at least three sensors in a computing system based on predetermined user interactions with an active sensor. Methods, apparatuses, systems, and computer readable media are provided. 1. A method comprising:identifying one of a plurality of predetermined user interactions at a first passive user interface sensor of a computing system using a signal processing unit;responsive to identifying a first of the plurality of predetermined user interactions, activating a second passive user interface sensor and deactivating the first sensor; andresponsive to identifying a second of the plurality of predetermined user interactions, activating a third passive user interface sensor and deactivating the first sensor.2. The method of claim 1 , further comprising:identifying a third predetermined user interaction at the second sensor while the second sensor is activated; andresponsive to the identifying of the third predetermined user interaction at the second sensor, reactivating the first sensor and deactivating the second sensor.3. The method of claim 2 , further comprising:identifying a fourth predetermined user interaction at the third sensor while the third sensor is activated; andresponsive to the identifying of the fourth predetermined user interaction at the third sensor, reactivating the first sensor and deactivating the third sensor.4. The method of further comprising repeating the method of to an extent of:identifying one of a plurality of predetermined ...

Mobile information terminal and gripping-feature authentication method

A mobile information terminal including a gripping-feature sample acquisition unit to acquire a gripping-feature sample, one or more environmental sensors outputting an environmental signal, a terminal status detector to acquire the environmental signal and detect a terminal status, a template selection unit to select a user authentication template fitting the detected terminal status, a user authentication unit collating the acquired gripping-feature sample with the selected user authentication template and outputting a user authentication result, a user authenticity level monitor that outputs a sensor power source OFF signal when the user authenticity level exceeds a threshold value and outputs a sensor power source ON signal when the user authenticity level falls below the threshold value, and a power source control unit halting energization to a sensor when acquiring the sensor power source OFF signal, and energizing a sensor when acquiring the sensor power source ON signal.

Method and System for MAC and PHY Synchronization for Energy Efficient Networking

Aspects of a method and system for MAC and PHY synchronization for energy efficient networking are provided. In this regard, an interface that enables communication between a MAC controller and a PHY device may be configured to operate in an energy saving mode. While the interface is operating in an energy saving mode, synchronization between the MAC controller and the PHY device may be maintained by one or both of adjusting a clock generated for the interface and/or communicating dummy data via the interface. The clock may be adjusted by one or more of adjusting a frequency of the clock, adjusting an amplitude of the clock, and/or duty cycling the clock. The MAC controller and/or the PHY device may generate the dummy data. The PHY device and/or the MAC controller may discard the dummy data upon receiving the dummy data.

POWER SUPPLY SYSTEM

A power supply system supplies power includes a single power supply unit to supply power for a number of motherboards. A number of power management chips are provided corresponding to the motherboards, to monitor a real-time power consumption of each motherboard. A microcontroller is connected to each of the motherboards through a data line, to control a total power consumption of the motherboards to control power consumption to remain within a nominal power of the power supply unit. 1. A power supply system for a plurality of motherboards of a computing device , comprising:a power supply unit, a microcontroller, a plurality of power management chips, and a plurality of switches, wherein:each of the switches comprises a voltage input terminal and a voltage output terminal, the voltage input terminal of each of the switches is electrically connected to the power supply unit, and the voltage output terminal of each of the switches is electrically connected to a corresponding motherboard to supply power to the corresponding motherboard;each of the power management chips is electrically connected to the microcontroller via a power management bus, to detect a real-time power consumption of a corresponding motherboard and transmits the real-time power consumption of the corresponding motherboard to the microcontroller;the microcontroller is electrically connected to each of the motherboards through a data line, to control a total power consumption of the motherboards to remain within a nominal power of the power supply unit.2. The power supply system according to claim 1 , wherein the power supply unit consists of one or more power devices having a predetermined nominal power claim 1 , and the nominal power of the power supply unit is equal to a sum of the nominal powers of the one or more power devices.3. The power supply unit according to claim 2 , wherein a number of the power devices of the power supply unit is less than a number of the motherboard.4. The power supply ...

Adjusting proximity thresholds for activating a device user interface

A smart-home device includes a user interface including an electronic display having a first display mode and a second display mode, the first display mode generally requiring more power than said second display mode. The device also includes a processing system in operative communication with one or more environmental sensors for determining at least one environmental condition. The device additionally includes at least one sensor configured to detect a physical closeness of a user to the at least one sensor. The processing system may be configured to cause the electronic display to be in the first display mode when a closeness threshold has been exceeded, where the processing system is further configured to automatically adjust the closeness threshold based at least in part on a historical plurality of physical closeness events as detected by the at least one sensor.

PROCESSOR SCHEDULING METHOD AND SYSTEM USING DOMAINS

Aspects of the present invention concern a method and system for scheduling a request for execution on multiple processors. This scheduler divides processes from the request into a set of domains. Instructions in the same domain are capable of executing the instructions associated with the request in a serial manner on a processor without conflicts. A relative processor utilization for each domain in the set of the domains is based upon a workload corresponding to an execution of the request. If there are processors available then the present invention provisions a subset of available processors to fulfill an aggregate processor utilization. The aggregate processor utilization is created from a combination of the relative processor utilization associated with each domain in the set of domains. If processors are not needed then some processors may be shut down. Shutting down processors in accordance with the schedule saves energy without sacrificing performing. 1. A method of scheduling a request for execution on one or more processors , comprising:dividing processes from the request into a set of domains where processes in the same domain are executable in a serial manner on a processor without conflict;identifying a relative processor utilization for each domain from the set of the domains based upon a workload corresponding to an execution of the request;provisioning a subset of available processors to fulfill an aggregate processor utilization created from a combination of the relative processor utilization associated with each domain from the set of domains; andshutting down any remaining processors from the one or more processors not provisioned in the subset of available processors in order to reduce power consumption while the processes in the set of domains are scheduled for execution.2. The method of further comprising:bringing online any processors from the one or more processors that have been provisioned in the subset of available processors but ...

EXPANSION CIRCUIT FOR SERVER SYSTEM AND SERVER SYSTEM USING SAME

An expansion circuit for a server system includes a first output terminal, a second output terminal, a switch circuit and a detection circuit. The first output terminal receives a first voltage and providing the first voltage to a first hard disk drive group. The second output terminal receives the first voltage and provides the first voltage to a second hard disk drive group. The switch circuit is connected between the first and the second output terminals. The detection circuit detects a number of the at least one server which is electrically connected to the expansion circuit. When two servers are electrically connected to the expansion circuit, the detection circuit switches off the switch circuit. When a server is electrically connected to the expansion circuit, the detection circuit switches on the switch circuit. 1. An expansion circuit connected between at least one server and a hard disk module , comprising:a first output terminal receiving a first voltage and providing the first voltage to a first hard disk drive group;a second output terminal receiving a second voltage and providing the second voltage to a second hard disk drive group;a switch circuit connecting between the first output terminal and the second output terminal; anda detection circuit detecting a number of the at least one server electrically connected to the expansion circuit and switching on or switching off the switch circuit according to the detection;wherein when two servers are electrically connected to the expansion circuit and corresponds to the first hard disk drive group and the second hard disk drive group respectively, the detection circuit switches off the switch circuit; and when a server is electrically connected to the expansion circuit and corresponds to the first hard disk drive group and the second hard disk drive group, the detection circuit switches on the switch circuit.2. The expansion circuit of claim 1 , wherein the detection circuit comprises a first detection ...

Information processing apparatus and control method thereof

Each of a plurality of circuit blocks includes a plurality of arithmetic elements. A power supply controller individually controls power supply to the plurality of circuit blocks. A resource management unit acquires first information regarding an arithmetic element necessary for an arithmetic process, and second information regarding an arithmetic element included in a circuit block which is supplied with power. Based on the first information and the second information, the resource management unit preferentially assigns, to the arithmetic element included in the circuit block which is supplied with power, a process for implementing the arithmetic process.

TERMINAL DEVICE AND METHOD FOR OPERATING THE SAME

The present disclosure discloses terminal devices and a method of operating the same, and relates to the field of terminal technology. The method includes: obtaining a current load occupancy parameter of a terminal device; and adjusting a working parameter of the terminal device's processing unit based on the current load occupancy parameter of the terminal device. The present disclosure can estimate the actual occupancy of a terminal device based on the load occupancy parameter of the terminal device, and can adjust a working parameter of the processing unit in real-time based on the load occupancy parameter, thereby controlling and reducing power usage from the bottom layer of the terminal device. In contrast to existing technologies, the disclosure does not require stopping certain services on the terminal device to achieve the goal of saving power, and power can be saved without affecting the normal operations of the terminal device. 1. A method of operating a terminal device , comprising:obtaining a current load occupancy parameter of the terminal device, andadjusting a working parameter of a processing unit of the terminal device in accordance with the current load occupancy parameter of the terminal device.2. The method of claim 1 , wherein obtaining the current load occupancy parameter of the terminal device comprises:obtaining, in accordance with an operating mode of the terminal device, a load occupancy parameter corresponding to the operating mode in accordance with a set correspondence between operating modes and load occupancy parameters, orobtaining, in accordance with a usage activity associated with the terminal device, a load occupancy parameter corresponding to the usage activity in accordance with the set correspondence between usage activities and load occupancy parameters.3. The method of claim 2 , wherein obtaining claim 2 , in accordance with the operating mode of the terminal device claim 2 , the load occupancy parameter corresponding to the ...

AUTONOMOUS MICROPROCESSOR RE-CONFIGURABILITY VIA POWER GATING EXECUTION UNITS USING INSTRUCTION DECODING

In an embodiment, a functional unit control system includes an instruction decoder of a processor comprising a pipeline, the instruction decoder being configured to decode an instruction to be performed by the processor. The system further includes a power controller unit coupled to the instruction decoder, and a functional unit which may operate during execution stages of the processor's pipeline coupled to the power controller unit and the instruction decode stage. The power controller unit is configured to determine whether the functional unit should be used to perform at least part of the instruction based on data of the instruction decoder. The power controller unit is further configured to perform at least one of activating and deactivating the functional unit in accordance with the determination of whether the functional unit should be used. 1. A functional unit control system comprising:an instruction decoder of a processor, the instruction decoder being configured to decode an instruction to be performed by the processor;a power controller unit coupled to the instruction decoder; anda first functional unit of the processor coupled to the power controller unit and the instruction decoder,wherein the power controller unit is configured to determine whether the first functional unit should be used to perform at least part of the instruction based on data of the instruction decoder, andwherein the power controller unit is further configured to perform at least one of activating and deactivating the functional unit in accordance with the determination of whether the functional unit should be used.2. The functional unit control system of claim 1 , further comprising a plurality of second functional units that are pipelined with the first functional unit.3. The functional unit control system of claim 1 , further comprisinga plurality of second functional units that are pipelined together, the additional functional units being the same type as the first functional ...

Methods and Apparatus for Mobile Device Power Management Using Accelerometer Data

A computer-implemented method for power management in a portable device includes receiving sensor information from a sensor in the portable device, associating the sensor information with one of a plurality of states of the portable device, and reducing electrical power consumption in one or more parts in the portable device according to the associated state of the portable device. In some embodiments, the method also includes collecting, from the accelerometer in the portable device, electrical signals associated with a plurality of known motion states of the portable device, and analyzing the collected electrical signals. The method also includes identifying attributes of the electrical signal with the known motion states of the portable device. 1. A computer-implemented method for power management in a portable device programmed to perform the method , the method comprising:receiving sensor information from a sensor in the portable device;associating the sensor information with one of a plurality of states of the portable device; andreducing electrical power consumption in one or more parts in the portable device according to the associated state of the portable device.2. The computer-implemented method of claim 1 , wherein the sensor in the portable device comprises a motion sensor.3. The computer-implemented method of claim 2 , wherein the sensor in the portable device comprises a MEMS (MicroElectroMechanical system) accelerometer integrated with CMOS (complementary metal oxide semiconductor) circuitry in a single integrated circuit (IC).4. The computer-implemented method of claim 3 , further comprising:collecting, from the accelerometer in the portable device, electrical signals associated with a plurality of known motion states of the portable device;analyzing the collected electrical signals; andidentifying attributes of the electrical signal with the known motion states of the portable device.5. The computer-implemented method of wherein the plurality of ...

NETWORK MANAGEMENT SYSTEM, NETWORK MANAGEMENT COMPUTER AND NETWORK MANAGEMENT METHOD

A network management system comprising: a network including a plurality of packet relay apparatuses; wherein the plurality of packet relay apparatuses include first packet relay apparatuses, second packet relay apparatuses, and third packet relay apparatuses located downstream of the first packet relay apparatuses and the second packet relay apparatuses, wherein each of the third packet relay apparatuses has a first path coupled to one of the first packet relay apparatuses to send and receive traffic and a second path coupled to one of the second packet relay apparatuses and being in a blocking state, a management computer includes: a state information collection unit for acquiring state information on the first to the third packet relay apparatuses; and a power management unit for selecting a candidate packet relay apparatus to be deactivated satisfying predetermined conditions based on the state information. 1. A network management system comprising:a network including a plurality of packet relay apparatuses; anda management computer for managing the plurality of packet relay apparatuses,wherein the plurality of packet relay apparatuses include first packet relay apparatuses, second packet relay apparatuses, and third packet relay apparatuses located downstream of the first packet relay apparatuses and the second packet relay apparatuses,wherein each of the third packet relay apparatuses has a first path coupled to one of the first packet relay apparatuses to send and receive traffic and a second path coupled to one of the second packet relay apparatuses and being in a blocking state, a state information collection unit for acquiring state information on the first to the third packet relay apparatuses; and', 'a power management unit for selecting a candidate packet relay apparatus to be deactivated satisfying predetermined conditions based on the state information as a first packet relay apparatus to be deactivated out of the first packet relay apparatuses which ...

Apparatus for powering a device

An apparatus includes a processor and a device. The processor generates an output signal and a control signal. The device consumes power while operating in first and second states. The device consumes less power while in the first state than while in the second state. The processor: accounts for a transition time for the device to transition among a powered off state, the first state, and the second state; and generates the control signal based on the transition time. The device: in response to the control signal, transitions to the second state at a speed of periodicity of a periodic signal of the processor; subsequent to the transitioning to the second state, performs a function based on the output signal; and subsequent to performing the function, transitions from the second state to either the first state or the powered off state.

Method and apparatus to save power upon resume in multi-core system

A method is provided for resuming one or more cores of a multi-core processor that is part of an electronic device, the method comprising: grouping wakeup sources into a plurality of computing domains; receiving an interrupt associated with a wakeup source; identifying a first computing domain from the plurality that the wakeup source is part of; mapping the first computing domain to a first indication of one or more states of a first core of the processor; configuring the first core to enter the one or more states that are indicated by the first indication; and resuming the first core after the first core is configured.

Power gated communication controller

A method includes detecting a communication event over a communication bus 130 coupled to a device, and in response to detecting the communication event, deactivating a module of the device. The method may further include sending a data throttle packet over the communication bus 130 while the deactivated module reactivates.

CIRCUIT SYSTEM AND SEMICONDUCTOR DEVICE

A circuit system includes: a plurality of memory blocks; a power supply circuit configured to supply operating power and substrate power to the plurality of memory blocks; a plurality of first power supply switches configured to control whether or not the operating power is supplied from the power supply circuit to the plurality of memory blocks; and a control circuit configured to control the power supply circuit and the plurality of first power supply switches, wherein the control circuit changes a voltage of the operating power to be supplied by the power supply circuit and a voltage of the substrate power to be supplied by the power supply circuit, based on a state of whether the first power supply switches are in a supplying state or a blocking state. 1. A circuit system comprising:a plurality of memory blocks;a power supply circuit configured to supply operating power and substrate power to the plurality of memory blocks;a plurality of first power supply switches configured to control whether or not the operating power is supplied from the power supply circuit to the plurality of memory blocks; anda control circuit configured to control the power supply circuit and the plurality of first power supply switches,wherein the control circuit changes a voltage of the operating power to be supplied by the power supply circuit and a voltage of the substrate power to be supplied by the power supply circuit, based on a state of whether the first power supply switches are in a supplying state or a blocking state.2. The circuit system according to claim 1 ,wherein the plurality of memory blocks are connected to a common data bus.3. The circuit system according to claim 2 , further comprising:a clock circuit configured to supply a clock that causes parts included in the circuit system to operate in synchronization with each other.4. The circuit system according to claim 3 , further comprising:at least one logic circuit connected to the plurality of memory blocks through ...

Sequence power control

The present disclosure includes apparatuses and methods for sequence power control. A number of embodiments include executing a number of sequences associated with a number of commands, wherein a number of logical unit (LUN) controllers execute the number of sequences by locating power consumption information and a starting address of the number of sequences stored in a data structure on the number of LUN controllers.

Boot State Restore from Nonvolatile Bitcell Array

A processing device using a plurality of volatile storage elements to execute a boot process for and stores in a plurality of non-volatile logic element arrays a boot state representing a state of the processing device after a given amount of the boot process is completed. When it is determined that the processing device needs to restart from a boot state, energy can be saved by restoring the machine state at that boot state instead of re-booting. The stored boot state will not change, and given the nature of certain non-volatile storage elements, the data read from the NVL storage elements needs to be re-written to the elements after read out. Accordingly, a round-trip data restoration operation is executed that automatically writes back data to an individual non-volatile logic element after reading data from the individual non-volatile logic element without completing separate read and write operations.

CONTROL DEVICE, DATA PROCESSING DEVICE, CONTROLLER, METHOD OF CONTROLLING THEREOF AND COMPUTER-READABLE MEDIUM

A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power. 1. A control device comprising:a data-copying unit that copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory, the data being to be processed at a first data processing unit;a data-processing instructing unit that instructs the first data processing unit to process the data copied to the second memory; anda power-control unit that switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory,the first power being power supplied to the first memory at a time when the data is copied from the first memory to the second memory, andthe second power being lower than the first power.2. The device according to claim 1 , further comprisinga data-size adjusting unit that adjusts a size of data that the data-copying unit is to be copying to the second memory at one time.3. The device according to claim 2 , whereinthe data-size adjusting unit divides or integrates one or more data stored in the first memory into one or more unitary data to be copied to the second memory.4. The device ...

Customizable Backup And Restore From Nonvolatile Logic Array

Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics. 1. A method for customizing wake time and peak power cost during a restoration of a computing device volatile storage system state from a non-volatile array backup , the method comprising:manufacturing a processing device having a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device and wherein the processing device is configured to enable reading out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;wherein a number of rows and a number of bits per row in individual ones of the plurality of non-volatile logic element arrays are based on a target wake up time based on a time used to read data one row at a time from one of the plurality of non-volatile logic element arrays and a peak power cost based on a peak power used to read a row of a given length of bits at a same time from the one of the plurality of non-volatile logic element arrays.2. The method of further comprising analyzing simulations of a design of the non-volatile logic ...

Charge Recycling Between Power Domains of Integrated Circuits

A mechanism is provided for efficiently recycling a charge from a power domain that is discharging. A side of a discharging power domain normally coupled to a voltage supply is disconnected from the voltage supply. The side of the precharging power domain normally coupled to the voltage supply is currently disconnected from the voltage supply. The side of the discharging power domain normally coupled to the voltage supply is connected to a side of the precharging power domain normally coupled to the voltage supply. A side of the discharging power domain normally coupled to the ground is disconnected from ground. The side of the discharging power domain normally coupled to ground is connected to the voltage supply, thereby precharging the precharging power domain with the charge from the discharging power domain that would normally be lost due to leakage.