Method and apparatus for providing power state information using in-band signaling

A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

Hardware unit for controlling operating frequency in a processor

In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

Techniques for flexible and dynamic frequency-related telemetry

Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.

TECHNIQUES FOR FLEXIBLE AND DYNAMIC FREQUENCY-RELATED TELEMETRY

Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:logic, coupled to a processor, to communicate information to a module,wherein the information is to comprise a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled.2. The apparatus of claim 1 , wherein the information is to comprise a magnitude counter value corresponding to a difference between a magnitude of a requested feature by the module and a magnitude of the requested feature to be provided by the processor.3. The apparatus of claim 1 , wherein the information is to be provided based at least in part on a plurality of points to be selected for sampling.4. The apparatus of claim 1 , wherein the information is to be provided based at least in part on a plurality of domains of the processor to be selected for comparison.5. The apparatus of claim 1 , wherein the information is to be provided based at least in part on a plurality of points with an offset to be selected for comparison.6. The apparatus of claim 2 , wherein the information is to comprise a complex composition between the duration counter and the magnitude counter to provide high order statistics.7. The apparatus of claim 1 , wherein the operating characteristic of the processor corresponds to an operating frequency of the processor or a detected temperature at a component of the processor.8. The apparatus of claim 1 , further comprising a duration counter to store the duration counter value claim 1 , wherein the duration counter is to be reset after a period of time.9. The apparatus of claim 1 , wherein ...

Controlling Operating Voltage Of A Processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores; anda power controller including a control logic to receive a first request to increase an operating voltage to be provided to a first core to a second voltage and, responsive to the first request, cause a voltage regulator to increase the operating voltage to an interim voltage, thereafter enable a second core to exit an inactive state and enter an active state, and thereafter enable an operating frequency of the first core to be increased.2. The processor of claim 1 , wherein the power controller is to receive a second request to wake up the second core after the increase of the operating voltage to the interim voltage has occurred.3. The processor of claim 1 , wherein the power controller comprises a microcontroller.4. The processor of claim 3 , wherein the microcontroller is to receive the first request responsive to a request for the first core to enter into an opportunistic performance state.5. The processor of claim 4 , wherein the microcontroller is to enable the first core to enter into the opportunistic performance state responsive to receipt of an acknowledgement from the voltage regulator that the operating voltage has reached the second voltage.6. The processor of claim 1 , wherein the control logic is to determine the interim voltage based at least in part on a number of the plurality of cores that are in the active state.7. The processor of claim 1 , wherein the control logic is to receive a first acknowledgement from the voltage ...

Performing soft throttling and hard throttling in a processor

In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.

Controlling forced idle state operation in a processor

In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

Programmable Power Management Agent

In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed. 1. A processor comprising:at least one core including a first core; and a static table to store a list of operations, and that includes a plurality of columns, each column to specify a corresponding flow, each flow to include a corresponding subset of the operations and each flow associated with a corresponding state of the first core;', 'a control register (CR) to include a plurality of storage elements, wherein each storage element corresponds to a respective operation listed in the static table, each storage element to receive one of a first value and a second value; and', 'execution logic, responsive to a command to place the first core into a first state, to execute each operation of a first flow for which the corresponding storage element stores the first value and to refrain from execution of each operation of the first flow for which the corresponding element stores the second value., 'a power management agent (PMA) coupled to the first core, the PMA to include2. The processor of claim 1 , further including a power management unit (PMU) to determine a corresponding value to be stored ...

METHOD AND APPARATUS FOR PROVIDING POWER STATE INFORMATION USING IN-BAND SIGNALING

A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC. 1. An integrated circuit (IC) device comprising:a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; andcontrol logic operable to obtain data for inclusion in a response to the command,wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.2. The device defined in wherein the power state information indicates whether the IC is currently in one or more reduced power consumption states claim 1 , and further wherein the control logic is operable to obtain the data for inclusion in the response without having the IC leave a power state in which the IC currently resides.3. The device of wherein the one or more reduced power consumption states comprises one or more deep sleep states selected from a group of C8 claim 2 , C9 and C10 C-states.4. The device defined in wherein the bus is a platform control bus.5. The device defined in wherein the platform control bus comprises a Platform Environment Control Interface (PECI) bus and the controller comprises a PECI controller.6. The device defined in wherein the power state information comprises a bit in the response.7. The device defined in wherein ...

Dynamically Controlling Cache Size To Maximize Energy Efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed. 1. A system comprising:an integrated memory controller; and a plurality of cores, wherein each of the plurality of cores includes a plurality of caches;', 'a shared cache coupled to the plurality of cores, wherein the shared cache is to be shared by the plurality of cores, and wherein the shared cache includes a plurality of portions that each include at least one way; and', determine a number of cache hits, and a number of cache misses, to the shared cache from the plurality of cores;', 'provide control for a dynamically variable size of the shared cache available for use by the plurality of cores, through at least one of the plurality of portions being enabled or disabled, based at least in part on the determined numbers of cache hits and cache misses; and', 'provide control for at least one of the plurality of portions of the shared cache being maintained in a retention state, when the plurality of cores are to be in a low power state, and while at least another of the plurality of portions of the shared cache is to be in a lower power state than the retention state, wherein in the retention state data stored in the at least one of the plurality of portions, which is being maintained in the retention state, is to be retained., 'a power control circuitry coupled to the plurality of cores and to the shared cache, the power control circuitry to], 'a processor coupled to the integrated memory controller, the processor comprising2. The system of claim 1 , wherein the shared cache is to be shared by the plurality of cores and a graphics unit.3. The system of claim 2 , wherein the ...

Dynamically controlling cache size to maximize energy efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Controlling operating voltage of a processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Controlling A Turbo Mode Frequency Of A Processor

In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed. 1. An article comprising a non-transitory machine-accessible storage medium including instructions that when executed cause a system to:analyze a plurality of power state change events of a multicore processor including a plurality of cores during an evaluation interval to determine a hypothetical number of frequency transitions responsive to the plurality of power state change events for each of N-core turbo frequencies;select one of the N-core turbo frequencies to be a maximum operating frequency of the multicore processor for a next operating interval based at least in part on the hypothetical number of frequency transitions, the selected N-core turbo frequency less than a configured maximum operating frequency of the multicore processor; andcontrol the plurality of cores to operate at no higher than the selected N-core turbo frequency for the next operating interval.2. The article of claim 1 , further comprising instructions that when executed enable the system to receive a turbo mode request for a first core of the multicore processor from a scheduler during the next operating interval claim 1 , and control the first core to operate at the selected N-core turbo frequency.3. The article of claim 1 , further comprising instructions that when executed enable the system to update a first entry of a table on a power state change event claim 1 , if a hypothetical frequency transition would be performed responsive to the power state change event ...

CPU CENTRIC PLATFORM POWER MANAGEMENT AND CURRENT UNDER REPORTING DETECTION

To address problems associated with power management of electronic devices, the subject matter described herein provides improved power management solutions that enable CPUs and other electronic components to characterize real-time power consumption. This may be used to assess an effect of added platform level features after factory testing, and may be used to improve or optimize system performance. These solutions may include an accurate platform-independent integrated voltage measurement, dedicated to a reliable absolute voltage measurement that may be used for multiple purposes. The subject matter described herein proposes a combination of a voltage detector and an algorithm implemented in the electronic component (e.g., CPU) that may be used to compensate for voltage variations due to tolerances or guard bands, and may be used to detect discrepancies of underreporting or overreporting of current information by the platform VR.

METHOD AND APPARATUS FOR SELECTING AN INTERCONNECT FREQUENCY IN A COMPUTING SYSTEM

In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (f CL ). The processor also includes a power management unit (PMU) including f CL logic to determine whether to adjust the f CL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

Estimating temperature of a processor core in a low power state without thermal sensor information

In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.

Forcing A Processor Into A Low Power State

In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores each to independently execute instructions; anda power controller coupled to the plurality of cores and including a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the plurality of cores to enter into a forced idle state while the at least one logical processor has a workload to execute and to cause the at least one logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor of the plurality of cores is prevented from entry into the forced idle state.2. The processor of claim 1 , further comprising a configuration register to enable HDC operation of the processor at a package level claim 1 , wherein the configuration register is controllable by system software.3. The processor of claim 2 , wherein the HDC logic is to set at least one of a maximum active time and a minimum idle time for the HDC operation.4. The processor of claim 2 , wherein the forced idle state is invisible to the system software and corresponds to a low power state of at least a level at which a core clock is disabled.5. The processor of claim 1 , wherein the HDC logic is to cause the at least one logical processor to exit the forced idle state at an expiration of a first timer claim 1 , if all of the plurality of cores have not entered into the forced idle state.6. The processor of claim 1 , further ...

METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate. 1. A processor to support energy conservation techniques , comprising:a plurality of processing cores,an uncore area, anda power management unit,wherein the power management unit to,receive a request from an operating system, wherein the request includes a first power saving state into which the processor is to be placed,demote the processor to a second power state, which is a shallower power saving state than the first power state if a low activity period of the processor overlaps with a burst of high interrupt rate, andun-demote the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low,wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from an operating system.2. The processor of claim 1 , wherein the power management unit to un-demote the processor to a fourth state power saving state claim 1 , which is deeper than third power saving state if a sleep duration of the ...

Dynamically controlling cache size to maximize energy efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Controlling Current Transients In A Processor

In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

Controlling a turbo mode frequency of a processor

In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

Device, system and method of wireless communication

Briefly, according to embodiments of the invention, there is provided a wireless communication system and a method to receive by a base station from a first mobile station a first chain of data symbols transmitted by at least two antennas and having a first transmit diversity, to receive from a second mobile station a second chain of data symbols transmitted by at least two antennas and having a second transmit diversity. Both first and second chains of data symbols are transmitted from the first and second mobile stations at the same time, modulated according to an Orthogonal Frequency Division Multiplexing (OFDM) scheme and encoded by a space time block codes scheme.

Device, system and method of point to multipoint communication

Some embodiments of the invention provide devices, systems and methods of point to multipoint communication. For example, an apparatus in accordance with an embodiment of the invention includes a resource allocator to allocate a wireless communication channel resource to one or more stations of a wireless communication system based on a net benefit function that takes into account an overhead incurred by controlling the allocation of said channel resource.

Controlling a turbo mode frequency of a processor

In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

Optimizing energy efficiency using device idle duration information and latency tolerance based on a pre-wake configuration of a platform associated to the device

Systems and methods may provide for aggregating a first idle duration from a first device associated with a platform and a second idle duration from a second device associated with the platform. Additionally, an idle state may be selected for the platform based at least in part on the first idle duration and the second idle duration. In one example, the idle durations are classified as deterministic, estimated or statistical.

Leakage degradation control and measurement

A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

Providing lifetime statistical information for a processor

In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

Method and apparatus for selecting an interconnect frequency in a computing system

In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

Programmable power management agent

In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

Dynamically controlling cache size to maximize energy efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Estimating Temperature Of A Processor Core In A Low Power State

In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores;a plurality of thermal sensors each associated with one of the plurality of cores; anda power control unit (PCU) coupled to the plurality of cores, the PCU including a first logic to estimate a temperature of a first core of the plurality of cores while the first core is in a low power state.2. The processor of claim 1 , wherein the first logic is to estimate a temperature of the plurality of cores while the processor is in a package low power state.3. The processor of claim 1 , wherein a first thermal sensor associated with the first core is powered down when the first core is in the low power state.4. The processor of claim 3 , wherein the first logic is to receive a temperature of the first core from the first thermal sensor when the first core is in an active state.5. The processor of claim 4 , wherein the first logic is to store the temperature in a thermal storage area associated with the first core claim 4 , the thermal storage area further including a valid indicator to indicate that the stored temperature is valid.6. The processor of claim 5 , wherein the first logic is to clear the valid indicator when the first core enters into the low power state.7. The processor of claim 6 , wherein the first logic is to set the valid indicator after a scan time period after the first core enters the active state.8. The processor of claim 1 , wherein the first logic is to estimate the temperature based on a stored temperature of the first core and a temperature of at least one ...

LEAKAGE DEGRADATION CONTROL AND MEASUREMENT

A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation. 1. An apparatus comprising:a first processor core;a second processor core; and measure a first leakage current through the first processor core;', 'measure a second leakage current through the second processor core;', 'determine whether the first and/or second leakage currents are above a threshold; and', 'modify voltage and/or frequency of the first and/or second processor core in response to a determination that the first and/or second leakage currents are above the threshold., 'a power control unit (PCU) coupled to the first and second processor cores, wherein the PCU comprises logic to2. The apparatus of claim 1 , wherein the PCU is to squash a first clock of the first processor core to measure the first leakage current claim 1 , and wherein the PCU is to squash a second clock of the second processor core to measure the second leakage current.3. The apparatus of comprises a first voltage regulator (VR) to supply a first power supply to the first processor core claim 1 , wherein the PCU is to measure the first leakage current with a current sensor associated with the first VR.4. The apparatus of comprises a second voltage regulator (VR) to supply a second power supply to the second processor core claim 1 , wherein the PCU is to measure the second leakage current with a current sensor associated with the second VR.5. The apparatus of claim 1 , wherein the PCU is to measure the first leakage current at a first temperature of the first processor core claim 1 , wherein the ...

Balanced control of processor temperature

In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

Mechanism for saving and retrieving micro-architecture context

A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.

Mechanism for facilitating faster suspend/resume operations in computing systems

A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.

Dynamically Optimizing Power Management Operational Parameters Of A Processor

In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed. 1. A processor comprising:at least one core;at least one thermal sensor; anda power controller including a first logic to dynamically update at least one operational parameter of a turbo mode for the at least one core, wherein the processor has a supported value for the at least one operational parameter stored in a storage.2. The processor of claim 1 , wherein the first logic is to dynamically update a time duration when a temperature of the processor is less than a thermal threshold claim 1 , the at least one operational parameter comprising the time duration.3. The processor of claim 2 , wherein the first logic is to update the time duration to an updated time duration based on a current time duration and a first value.4. The processor of claim 3 , wherein the first logic is to calculate a computed time duration based on a thermal differential between a first measured power consumption level of the processor and a second measured power consumption level of the processor claim 3 , a power step between the first measured power consumption level and the second measured power consumption level claim 3 , and a time interval over which the power step occurred.5. The processor of claim 4 , wherein the first logic is to increase the time duration when the current time duration is less than the computed time duration.6. The processor of claim 1 , wherein the first logic is to be disabled based on a first setting of a basic input/output system (BIOS).7. The processor of claim 2 , wherein the first logic is to store the updated time duration in a non-volatile storage claim 2 , to enable the first logic to access the updated time duration on a next reset of the processor.8. The processor of claim ...

DYNAMICALLY ALLOCATING A POWER BUDGET OVER MULTIPLE DOMAINS OF A PROCESSOR

In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. 1. An apparatus , comprising: a first entity having a processor including a plurality of processing cores;', 'a second entity having a graphics engine;', 'a cache;', 'an integrated memory controller;', 'a Peripheral Component Interconnect Express (PCIe™) interface;', 'first logic to dynamically allocate a power budget between the processor and the graphics engine; and', 'second logic to determine a voltage and frequency point for the graphics engine based on a thermal design power (TDP) limit., 'a system on an integrated circuit, comprising2. The apparatus of claim 1 , wherein the first logic comprises a power controller.3. The apparatus of claim 2 , wherein the power controller to dynamically allocate a power budget between the processor and the graphics engine comprises the power controller to dynamically allocate more of the power budget to the processor than the graphics engine.4. The apparatus of claim 3 , wherein the power controller to dynamically allocate a power budget between the processor and the graphics engine comprises the power controller to dynamically allocate less of the power budget to the processor than the graphics engine.5. The apparatus of claim 1 , wherein the first logic and the second logic are included in a power controller claim 1 , and wherein the second logic is configured to execute code to determine the voltage and frequency point for the graphics engine based on the TDP limit.6. The apparatus of claim 1 , wherein the TDP limit is a limit based on a power and thermal ...

Dynamically Controlling Cache Size To Maximize Energy Efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed. 1a first domain including a plurality of cores to independently execute instructions;a second domain including at least one graphics engine;a cache memory coupled to the plurality of cores and including a plurality of partitions; anda power controller coupled to the first domain and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based at least in part on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the first domain and the second domain are in a low power state.. A processor comprising: This application is a continuation of U.S. patent application Ser. No. 14/840,639, filed Aug. 31, 2015, which is a continuation of U.S. patent application Ser. No. 13/285,465, filed Oct. 31, 2011, now U.S. Pat. No. 9,158,693, issued Oct. 13, 2015, the content of which is hereby incorporated by reference.Modern processors support different low power states including package low power states in which various sub-components of the processor are either powered down or clock gated. Typically in a package low power state, cache memories of the processor are flushed and powered down. Flushing the cache memory removes context that a core might try to access on a subsequent wake up. If on wake up the core seeks to access content that was flushed from the cache, the ...

Programmable Power Management Agent

In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed. 1. A processor comprising:at least one core including a first core; and a static table to store a list of operations, and that includes a plurality of columns, each column to specify a corresponding flow, each flow to include a corresponding subset of the operations and each flow associated with a corresponding state of the first core;', 'a control register (CR) to include a plurality of storage elements, wherein each storage element corresponds to a respective operation listed in the static table, each storage element to receive one of a first value and a second value; and', 'execution logic, responsive to a command to place the first core into a first state, to execute each operation of a first flow for which the corresponding storage element stores the first value and to refrain from execution of each operation of the first flow for which the corresponding element stores the second value., 'a power management agent (PMA) coupled to the first core, the PMA to include2. The processor of claim 1 , further including a power management unit (PMU) to determine a corresponding value to be stored ...

Forcing a processor into a low power state

In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

HARDWARE UNIT FOR CONTROLLING OPERATING FREQUENCY IN A PROCESSOR

In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed. 1. A processor comprising:a plurality of processing engines to execute instructions; and control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and', 'in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve;', 'wherein, for at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve., 'a power management unit to2. The processor of claim 1 , comprising a storage to store a set of points associated with the first voltage/frequency curve.3. The processor of claim 2 , wherein the power management unit performs a curve fit of the first set of points to generate the first voltage/frequency curve.4. The processor of claim 2 , wherein the storage is to store:curve data associated with the second voltage/frequency curve; anddata defining a crossover voltage, wherein the first and second voltage/frequency curves cross at the crossover voltage,wherein the first range of voltages is above the crossover voltage, andwherein a second range of voltages is below the crossover voltage.5. The processor of claim 4 , wherein the curve data ...

Controlling operating voltage of a processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

MULTI-CORE PROCESSOR FREQUENCY LIMIT DETERMINATION

Embodiments herein relate to a technique to be performed by a power control unit (PCU) of an electronic device. Specifically, the PCU may identify, based on a metric related to an activity level of a processor core of a multi-core processor of the electronic device, first, second, and third weights that are respectively related to first, second, and third cores of the multi-core processor. Based on these weights, the PCU may identify a number of active processor cores of the multi-core processor, and alter a frequency limit of the multi-core processor accordingly. Other embodiments may be described and claimed.

Device, system and method of wireless communication

Briefly, according to embodiments of the invention, there is provided a wireless communication system and a method to receive by a base station from a first mobile station a first chain of data symbols transmitted by at least two antennas and having a first transmit diversity, to receive from a second mobile station a second chain of data symbols transmitted by at least two antennas and having a second transmit diversity. Both first and second chains of data symbols are transmitted from the first and second mobile stations at the same time, modulated according to an Orthogonal Frequency Division Multiplexing (OFDM) scheme and encoded by a space time block codes scheme.

Controlling a turbo mode frequency of a processor

In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

Package level power state optimization

Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed.

CONTROLLING OPERATING VOLTAGE OF A PROCESSOR

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

CONTROLLING A GUARANTEED FREQUENCY OF A PROCESSOR

In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed. 1. A processor comprising:one or more cores to execute instructions; anda power controller coupled to the one or more cores, the power controller including a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the at least one of the one or more cores are to operate for a next window, and to communicate the final guaranteed frequency to at least one entity.2. The processor of claim 1 , wherein control logic is to select the final guaranteed frequency to be one of a plurality of requested guaranteed frequencies indicated by the one or more sources.3. The processor of claim 2 , wherein the control logic is to select the final guaranteed frequency to be a minimum of the plurality of requested guaranteed frequencies.4. The processor of claim 1 , wherein the control logic is to calculate the final guaranteed frequency based at least in part on a power limit to be placed on the processor.5. The processor of claim 4 , wherein the control logic is to calculate the final guaranteed frequency further based on a thermal limit to be placed on the processor.6. The processor of claim 1 , further comprising a first status register to store a guaranteed frequency change indicator to indicate the dynamic change to the guaranteed frequency.7. ...

Programmable power management agent

In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

Method, apparatus, and system for energy efficiency and energy conservation including thread consolidation

An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.

Controlling Operating Voltage Of A Processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed. 1a plurality of cores; anda power controller including a control logic to receive a first request to increase an operating voltage to be provided to a first core to a second voltage and, responsive to the first request, cause a voltage regulator to increase the operating voltage to an interim voltage, thereafter enable a second core to exit an inactive state and enter an active state, and thereafter enable an operating frequency of the first core to be increased.. A processor comprising: This application is a continuation of U.S. patent application Ser. No. 15/966,397, filed Apr. 30, 2018, which is a continuation of U.S. application Ser. No. 15/157,553, filed May 18, 2016, now U.S. Pat. No. 9,996,135, issued Jun. 12, 2018, which is a continuation application of U.S. Ser. No. 13/793,037, filed Mar. 11, 2013, now U.S. Pat. No. 9,367,114, issued Jun. 14, 2016, the content of which is hereby incorporated by reference.Embodiments relate to power management of a system, and more particularly to operating voltage control in a processor.Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power ...

Application priority based power management for a computer device

Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

Power consumption monitoring device for a power source

Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal.

Dynamically updating at least one power management operational parameter pertaining to a turbo mode of a processor for increased performance

In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.

Controlling operating voltage of a processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Method and apparatus for automatic adaptive voltage control

A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT

Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block. 1. An apparatus comprising:an execution unit within a processor to execute a code block; monitor a first execution of the code block;', 'store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters;', 'read the associated metadata block upon a second execution of the code block; and', 'tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block., 'power management hardware coupled to the execution unit, wherein the power management hardware is to2. The apparatus of claim 1 , wherein the metadata block associated with the code block stores the performance data collected from executing the associated code block on two different processor cores that have different performances claim 1 , and wherein the power management hardware is to determine which one of the two ...

Apparatus and method to track device usage

In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.

METHOD AND APPARATUS OF SYSTEM SCHEDULER

Briefly, according to embodiments of the invention, there is provided a wireless communication system and a method to receive by a base station from a first mobile station a first chain of data symbols transmitted by at least two antennas and having a first transmit diversity, to receive from a second mobile station a second chain of data symbols transmitted by at least two antennas and having a second transmit diversity. Both first and second chains of data symbols are transmitted from the first and second mobile stations at the same time, modulated according to an Orthogonal Frequency Division Multiplexing (OFDM) scheme and encoded by a space time block codes scheme.

Synchronization of domain counters

In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

Forcing a processor into a low power state

In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Device, system and method of point to multipoint communication

Some embodiments of the invention provide devices, systems and methods of point to multipoint communication. For example, an apparatus in accordance with an embodiment of the invention includes a resource allocator to allocate a wireless communication channel resource to one or more stations of a wireless communication system based on a net benefit function that takes into account an overhead incurred by controlling the allocation of said channel resource.

Dynamically controlling cache size to maximize energy efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

METHOD AND APPARATUS OF SYSTEM SCHEDULER

Briefly, according to embodiments of the invention, there is provided a wireless communication system and a method to receive by a base station from a first mobile station a first chain of data symbols transmitted by at least two antennas and having a first transmit diversity, to receive from a second mobile station a second chain of data symbols transmitted by at least two antennas and having a second transmit diversity. Both first and second chains of data symbols are transmitted from the first and second mobile stations at the same time, are modulated according to an Orthogonal Frequency Division Multiplexing (OFDM) scheme and encoded by a space time block codes scheme.

PERFORMING SOFT THROTTLING AND HARD THROTTLING IN A PROCESSOR

In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed. 1. A processor comprising:a plurality of processing engines to execute instructions; and in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine;', 'determine a ratio of the soft throttling events to the hard throttling events;', 'compare the determined ratio to a desired goal; and', 'adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal., 'power limit logic to2. The processor of claim 1 , the power limit logic to:detect a first power spike based on a determination that a level of electrical current provided to the first processing engine exceeds a threshold value;in response to the first power spike, perform soft throttling in the first processing engine;after completion of the soft throttling, determine whether the first power spike was resolved by the soft throttling; andin response to a determination that the first power spike was not resolved by the soft throttling, perform hard throttling in the first processing engine.3. The processor of claim 2 , wherein the soft throttling comprises a first reduction of an operating frequency of the first processing engine claim 2 , wherein the hard throttling comprises a second reduction of the operating frequency of the first processing engine claim 2 , and wherein ...

USING DEVICE IDLE DURATION INFORMATION TO OPTIMIZE ENERGY EFFICIENCY

Systems and methods may provide for aggregating a first idle duration from a first device associated with a platform and a second idle duration from a second device associated with the platform. Additionally, an idle state may be selected for the platform based at least in part on the first idle duration and the second idle duration. In one example, the idle durations are classified as deterministic, estimated or statistical. 1. An apparatus comprising:first aggregator logic to aggregate a first idle duration from a first device and a second idle duration from a second device; andpower management logic to select an idle state for the platform based at least in part on the first idle duration and the second idle duration.2. The apparatus of claim 1 , wherein the first aggregator logic is to claim 1 ,identify the first idle duration and the second idle duration as deterministic idle durations, anddetermine a platform idle duration based at least in part on the deterministic idle durations, wherein the idle state is to be selected based at least in part on the platform idle duration.3. The apparatus of claim 2 , wherein the first aggregator logic is to determine a first latency tolerance associated with the platform idle duration claim 2 , and the power management logic is to conduct a pre-wake activity prior to an expiration of the platform idle duration.4. The apparatus of claim 3 , further including a register to store a second latency tolerance claim 3 , wherein the first aggregator logic is to claim 3 ,determine a wake duration for the platform based at least in part on the second latency tolerance, wherein the second latency tolerance is to be less than the first latency tolerance; anduse the wake duration to monitor a device associated with the platform idle duration for activity.5. The apparatus of claim 3 , wherein the power management logic is to compensate one or more of the platform idle duration and the pre-wake activity for clock drift.6. The apparatus of ...

Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations ( 1 ) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and ( 2 ) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING THREAD CONSOLIDATION

An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.

MECHANISM FOR FACILITATING FASTER SUSPEND/RESUME OPERATIONS IN COMPUTING SYSTEMS

A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state. 1. A method comprising:initiating an entrance process into a first sleep state in response to a sleep call at a computing system;transforming from the first sleep state to a second sleep state, wherein transforming includes preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system; andentering the second sleep state.2. The method of claim 1 , further comprising:initiating an exit process from the second sleep state in response to a wakeup call;restoring the preserved processor context from the local memory; andexiting the second sleep state.3. The method of claim 1 , further comprising notifying a platform controller at the computing system to enter a reduced power for entering the second sleep state.4. The method of claim 1 , wherein entering the second sleep state comprises entering a reduced power state of the computing system claim 1 , wherein powering down includes powering down one or more devices coupled to the computing system claim 1 , wherein the one or more devices include one or more of memory devices or peripheral devices.5. The method of claim 1 , wherein initiating the entrance process comprises initiating an S3 sequence at an operating system at the computing system claim 1 , wherein the first sleep state includes an S3 state.6. The method of claim 5 , wherein ...

Dynamically Controlling Cache Size To Maximize Energy Efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed. 1. A method comprising:determining, in a power controller of a multicore processor, whether a memory dependency value of a workload is greater than a first threshold, and if so enabling all of a plurality of ways of a cache memory of the multicore processor; andotherwise determining, in the power controller, if the memory dependency value is less than a third threshold, and if so disabling at least one way of the cache memory.2. The method of claim 1 , further comprising enabling at least one more way of the cache memory if the memory dependency value is greater than a second threshold claim 1 , the second threshold between the first and second thresholds.3. The method of claim 1 , further comprising enabling all of the plurality of ways of the cache memory if time spent in an active state is greater than a time interval threshold.4. The method of claim 1 , further comprising calculating the memory dependency value of the workload.5. The method of claim 4 , wherein calculating the memory dependency value of the workload includes determining an order buffer residency during a time interval.6. The method of claim 5 , further comprising updating a counter of an entry of an order buffer for each cycle that an outstanding load operation is stored in the order buffer entry.7. The method of claim 6 , further comprising:determining an average of a plurality of counters, each counter of an entry of the order buffer; andcalculating a ratio between the average and a length of the time interval.8. The method of claim 7 , further comprising controlling a size of the cache memory based at ...

Controlling Operating Voltage Of A Processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed. 1a plurality of cores; anda power controller including a control logic to receive a first request to increase an operating voltage to be provided to a first core to a second voltage and, responsive to the first request, cause a voltage regulator to increase the operating voltage to an interim voltage, thereafter enable a second core to exit an inactive state and enter an active state, and thereafter enable an operating frequency of the first core to be increased.. A processor comprising: This application is a continuation of U.S. patent application Ser. No. 15/157,553, filed May 18, 2016, which is a continuation application of U.S. patent Ser. No. 13/793,037, filed Mar. 11, 2013, now U.S. Pat. No. 9,367,114, issued Jun. 14, 2016, the content of which is hereby incorporated by reference.Embodiments relate to power management of a system, and more particularly to operating voltage control in a processor.Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its ...

Providing Lifetime Statistical Information For A Processor

In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed. 1. A processor comprising:at least one core;a power control unit (PCU) coupled to the at least one core, the PCU including a stress detector to receive at least one of a voltage and a temperature at which the processor is to operate and to calculate an effective reliability stress, and to maintain the effective reliability stress over a plurality of boot cycles;a non-volatile storage to store the effective reliability stress; andan interface to enable a user to access at least the effective reliability stress.2. The processor of claim 1 , wherein the stress detector includes a reliability odometer to receive the voltage and the temperature.3. The processor of claim 1 , wherein the non-volatile storage is present in a peripheral controller hub (PCH) coupled to the processor claim 1 , and the PCU is to obtain the effective reliability stress from the PCH via a first message.4. The processor of claim 1 , wherein the PCU is to control a plurality of operating parameters of the processor based on the effective reliability stress and to update at least one of the plurality of operating parameters of the processor to a first degraded level when the effective reliability stress reaches a ...

Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor

In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. 1. An apparatus comprising:a multi-domain processor including a first domain and a second domain, each of the first and second domains to operate at an independent voltage and frequency, the multi-domain processor further including first logic to dynamically allocate a power budget for the multi-domain processor between the first and second domains at run time.2. The apparatus of claim 1 , wherein the first logic is to dynamically allocate the power budget according to a first sharing policy value for the first domain and a second sharing policy value for the second domain claim 1 , the first and second sharing policy values controllable by user-level software.3. The apparatus of claim 2 , wherein the first logic is to determine a portion of the power budget to allocate to the first domain based on the first sharing policy value.4. The apparatus of claim 2 , wherein the first logic is to dynamically allocate the power budget further according to a first minimum reservation value for the first domain and a second minimum reservation value for the second domain claim 2 , the first and second minimum reservation values controllable by the user-level software.5. The apparatus of claim 4 , wherein the first logic is to provide at least a first portion of the power budget to the first domain claim 4 , the first portion corresponding to the first minimum reservation value.6. The apparatus of claim 1 , wherein the first logic is to determine the power budget for a current time interval based at least in part on ...

System, apparatus and method of scheduling transmissions

Briefly, a wireless system, a base station and a method of scheduling data transmissions by allocating resources to a mobile station based on at least an estimated obsoleteness rate of a channel knowledge of the mobile station.

System maximum current protection

A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.

Flushing and restoring core memory content to external memory

A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality ...

METHODS AND APPARATUS TO DYNAMICALLY CONFIGURE OVERCLOCKING FREQUENCY

Methods, apparatus, and articles of manufacture to dynamically configure overclocking frequency have been disclosed. An example apparatus include a clock rate adjuster to cause a processor core to operate at a first overclocked clock rate; a comparator to compare a sensed temperature corresponding to the processor core to a threshold; and the clock rate adjuster to, when the sensed temperature satisfies the threshold, decrease a clock rate of the processor core from the first overclocked clock rate by a user-defined amount, the decreased clock rate being above a normal operating clock rate of the processor core.

Device, system and method of wireless communication

Briefly, according to embodiments of the invention, there is provided a wireless communication system and a method to receive by a base station from a first mobile station a first chain of data symbols transmitted by at least two antennas and having a first transmit diversity, to receive from a second mobile station a second chain of data symbols transmitted by at least two antennas and having a second transmit diversity. Both first and second chains of data symbols are transmitted from the first and second mobile stations at the same time, modulated according to an Orthogonal Frequency Division Multiplexing (OFDM) scheme and encoded by a space time block codes scheme.

SYSTEM MAXIMUM CURRENT PROTECTION

A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit. 1. A method comprising:calculating a sum of expected powers for a plurality of domains in an IC for a new state;comparing the sum to a power limit; andif the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit by reducing the individual domain frequency associated with at least one domain in the plurality of domains according to a relationship between the power limit and the sum of the expected powers.2. The method defined in wherein calculating the expected current for each of the plurality of domains is based on current leakage claim 1 , target frequency claim 1 , and dynamic capacitance (C).3. The method defined in wherein calculating the expected current for each of the plurality of domains comprises calculating active and static current and summing the active and static current.4. The method defined in wherein calculating active current comprises summing worst case Cfor each core in the domain that is in a waking state and multiplying the worst case Cby the frequency and the associated voltage for the domain claim 3 , wherein the ...

Power consumption monitoring device for a power source

Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

Dynamically controlling cache size to maximize energy efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

APPARATUS AND METHOD FOR CONTROLLING THE RELIABILITY STRESS RATE ON A PROCESSOR

An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate. 1. A processor comprising:stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; andstress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.2. The processor as in wherein the stress tracked by the stress tracking logic comprises an accumulated stress tracking logic tracks a rate of stress accumulation experienced by the one or more portions of the processor.3. The processor as in wherein the stress tracking logic tracks stress for N portions of the processor claim 1 , wherein N>1.4. The processor as in wherein the stress tracking logic outputs N different stress measurements claim 3 , one for each of the N portions of the processor.5. The processor as in wherein the stress control logic determines N different limits on the operating characteristics claim 4 , one for each of the N portions of the processor claim 4 , the processor further comprising first minimization logic to determine a minimum of the N different limits.6. The processor as in further comprising second minimization logic to determine a minimum of a desired operating characteristic of the processor and the minimum of the N different limits determined by the first minimization logic.7. The processor as in wherein the operating characteristics of the processor comprises a frequency at ...

METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate. 1. A processor comprising:a plurality of processing cores;at least one cache memory; anda power management unit to receive a first request from an operating system for entry into a first power saving state into which the processor is to be placed, demote the processor to a second power saving state, which is a lesser power saving state than the first power saving state if a low activity period of the processor overlaps with a burst of high interrupt rate, and un-demote the processor to a third power saving state, which is a greater power saving state than the first power saving state in response to determining that an interrupt rate is low, without receipt of an interrupt from the operating system.2. The processor of claim 1 , wherein the power management unit is to un-demote the processor to a fourth power saving state claim 1 , which is a greater power saving state than the third power saving state if a sleep duration of the processor in the third power saving state exceeds a demotion threshold.3. The processor of claim 2 , wherein the power management unit is to track the sleep ...

Dynamically Controlling Cache Size To Maximize Energy Efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores, wherein each of the plurality of cores includes a plurality of caches;a shared cache coupled to the plurality of cores, wherein the shared cache is to be shared by the plurality of cores, and wherein the shared cache includes a plurality of portions that each include at least one way; and determine a number of cache hits, and a number of cache misses, to the shared cache from the plurality of cores;', 'provide control for a dynamically variable size of the shared cache available for use by the plurality of cores, through at least one of the plurality of portions being enabled or disabled, based at least in part on the determined numbers of cache hits and cache misses; and', 'provide control for at least one of the plurality of portions of the shared cache being maintained in a retention state, when the plurality of cores are to be in a low power state, and while at least another of the plurality of portions of the shared cache is to be in a lower power state than the retention state, wherein in the retention state data stored in the at least one of the plurality of portions, which is being maintained in the retention state, is to be retained., 'a power control circuitry coupled to the plurality of cores and to the shared cache, the power control circuitry to2. The processor of claim 1 , wherein the shared cache is to be shared by the plurality of cores and a graphics unit.3. The processor of claim 2 , wherein the power control circuitry is to control the shared cache based on an assignment of one or more ways of the shared cache to ...

Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency

Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

CONTROLLING OPERATING VOLTAGE OF A PROCESSOR

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Power control arbitration

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Controlling A Turbo Mode Frequency Of A Processor

In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

Controlling operating frequency of a processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

FLUSHING AND RESTORING CORE MEMORY CONTENT TO EXTERNAL MEMORY

A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores. 1. An integrated circuit (IC) comprising:a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; anda power management controller coupled to the plurality of cores and located outside the plurality of cores.2. The processor defined in wherein the first memory is a static random access memory (SRAM) and the second memory is a ...

PACKAGE LEVEL POWER STATE OPTIMIZATION

Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed.

Controlling Forced Idle State Operation In A Processor

In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores; anda power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state.2. The processor of claim 1 , wherein the first logic is to determine that the processor resided in the forced idle state or a deeper package idle state for less than the threshold duration responsive to an exit of the processor from the forced idle state to handle an event.3. The processor of claim 1 , wherein the first logic is to prevent the processor from entry into the forced idle state for a first time duration.4. The processor of claim 3 , wherein the first logic is to reset an enable indicator of a control register of the processor to prevent the processor from entry into the forced idle state.5. The processor of claim 3 , wherein the first logic is to enable the processor to enter the forced idle state after the first time duration.6. The processor of claim 1 , wherein the first logic is to maintain the processor enabled for entry into the forced idle state responsive to a determination that the processor resided in the forced idle state for at least the threshold duration.7. The processor of claim 5 , wherein the first logic is to reset the first counter responsive to the determination that the processor resided in the forced idle state for at least the ...

Techniques and system for managing platform temperature

In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.

METHOD AND APPARATUS OF SYSTEM SCHEDULER

Briefly, according to embodiments of the invention, there is provided a wireless communication system and a method to receive by a base station from a first mobile station a first chain of data symbols transmitted by at least two antennas and having a first transmit diversity, to receive from a second mobile station a second chain of data symbols transmitted by at least two antennas and having a second transmit diversity. Both first and second chains of data symbols are transmitted from the first and second mobile stations at the same time, modulated according to an Orthogonal Frequency Division Multiplexing (OFDM) scheme and encoded by a space time block codes scheme.

Controlling a guaranteed frequency of a processor

In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.

Dynamically controlling cache size to maximize energy efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Controlling operating voltage of a processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

System, apparatus and method for controlling a processor based on effective stress information

In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

Controlling current transients in a processor

In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency

Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

Method and apparatus of system scheduler

Briefly, according to embodiments of the invention, there is provided a wireless communication system and a method to receive by a base station from a first mobile station a first chain of data symbols transmitted by at least two antennas and having a first transmit diversity, to receive from a second mobile station a second chain of data symbols transmitted by at least two antennas and having a second transmit diversity. Both first and second chains of data symbols are transmitted from the first and second mobile stations at the same time, modulated according to an Orthogonal Frequency Division Multiplexing (OFDM) scheme and encoded by a space time block codes scheme.

Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor

In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. 1. A processor comprising:a first domain and a second domain, each of the first and second domains to operate at an independent voltage and frequency;a memory controller coupled to the first and second domains;at least one interface; andfirst logic to dynamically allocate a power budget for the processor between the first and second domains at run time.2. The processor of claim 1 , wherein the first logic is to dynamically allocate the power budget according to a first sharing policy value for the first domain and a second sharing policy value for the second domain claim 1 , the first and second sharing policy values controllable by user-level software.3. The processor of claim 2 , wherein the first logic is to determine a portion of the power budget to allocate to the first domain based on the first sharing policy value.4. The processor of claim 2 , wherein the first logic is to dynamically allocate the power budget further according to a first minimum reservation value for the first domain and a second minimum reservation value for the second domain claim 2 , the first and second minimum reservation values controllable by the user-level software.5. The processor of claim 4 , wherein the first logic is to provide at least a first portion of the power budget to the first domain claim 4 , the first portion corresponding to the first minimum reservation value.6. The processor of claim 1 , wherein the first logic is to determine the power budget for a current time interval based at least in part on a power ...

AUTONOMOUS C-STATE ALGORITHM AND COMPUTATIONAL ENGINE ALIGNMENT FOR IMPROVED PROCESSOR POWER EFFICIENCY

Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:logic, at least a portion of which is in hardware, to determine whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states.2. The apparatus of claim 1 , comprising logic to calculate the energy consumption values for entry into and exit from the package C state.3. The apparatus of claim 1 , comprising logic to detect a delay by an imaging computational unit of the semiconductor package to enter a low power consumption state relative to one or more other computational units of the semiconductor package.4. The apparatus of claim 3 , wherein the logic to detect the delay is to cause the imaging computational unit to enter the low power consumption state in response to detection of the delay.5. The apparatus of claim 1 , further comprising one or more sensors to detect variations in one or more of: temperature claim 1 , operating frequency claim 1 , operating ...

Apparatus And Method To Track Device Usage

In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed. 1. A processor comprising:measurement logic to measure a usage associated with the processor;statistical logic to determine based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication of a defined increase in the usage; andcontrol logic to record the defined increase in the usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic.2. The processor of claim 1 , further comprising the non-volatile memory to store each instance of a plurality of successive instances of the defined increase in the usage.3. The processor of claim 2 , wherein the non-volatile memory comprises programmable fuses.4. The processor of claim 1 , wherein the statistical logic is to determine whether to provide the permission to record the defined increase in the usage based on a comparison of a test number that is randomly selected from a pool comprising a set of defined numbers claim 1 , to a reference number.5. The processor of claim 4 , wherein the statistical logic is to select one of the defined numbers in the pool as the reference number.6. The processor of claim 5 , wherein the statistical logic is to repeat the determination for each successive instance of receipt of the indication of the defined increase in the usage claim 5 , and wherein the reference number remains a same value in each successive determination.7. ...

TECHNIQUES AND SYSTEM FOR MANAGING PLATFORM TEMPERATURE

In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed. 1. An apparatus , comprising:a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform; anda controller comprising logic at least a portion of which is in hardware, the logic to receive from the temperature sensor the multiplicity of junction temperature measurements and to instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and to instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold.2. The apparatus of claim 1 , the first threshold comprising a maximum junction temperature Tfor the component claim 1 , the logic to perform a rapid throttling of the component when the first threshold is exceeded claim 1 , the rapid throttling comprising reducing micro-operations input rate and/or operating frequency for the component.3. The apparatus of claim 1 , the second threshold comprising a maximum steady state junction temperature T claim 1 , the logic to perform a controlled power down of the component when the second threshold is exceeded claim 1 , ...

Dynamically Controlling Cache Size To Maximize Energy Efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed. 1. A processor comprising:a first domain including a plurality of cores each to independently execute instructions;a second domain including at least one graphics engine;a cache memory coupled to the plurality of cores and including a plurality of partitions; anda power controller coupled to the first domain and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based at least in part on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the first domain and the second domain are in a low power state.2. The processor of claim 1 , wherein the plurality of partitions correspond to ways of the cache memory claim 1 , and wherein the power controller is to dynamically enable or disable each of a plurality of ways independently.3. The processor of claim 2 , wherein the power controller is to cause at least one first way of the cache memory to be enabled with the retention voltage when the processor is in the package low power state.4. The processor of claim 3 , wherein the power controller is to cause at least one second way of the cache memory to be disabled while the at least one first way is enabled with the retention voltage when the processor is in the package low power state claim 3 , wherein the at least one second way is to be flushed to a system ...

Dynamically Controlling Cache Size To Maximize Energy Efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed. 1a first domain including a plurality of cores to independently execute instructions;a second domain including at least one graphics engine;a cache memory coupled to the plurality of cores and including a plurality of partitions; anda power controller coupled to the first domain and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based at least in part on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the first domain and the second domain are in a low power state.. A processor comprising: This application is a continuation of U.S. patent application Ser. No. 15/270,208, filed Sep. 20, 2016, which is a continuation of U.S. patent application Ser. No. 14/840,639, filed Aug. 31, 2015, now U.S. Pat. No. 9,471,490, issued Oct. 18, 2016, which is a continuation of U.S. patent application Ser. No. 13/285,465, filed Oct. 31, 2011, now U.S. Pat. No. 9,158,693, issued Oct. 13, 2015, the content of which is hereby incorporated by reference.Modern processors support different low power states including package low power states in which various sub-components of the processor are either powered down or clock gated. Typically in a package low power state, cache memories of the processor are flushed and powered down. Flushing the cache memory removes context ...

Autonomous c-state algorithm and computational engine alignment for improved processor power efficiency

Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

Power control arbitration

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

BALANCED CONTROL OF PROCESSOR TEMPERATURE

In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores;a plurality of temperature sensors, wherein each core is proximate to at least one temperature sensor; anda power control unit (PCU) including temperature logic to receive temperature data including a corresponding temperature value from each of the temperature sensors, and responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores, wherein each domain frequency is associated with a corresponding domain that includes at least of one of the plurality of cores and each domain frequency is independently adjustable.2. The processor of claim 1 , wherein the temperature logic includes temperature assessment logic to identify the highest temperature value of the temperature values received from the temperature sensors.3. The processor of claim 2 , wherein the temperature logic further includes a low pass filter to determine a temperature ...

BALANCED CONTROL OF PROCESSOR TEMPERATURE

In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed. 1a plurality of cores;a plurality of temperature sensors, wherein each core is proximate to at least one temperature sensor; anda power control unit (PCU) including temperature logic to receive temperature data including a corresponding temperature value from each of the temperature sensors, and responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores, wherein each domain frequency is associated with a corresponding domain that includes at least of one of the plurality of cores and each domain frequency is independently adjustable.. A processor comprising: This application is a continuation of U.S. patent application Ser. No. 14/461,039, filed Aug. 15, 2014, the content of which is hereby incorporated by reference.Embodiments relate to balanced control of processor temperature.Advances in semiconductor processing and logic design have permitted an increase in the amount of logic ...

Method and apparatus for automatic adaptive voltage control

A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

SYNCHRONIZATION OF DOMAIN COUNTERS

In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed. 1. A processor comprising:a master counter to store a time stamp count for the processor;a plurality of cores, each core including a core counter to store a time stamp count for the core; and obtain a value of the master counter;', 'initiate a first core counter using the value of the master counter, wherein the first core counter is included in the first core;', 'compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and', 'in response to a determination that the synchronization digit of the first core counter does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal., 'synchronization logic to, in response to a de-synchronization event in a first core of the plurality of cores2. The processor of claim 1 , wherein the synchronization logic is to:in response to a determination that an edge of the synchronization digit of the first core counter does not match an edge of the synchronization signal, set the ...

ENERGY MONITOR FOR A POWER SOURCE

Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed. 1. An apparatus comprising:a current sensor to provide a first voltage that indicates a current delivered by an energy source;a voltage sensor to provide a second voltage that indicates voltage measurement of a voltage associated with the current delivered by the energy source; anda controller comprising logic, at least a portion of which is in hardware, the controller to digitize the first voltage, and to accumulate the digitized first voltage when triggered by a signal based upon the second voltage, and to scale an accumulation of digitized first voltages into a measurement of energy.2. The apparatus of claim 1 , the controller further to digitize the second voltage.3. The apparatus of claim 2 , the controller to digitize at a periodic rate from about 1.0 GHz to about 5.0 GHz.4. The apparatus of claim 2 , the controller to digitize at a periodic rate that is responsive to an operating mode of the apparatus.5. The apparatus of claim 2 , the controller further to accumulate digitized second voltages using a voltage measurement accumulator claim 2 , and to trigger accumulation ...

Controlling A Turbo Mode Frequency Of A Processor

In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores to independently execute instructions; anda power controller coupled to the plurality of cores to control a frequency at which the processor is to operate, the power controller to limit a maximum operating frequency of the processor to less than a configured maximum operating frequency, wherein the power controller is to analyze a plurality of power state change events during an evaluation interval to determine, for each of N-core turbo frequencies, a number of frequency transitions if the processor was to operate at the N-core turbo frequency at occurrence of the plurality of power state change events, select one of the N-core turbo frequencies to be the maximum operating frequency for a next operating interval based at least in part on the number of frequency transitions, and control the plurality of cores to operate at no higher than the selected N-core turbo frequency for the next operating interval.2. The processor of claim 1 , wherein the selected N-core turbo frequency is less than the configured maximum operating frequency.3. The processor of claim 1 , wherein the power controller is coupled to a table including a plurality of entries each associated with an N-core turbo frequency and to store a counter value corresponding to the number of frequency transitions during the evaluation interval if the processor was to operate at the N-core turbo frequency.4. The processor of claim 3 , wherein ...

PROCESSOR VOLTAGE CONTROL USING RUNNING AVERAGE VALUE

In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed. 1. A processor comprising:a plurality of components, a first component of the plurality of components to receive a power input from a power supply device; and determine a received voltage at a power input terminal of the first component;', 'determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component;', 'determine a running average value based on the voltage difference; and', 'adjust a supply voltage of the power supply device based on the running average value., 'a power control unit to2. The processor of claim 1 , the power control unit further to:determine that the running average value is below a first value; andin response to determining that the running average value is below the first value, reduce the supply voltage.3. The processor of claim 1 , the power control unit further to:determine that the running average value is above a first value; andin response to determining that the running average value is above the first value, increase the supply voltage.4. The processor of claim 3 , wherein the first value is zero.5. The processor of claim 3 , wherein the first value is an earlier running average value claim 3 , wherein the earlier running average value is determined prior to determining the running average value.6. The processor of claim 1 , the ...

Forcing A Processor Into A Low Power State

In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Dynamically Controlling Cache Size To Maximize Energy Efficiency

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores, wherein each of the plurality of cores includes a plurality of caches;a shared cache coupled to the plurality of cores, wherein the shared cache is to be shared by the plurality of cores, and wherein the shared cache includes a plurality of portions that each include at least one way; and determine a number of cache hits, and a number of cache misses, to the shared cache from the plurality of cores;', 'provide control for a dynamically variable size of the shared cache available for use by the plurality of cores, through at least one of the plurality of portions being enabled or disabled, based at least in part on the determined numbers of cache hits and cache misses; and', 'provide control for at least one of the plurality of portions of the shared cache being maintained in a retention state, when the plurality of cores are to be in a low power state, and while at least another of the plurality of portions of the shared cache is to be in a lower power state than the retention state, wherein in the retention state data stored in the at least one of the plurality of portions, which is being maintained in the retention state, is to be retained., 'a power control circuitry coupled to the plurality of cores and to the shared cache, the power control circuitry to2. The processor of claim 1 , wherein the shared cache is to be shared by the plurality of cores and a graphics unit.3. The processor of claim 2 , wherein the power control circuitry is to control the shared cache based on an assignment of one or more ways of the shared cache to ...

APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE

Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed. 1. A computer device , comprising:one or more processors; receive a first power information including a first priority information for a first application to be operated on the one or more processors, and a second power information including a second priority information for a second application to be operated on the one or more processors, wherein the first priority information is different from the second priority information;', 'determine to control a first power consumption based on the first power information for the first application to be operated on the one or more processors, and to control a second power consumption based on the second power information for the second application to be operated on the one or more processors., 'a power control unit coupled to the one or more processors, wherein the power control unit is to2. The computer device of claim 1 , wherein the first priority information is to indicate that the first application is of a power class selected from a quality of service application class claim 1 , a background application class claim 1 , a user experience application class claim 1 , a mission critical application class claim 1 , or a responsiveness application class.3. The computer device of claim 1 , wherein the first power information further includes a minimal allowable voltage claim 1 , a maximal allowable voltage claim 1 , a minimal allowable frequency claim 1 , or ...

Power consumption monitoring device for a power source

Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

Controlling Operating Voltage Of A Processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

SYSTEM MAXIMUM CURRENT PROTECTION

A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit. 1. A method comprising:prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state;comparing the sum to a power limit; andif the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.2. The method defined in wherein calculating the expected current for each of the plurality of domains based on current leakage claim 1 , target frequency claim 1 , and dynamic capacitance (C).3. The method defined in wherein calculating the expected current for each of the plurality of domains comprises calculating active and static current and summing the active and static current.4. The method defined in wherein calculating active current comprises summing worst case Cfor each core in the domain that is in a waking state and multiplying ...

System, Apparatus And Method For Controlling A Processor Based On Effective Stress Information

In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT

A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data. 1. An apparatus comprising;an execution unit within a processor to execute a code block that has been compiled to have a reserved space, including a metadata block associated with the code block or an identifier of the metadata block, appended to one end of the code block, and monitor a first execution of the code block;', 'store a micro-architectural context of the processor in the metadata block, the micro-architectural context including performance data resulting from the first execution of the code block;', 'read the metadata block upon a second execution of the code block; and', 'tune the second execution based on the performance data to increase efficiency of executing the code block., 'performance management hardware coupled to execution unit, wherein the performance management, hardware is adapted to2. The apparatus of claim 1 , wherein the reserved space contains the metadata block claim 1 , and wherein the code block and the metadata block are stored in system memory.3. The apparatus of claim 1 , wherein the reserved space contains the identifier of the metadata block claim 1 , and wherein a copy of the identifier and the metadata block are stored within the performance management hardware.4. The apparatus of claim 1 , ...

Dynamically allocating a power budget over multiple domains of a processor

In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

Dynamically allocating a power budget over multiple domains of a processor

In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

Dynamically allocating a power budget over multiple domains of a processor

In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

Method and apparatus of system scheduler

Briefly, according to embodiments of the invention, there is provided a wireless communication system and a method to schedule a wireless system resource. The wireless communication resource is being used by both first and second wireless communication devices. The first and second communication devices are able to transmit space time block codes according to a predetermined diversity scheme on substantially the same Time-Frequency resources.

Controlling a turbo mode frequency of a processor

在一實施例中，本發明提供一種多核心處理器具有一電力控制器以控制該處理器操作的一頻率。更精確地，該電力控制器可限定該處理器一最高操作頻率低於一組配的最高操作頻率以使一反應於電力狀態事件而發生的頻率轉換次數降低，從而避免因應付此等轉換執行的操作造成的負載。其他實施例同時被描述並請求。

mobile station configured to operate on a long-term evolving cellular system

método e aparelho para programador de sistema a presente invenção refere-se a um sistema de comunicação sem-fio e a um método para programar um recurso do sistema sem-fio. o recurso de comunicação sem-fio está sendo utilizado tanto por um primeiro como por um segundo dispositivo de comunicação sem-fio. o primeiro e o segundo dispositivos de comunicação estão aptos a transmitir códigos de bloco tempo-espaço de acordo com o esquema de diversidade predeterminado substancialmente em relação aos mesmos recursos de tempo - frequência Method and Apparatus for System Programmer The present invention relates to a wireless communication system and a method for programming a wireless system feature. The wireless communication feature is being used by both a first and a second wireless communication device. the first and second communication devices are capable of transmitting time-space block codes according to the predetermined diversity scheme substantially with respect to the same time-frequency resources.

Apparatus and method for controlling the reliability stress rate on a processor

An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.

Balanced control of processor temperature

Techniques for flexible and dynamic frequency-related telemetry

Mechanism for saving and retrieving micro-architecture context

Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

Controlling operating voltage of a processor

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Techniques and system for managing platform temperature

In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.

A method, apparatus, and system for energy efficiency and energy conservation including optimizing c-state selection under variable wakeup rates

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1 ) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

Apparatus and method to track device usage

In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.

Method and apparatus for providing power state information using in-band signaling

A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

Performing soft throttling and hard throttling in a processor

Performing soft throttling and hard throttling in a processor

In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.