Power control circuitry for controlling power domains

Power control circuitry for controlling power domains

A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus 2. The mapping parameters may be fixed or software programmable. The mapping parameters may be accessible as memory mapped values within a memory address space of a data processing apparatus.

Message handling unit

An integrated circuit 2 has first and second power domains 4, and a message handling unit 20. The unit passes messages sent from a device 8 in the first power domain to a receiver device 8 in the second power domain. The message handling unit 20 writes messages sent from the sender device to a message storage area in the second power domain. If a communication device in the second power domain is in a quiescent state, then the message handling unit sends a wakeup signal to a power controller 6 to request that the communication device enter an awake state. The communication device may be the storage area of the message passing unit. The unit may use a status parameter or an interrupt to indicate to devices in the first domain that the second domain is ready to receive messages. The unit may pass messages in a single direction and a second unit may be used to pass messages in the opposite direction.

Reset isolation bridge

Interface apparatus and method

An interface comprises routing means 530 configured to receive data items from a data source device 500 and to route the received data items to a data sink device 510 by either a first data path including a data buffer 560 or a second data path 570, in response to an indication of a current state of a data sink device; the routing means being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing means being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing means receives a subsequent indication that the data sink device is ready to receive the data item; and the routing means being configured to route the received data item by the second data path in response to an indication that the ...

Reset isolation bridge

Disclosed is an integrated circuit 2 with two domains 4, the first domain has a power controller 22 to control the power state of a device 20 in the second domain based on power management signals exchanged on a power management channel 24 between the domains. The circuit has a reset isolation bridge 40 on the power management channel between the domains. The bridge has first and second interfaces (42, 44 fig 11) to exchange the power management signals with the first and second domains respectively. Isolating circuitry is provided in the bridge to respond to a reset indication 8 indicating reset of one of the domains, to isolate state transitions of the power management signals at the first and second interfaces from each other. The domains may have independent reset trees. In response to a reset indication the isolating circuitry may trigger a state transition of the power management signals at one of the interfaces during a reset period, until the power management signals at the interfaces ...

Message handling unit to control passing of messages between power domains in an integrated circuit