Under die surface mounted electrical elements

A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element.

Managing interconnect electromigration effects

A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.

SYSTEM AND METHOD OF ACHIEVING MECHANICAL AND THERMAL STABILITY IN A MULTI-CHIP PACKAGE

A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package. 1. A system for achieving mechanical and thermal stability in a multi-chip package , the system comprising:plural thermal interface materials arranged between chips and a lid of the multi-chip package.2. The system of claim 1 , wherein the lid is a stepped lid that covers the chips of the multi-chip package.3. The system of claim 1 , wherein the plural thermal interface materials comprise:a first thermal interface material arranged on one chip; anda second thermal interface material arranged on another chip.4. The system of claim 3 , wherein the first and second materials are different thicknesses.5. The system of claim 3 , wherein the first and second materials are different materials.6. The system of claim 3 , wherein the first and second materials are materials have different thermal properties.7. The system of claim 1 , wherein the multiple thermal interface materials comprise:a first thermal interface material having a first thickness and a first conductivity; anda second thermal interface material having a second thickness and a second conductivity,wherein the second thickness is greater than the first thickness and the first conductivity is greater than the second conductivity.8. The system of claim 7 , wherein the first thermal interface material is arranged on a first chip and the second thermal interface material is arranged on a second chip.9. The system of claim 8 , wherein the first chip is a higher-power chip than the second chip.10. The system of claim 8 , wherein the second chip is a thinned chip.11. The system of claim 7 , wherein one of:the first thermal interface material is arranged between a first chip and a first surface of the lid and the ...

ELECTRONIC DEVICE CONSOLE WITH NATURAL DRAFT COOLING

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation. 1. An electronic device console , comprising:a console body that houses a chip package;a duct extending from the console body, wherein an interior volume of the duct is in fluid communication with an interior volume of the console body;a first vent at a distal end of the duct; anda second vent in a wall of the console body;wherein the console is structured and arranged to be oriented in a first orientation and a second orientation;the duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation; andthe console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.2. The console of claim 1 , wherein the console is devoid of a fan.3. The console of claim 1 , wherein a length of the duct is greater than a width of the duct.4. The console of claim 1 , wherein:the first vent is an outlet and the second vent is an inlet in the first orientation; andthe first vent is an inlet and the second vent is an outlet in the second orientation.5. The console of claim 1 , wherein:the first vent is vertically aligned with the chip package in the first orientation; andthe second vent is vertically aligned with the chip package in the second orientation.6. The console ...

ELECTRONIC DEVICE CONSOLE WITH NATURAL DRAFT COOLING

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.

ELECTRONIC DEVICE CONSOLE WITH NATURAL DRAFT COOLING

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation. 1. An electronic device console , comprising:a console body that houses a chip package;a duct extending from the console body;a first vent at a distal end of the duct; anda second vent in a wall of the console body,wherein the electronic device console is structured and arranged to be oriented in a first orientation and a second orientation, andthe electronic device comprises a slide mechanism positioned at a top orientation of the console body such that a proximate end of the duct is moveable into the console body through the slide mechanism that allows translational movement of the duct relative to the console body when the electronic device console is oriented in the first orientation, and the slide mechanism allows a portion of the duct to be moved within the console body.2. The electronic device console of claim 1 , wherein the electronic device console is devoid of a fan.3. The electronic device console of claim 1 , wherein a length of the duct is greater than a width of the duct.4. The electronic device console of claim 1 , wherein:the first vent is an outlet and the second vent is an inlet in the first orientation; andthe first vent is an inlet and the second vent is an outlet in the second orientation.5. The electronic device console of claim 1 , wherein:the first vent is vertically ...

Polygon integrated circuit (ic) packaging

An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

Managing Interconnect Electromigration Effects

A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent. 1. A method , in a data processing system , for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors , the method comprising:for each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, determining a current modeled age of the interconnect group;determining whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value; andresponsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, sending an indication to take corrective action with the at least one associated interconnect group.2. The method of claim 1 , further comprising:responsive to none of the current modeled age of the interconnect group for the set of interconnect groups being less than or equal to the end-of-life value, repeating the process to calculate a new modeled age for each of the set of interconnect groups;determining whether at least one of the new modeled age of the interconnect group for the set of interconnect groups is greater than the end-of-life value; andresponsive to at least one new modeled age of the interconnect group being greater ...

Direct bonded heterogeneous integration packaging structures

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

DIRECT BONDED HETEROGENEOUS INTEGRATION PACKAGING STRUCTURES

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate. 1. An integrated circuit packaging structure free of an interposer layer , the integrated circuit packaging structure comprising:a packaging substrate comprising first and second opposing surfaces, and a trench provided in the first opposing surface, wherein the first opposing surface defining the trench is free to electrical connections;a bridge disposed in the trench; andat least two chips in a side by side arrangement overlying the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement, the at least two chips comprising a plurality of electric connections coupled to corresponding electrical connections on the bridge and on the packaging substrate, wherein each of the at least two chips are supported completely by the corresponding electrical connections and an underfill material.2. The integrated circuit packaging structure of claim 1 , further comprising a lid and a thermal interface material overlaying the chips.3. The integrated circuit packaging structure of claim 1 , further comprising an underfill material between the plurality of electrical connections coupled to the corresponding electrical ...

Passivation layer surface topography modifications for improved integrity in packaged assemblies

A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.

Thermoelectric devices and methods for making the same

Thermoelectric devices having enhanced thermal characteristics are fabricated using multilayer ceramic (MLC) technology methods. Aluminum nitride faceplates with embedded electrical connections provide the electrical series configuration for alternating dissimilar semiconducting materials. Embedded electrical connections are formed by vias and lines in the faceplate. Methods are employed for forming tunnels through lamination and etching. A portion of the dissimilar materials are then melted within the tunnels to form a bond. Thermal conductivity of the faceplate is enhanced by adding electrically isolated vias to one surface, filled with high thermal conductivity metal paste. A low thermal conductivity material is also introduced between the two high thermal conductivity material faceplates. Alternating semiconducting materials are introduced within the varying thermal conductivity layers by punching vias within greensheets of predetermined thermal conductivity and filling with n-type and p-type paste. Alternating semiconducting materials may also be patterned in linear or radial fanout patterns through screening techniques and lamination of wire structures. A liquid channel within the faceplate is used to enhance thermal energy transfer. Thermoelectric devices are physically incorporated within the IC package using MLC technology.

Process for screening features on an electronic substrate with a low viscosity paste

A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.

Process for fabricating a low dielectric composite substrate

The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addressed by backfilling the permeable cracks with a flexible material. Uniform gaps between the metal and dielectric materials can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.

Aluminum nitride body having graded metallurgy

Phenyl-endcapped depolymerizable polymer

Phenyl-endcapped depolymerizable polymers are disclosed. The phenyl endcap eliminates the reactive terminal vinyl group resulting in increased depolymerization threshold temperatures and reduced residue after depolymerization. A multilevel metal lift-off process using the phenyl-endcapped polymers is disclosed. Additionally, the polymers are improved ceramic glass binder resins.

Method and apparatus for filling vias

Materials and method to seal vias in silicon substrates

Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via (100) at an elevated temperature, A supply chamber (630) is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Method and structure for integrated thermistor

Low dielectric composite substrate

The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addressed by backfilling the permeable cracks with a flexible material. Uniform gaps between the metal and dielectric materials can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.

Method and apparatus for filling vias

Method of joining laminates for z-axis interconnection

Electronic device console with natural draft cooling

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.

Method of making an interface layer for stacked lamination sizing and sintering

An interface layer for separating first and second microelectronic ceramic substrates during firing includes a thermally degradable binder, preferably a polymer, that degrades at temperatures above room temperature and below a firing temperature for the microelectronic ceramic substrates, and a separating material, such as boron nitride or graphite. The method of making the interface layer includes mixing the binder, one or more solvents for the binder, a plasticizer and the separating material for a sufficient period of time to form a homogeneous mass, then casting the material in a thin sheet to form the interface layer.

Multi-level web structure in use for thin sheet processing

A method of processing greensheets, wherein the following steps are performed: a) providing a greensheet (1) having a width, length, thickness, a first side (5) and a second side (7); b) bonding to the first side of the greensheet at least one strip (a, b, c...), wherein the strip lies in a first plane; c) bonding to the second side of the green sheet at least one strip, wherein the strip lies in a second plane; d) processing the greensheet; and e) removing the strips from the processed greensheet.

Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners

Structures and a method for forming the same. The structure includes a semiconductor substrate (11), a transistor (11a, 11b, 11c) on the semiconductor substrate, and N interconnect layers (13) on top of the semiconductor substrate (11), N being a positive integer. The transistor (11a, 11b, 11c) is electrically coupled to the N interconnect layers (13). The structure further includes a first dielectric layer (13d) on top of the N interconnect layers (13) and P crack stop regions (130a-e) on top of the first dielectric layer (120), P being a positive integer. The structure further includes a second dielectric layer (140) on top of the first dielectric layer. Each crack stop region (130a-c) of the P crack stop regions (130a-e) is completely surrounded by the first dielectric layer (120) and the second dielectric layer (130). The structure further includes an underfill layer (190) on top of the second dielectric layer (130). The second dielectric layer (130) is sandwiched between the first dielectric layer (120) and the underfill layer (190).