Integrierter Speicher

Der integrierte Speicher weist einen ersten Adreßpfad auf, über den Adreßanschlüsse (ADR) mit ersten Auswahlleitungen (CSL) einer ersten Gruppe (G1) verbunden sind und der entsprechende erste Leitungen (L1) und eine erste Decoderschaltung (DEC1) aufweist. Außerdem weist er einen zweiten Adreßpfad auf, über den die Adreßanschlüsse (ADR) mit ersten Auswahlleitungen (CSL) einer zweiten Gruppe (G2) verbunden sind und der entsprechende zweite Leitungen (L2) und eine zweite Decoderschaltung (DEC2) aufweist. Die erste Decoderschaltung (DEC1) ist schneller als die zweite Decoderschaltung (DEC2). Die ersten Leitungen (L1) weisen eine größere Signallaufzeit auf als die zweiten Leitungen (L2).

Storage circuit has multiple parallel bit lines, which are connected to storage cells, and multiple switches which are connected with corresponding pair of bit lines of multiple bit lines

The storage circuit (10) has multiple parallel bit lines (21,22,23,24,25,26,27,28) connected to a storage cell (12). The storage circuit has multiple switches (51,52,53,54) which are connected with a corresponding pair of bit lines of the multiple bit lines in order to short circuit the corresponding pair. The bit lines of the corresponding pair are connected with two different read amplifiers (41,42,43,44). The bit lines of the corresponding pair next adjacent to a further bit lines are between the bit lines of the corresponding pair. Independent claims are also included for the following: (1) a microelectronic element, which has a storage circuit (2) a method for operating storage circuit, which involves connecting storage cell, bit lines.

Voltage pump with turn-on control

A voltage pump for generating an increased output voltage VPP has a turn-on control comprising a transistor 1 connected between a connection 3 for a supply voltage VEXT and a connection 4 for tapping-off the increased output voltage VPP. After the voltage pump 7 starts to operate, the increased output voltage VPP is decoupled from the supply voltage VEXT by the transistor 1. A switch 2 conveys the higher of the output voltage or supply voltage VPP, VEXT to the substrate connection and the gate connection of the transistor 1. The turn-on control makes possible an early provision of an increased output voltage with safe start-up operation of the voltage pump 7, only a small circuit complexity being necessary.

Integrated memory

The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

Resistive memory cell for use in a memory component, comprises resistive memory element with two resistive conditions, where selection unit is provided with interconnected and disconnected condition

The resistive memory cell comprises a resistive memory element (11) with two resistive conditions. A selection unit is provided with an interconnected and a disconnected condition. A conductor (1) is connected with a connection (102) of the selection unit. A current is applied on the conductor for determining the resistive condition of the resistive memory element by the selection unit in the interconnected condition. An independent claim is also included for a method for operating an integrated circuit with a resistive memory cell.

VORRICHTUNG ZUM AUSPRESSEN VON TUBEN DES TAEGLICHEN TOILETTEBEDARFES.

Resistive switching memory cell e.g. phase change random access memory cell, operating method for e.g. flash memory, involves reading memory cell data content by applying voltage to cell in range of one threshold voltage or higher voltage

The method involves displacing a resistive switching memory cell by applying a threshold voltage in a low impedance condition and by applying another threshold voltage in a high impedance condition. Data content of the memory cell is read-out by applying a voltage to the memory cell in a range of one of the threshold voltages or a higher voltage. A voltage pulse is applied at the memory cell for reading the data content, where the voltage pulse is temporary so that the data content of the memory cell is formed in an unchanged condition. An independent claim is also included for a memory system with a set of resistive switching memory cells.

Integrierte Schaltung mit Testbetriebsart und Verfahren zum Testen einer Vielzahl solcher integrierter Schaltungen

FB DRAM-Speicher mit Zustandsspeicher

Vorrichtung (400) zum Austauschen von binären Daten, mit folgenden Merkmalen: einem FB DRAM-Array (410) mit einer Mehrzahl von FB DRAM-Zellen, die über ein Lesesignal, ein Schreibsignal oder ein Leerlaufsignal ansprechbar sind; einer Leseeinrichtung (420) zum Bestimmen eines Zustandes einer FB DRAM-Zelle; einer Mehrzahl von Zustandsspeichern (430), wobei ein Zustandsspeicher zum Speichern eines Zustandes einer FB DRAM-Zelle ausgebildet ist; und einer Steuerung (440) zum Empfangen eines Aktivierungssignals, einer FB DRAM-Adresse, eines Lesebefehls oder eines Schreibbefehls, wobei die Steuerung (440) ausgebildet ist, um bei Empfang des Aktivierungssignals und der FB DRAM-Adresse das FB DRAM-Array (410) an der FB DRAM-Adresse mit dem Lesesignal und sonst mit dem Leerlaufsignal anzusteuern, die Leseeinrichtung (420) mit den FB DRAM-Zellen des FB DRAM-Arrays (410) der FB DRAM-Adresse zu koppeln und die Zustände der FB DRAM-Zellen der FB DRAM-Adresse in den Zustandsspeichern (430) zu speichern ...

Rohrelement für Gasdruckbehälter, Gasdruckbehälter und Verfahren zur Herstellung eines Rohrelementes

Die vorliegende Erfindung bezieht sich auf ein Rohrelement für einen Gasdruckbehälter eines Airbagmoduls, insbesondere eines Fahrzeuges, wobei das Rohrelement (1) aus hochfestem Stahl besteht, ein erstes und ein zweites Ende (17, 18) aufweist und von dem ersten Ende (17) zu dem zweiten Ende (18) das Rohrelement (1) einen unverformten Abschnitt (11), einen Übergangsabschnitt (12) und einen Verjüngungsabschnitt (13) aufweist und an dem Verjüngungsabschnitt (13) zumindest ein radial nach außen ragender Vorsprung (14) ausgebildet ist. Das Rohrelement (1) ist dadurch gekennzeichnet, dass der Vorsprung (14) von dem Übergangsabschnitt (12) durch einen ersten Längenabschnitt (130) mit einem Außendurchmesser (A1), der geringer als der Außendurchmesser (A2) des Vorsprungs (14) ist, getrennt ist und die Wandstärke des Vorsprungs (14) größer ist als die Wandstärke des ersten Längenabschnittes (130). Weiterhin betrifft die Erfindung einen Gasdruckbehälter und ein Verfahren zum Herstellen eines erfindungsgemäßen ...

ADAPTER WITH AN ATTACHMENT FOR AN ATOMIZER

An adapter comprises an attachment (20) for an atomizer (1) for a fluid ( 2), in particular one containing a pharamaceutical, as aerosol through an at omizer nozzle (12), wherein the attachment (20) is coupled via a bore (23) t o an outlet (22) towards the patient, and an inlet (25) on which a respirato ry air tube is to be secured and which is connected to the bore (23) in term s of flow technology in such a way that the main direction of atomization of the fluid (2) is oriented parallel to the direction of flow of a respirator y gas, wherein an opening (27) extending parallel to the bore (23) in the di rection of the atomizer (1) is let into a passage (24) assigned to the inlet (25). The opening (27) extends into an area facing towards the atomizer (1) and behind the atomizer nozzle (12).

Circuit configuration for programming a delay in a signal path

A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

Memory chip has multiple floating body dynamic random access memory cells and word line, which is coupled with two floating body dynamic random access memory cells

The memory chip (100) has multiple floating body dynamic random access memory (FB DRAM) cells (110,112), a word line, which is coupled with a FB DRAM cell and another FB DRAM cell. A bit line (130) is coupled with the former FB DRAM cell. A state memory circuit (135) is coupled with a bit line. Another bit line is coupled with the latter FB DRAM cell. Another state memory circuit (145) is coupled with the latter bit line. A read amplifier (150) is coupled with the former FB DRAM cell, the latter FB DRAM cell, the former state memory circuit or the latter state memory circuit. Independent claims are included for the following: (1) a device for changing binary data; (2) a method for changing binary data with floating body dynamic random access memory cells; and (3) a computer program for execution of the method.

Integrierter Speicher und Verfahren zum Betrieb eines integrierten Speichers

Integrierter Speicher – mit einem Speicherzellenfeld (2), das Zeilenleitungen (WL) zur Auswahl von Speicherzellen (MC) und Spaltenleitungen (BL) zum Lesen oder Schreiben von Datensignalen über zugeordnete Schreib-Lese-Verstärker (11,12,21,22; SAO-SA3) und Spaltenauswahlleitungen (CSLl,CSL2; CSL) zum Aktivieren der Schreib-Lese-Verstärker (11,12,21,22; SAO-SA3) aufweist, wobei jeweils eine Gruppe von Speicherzellen (MC) einer vorbestimmten Anzahl zu einer Zeilen- und Spaltenadresse gehört, – mit einer der vorbestimmten Anzahl entsprechenden Mehrzahl von Anschlußpads (5; 15,25; 35) zur Ein- und Ausgabe der in den Speicherzellen (MC) gespeicherten Datensignale, wobei jede Speicherzelle einer Gruppe von Speicherzellen einem der Anschlußpads (5; 15,25;35) zugeordnet ist, und – mit einer Steuerschaltung (7) zur Steuerung eines Speicherzugriffs auf die Speicherzellen, die derart ausgebildet und betreibbar ist, daß sie mit einer Spaltenadresse zumindest zwei verschiedene Spaltenauswahlleitungen (CSL1,CSL2) aktiviert und eine der Spaltenauswahlleitungen bei zwei oder mehreren Spaltenadressen aktiviert: Integrated memory - With a memory cell array (2), the row lines (WL) for selecting memory cells (MC) and column lines (BL) for reading or writing data signals via assigned read / write amplifiers (11, 12, 21, 22; SAO-SA3 ) and column selection lines (CSL1, CSL2; CSL) for activating the read / write amplifiers (11, 12, 21, 22; SAO-SA3), each with a group of memory cells (MC) of a predetermined number of one row and Column address belongs to - With a predetermined number of connection pads (5; 15,25; 35) for input and output of the data signals stored in the memory cells (MC), each memory cell of a group of memory cells one of the connection pads (5; 15,25 ; 35) is assigned, and - With a control circuit (7) for controlling memory access to the memory cells, which is designed and operable in such a way that it activates at least two different column selection lines (CSL1, CSL2) ...

Voltage pump with turn-on control

Test arrangement for integrated circuit memory chips

A parallel arrangement tests integrated circuits especially DDR SDRAM memory chips. An input connection (10) to one channel of an automatic test unit is linked to a circuit (30), through which the output driver can be switched off in response to an input (10) control signal. The circuit has especially a demultiplexer (31) and a multiplexer (32).In addition to the test control signal (TMCOMP) the demultiplexer can also be controlled by a TMRDS test signal. The input connector (10) is already linked to a test channel, dispensing with the prior art requirement for additional external connections.

REGENSCHIRM MIT LEUCHTVORRICHTUNG.

Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits

Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

Memory array, particularly memory array with resistive memory elements, has multiple memory devices, multiple bit lines, multiple word lines and multiple additional lines

The memory array has multiple memory devices (10a), multiple bit lines, multiple word lines and multiple additional lines. A primary voltage is applied to a certain word line to select a gap of memory devices, which are connected with its other attachments at a certain word line. A secondary voltage is applied to a certain bit line of the multiple bit lines to select a row of memory devices, where secondary voltage is applied to each of the additional lines, exterior to additional line, where additional line is connected with the third attachment of the memory device of the selected gap. An independent claim is also included for a method for reducing leakage current in memory array.

Schaltungsanordnung zur Programmierung einer Verzögerungszeit eines Signalpfads

Adapter mit einem Anschluss für einen Zerstäuber

Ein Adapter umfasst einen Anschluss (20) für einen Zerstäuber (1) für ein, insbesondere ein Arzneimittel aufweisendes, Fluid (2) als Aerosol durch eine Zerstäuberdüse (12), wobei der Anschluss (20) über eine Bohrung (23) mit einem patientenseitigen Abgang (22) gekoppelt ist, und einen mit der Bohrung (23) strömungstechnisch derart verbundenen Eingang (25) für einen daran befestigenden Atemluftschlauch, dass die Hauptzerstäubungsrichtung des Fluids (2) parallel zur Strömungsrichtung eines Atemgases ausgerichtet ist, wobei in einen dem Eingang (25) zugeordneten Durchbruch (24) eine parallel zur Bohrung (23) in Richtung des Zerstäubers (1) verlaufende Öffnung (27) eingelasen ist. Die Öffnung (27) erstreckt sich bis in einen dem Zerstäuber (1) zugewandten Bereich hinter der Zerstäuberdüse (12). One Adapter comprises a connection (20) for a sprayer (1) for a, in particular, a drug exhibiting, fluid (2) as an aerosol through a spray nozzle (12), wherein the terminal (20) via a Bore (23) is coupled to a patient-side outlet (22), and a fluidically connected to the bore (23) Input (25) for a breathing air hose attaching thereto, that the main atomization direction of the fluid (2) parallel to the flow direction a breathing gas is aligned, wherein in a the input (25) associated aperture (24) one parallel to the bore (23) in the direction the atomizer (1) running opening (27) is einlas. The opening (27) extends into a region facing the atomizer (1) behind the atomizer nozzle (12).

Layout eines Sense-Verstärkers mit beschleunigter Signalauswertung

Schaltungsanordnung zur Programmierung einer Verzögerungszeit eines Signalpfads

Semiconductor memory device has driver transistor pair for each memory module and coupling transistor for coupling adjacent memory row selection lines

The memory device (100) has at least one memory module and associated word decoder block and at least one driver transistor pair (101a,101b), coupled to the word decoder block at their gates (104) in a ring structure (RDC). The sources (102) of the driver transistor pair lie outside the ring structure and have a common diffusion zone, the drains lying within the ring structure and coupled to at least one memory row selection line (106a,106b), adjacent selection lines coupled via a coupling transistor (105) receiving the same gate signal as the driver transistor pair.

Semiconductor memory arrangement

The memory includes a number of adjacent, inverting bit conductors (bBL0, bBLl, bBL2) carrying information read from corresponding memory cells (4, 2, 6) which store the corresponding data in inverted form, and non-inverting bit conductors (BL0, BL1, BL2) which are connected with memory cells (1, 5, 3) which store data in non-inverted form. A switching transistor associated with each bit conductor, connects the corresponding bit conductor, either to an inverted or a non-inverted collecting conductor (bLDQ, LDQ). Two inverting, or two non-inverting bit conductors are arranged side by side, without an intermittent further bit conductor.

MEMORY CIRCUIT, CAPABLE OF SWITCHABLY SHORT-CIRCUITING BIT LINE PAIR

PURPOSE: A memory circuit is provided to generate a reference potential by providing two different well-defined potentials to two different bit lines and then short-circuiting the bit lines. CONSTITUTION: According to a memory circuit, a plurality of parallel bit lines(21-28) is connected to a plurality of memory cells. A plurality of sense amplifiers(341,342,343,344) is connected to the bit lines. The memory circuit further includes a plurality of switches(351,352,353,354). Each switch is connected to each bit line pair and short-circuits each bit line pair switchably. The bit lines of each bit line pair are connected two different sense amplifiers, and the bit lines of each bit line pair are adjacent to another bit line arranged between bit lines of the bit line pair. © KIPO 2008 ...

Layout of a sense amplifier with accelerated signal evaluation

A layout of a sense amplifier configuration for a semiconductor memory is described. The layout has a plurality of read/write amplifiers, extending as strips in the form of rows one under the other, and having NMOS and PMOS transistors. At least one of the two driver transistors is disposed with its doping regions between the associated NMOS or PMOS transistors of the read/write amplifiers. A gate of the driver transistor is configured as a two-strip gate, in order to accelerate the signal evaluation in the sense amplifiers.

Spannungspumpe mit Einschaltsteuerung

Eine Spannungspumpe zur Erzeugung einer erhöhten Ausgangsspannung (VPP) weist eine Einschaltsteuerung mit einem Transistor (1) auf, der zwischen einen Anschluß (3) zur Zuführung einer Versorgungsspannung (VEXT) und den Anschluß (4) zum Abgriff der erhöhten Ausgangsspannung (VPP) geschaltet ist. Nach Betriebsbeginn der Spannungspumpe (7) wird vermittels des Transistors (1) die erhöhte Ausgangsspannung (VPP) von der Versorgungsspannung (VEXT) entkoppelt. Ein Umschalter (2) leitet die jeweils höhere der Ausgangs- oder Versorgungsspannungen (VPP, VEXT) an den Substrat- und den Gateanschluß des Transistors (1) weiter. Die Einschaltsteuerung ermöglicht ein frühzeitiges Bereitstellen einer erhöhten Ausgangsspannung (VPP) bei sicherem Anlaufbetrieb der Spannungspumpe (7), wobei ein nur geringer Schaltungsaufwand erforderlich ist.

Spannungspumpe mit Einschaltsteuerung

Spannungspumpe mit einer Einschaltsteuerung, umfassend: - einen Anschluß (3) für eine Versorgungsspannung (VEXT), - einen Anschluß (4) für eine erhöhte Ausgangsspannung (VPP), - eine Schaltungsanordnung zur Einschaltsteuerung der Spannungspumpe, umfassend: - einen ersten Transistor (1), dessen gesteuerte Strecke zwischen den Anschluß (3) für die Versorgungsspannung (VEXT) und den Anschluß (4) für die erhöhte Ausgangsspannung (VPP) geschaltet ist, der einen Substratanschluß und einen Steueranschluß aufweist, - einen Umschalter (2), der eingangsseitig an den Anschluß (3) für die Versorgungsspannung (VEXT) und den Anschluß (4) für die erhöhte Ausgangsspannung (VPP) angeschlossen ist und einen Ausgang (23) aufweist, der an den Substratanschluß des ersten Transistors (1) angeschlossen ist und an den Steueranschluß des ersten Transistors (1) gekoppelt ist und durch den wechselweise der Anschluß (3) für die Versorgungsspannung (VEXT) oder der Anschluß (4) für die erhöhte Ausgangsspannung (VPP) ...

Integrated circuit, has memory arrangement divided into plates, and word line control assigned to each plate, where part of control is arranged at edge of plate and other part of control arranged on another edge of plate

The circuit (1) has a memory e.g. static RAM, arrangement (2) divided into plates (3a-3d), and a word line control (4) assigned to each plate. A part (4a) of the word line control is arranged at an edge (3e) of the plate, and another part (4b) of the word line control is arranged on another edge (3f) of the plate. The plate is divided into two parts (6a, 6b) by a boundary line (6) that runs parallel to opposite edges. Data lines (8a-8d) are provided for writing into the plate and/or for reading from the plate arranged at an additional edge (3g) of the plate.

Integrated memory, double data rate DRAM

The memory cells are selected using a first chip select line (CSL) and word line (WL). The chip select line is subdivided into a first (G1) and a second group (G2). The first chip select lines of both groups are addressable with address connections (ADR). An address path connects the address connection with the first chip select line of the first group and the corresponding first line and a first decoder circuit (DEC1). A second address path connects the address connections with the first chip select line of the second group and the corresponding second line (L2) and a second decoder circuit (DEC2). The first decoder circuit carries out the decoding of addresses fed to it, quicker than the second decoder circuit. The first line (L1) has a larger signals delay, is longer and has less conductivity than the second line.

Funny current (If) inhibitors for use in a method of treating and/or preventing heart disease in canine

The present invention relates to an If blocker or a pharmaceutically acceptable salt thereof for the treatment and/or prevention of a canine patient suffering from heart diseases, preferably heart diseases such as dilated cardiomyopathy (DCM), mitral valve insufficiency (MI), arrthymias, preferably tachyarrthymias, preferably artrial arrythmias, atrioventricular nodal arrythmias and/or tachycardia. Each of these diseases may or may not result in heart failure (HF) in canine patients. The invention also relates to improving the quality of life, improving the general health condition as well as a prolonging the life expectancy in canine patients suffering from heart diseases and/or heart failure due to one or more of the following aetiologies dilated cardiomyopathy (DCM), mitral valve insufficiency (MI), arrthymias, preferably tachyarrthymias, preferably artrial arrythmias, atrioventricular nodal arrythmias and/or tachycardia.

Integrated memory has control circuit that activates at least two different column selection lines with one column address, one of the column selection lines for two or more column addresses

The memory has a cell field with row lines for cell selection, column lines for reading or writing data signals via read-write amplifiers and column selection lines for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads. A control circuit activates at least 2 different column selection lines with one column address and one of the column lines for 2 or more column addresses. The device has a memory cell field with row lines (WL1-4) for selecting cells and column lines for reading or writing data signals via read-write amplifiers (11,12,21,22) and column selection lines (CSL1,2) for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads (15,25). A control circuit activates at least two different column selection lines with one column address and one of the column lines for two or more column addresses. AN Independent claim is also included for the ...

Kraftstoffeinspritzleitung und rohrförmiger Leitungskanal

Die vorliegende Erfindung betrifft ein Kraftstoffeinspritzleitung für einen Dieselmotor, umfassend einen rohrförmigen zumindest bereichsweise gekrümmten Leitungskanal (10) aus einer Stahllegierung zur Durchleitung eines Kraftstoffes. Die Kraftstoffeinspritzleitung ist dadurch gekennzeichnet, dass der Leitungskanal (10) eine Zugfestigkeit von mindestens 1.050 MPa sowie ein Gefüge mit einem Bainitanteil von mindestens 70% aufweist. Weiterhin wird ein rohrförmiger Leitungskanal (10) beschrieben.

Memory unit e.g. magnetic RAM memory unit, for storing data, has potential supply unit supplying potential to amplifying circuits, such that leakage current through circuits is decreased or avoided in deactivated condition of circuits

The memory unit (100) has bit lines (104) electrically connected with the memory cells (106) of the memory cell array (107). Amplifying circuits (103) are electrically connected with the bit lines and amplifies electric signals guided in the bit lines, where the amplifying circuits are activated and deactivated by amplifier circuit control nodes. A potential supply unit supplies potential to the amplifying circuits, such that leakage current through the amplifier circuits is decreased or avoided in the deactivated condition of the amplifier circuits. An independent claim is also included for a method for improving reliability of a memory unit.

Memory circuit

Bus-system for e.g. microprocessor, has lines with two sections, in each case., where sections are connected with each other by repeater and/or buffer mechanisms as inverted and non-inverted repeater and/or buffer mechanisms

The system has lines with two sections in each case. The sections are connected with each other by repeater and/or buffer mechanisms (101, 102, 103). The repeater and/or mechanism (102) connected with the sections (12a, 12b) are designed as inverted repeater and/or mechanism. The repeater and/or mechanism(101, 103) connected to the sections (11a, 11b, 13a, 13b) is designed as non-inverted repeater and/or mechanism : An independent claim is also included for a method for operating a bus-system.

Schaltungsanordnung zur Programmierung einer Verzögerungszeit eines Signalpfads

Zur Programmierung der Verzögerungszeit eines Signalpfads (1, 2), insbesondere in DRAMs, umfaßt die Schaltungsanordnung zwei eingangsseitig parallel ansteuerbare Signalstrecken (3, 4) mit unterschiedlicher Verzögerungszeit, die über einen Multiplexer auf den Ausgangsanschluß (2) schaltbar sind. Eine Auswahlschaltung (5) umfaßt zwei zwischen die Versorgungsspannung (VDD, VSS) geschaltete Signalstrecken mit zwei in Reihe geschalteten komplementären Transistoren (511, 512; 521, 522) sowie sourceseitigen programmierbaren Elementen. Die Transistoren sind von komplementären Steuersignalen (HSPEED, bHSPEED) ansteuerbar. Dadurch wird eine flexible Programmierung der Verzögerungszeit bei geringem Schaltungsaufwand ermöglicht.

INTEGRATED CIRCUIT HAVING TEST OPERATION MODE AND METHOD FOR TESTING NUMBER OF INTEGRATED CIRCUITS

PURPOSE: An integrated circuit having a test operation mode and a method for testing a number of the above integrated circuits are provided, which is tested with a low cost. CONSTITUTION: According to the integrated circuit, function tests(TMCOMP,TMRDIS) of one function units(43,44) of an integrated circuit are executed in the first operation mode. And in the second operation mode, the function units are operated in a regular operation mode. A data output driver(41) and a data input signal path(40) are connected to each function unit and to a port for data signals(23,24,25) for supplying and transmitting data. The integrated circuit also includes an input port(10) supplying a control signal and a control circuit(30). According to the operation mode set by the control circuit, the data input signal path is connected or isolated by an abnormal state of the control signal in the regular operation mode, and the data output driver is inputted or isolated by an abnormal state of the control signal ...

Integrated circuit having a resistively switching memory and method

An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage.

Speicherelement zur Verbesserung der Zuverlässigkeit eines Speicherelements

Speicherelement; mit einem Speicherzellen-Array, das eine Mehrzahl von Speicherzellen aufweist; mit Bitleitungen, die mit den Speicherzellen des Speicherzellen-Arrays elektrisch verbunden sind; mit Verstärkerschaltungen, die mit den Bitleitungen elektrisch verbunden sind und in den Bitleitungen geführte elektrische Signale verstärken, wobei die Verstärkerschaltungen über Verstärkerschaltungs-Steuerungsknoten aktiviert und deaktiviert werden, wobei die Verstärkerschaltungs-Steuerungsknoten jeder Verstärkerschaltung einen positiven Aktivierungsknoten und einen negativen Aktivierungsknoten aufweisen; und mit wenigstens einer Potenzial-Versorgungseinheit, durch die der negative Aktivierungsknoten während des Schreibzustands auf das höchste Potenzial setzbar ist, das während des Schreibzustands auf den Bitleitungen auftritt, und der positive Aktivierungsknoten während des Schreibzustands auf das niedrigste Potenzial setzbar ist, das während des Schreibzustands auf den Bitleitungen auftritt, ...

System, und Verfahren zum Betreiben eines Systems, welches ein Halbleiter-Bauelement aufweist

System, welches ein Halbleiter-Bauelement (3) aufweist, welches über eine erste auf dem Halbleiter-Bauelement (3) vorgesehene Signal-Treiber-Einrichtung (7a), und eine mit der ersten Signal-Treiber-Einrichtung (7a) verbundene erste Leitung (11) eines an das Halbleiter-Bauelement (3) angeschlossenen externen Bus-Systems (2), sowie über eine zweite auf dem Halbleiter-Bauelement (3) vorgesehene Signal-Treiber-Einrichtung (7b), und eine mit der zweiten Signal-Treiber-Einrichtung (7b) verbundene zweite Leitung (12) des externen Bus-Systems (2) an ein weiteres Halbleiter-Bauelement (4) anschließbar ist, wobei die Leitungen (11, 12) jeweils zwei Leitungs-Abschnitte (11a, 11b; 12a, 12b) aufweisen, die jeweils durch eine Buffer-Einrichtung (101, 102) miteinander verbunden sind, wobei die mit den Leitungs-Abschnitten (11a, 11b) der ersten Leitung (11) verbundene Buffer-Einrichtung (101) als nicht-invertierende Buffer-Einrichtung (101), und die mit den Leitungs-Abschnitten (12a, 12b) der zweiten Leitung ...

Layout eines Sense-Verstärkers mit beschleunigter Signalauswertung

Bei einem Layout einer Senseverstärkeranordnung für einen Halbleiterspeicher mit mehreren sich als Streifen zeilenförmig untereinander erstreckenden Schreib/Lese-Verstärkern (20) mit NMOS- und PMOS-Transistoren ist vorgesehen, daß zumindest einer der beiden Treibertransistoren (N1, P1) mit seinen Dotierungsgebieten zwischen den dazugehörigen NMOS- oder PMOS-Transistoren der Schreib/Lese-Verstärker (N2, N3, P2, P3) angeordnet ist, und daß das Gate des Treibertransistors (N1, P1) dabei als Zweistreifengate (N111, P111) ausgebildet ist, um die Signalauswertung in den Sense-Verstärkern zu beschleunigen.

MEMORY CIRCUIT

A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

FB DRAM memory with state memory

A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

INTEGRATED CIRCUIT HAVING A MEMORY ARRAY

An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed. One embodiment provides a memory array including a plurality of storage devices arranged as a plurality of rows and a plurality of columns. A first voltage is applied to a particular word line to select a column of storage devices. A second voltage is applied to a particular bit line of the plurality of bit lines to select a row of storage devices, and the second voltage is applied to each of further lines except for a further line being connected to the storage devices of the selected column.

Voltage pump with switch-on control

The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

VOLTAGE PUMP WITH THROW-IN CONTROL MECHANISM

PROBLEM TO BE SOLVED: To provide a voltage pump with a throw-in control mechanism in which the operation is stable at the time of increasing supply voltage and the output voltage being pumped is prepared as quickly as possible. SOLUTION: The voltage pump 7 for generating an increased output voltage is provided with a throw-in control mechanism having a transistor 1 connected between a terminal 3 for introducing a supply voltage and a terminal 4 for taking out an increased output voltage. Upon starting operation of the voltage pump 7, the increased output voltage is interrupted from the supply voltage through the transistor 1. A switch 2 transfers the higher one of the output voltage or the supply voltage to a substrate terminal and a gate terminal of the transistor 1, respectively. The throw-in control mechanism allows standby at the early state of increased output voltage in the safety rising operation of the voltage pump 7 without requiring a significant circuit cost. COPYRIGHT: (C)2002 ...

FB DRAM Memory with State Memory

A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

TUBULAR ELEMENT FOR GAS PRESSURE VESSEL, GAS PRESSURE VESSEL AND METHOD OF MANUFACTURING A TUBULAR ELEMENT

This invention concerns a tubular element for a gas pressure vessel of an airbag module, in particular of a vehicle, wherein the tubular element (1) consists of high-strength steel, has a first and a second end (17, 18) and from the first end (17) to the second end (18) the tubular element (1) has an undeformed section (11), a transition section (12) and a tapering section (13) and on the tapering section (13) at least one radially outwardly extending collar (14) is formed, characterized in that the collar (14) is separated from the transition section (12) by a first length section (130) having an outer diameter (A1) smaller than the outer diameter (A2) of the collar (14) and the wall thickness of the collar (14) is greater than the wall thickness of the first length section (130). Furthermore, the invention concerns a gas pressure vessel and a process for manufacturing a tubular element according to the invention (1).

INTEGRATED CIRCUIT AND TEST METHOD OF SAME

(57)【要約】 【課題】 規格に合致しごく僅かなコストで集積回路を テストできるように構成し、また、外部での手間をほと んどかけずにそのような回路を多数、テストできるよう にする。 【解決手段】 テストモード中に複数の集積回路が相反 して駆動されてしまうのを避けるため、いずれにせよす でに自動テスト装置のチャネルと接続されている入力端 子１０が回路手段３０と接続される。そしてこの回路手 段３０により、入力端子１０に供給される制御信号に依 存して出力ドライバを遮断することができる。回路手段 ３０はデマルチプレクサ３１とマルチプレクサ３２を有 している。デマルチプレクサは、テスト制御信号ＴＭＣ ＯＭＰのほかに付加的に生成されるテスト制御信号ＴＭ ＲＤＩＳによって制御可能である。入力端子１０はテス トモード中、いずれにせよテスタチャネルと接続されて いるので、付加的な外部のコストはかからない。

INTEGRATED CIRCUIT HAVING A RESISTIVE MEMORY

An integrated circuit having a resistive memory including a resistive memory element, a selection device, a conductive line, and a reference electrode is disclosed. In one embodiment, the conductive line is set to a first voltage for establishing a first resistive state of the resistive memory element and to a second voltage, being lower than the first voltage, for establishing a second resistive state of the resistive memory element. The reference electrode is coupled to the resistive memory element and is set to a voltage level being provided between the first voltage and the second voltage.

Integrated memory, and a method of operating an integrated memory

An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

HANDSWITCH QUICK CONNECT EXPOSURE CONTROL

A radiation imaging system includes a radiation detector for detecting radiation emitted from a radiation generator; a quick-connect unit configured to activate the radiation generator to initiate radiation emission and to activate the radiation detector to initiate detection of the radiation; and a notification unit included within the quick-connect unit that is configured to notify an operator of a time when the radiation detector is ready to detect the radiation. The quick-connect unit is connectable to the radiation detector and the radiation generator without having to make hardware modifications therein. In an alternate embodiment, the quick-connect unit is a handswitch to be held by an operator, where the notification unit notifies the operator that the radiation detector is ready to detect the radiation, by emitting at least one of a visual signal, a tactile signal and an audible signal. 1. A radiation imaging apparatus , comprising:a radiation detector for detecting radiation emitted from a radiation generator;a trigger unit configured to activate said radiation generator to initiate radiation emission and to activate said radiation detector to initiate detection of said radiation; anda notification unit configured to notify an operator of a time when the radiation detector is ready to detect said radiation,wherein the notification unit is included within the trigger unit.2. The radiation imaging apparatus according to claim 1 , wherein the trigger unit includes a hand switch.3. The radiation imaging apparatus according to claim 1 , wherein the notification unit includes a light emitting unit.4. The radiation imaging apparatus according to claim 1 , further comprising a timing control circuit configured to control said radiation generator and said radiation detector.5. The radiation imaging apparatus according to claim 4 , wherein said trigger unit is operatively connected to said timing control circuit claim 4 , and{'b': 0', '1, 'wherein said timing ...

Portable x-ray system

A portable X-Ray system that includes a first module with an x-ray processor, an input, a monitor, a power supply, an exterior interface, and a sensor panel, the sensor panel being operatively connected in data transfer communication with the x-ray processor by a first connector. The first connector permits the sensor panel to be disposed in spaced apart adjustable position relative to the x-ray processor and a subject to be x-rayed. The first module can be adjusted into a portable stored configuration and an operative configuration, and further includes a shock absorbent element structured to protect the sensor panel, the x-ray processor and the monitor from impacts when in the stored configuration. The system further includes a second module having an x-ray generator that can be disposed between a stored configuration and an operative configuration. A shock absorbent element is provided in the second module to protect the x-ray generator from impacts when the second module is in the stored ...

Universal rotation hinge

FUNNY CURRENT (IF) INHIBITORS FOR USE IN A METHOD OF TREATING AND PREVENTING HEART DISEASE IN CANINE

The present invention relates to an Iblocker or a pharmaceutically acceptable salt thereof for the treatment and/or prevention of a canine patient suffering from heart diseases, preferably heart diseases such as dilated cardiomyopathy (DCM), mitral valve insufficiency (MI), arrthymias, preferably tachyarrthymias, preferably arterial arrhythmias, atrioventricular nodal arrhythmias and/or tachycardia. Each of these diseases may or may not result in heart failure (HF) in canine patients. The invention also relates to improving the quality of life, improving the general health condition as well as a prolonging the life expectancy in canine patients suffering from heart diseases and/or heart failure due to one or more of the following etiologies dilated cardiomyopathy (DCM), mitral valve insufficiency (MI), arrthymias, preferably tachyarrthymias, preferably arterial arrhythmias, atrioventricular nodal arrhythmias and/or tachycardia. 1. A funny current (I) inhibitor or a pharmaceutically acceptable salt thereof for use in a method for treating a canine patient suffering from heart disease.2. The funny current (I) inhibitor or a pharmaceutically acceptable salt thereof for use in a method according to claim 1 , wherein the canine patient suffers from heart failure.3. The funny current (I) inhibitor or a pharmaceutically acceptable salt thereof for use in a method according to claim 1 , wherein the canine patient suffers from arrhythmia.4. The funny current (I) inhibitor or a pharmaceutically acceptable salt thereof for use in a method according to claim 1 , wherein the heart disease is selected from the group consisting of: dilated cardiomyopathy claim 1 , mitral valve insufficiency claim 1 , arrhythmia claim 1 , tachyarrhythmia claim 1 , arterial arrhythmia claim 1 , atrioventricular nodal arrhythmia claim 1 , tachycardia claim 1 , supra and/or ventricular tachycardia.5. The funny current (I) inhibitor or a pharmaceutically acceptable salt thereof for use in a method ...

Memory device and method of improving the reliability of a memory device

A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being electrically connected to the bitlines and amplifying electrical signals carried in the bitlines, the amplifier circuits being activated and deactivated by means of amplifier circuit control nodes, and at least one potential supplying unit, by means of which potentials can be supplied to the amplifier circuits such that, in the deactivated state of the amplifier circuits, a decrease or a prevention of leakage currents through the amplifier circuits is caused.

INTEGRATED MEMORY

PROBLEM TO BE SOLVED: To obtain an activation time having an approximately same length with respect to a first selection line of first and second groups by providing the situation in which first and second address paths have first and second lines and first and second decoder circuits, the first decoder circuit decodes a supplied address faster than the second decoder circuit and the first line has a longer signal progressing time than the second line. SOLUTION: An address terminal ADR is connected to column selection lines CSL of first and second groups G1 and G2 through first and second address paths made up with first and second lines L1 and L2 and first and second decoder circuits DEC1 and DECK. The speed of the circuit DEC2 is slower than the speed of the circuit DEC1. By making the total length of the line L2 to be longer than the total length of the line L1, the signal progressing time of the line L1 becomes longer than the signal progressing time of the line L2 and the difference ...

Universal rotation hinge

The invention relates to an all-purpose turning joint which is a furniture member and comprises a right connecting plate and a left connecting plate, each of the two connecting plates is provided with a matching bearing surface and a gear surface at one end, the two connecting plates can enlarge the rotation angle through a plurality of steps of connecting device, each step of connecting device comprises an upper gear form plate and a lower gear form plate, the two ends of the upper gear form plate and the lower gear form plate are all provided with a bearing surface and a gear surface, the corresponding upper gear form plate and the lower gear form plate are movably connected through a rotation shaft; when the two connecting plates are stressed by the rotating force from the respective gear faces, the rotating force is stably transferred through the engaged gear surface and the limiting effect between the neighboring rotation shafts, and thus, the rotation angle between the two connecting ...

MEMORY CIRCUIT

PROBLEM TO BE SOLVED: To provide a memory circuit always arranged between two bit lines connected to predetermined different potentials where all bit lines have potential differences opposite to an arithmetic mean potential. SOLUTION: This memory circuit includes a plurality of parallel bit lines 21 to 28 connected to a plurality of memory cells 12, a plurality of sense amplifiers 341 to 344 connected to the bit lines, and a plurality of switches 351 to 354 each being connected to a pair of bit lines out of the plurality of bit lines for switchably short-circuiting the pair of bit lines. The bit lines of the pair of bit lines are connected to two different sense amplifiers, and the bit lines of the pair of bit lines are adjacent to a further bit line disposed between the bit lines of the pair of bit lines. COPYRIGHT: (C)2008,JPO&INPIT ...

METHOD FOR THE PRODUCTION OF AN INTERNAL STOP IN A TUBULAR COMPONENT

An inner diameter of a first end of a tubular component, positioned in relation to a first die, is reduced through relative movement between the tubular component and the first die such as to produce a first conical area between first and second ends of the tubular component. The first conical area is then formed through relative movement of a second die to create in a longitudinal section of the first conical area an outer circumferential embossment and an inner bead having an inner diameter smaller than the inner diameter of the first end. The first end is widened through insertion of an inner tool, while the tubular component is supported on an outside in a mold cavity of an outer tool. An inner contour with an internal stop is formed as an outer surface of the first end of the tubular component rests flatly in the mold cavity. 1. A method , comprising the steps of:positioning a tubular component of steel in relation to a first die having an inner diameter which is smaller than an outer diameter of the tubular component;reducing an inner diameter of a first end of the tubular component by a relative movement between the tubular component and the first die in an axial direction of the tubular component such as to produce a first conical area between the first end of reduced inner diameter and a second end of the tubular component;forming the first conical area by a relative movement of a second die in the axial direction of the tubular component in a direction of the second end of the tubular component, so as to create in a longitudinal section of the first conical area a circumferential embossment on an outside and a bead on an inside, with the bead having an inner diameter which is smaller than the reduced inner diameter of the first end;widening the first end of the tubular component by inserting an inner tool axially into the first end of the tubular component, while the tubular component is supported on an outside in a mold cavity of an outer tool; andforming ...

Adapter mit einem anschluss für einen zerstäuber

Ein Adapter umfasst einen Anschluss (20) für einen Zerstäuber (1) für ein, insbesondere ein Arzneimittel aufweisendes, Fluid (2) als Aerosol durch eine Zerstäuberdüse (12), wobei der Anschluss (20) über eine Bohrung (23) mit einem patientenseitigen Abgang (22) gekoppelt ist, und einen mit der Bohrung (23) strömungstechnisch derart verbundenen Eingang (25) für einen daran zu befestigenden Atemluftschlauch, dass die Hauptzerstäubungsrichtung des Fluids (2) parallel zur Strömungrichtung eines Atemgases ausgerichtet ist, wobei in einen dem Eingang (25) zugeordneten Durchbruch (24) eine parallel zur Bohrung (23) in Richtung des Zerstäubers (1) verlaufende Öffnung (27) eingelassen ist. Die Öffnung (27) erstreckt sich bis in einen dem Zerstäuber (1) zugewandten Bereich hinter der Zerstäuberdüse (12).

Memory device and method of improving the reliability of a memory device

A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being electrically connected to the bitlines and amplifying electrical signals carried in the bitlines, the amplifier circuits being activated and deactivated by means of amplifier circuit control nodes, and at least one potential supplying unit, by means of which potentials can be supplied to the amplifier circuits such that, in the deactivated state of the amplifier circuits, a decrease or a prevention of leakage currents through the amplifier circuits is caused.

Process for manufacturing an internal stop in a tubular component

Verfahren zur Herstellung eines inneren Anschlags (22) in einem Rohrbauteil (1) mit folgenden Schritten:a) Bereitstellen eines Rohrbauteils (1) aus Stahl mit einem ersten Ende (3) und einem zweiten Ende (5);b) Reduzieren eines Innendurchmessers (D4) des ersten Endes (3) mittels einer Relativbewegung zwischen dem Rohrbauteil (1) und einer das Rohrbauteil (1) innen aufnehmenden ersten Matrize (4), wobei die erste Matrize (4) einen Innendurchmesser (D2) besitzt, der kleiner ist als ein Außendurchmesser (D1) des Rohrbauteils (1), und wobei die Relativbewegung zur Umformung des Rohrbauteils (1) in Axialrichtung des Rohrbauteils (1) erfolgt, wobei ein erster konischer Bereich (6) zwischen dem im Innendurchmesser (D4) reduzierten ersten Ende (3) und zweiten Ende (5) hergestellt wird;c) Umformen des ersten konischen Bereichs (6) mittels einer Relativbewegung einer weiteren Matrize (7) in Axialrichtung des Rohrbauteils (1) in Richtung zum zweiten Ende (5), wodurch im Längenabschnitt des ersten konischen Bereiches (6) außenseitig eine umlaufende Sicke (8) und innenseitig ein Wulst (25) entsteht mit einem Innendurchmesser (D5), der kleiner als der Innendurchmesser (D4) des ersten Endes (3) ist, und wobei auf die Sicke (8) in Richtung zum zweiten Ende (5) folgend ein zweiter konischer Bereich (9) durch die Matrize (7) geformt wird;d) Aufweiten des ersten Endes (3) mittels wenigstens eines Innenwerkzeuges (12, 16), das axial in das erste Ende (3) eingeführt wird, während das Rohrbauteil (1) außenseitig in einem Formhohlraum (11) eines Außenwerkzeugs (10) abgestützt ist und Ausformen einer Innenkontur (20) mit dem inneren Anschlag (22), indem die Außenfläche (15) des ersten Endes (3) flächig im Formhohlraum (11) zur Anlage gebracht wird. Method for producing an inner stop (22) in a tubular component (1), comprising the following steps:a) providing a tubular component (1) made of steel with a first end (3) and a second end (5);b) reducing an inner diameter ( D4) of the first end ( ...

Circuit for programming the delay time of a signal path

Voltage pump with switch-on control

The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

Circuit configuration for programming a delay in a signal path

A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

Tubular element for gas pressure vessel, gas pressure vessel and method of manufacturing a tubular element

This invention concerns a tubular element for a gas pressure vessel of an airbag module, in particular of a vehicle, wherein the tubular element (1) consists of high-strength steel, has a first and a second end (17, 18) and from the first end (17) to the second end (18) the tubular element (1) has an undeformed section (11), a transition section (12) and a tapering section (13) and on the tapering section (13) at least one radially outwardly extending collar (14) is formed, characterized in that the collar (14) is separated from the transition section (12) by a first length section (130) having an outer diameter (A1) smaller than the outer diameter (A2) of the collar (14) and the wall thickness of the collar (14) is greater than the wall thickness of the first length section (130). Furthermore, the invention concerns a gas pressure vessel and a process for manufacturing a tubular element according to the invention (1).

Layout of a sense amplifier with accelerated signal evaluation

A layout of a sense amplifier configuration for a semiconductor memory is described. The layout has a plurality of read/write amplifiers, extending as strips in the form of rows one under the other, and having NMOS and PMOS transistors. At least one of the two driver transistors is disposed with its doping regions between the associated NMOS or PMOS transistors of the read/write amplifiers. A gate of the driver transistor is configured as a two-strip gate, in order to accelerate the signal evaluation in the sense amplifiers.

Layout of a sense-amplifier with accelerated signal-evaluation

Semiconductor-memory with differential bit-lines

FB DRAM Memory with State Memory

A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

Integrierte Schaltung mit Testbetriebsart und Verfahren zum Testen einer Vielzahl solcher integrierter Schaltungen

Das Testen integrierter Schaltungen, insbesondere von Speicherchips des Typs DDR SDRAM, erfolgt in paralleler Weise. Um zu vermeiden, daß die Schaltungen im Testbetrieb gegeneinander treiben, wird ein bereits ohnehin mit einem Kanal eines Testautomaten verbundener Eingangsanschluß (10) mit Schaltmitteln (30) verbunden, durch die die Ausgangstreiber in Abhängigkeit vom am Eingangsanschluß (10) zuführbaren Steuersignal abschaltbar sind. Die Schaltmittel (30) enthalten vorzugsweise einen Demultiplexer (31) sowie einen Multiplexer (32). Der Demultiplexer ist durch ein neben dem Teststeuersignal (TMCOMP) zusätzlich erzeugtes Teststeuer (TMRDIS) ansteuerbar. Der Eingangsanschluß (10) ist im Testbetrieb ohnehin mit einem Testerkanal verbunden, so daß kein zusätzlicher externer Aufwand entsteht.